Adjustable charge pump circuit and memory
By designing an adjustable charge pump circuit, the potential of the switching array and capacitors is controlled by using non-cross clock signals and adjustable control signals, the problems of large circuit power consumption and large area in the memory chip are solved, and the flexibility of multi-stage voltage output and power consumption saving are achieved.
Patent Information
- Application Number
- CN202311703043.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2025-06-13
AI Technical Summary
The circuits that provide various operating voltages in existing memory chips consume a large power and occupy a large chip area.
An adjustable charge pump circuit is designed, including a non-crossing clock generation unit, a switch control signal generation unit and a charge pump unit, and the potential of the switch array and capacitor are controlled through the non-crossing clock signal and the adjustable control signal to realize multi-stage voltage output.
The flexibility of multi-speed voltage output is achieved, reducing dependence on multiple sets of charge pumps and LDO circuits, saving power consumption and chip area.
Smart Images
Figure CN120148567A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to an adjustable charge pump circuit and a memory. Background Art
[0002] In current memory chips, multiple voltages are required to program memory cells (V PGM ), Erase(V ERASE ) and readout (V READ ) etc., wherein the high voltage can be obtained by a conventional Dickson charge pump 1, such as Figure 1 As shown, the Dickson charge pump 1 includes N cascaded MOS transistors (M1, M2, ..., MN), each MOS transistor is used as a diode to realize unidirectional charge transmission, and the connection node of each MOS transistor is respectively connected to a capacitor (C 1 , C 2 ……C N ), the lower plates of each capacitor are alternately connected to the clock signal CLK and its inverse signal CLKB, one end of the cascade structure is connected to the power supply voltage VDD, and the other end is connected to the load capacitor C load And output the boosted voltage Vout. The circuit principle is as follows: when the clock signal CLK is at a low level in the first clock cycle, the potential at point A is pulled up to VDD-V by transistor M1. THN ; When the clock signal CLK is at a high level in the first clock cycle, the potential at point A will be raised to 2*VDD-V THN At this time, transistor M2 is turned on, and the potential of point B is charged to 2*(VDD-V THN ); When the clock signal CLK is at a low level in the second clock cycle, the clock signal's inverted signal CLKB is at a high level, and the potential at point B is raised to 3*VDD-2*V THN When the clock signal CLK is at a high level in the second clock cycle, the clock signal's inverted signal CLKB is at a low level, and the potential at point B is pulled back to 2*(VDD-V THN ). By analogy, the output potential of the charge pump is Vout = (N + 1) * (VDD-V THN ).
[0003] The output voltage of the existing charge pump is single and fixed. In order to meet the above requirements, it is necessary to design two charge pumps and an LDO (linear regulator), such as Figure 2 As shown, the charge pump CP1 provides the programming circuit with a programming voltage V PGM , the charge pump CP2 provides the erase voltage V to the erase circuit ERASE , LDO provides the readout circuit with a readout voltage V READ , which invisibly increases the chip power consumption and chip area.
[0004] Therefore, how to reduce the power consumption and chip area of the circuit that provides the voltages required for various operations in a memory chip has become one of the problems that need to be solved urgently by those skilled in the art.
[0005] It should be noted that the above introduction of the technical background is only for the purpose of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an adjustable charge pump circuit and a memory, which are used to solve the problems such as large power consumption and large chip area occupied by the circuit that provides the voltages required for various operations in the existing memory chip.
[0007] To achieve the above object and other related objects, the present invention provides an adjustable charge pump circuit, and the adjustable charge pump circuit includes:
[0008] A non-overlapping clock generation unit, a switch control signal generation unit, and a charge pump unit;
[0009] The non-overlapping clock generation unit receives a working clock and generates at least two non-overlapping clock signals based on the working clock;
[0010] The switch control signal generation unit is connected to the output end of the non-overlapping clock generation unit, receives an adjustable control signal, and generates corresponding switch control signals based on the adjustable control signal and the output signal of the non-overlapping clock generation unit;
[0011] The charge pump unit includes a switch array and at least two capacitors. The charge pump unit is connected to the output end of the switch control signal generation unit, controls each switch of the switch array to be turned on or off based on the switch control signal, so as to adjust the potentials of the upper and lower plates of each capacitor, and further outputs a voltage value corresponding to the adjustable control signal.
[0012] Optionally, the relationship between the number of switches and capacitors in the charge pump unit satisfies the following formula:
[0013] Ns ≤ (Nc + 1) * Nc;
[0014] Wherein, Ns is the number of switches in the switch array, and Nc is the number of capacitors.
[0015] More optionally, the charge pump unit includes eighteen switches and four capacitors; among them,
[0016] One end of the first switch, the second switch, the third switch and the fourth switch is grounded, and the other ends are respectively connected to the lower plates of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor;
[0017] One end of the fifth switch, the sixth switch and the seventh switch are respectively connected to the upper plates of the first capacitor, the second capacitor and the third capacitor, and the other ends are connected to the upper plate of the fourth capacitor via the eighth switch;
[0018] One end of the ninth switch is connected to the upper plate of the first capacitor, and the other end is connected to the lower plate of the second capacitor;
[0019] One end of the tenth switch is connected to the upper plate of the first capacitor, and the other end is connected to the lower plate of the third capacitor;
[0020] One end of the eleventh switch is connected to the upper plate of the second capacitor, and the other end is connected to the lower plate of the third capacitor;
[0021] One end of the twelfth switch is connected to the upper plate of the third capacitor, and the other end is connected to the lower plate of the fourth capacitor;
[0022] One end of the thirteenth switch is connected to the input voltage, and the other end is connected to the lower plate of the first capacitor;
[0023] One end of the fourteenth switch is connected to the input voltage, and the other end is connected to the lower plate of the second capacitor;
[0024] One ends of the fifteenth switch, the sixteenth switch, the seventeenth switch and the eighteenth switch are respectively connected to the upper plates of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor, and the other ends are connected together as the output terminal of the charge pump unit.
[0025] More optionally, the capacitance values of the capacitors are equal.
[0026] More optionally, the output-to-input voltage ratio of the charge pump unit is 0.5 times, 1.0 times, 1.5 times, 2.0 times, 2.5 times, 3.0 times, 3.5 times or 4.0 times.
[0027] Optionally, the adjustable charge pump circuit further includes a voltage dividing unit, which is connected to the output terminal of the charge pump unit to divide the output signal of the charge pump unit.
[0028] More optionally, the adjustable charge pump circuit further includes a feedback unit, a comparison unit and an adjustable control signal adjustment unit;
[0029] The feedback unit, connected to the charge pump unit, is used to generate a feedback voltage of the output voltage of the charge pump unit;
[0030] The first input terminal of the comparison unit is connected to the feedback unit to receive the feedback voltage, and the second input terminal receives a reference voltage and outputs a comparison result;
[0031] The adjustable control signal adjustment unit is connected to the output terminal of the comparison unit and adjusts the adjustable control signal based on the comparison result so that the charge pump unit outputs a corresponding voltage value.
[0032] Optionally, the feedback unit includes at least two resistors connected in series.
[0033] Optionally, the adjustable control signal adjustment unit includes a counter and a multiplexer;
[0034] The counter is connected to the output terminal of the comparison unit and receives an initial control signal, and increments or decrements the adjustable control signal in the previous state based on the comparison result;
[0035] The first input terminal of the multiplexer receives the initial control signal, and the second input terminal is connected to the output terminal of the counter to output the adjustable control signal.
[0036] To achieve the above object and other related objects, the present invention further provides a memory, which at least includes: the above adjustable charge pump circuit, and the adjustable charge pump circuit provides an erase voltage, a programming voltage, and a read voltage for the memory in a time-sharing manner.
[0037] Optionally, when the output terminal of the charge pump unit is connected to a voltage dividing unit, the adjustable charge pump circuit simultaneously provides an erase voltage, a programming voltage, and a read voltage for the memory.
[0038] As described above, the adjustable charge pump circuit and the memory of the present invention have the following beneficial effects:
[0039] The adjustable charge pump circuit and the memory of the present invention can achieve multi-level voltage output, greatly improving flexibility. At the same time, various operating voltages required by the memory can be obtained without multiple sets of charge pumps and LDO circuits, greatly saving power consumption and chip area. Description of the Drawings
[0040] Figure 1 It shows a circuit structure diagram of a Dickson charge pump.
[0041] Figure 2 It shows a circuit structure diagram for providing voltages required for various operations in a storage chip in the prior art.
[0042] Figure 3 It shows a structure diagram of an adjustable charge pump circuit of the present invention.
[0043] Figure 4 Waveform schematic diagram showing the non-overlapping clock of the present invention.
[0044] Figure 5 Schematic diagram showing the corresponding relationship between the output-input voltage ratio of the present invention and the adjustable control signal and the switch control signal.
[0045] Figure 6 Schematic diagram showing the structure of the charge pump unit of the present invention.
[0046] Figure 7 Schematic diagram showing the principle of the charge pump unit of the present invention when the output-input voltage ratio is 4 times.
[0047] Figure 8 Another schematic diagram showing the structure of the adjustable charge pump circuit of the present invention.
[0048] Description of component labels
[0049] 1 Adjustable charge pump circuit
[0050] 11 Non-overlapping clock generation unit
[0051] 12 Switch control signal generation unit
[0052] 13 Charge pump unit
[0053] 131 Switch array
[0054] 14 Voltage dividing unit
[0055] 15 Feedback unit
[0056] 16 Comparison unit
[0057] 17 Adjustable control signal adjustment unit Detailed implementation manners
[0058] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0059] Please refer to Figures 3 to 8 . It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0060] Embodiment 1
[0061] As Figure 3 shown, this embodiment provides an adjustable charge pump circuit 1, and the adjustable charge pump circuit 1 includes:
[0062] a non-overlapping clock generation unit 11, a switch control signal generation unit 12, and a charge pump unit 13.
[0063] As Figure 3 shown, the non-overlapping clock generation unit 11 receives a working clock CK and generates at least two non-overlapping clock signals based on the working clock CK.
[0064] Specifically, as Figure 4 shown, in this embodiment, the non-overlapping clock generation unit 11 generates a non-overlapping first clock signal CLK1 and a second clock signal CLK2. Any circuit structure capable of generating non-overlapping clocks is applicable to the present invention. In this embodiment, the non-overlapping clock generation unit 11 further generates an inverted signal CLK2B of the second clock signal CLK2. In actual use, an inverted signal CLK1B of the first clock signal CLK1 may also be provided as needed, not limited to this embodiment.
[0065] As Figure 3 shown, the switch control signal generation unit 12 is connected to the output end of the non-overlapping clock generation unit 11, receives an adjustable control signal CTR<2:0>, and generates a corresponding switch control signal SW<12:0> based on the adjustable control signal CTR<2:0> and the output signal of the non-overlapping clock generation unit 11.
[0066] Specifically, in this embodiment, the adjustable control signal CTR<2:0> is configured as a three-bit signal, and the switch control signal SW<12:0> is configured as a 13-bit signal. In actual use, the number of bits of the adjustable control signal and the switch control signal can be configured as needed. As an example, the switch control signal generation unit 12 includes a logic module and a level conversion module (not shown in the figure); the logic module converts the adjustable control signal into the switch control signal based on digital logic circuits; the level conversion module is connected to the output end of the logic module and performs level conversion on the switch control signal output by the logic module to meet the level requirements for subsequent switch control.
[0067] Specifically, as an example, the adjustable charge pump circuit 1 of this embodiment is used to achieve an adjustable voltage multiplication output with an output-input voltage ratio VDDP / VDD of 0.5 times, 1.0 times, 1.5 times, 2.0 times, 2.5 times, 3.0 times, 3.5 times, and 4.0 times. The corresponding relationship between the adjustable control signal CTR<2:0> and the switch control signal SW<12:0> is as Figure 5 shown. Among them, the voltage amplitude of CTR<2:0> is consistent with the input voltage VDD, the voltage amplitudes of SW<0>, SW<3>, and SW<5> are consistent with the input voltage VDD, and the voltage amplitudes of SW<2:1>, SW<4>, and SW<12:6> are consistent with the output voltage VDDP. In actual use, the corresponding relationship and the voltage amplitudes corresponding to each switch control signal can be set according to needs, as long as an adjustable voltage multiplication output can be achieved.
[0068] As Figure 3 shown, the charge pump unit 13 includes a switch array 131 and at least two capacitors. The charge pump unit 13 is connected to the output end of the switch control signal generation unit 12, and based on the switch control signal SW<12:0>, each switch is controlled to conduct or turn off to adjust the potentials of the upper and lower plates of each capacitor, and then a voltage value corresponding to the adjustable control signal CTR<2:0> is output. In this example, the charge pump unit 13 further includes a load capacitor C load , one end of the load capacitor C load is connected to the output end of the switch array 131, and the other end is grounded to VSS.
[0069] Specifically, in this embodiment, the relationship between the number of capacitors Nc and the corresponding number of switches Ns is determined as follows: Nc capacitors correspond to Nc nodes, and adding the node of the power supply itself forms Nc + 1 nodes. The maximum number of switches Ns is (Nc + 1)*Nc. In different application scenarios, not all of the (Nc + 1)*Nc switches will be utilized. Therefore, the charge pump structure can be simplified, and then the number of switches can be reduced, that is, Ns ≤ (Nc + 1)*Nc. In actual use, the number of capacitors and switches can ensure the realization of the charge pump function, and will not be elaborated one by one here.
[0070] More specifically, as Figure 6As shown, by way of example, the charge pump unit 13 includes eighteen switches and four capacitors. Among them, one ends of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are grounded to VSS, and the other ends are respectively connected to the lower plates (denoted as C1M, C2M, C3M, C4M) of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4; one ends of the fifth switch K5, the sixth switch K6, and the seventh switch K7 are respectively connected to the upper plates (denoted as C1P, C2P, C3P) of the first capacitor C1, the second capacitor C2, and the third capacitor C3, and the other ends are connected to the upper plate (denoted as C4P) of the fourth capacitor C4 via the eighth switch K8; one end of the ninth switch K9 is connected to the upper plate (C1P) of the first capacitor C1, and the other end is connected to the lower plate (C2M) of the second capacitor C2; one end of the tenth switch K10 is connected to the upper plate (C1P) of the first capacitor C1, and the other end is connected to the lower plate (C3M) of the third capacitor C3; one end of the eleventh switch K11 is connected to the upper plate (C2P) of the second capacitor C2, and the other end is connected to the lower plate (C3M) of the third capacitor C3; one end of the twelfth switch K12 is connected to the upper plate (C3P) of the third capacitor C3, and the other end is connected to the lower plate (C4M) of the fourth capacitor C4; one end of the thirteenth switch K13 is connected to the input voltage VDD, and the other end is connected to the lower plate (C1M) of the first capacitor C1; one end of the fourteenth switch K14 is connected to the input voltage VDD, and the other end is connected to the lower plate (C2M) of the second capacitor C2; one ends of the fifteenth switch K15, the sixteenth switch K16, the seventeenth switch K17, and the eighteenth switch K18 are respectively connected to the upper plates (C1P, C2P, C3P, C4P) of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, and the other ends are connected together as the output end (output VDDP) of the charge pump unit 13.In this example, the first switch K1 receives the switch control signal SW<0>, the second switch K2 receives the switch control signal SW<3>, the third switch K3 receives the switch control signal SW<7>, the fourth switch K4 receives the switch control signal SW<10>, the fifth switch K5 receives the switch control signal SW<2>, the sixth switch K6 receives the switch control signal SW<1>, the seventh switch K7 receives the switch control signal SW<7>, the eighth switch K8 receives the switch control signal SW<10>, the ninth switch K9 receives the switch control signal SW<4>, the tenth switch K10 receives the inverted signal SWB<8> of the switch control signal SW<8>, the eleventh switch K11 receives the inverted signal SWB<8> of the switch control signal SW<8>, the twelfth switch K12 receives the inverted signal SWB<11> of the switch control signal SW<11>, the thirteenth switch K13 receives the inverted signal SWB<5> of the switch control signal SW<5>, the fourteenth switch K14 receives the inverted signal SWB<5> of the switch control signal SW<5>, the fifteenth switch K15 receives the inverted signal SWB<6> of the switch control signal SW<6>, the sixteenth switch K16 receives the inverted signal SWB<6> of the switch control signal SW<6>, the seventeenth switch K17 receives the inverted signal SWB<9> of the switch control signal SW<9>, and the eighteenth switch K18 receives the inverted signal SWB<12> of the switch control signal SW<12>. As an example, the capacitance values of the capacitors are equal, i.e., C1 = C2 = C3 = C4.
[0071] It should be noted that in actual use, the number of switches and capacitors can be set as needed, and the connection relationship between each switch and each capacitor can also be set as needed, as long as the voltage multiplication output can be achieved based on the switch control signal, which will not be elaborated here one by one.
[0072] Specifically, the charge pump unit 13 continuously switches the potentials corresponding to the upper and lower plates of each capacitor based on the conduction or cutoff of each switch, and finally obtains the desired output voltage VDDP. Taking the output-input voltage ratio VDDP / VDD equal to 4.0 times as an example, the switch control signals are shown in Figure 5 , as Figure 7 shown. In this case, the ninth switch K9, the fifteenth switch K15, the sixteenth switch K16, and the seventeenth switch K17 are always in the off state ( Figure 7Remove the corresponding switches and circuits), the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7, and the eighth switch K8 are controlled by the first clock signal CLK1, and the tenth switch K10, the eleventh switch K11, the twelfth switch K12, the thirteenth switch K13, the fourteenth switch K14, and the eighteenth switch K18 are controlled by the second clock signal CLK2. When the first clock signal CLK1 is at the high level of the first clock cycle and the second clock signal CLK2 is at the low level of the first clock cycle, the lower plate potentials of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are pulled to VSS, and the upper plate potentials of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 follow the output voltage VDDP of the previous state, which is VDD; when the first clock signal CLK1 is at the low level of the first clock cycle and the second clock signal CLK2 is at the high level of the first clock cycle, the lower plate potentials of the first capacitor C1 and the second capacitor C2 are pulled to VDD, the upper plate potentials of the first capacitor C1 and the second capacitor C2 are raised to 2VDD, the lower plate (connected to the upper plates of the first capacitor C1 and the second capacitor C2) of the third capacitor C3 is pulled to 2VDD, the upper plate potential of the third capacitor C3 is raised to 3VDD, the lower plate (connected to the upper plate of the third capacitor C1) of the fourth capacitor C4 is pulled to 3VDD, and the upper plate of the fourth capacitor C4 is raised to 4VDD and output. The working principles of other output-input voltage ratios are similar and will not be elaborated here one by one.
[0073] As Figures 3 to 7 shown, the adjustable charge pump circuit of the present invention can adjust the ratio of the output voltage to the input voltage based on the adjustable control signal CTR<2:0>, set the adjustable control signal to the first state in one application scenario as needed and obtain the output voltage of the corresponding multiple (for example, the adjustable control signal CTR<2:0> is set to 010, and the output voltage is 1.5 times the input voltage), set the adjustable control signal to the second state in another application scenario and obtain the output voltage of the corresponding multiple (for example, the adjustable control signal CTR<2:0> is set to 101, and the output voltage is 3.0 times the input voltage), and meet different output voltage requirements through time division multiplexing, which can greatly save the circuit area, power consumption, and cost.
[0074] Embodiment 2
[0075] As Figure 8As shown in the figure, this embodiment provides an adjustable charge pump circuit 1, which is different from that of the first embodiment in that the adjustable charge pump circuit 1 further includes a voltage dividing unit 14.
[0076] Specifically, the voltage dividing unit 14 is connected to the output terminal of the charge pump unit 13 to divide the output signal of the charge pump unit 13. One or more voltage values proportional to the output voltage of the charge pump unit 13 are obtained through voltage division to meet the voltage requirements of different circuits. In this embodiment, the voltage dividing unit 14 includes a plurality of resistors (R F1 ~R F(N+1) ) connected in series. Three voltages are obtained through resistor voltage division and are respectively used as the erase voltage V ERASE , programming voltage V PGM and read voltage V READ of the storage unit.
[0077] As Figure 8 shown, another difference between the adjustable charge pump circuit 1 of this embodiment and that of the first embodiment is that the adjustable charge pump circuit 1 further includes a feedback unit 15, a comparison unit 16, and an adjustable control signal adjustment unit 17.
[0078] As Figure 8 shown, the feedback unit 15 is used to generate a feedback voltage of the output voltage VDDP of the charge pump unit 13.
[0079] Specifically, in this embodiment, the feedback unit 15 includes at least two resistors connected in series; in actual use, any current structure that can realize the feedback of the output voltage VDDP of the charge pump unit 13 is applicable. As an example, the feedback unit 15 is connected in series with the voltage dividing unit 14, and the feedback voltage is output through voltage division of the resistor R F0 and each resistor in the voltage dividing unit 14; in actual use, the feedback unit 15 can be directly connected to the output terminal of the charge pump unit 13 (as an example, when the voltage dividing unit 14 is not provided, the feedback unit 15 is connected to the output terminal of the charge pump unit 13; as another example, when the voltage dividing unit 14 is provided, the feedback unit 15 can also be connected to the output terminal of the charge pump unit 13), which is not limited to this embodiment.
[0080] As Figure 8 shown, the first input terminal of the comparison unit 16 is connected to the feedback voltage, the second input terminal receives a reference voltage VREF, and a comparison result V CP is output.
[0081] Specifically, in this embodiment, the inverting input terminal of the comparison unit 16 is connected to the feedback voltage, and the non-inverting input terminal is connected to the reference voltage VREF; in actual use, the relationship between the input terminal polarity and the corresponding input signal can be adjusted as needed, and this embodiment is not limiting.
[0082] As Figure 8 shown, the adjustable control signal adjustment unit 17 is connected to the output terminal of the comparison unit 16, and adjusts the adjustable control signal CTR<2:0> based on the comparison result V CP so that the charge pump unit 13 outputs a corresponding voltage value.
[0083] Specifically, in this embodiment, the adjustable control signal adjustment unit 17 includes a counter and a multiplexer (not shown in the figure). The counter is connected to the output terminal of the comparison unit 16 and receives an initial control signal (the initial control signal can be set to any state of the adjustable control signal CTR<2:0>), and based on the comparison result V CP performs an increment count or a decrement count on the adjustable control signal CTR<2:0> of the previous state. The first input terminal of the multiplexer receives the initial control signal, the second input terminal is connected to the output terminal of the counter, and outputs the adjustable control signal CTR<2:0>.
[0084] As Figure 8 shown, when starting to work, the multiplexer transfers the initial control signal as the adjustable control signal CTR<2:0> to the switch control signal generation unit 12 and generates an initial output voltage VDDP (preliminary adjustment). The output voltage VDDP is fed back to the comparison unit 16 and a comparison result is generated; if the feedback signal of the output voltage VDDP is greater than the reference voltage VREF, the counter performs a decrement count on the initial control signal, so that the output-input voltage ratio corresponding to the adjustable control signal CTR<2:0> decreases by one step, and the output voltage VDDP decreases; if the feedback signal of the output voltage VDDP is less than the reference voltage VREF, the counter performs an increment count on the initial control signal, so that the output-input voltage ratio corresponding to the adjustable control signal CTR<2:0> increases by one step, and the output voltage VDDP increases; continuously adjust the adjustable control signal CTR<2:0> so that the feedback voltage of the output voltage VDDP is equal to the reference voltage VREF. At this time, the output voltage VDDP is the voltage value required for the subsequent circuit to work. In actual use, the relationship between the adjustable control signal and the output-input voltage ratio can also be adjusted, and the output voltage VDDP is decreased by increment count and increased by decrement count, and this embodiment is not limiting.
[0085] It should be noted that the adjustable charge pump circuit of the present invention (including but not limited to Embodiment 1 and Embodiment 2) can be applied not only to the memory mentioned in the background art, but also to any occasion that requires a charge pump and improves flexibility. The adjustable charge pump circuit of the present invention is not limited to this embodiment.
[0086] Embodiment 3
[0087] This embodiment provides a memory, which at least includes: the adjustable charge pump circuit 1 of Embodiment 1 or Embodiment 2. The memory also includes structures such as a storage array, a row control circuit, and a column control circuit. The specific connection relationships are not elaborated here one by one.
[0088] As an example, when the adjustable charge pump circuit 1 does not have a voltage dividing unit, the adjustable charge pump circuit 1 provides an erase voltage, a programming voltage, and a read voltage for the memory in a time-sharing manner. That is, when the memory performs an erase operation, the adjustable charge pump circuit 1 provides an erase voltage V ERASE based on the adjusted adjustable control signal; when the memory performs a programming operation, the adjustable charge pump circuit 1 provides a programming voltage V PGM based on the adjusted adjustable control signal; when the memory performs a read operation, the adjustable charge pump circuit 1 provides a read voltage V READ .
[0089] As another example, when the adjustable charge pump circuit 1 has a voltage dividing unit, the adjustable charge pump circuit 1 simultaneously provides an erase voltage V ERASE , a programming voltage V PGM , and a read voltage V READ for the memory. The charge pump unit 13 outputs a preset voltage VDDP, and then obtains the required erase voltage V ERASE , programming voltage V PGM , and read voltage V READ for operation based on voltage division by each resistor.
[0090] In summary, the present invention provides an adjustable charge pump circuit and a memory, including: a non-overlapping clock generation unit, a switch control signal generation unit, and a charge pump unit; the non-overlapping clock generation unit receives a working clock and generates at least two non-overlapping clock signals based on the working clock; the switch control signal generation unit is connected to the output end of the non-overlapping clock generation unit, receives an adjustable control signal, and generates corresponding switch control signals based on the adjustable control signal and the output signal of the non-overlapping clock generation unit; the charge pump unit includes a switch array and at least two capacitors, the charge pump unit is connected to the output end of the switch control signal generation unit, and controls each switch to conduct or turn off based on the switch control signal to adjust the potentials of the upper and lower plates of each capacitor, and further outputs a voltage value corresponding to the adjustable control signal. The adjustable charge pump circuit and memory of the present invention can achieve multi-level voltage output, greatly improving flexibility. At the same time, various operating voltages required by the memory can be obtained without multiple sets of charge pump and LDO circuits, greatly saving power consumption and chip area. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0091] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. An adjustable charge pump circuit, characterized in that, the adjustable charge pump circuit comprises: a non-overlapping clock generation unit, a switch control signal generation unit, and a charge pump unit; the non-overlapping clock generation unit receives a working clock and generates at least two non-overlapping clock signals based on the working clock; the switch control signal generation unit is connected to the output end of the non-overlapping clock generation unit, receives an adjustable control signal, and generates corresponding switch control signals based on the adjustable control signal and the output signal of the non-overlapping clock generation unit; the charge pump unit includes a switch array and at least two capacitors, the charge pump unit is connected to the output end of the switch control signal generation unit, and controls the conduction or cutoff of each switch of the switch array based on the switch control signal to adjust the potentials of the upper and lower plates of each capacitor, and further outputs a voltage value corresponding to the adjustable control signal.
2. The adjustable charge pump circuit according to claim 1, characterized in that: the relationship between the number of switches and capacitors in the charge pump unit satisfies the following formula: Ns≤(Nc + 1)*Nc; wherein, Ns is the number of switches in the switch array, and Nc is the number of capacitors.
3. The adjustable charge pump circuit according to claim 1 or 2, characterized in that: the charge pump unit includes eighteen switches and four capacitors; wherein, one ends of the first switch, the second switch, the third switch, and the fourth switch are grounded, and the other ends are respectively connected to the lower plates of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor; one ends of the fifth switch, the sixth switch, and the seventh switch are respectively connected to the upper plates of the first capacitor, the second capacitor, and the third capacitor, and the other ends are connected to the upper plate of the fourth capacitor via the eighth switch; one end of the ninth switch is connected to the upper plate of the first capacitor, and the other end is connected to the lower plate of the second capacitor; one end of the tenth switch is connected to the upper plate of the first capacitor, and the other end is connected to the lower plate of the third capacitor; one end of the eleventh switch is connected to the upper plate of the second capacitor, and the other end is connected to the lower plate of the third capacitor; one end of the twelfth switch is connected to the upper plate of the third capacitor, and the other end is connected to the lower plate of the fourth capacitor; one end of the thirteenth switch is connected to the input voltage, and the other end is connected to the lower plate of the first capacitor; one end of the fourteenth switch is connected to the input voltage, and the other end is connected to the lower plate of the second capacitor; one ends of the fifteenth switch, the sixteenth switch, the seventeenth switch, and the eighteenth switch are respectively connected to the upper plates of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor, and the other ends are connected together as the output end of the charge pump unit.
4. The adjustable charge pump circuit according to claim 3, characterized in that: the capacitance values of the capacitors are equal.
5. The adjustable charge pump circuit according to claim 4, characterized in that: the output-to-input voltage ratio of the charge pump unit is 0.5 times, 1.0 times, 1.5 times, 2.0 times, 2.5 times, 3.0 times, 3.5 times, or 4.0 times.
6. The adjustable charge pump circuit according to claim 1, characterized in that: The adjustable charge pump circuit further includes a voltage division unit, which is connected to the output end of the charge pump unit and divides the output signal of the charge pump unit.
7. The adjustable charge pump circuit according to any one of claims 1-6, wherein: the adjustable charge pump circuit further includes a feedback unit, a comparison unit and an adjustable control signal adjustment unit; the feedback unit is connected to the charge pump unit and is used to generate a feedback voltage of the output voltage of the charge pump unit; a first input end of the comparison unit is connected to the feedback unit to receive the feedback voltage, a second input end receives a reference voltage, and a comparison result is output; the adjustable control signal adjustment unit is connected to the output end of the comparison unit and adjusts the adjustable control signal based on the comparison result so that the charge pump unit outputs a corresponding voltage value.
8. The adjustable charge pump circuit according to claim 7, wherein: the feedback unit includes at least two resistors connected in series.
9. The adjustable charge pump circuit according to claim 7, wherein: the adjustable control signal adjustment unit includes a counter and a multiplexer; the counter is connected to the output end of the comparison unit and receives an initial control signal, and incrementally counts or decrements the adjustable control signal in the previous state based on the comparison result; a first input end of the multiplexer receives the initial control signal, a second input end is connected to the output end of the counter, and the adjustable control signal is output.
10. A memory, wherein, the memory at least includes: the adjustable charge pump circuit according to any one of claims 1-9, and the adjustable charge pump circuit provides an erase voltage, a programming voltage and a read voltage for the memory in a time-sharing manner.