Carbon-based MRAM (Magnetic Random Access Memory) storage unit, storage array and working method thereof

Abstract

The invention provides a carbon-based MRAM (Magnetic Random Access Memory) storage unit, a storage array and a working method thereof. The carbon-based MRAM storage unit comprises a first carbon-based transistor, a second carbon-based transistor, a third carbon-based transistor and a magnetic tunnel junction, the grid electrode of the first carbon-based transistor is connected to the WWL, the first end is connected to the WBL, and the second end is connected to the first end of the magnetic tunnel junction; the grid electrode of the second carbon-based transistor is connected to the WWR, the first end is connected to the WBLB, and the second end is connected to the T1 end of the magnetic tunnel junction; the grid electrode of the third carbon-based transistor is connected to the RWL, the first end is connected to the third end of the magnetic tunnel junction, and the second end is connected to the RBL; the second end of the magnetic tunnel junction is connected to a source line (SL). The two inputs of the present application are mapped to word line and bit line voltages, so there is no requirement for the TMR value of the memory cell. In addition, an operation result is stored back into the unit, so that the circuit design is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory computing, and in particular, to a carbon-based MRAM storage cell, an in-memory computing array, and a working method thereof. Background Art

[0002] In the past, the development of complementary metal-oxide-semiconductor technology and the support of Moore's law have been promoting the design of very large-scale integrated circuits. However, as the size of metal-oxide field-effect transistors (MOSFETs) shrinks and even approaches the physical limit, the performance of transistors does not increase correspondingly, but the leakage current increases accordingly. Therefore, the continuation of Moore's law faces huge challenges. In recent years, with the advent of the Internet of Things and big data era, the in-depth analysis and processing of massive unstructured data have put forward higher requirements for computing speed and energy efficiency, and the systems based on the von Neumann architecture can gradually no longer meet the needs. Therefore, exploring new physical mechanism devices and developing an integrated architecture for storage and computing have become the forefront focuses of attention in the academic and industrial circles. Computing in-memory (CIM) technology has emerged as the times require. However, the current silicon-based in-memory computing architecture has reached its performance limit.

[0003] The current existing in-memory Boolean logic operations based on CMOS technology and magnetoresistive random access memory (MRAM) are mainly divided into two types: read-out type and write-in type. The read-out type of in-memory Boolean logic operation is to activate two rows of word lines in the array at one time, and identify the bit line voltage through a sense amplifier to achieve logical operations. However, when performing XOR / XNOR operations, additional logic gate circuits and sense amplifiers need to be added; and only two rows of data in the array can be accessed at one time, and its throughput will also be limited. The write-in type of in-memory Boolean logic operation determines whether the target cell is rewritten according to the resistance states of two input cells. Therefore, this technology requires an initialization operation for the target cell and the tunnel magnetoresistance (TMR) of the input cell also affects the accuracy of its output result. Summary of the Invention

[0004] In view of this, the present invention provides a carbon-based MRAM storage cell, an in-memory computing array, and a working method thereof to solve at least one of the above-mentioned problems.

[0005] To achieve the above object, the present invention adopts the following solutions:

[0006] According to a first aspect of the present invention, a carbon-based MRAM storage cell is provided. The carbon-based MRAM storage cell includes: a first carbon-based transistor, a second carbon-based transistor, a third carbon-based transistor, and a magnetic tunnel junction. The gate of the first carbon-based transistor is connected to the left write word line, the first end is connected to the write bit line, and the second end is connected to the first end of the magnetic tunnel junction. The gate of the second carbon-based transistor is connected to the right write word line, the first end is connected to the inverted write bit line, and the second end is connected to the first end of the magnetic tunnel junction. The gate of the third carbon-based transistor is connected to the read word line, the first end is connected to the third end of the magnetic tunnel junction, and the second end is connected to the read bit line. The second end of the magnetic tunnel junction is connected to the source line, and the first end and the second end of the magnetic tunnel junction are located at the bottom electrode of the magnetic tunnel junction, and the third end of the magnetic tunnel junction is located at the top electrode of the magnetic tunnel junction.

[0007] As an embodiment of the present invention, when the carbon-based MRAM storage cell performs a Boolean logic operation, the first logical operand in the Boolean logic operation is mapped to the voltage combination of the write bit line and the inverted write bit line, the second logical operand is mapped to the voltage combination of the left write word line and the right write word line, and the operation result in the Boolean logic operation is stored in the resistance state of the magnetic tunnel junction.

[0008] As an embodiment of the present invention, the above magnetic tunnel junction is a spin-orbit torque magnetic tunnel junction.

[0009] As an embodiment of the present invention, the above spin-orbit torque magnetic tunnel junction includes a free layer, an insulating layer, and a fixed layer stacked in sequence. The free layer is close to the bottom electrode, and the fixed layer is close to the top electrode.

[0010] As an embodiment of the present invention, the above first carbon-based transistor, the second carbon-based transistor, and the third carbon-based transistor are PMOS or NMOS.

[0011] According to a second aspect of the present invention, a carbon-based MRAM computing matrix is provided, including: a plurality of the above-mentioned carbon-based MRAM storage cells. The plurality of carbon-based MRAM storage cells are arranged in an m×n matrix form, where m and n are both integers greater than or equal to 1. In the matrix, the read word line, the left write word line, and the right write word line are all connected by columns, and the write bit line, the inverted write bit line, the source line, and the read bit line are all connected by rows.

[0012] According to a third aspect of the present invention, there is provided a working method for a carbon-based MRAM storage cell as described above, the method comprising: setting the read word line and the read bit line to be both disabled, and setting the source line to 0 V; setting the voltage combinations of the write bit line and the inverted write bit line, and the voltage combinations of the left write word line and the right write word line according to the type of Boolean logic operation to be performed; changing the resistance state of the magnetic tunnel junction according to the set voltage combinations; enabling the read word line and the read bit line; and obtaining the corresponding Boolean logic operation result by reading the output signal of the third carbon-based transistor.

[0013] As an embodiment of the present invention, the above-mentioned type of Boolean logic operation includes at least one of AND, OR, XOR, IMP, NAND, NOR, XNOR, and NIMP.

[0014] As an embodiment of the present invention, in the above working method, setting the voltage combinations of the write bit line and the inverted write bit line, and the voltage combinations of the left write word line and the right write word line according to the type of Boolean logic operation to be performed includes: setting the voltage combinations of the write bit line and the inverted write bit line, and the voltage combinations of the left write word line and the right write word line according to the preset voltage mapping table according to the type of Boolean logic operation to be performed.

[0015] As an embodiment of the present invention, the above working method further includes: before performing the logic operation, initializing the magnetic tunnel junction to ensure the accuracy of the operation result.

[0016] For the carbon-based MRAM storage cell, the memory and computing array, and their working methods provided by the present invention, both inputs are mapped to word line and bit line voltages, and logical operations are completed by writing different resistance states to the storage cell. Therefore, there is no requirement for the TMR value of the storage cell. In addition, the present application reconstructs the structure of the MRAM storage cell using a 3T1M cell, which can implement full-array Boolean logic operations, and the operation results are stored back in the storage cell, without the need for additional storage space and peripheral circuits, further simplifying the circuit design. Finally, since both inputs are mapped to word line and bit line voltages, the entire memory and computing array can be activated, greatly increasing the throughput of the operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0018] Figure 1It is a schematic structural diagram of a carbon-based MRAM storage cell provided by an embodiment of the present application;

[0019] Figure 2 It is a mapping diagram of AND operation and a calculation result diagram provided by an embodiment of the present application;

[0020] Figure 3 It is a mapping diagram of OR operation and a calculation result diagram provided by an embodiment of the present application;

[0021] Figure 4 It is a mapping diagram of XOR operation and a calculation result diagram provided by an embodiment of the present application;

[0022] Figure 5 It is a mapping diagram of IMP operation and a calculation result diagram provided by an embodiment of the present application;

[0023] Figure 6 It is a mapping diagram of NAND operation and a calculation result diagram provided by an embodiment of the present application;

[0024] Figure 7 It is a mapping diagram of NOR operation and a calculation result diagram provided by an embodiment of the present application;

[0025] Figure 8 It is a mapping diagram of NXOR operation and a calculation result diagram provided by an embodiment of the present application;

[0026] Figure 9 It is a mapping diagram of NIMP operation and a calculation result diagram provided by an embodiment of the present application;

[0027] Figure 10 It is a schematic structural diagram of a carbon-based MRAM memory and computing matrix provided by an embodiment of the present application;

[0028] Figure 11 It is a schematic flowchart of a working method of a carbon-based MRAM storage cell provided by an embodiment of the present application. Detailed implementation manners

[0029] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer and more understandable, the following further describes the embodiments of the present invention in detail with reference to the accompanying drawings. Herein, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but do not limit the present invention.

[0030] As shown in the present application and the claims, unless the context clearly indicates an exceptional situation, words such as "a", "an", "one" and / or "the" are not specifically singular, but may also include plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements.

[0031] Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for the sake of convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationships. Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be regarded as part of the authorization specification. In all the examples shown and discussed here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0032] In the description of the present application, it should be understood that the orientation or positional relationships indicated by orientation words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal", and "top, bottom" are generally based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present application and simplifying the description. Without contrary description, these orientation words do not indicate and imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of the present application; the orientation words "inside, outside" refer to the inside and outside relative to the contour of each component itself.

[0033] For the convenience of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above" can be used here to describe the spatial positional relationships of one device or feature to other devices or features as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device depicted in the figures. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations should be made for the spatial relative descriptions used here.

[0034] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is merely for the convenience of differentiating the corresponding components. Without additional declaration, the above terms have no special meaning, and thus should not be construed as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of this application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand this application not only through the actual terms used, but also through the meanings implied by each term.

[0035] It should be understood that when a component is referred to as "on another component", "connected to another component", "coupled to another component" or "in contact with another component", it can be directly on, connected to or coupled to, or in contact with that other component, or there may be an intervening component. In contrast, when a component is referred to as "directly on another component", "directly connected to", "directly coupled to" or "directly in contact with" another component, there is no intervening component. Similarly, when a first component is referred to as "electrically contacting" or "electrically coupled to" a second component, there is an electrical path allowing current flow between the first component and the second component. The electrical path may include capacitors, coupled inductors, and / or other components allowing current flow, even if there is no direct contact between the conductive components.

[0036] As Figure 1 shown is a schematic structural diagram of a carbon-based MRAM storage cell provided by an embodiment of this application. The carbon-based MRAM storage cell of this embodiment has a 3T1M structure, that is, it consists of 3 carbon-based transistors and a magnetic tunnel junction.

[0037] It can be seen from Figure 1 that the carbon-based MRAM storage cell includes a first carbon-based transistor M1, a second carbon-based transistor M2, a third carbon-based transistor M3, and a magnetic tunnel junction MTJ1. Among them:

[0038] The gate of the first carbon-based transistor M1 is connected to the left write word line WWL, the first end is connected to the write bit line WBL, and the second end is connected to the T1 end of the magnetic tunnel junction MTJ1. Depending on the direction of current flow, the first end of the first carbon-based transistor M1 here can be either the drain or the source, and similarly the second end can also be either the drain or the source. The descriptions of the first end and the second end of the subsequent carbon-based transistors are the same as those of the first carbon-based transistor M1.

[0039] The gate of the second carbon-based transistor M2 is connected to the right write word line WWR, the first end is connected to the inverted write bit line WBLB, and the second end is connected to the T1 end of the magnetic tunnel junction MTJ1.

[0040] The gate of the third carbon-based transistor M3 is connected to the read word line RWL, the first end is connected to the T3 end of the magnetic tunnel junction MTJ1, and the second end is connected to the read bit line RBL;

[0041] The T2 end of the magnetic tunnel junction MTJ1 is connected to the source line SL, and the T1 end and the T2 end of the magnetic tunnel junction MTJ1 are located at the bottom electrode of the magnetic tunnel junction MTJ1, and the T3 end is located at the top electrode of the magnetic tunnel junction MTJ1.

[0042] The first carbon-based transistor M1 and the second carbon-based transistor M2 are mainly responsible for writing data. They are respectively connected to the left write word line WWL and the right write word line WWR, as well as the write bit line WBL and the inverted write bit line WBLB. In this embodiment, by controlling the voltage combination of these write word lines and write bit lines, the current flow direction in the MTJ can be controlled, thereby changing the resistance state of the MTJ, so that it is in a high resistance (R H ), and low resistance (R L ), where R H represents 1, and R L represents 0.

[0043] The third carbon-based transistor M3 is responsible for reading data. It is connected to the read word line RWL, the read bit line RBL, and the top electrode of the magnetic tunnel junction MTJ1. When the read word line RWL is enabled, current will flow through the magnetic tunnel junction MTJ1. According to the resistance state of the magnetic tunnel junction MTJ1, different voltage outputs will be generated to the read bit line RBL, thereby reading "0" or "1". It acts as a sense amplifier, converting the weak resistance change of the magnetic tunnel junction MTJ1 into a measurable voltage signal. Therefore, this application does not require an additional sensitive amplifier.

[0044] Preferably, the above-mentioned first carbon-based transistor M1, second carbon-based transistor M2, and third carbon-based transistor M3 can be gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs).

[0045] Preferably, the resistance state of the magnetic tunnel junction MTJ1 represents the stored "0" or "1". The write operation changes the resistance state of the magnetic tunnel junction MTJ1, and the read operation reads the resistance state of the MTJ. The resistance state of the magnetic tunnel junction MTJ1 is controlled by the write voltage and represents the result of the Boolean logic operation.

[0046] Preferably, in the present application, the mapping of two inputs in Boolean logic operations can be achieved through the voltage combinations of the left write word line WWL and the right write word line WWR, as well as the write bit line WBL and the inverted write bit line WBLB. Specifically, the first logical operand in Boolean logic is mapped to the voltage combination of the write bit line WBL and the inverted write bit line WBLB, and the second logical operand is mapped to the voltage combination of the left write word line WWL and the right write word line WWR. The operation result can be stored in the resistance state of the magnetic tunnel junction MTJ1.

[0047] Preferably, the above-mentioned magnetic tunnel junction MTJ1 is a spin-orbit torque magnetic tunnel junction (SOT-MTJ). In traditional MTJs, the magnetization direction needs to be changed by the magnetic field of the current, while SOT-MTJs use spin-orbit torque to control the switching of the magnetization direction. This means that the write operation no longer depends solely on the magnitude of the current, but also on the magnitude and direction of the spin-orbit torque. In addition, the write mechanism of SOT-MTJs is generally more energy-efficient than that of traditional MTJs because its write process does not rely on a large current, but only on a relatively small current to generate spin-orbit torque, which makes the 3T1M cell have lower power consumption.

[0048] More preferably, the above-mentioned spin-orbit torque magnetic tunnel junction includes a free layer, an insulating layer, and a fixed layer stacked in sequence, where the free layer is close to the bottom electrode and the fixed layer is close to the top electrode. This stacking order means that the current used to generate spin-orbit torque will first pass through the free layer, and then through the insulating layer to reach the fixed layer. The current will generate spin-orbit torque in the free layer, thereby changing the magnetization direction of the free layer and realizing the write operation. The read operation is achieved by measuring the tunneling magnetoresistance effect between the free layer and the fixed layer.

[0049] Preferably, the above-mentioned first carbon-based transistor M1, second carbon-based transistor M2, and third carbon-based transistor M3 are P-type metal-oxide-semiconductor field-effect transistors (PMOS) or N-type metal-oxide-semiconductor field-effect transistors (NMOS), that is, the first carbon-based transistor M1, second carbon-based transistor M2, and third carbon-based transistor M3 can all be PMOS or NMOS, or both can be used in combination.

[0050] Consisting of Figure 1 The carbon-based MRAM storage cell with the structure can achieve full-array Boolean logic operations, including AND / NAND, OR / NOR, IMP / NIMP, and XOR / XNOR. Each Boolean logic operation will be described separately below. As shown here Figure 1 It is assumed that the SOT current generated in the storage cell writes high resistance R from left to right H (1), where 1 in the parentheses represents logical 1. Conversely, the SOT current writes low resistance R from right to leftL (0), where 0 in the parentheses represents logical 0.

[0051] (1) AND operation

[0052] As Figure 2 shown in the AND operation mapping and calculation result diagram provided by the embodiment of the present application, when performing the AND logical operation, both the read word line RWL and the read bit line RBL are not enabled, and the source line SL is set to 0 V. The read word line RWL and the read bit line RBL play a role in the read operation. During the logical operation, data does not need to be read, so these two lines are disabled to avoid interfering with the write operation. The source line SL is connected to the bottom electrode T2 terminal of the magnetic tunnel junction. Setting the source line SL to 0 V is to control the direction of the SOT (spin-orbit torque), which is a specific condition for the AND operation, ensuring that the SOT current can correctly change the state of the MTJ to reflect the result of the AND operation, which will be described later.

[0053] As Figure 2 shown in the AND operation value mapping table, the operand 1 (Operant 1, O1) is represented by the voltages of the write bit line WBL and the inverted write bit line WBLB. When WBL / WBLB = (-1V, -1V), it means O1 = 0; when WBL / WBLB = (-1V, 1V), it means O1 = 1. Similarly, the operand 2 (Operant 2, O2) is represented by the voltages of the left write word line WWL and the right write word line WWR. When WWL / WWR = (0V, 1V), it means O2 = 0; when WWL / WWR = (1V, 0V), it means O2 = 1.

[0054] When different combinations of O1 and O2 are input, the AND operation results as shown on the right can be obtained. For example, when O1 = 0 and O2 = 1, the first carbon-based transistor M1 is turned off, while the second carbon-based transistor M2 is turned on. At this time, the inverted write bit line WBLB is -1 V. Since SL is 0 V, a SOT current from right to left will be generated to flip the magnetic tunnel junction MTJ1 to R Figure 2 L . When both O1 and O2 are 1, the magnetic tunnel junction MTJ1 is written as R H . In summary, the AND operation is completed within the storage cell.

[0055] (2) OR operation

[0056] Figure 3 As Figure 3 shown in the OR operation mapping and calculation result diagram provided by the embodiment of the present application, when performing the OR logical operation, both the read word line RWL and the read bit line RBL are not enabled, and SL is set to 0 V.

[0057] As Figure 3As shown in the OR operation value mapping table, the operand 1 (Operant 1, O1) is represented by the voltages of the write bit line WBL and the inverted write bit line WBLB. When WBL / WBLB = (-1V, 1V), it indicates that O1 = 0; when WBL / WBLB = (1V, 1V), it indicates that O1 = 1. Similarly, the operand 2 (Operant 2, O2) is represented by the voltages of the left write word line WWL and the right write word line WWR. When WWL / WWR = (0V, 1V), it indicates that O2 = 0; when WWL / WWR = (1V, 0V), it indicates that O2 = 1.

[0058] After inputting different combinations of O1 and O2, the OR operation results as shown on the right side of Figure 3 can be obtained. For example, when O1 = 0 and O2 = 1, the first carbon-based transistor M1 is turned off, while the second carbon-based transistor M2 is turned on. At this time, the inverted write bit line WBLB is 1 V. Since SL is 0 V, a SOT current from left to right will be generated to flip the magnetic tunnel junction MTJ1 to R H . The magnetic tunnel junction MTJ1 is written as R only when both O1 and O2 are 0 L . In summary, the OR operation is completed within the storage cell.

[0059] (3)XOR operation

[0060] As Figure 4 shown in the XOR operation mapping and calculation result diagram provided by the embodiment of the present application, when performing the XOR logic operation, both the read word line RWL and the read bit line RBL are not enabled, and SL is set to 0 V.

[0061] As Figure 4 shown in the XOR operation value mapping table, the operand 1 (Operant 1, O1) is represented by the voltages of the write bit line WBL and the inverted write bit line WBLB. When WBL / WBLB = (-1V, 1V), it indicates that O1 = 0; when WBL / WBLB = (1V, -1V), it indicates that O1 = 1. Similarly, the operand 2 (Operant 2, O2) is represented by the voltages of the left write word line WWL and the right write word line WWR. When WWL / WWR = (0V, 1V), it indicates that O2 = 0; when WWL / WWR = (1V, 0V), it indicates that O2 = 1.

[0062] After inputting different combinations of O1 and O2, the XOR operation results as shown on the right side of Figure 4 can be obtained. For example, when O1 = 0 and O2 = 1, the first carbon-based transistor M1 is turned off, while the second carbon-based transistor M2 is turned on. At this time, the inverted write bit line WBLB is 1 V. Since SL is 0 V, a SOT current from left to right will be generated to flip the magnetic tunnel junction MTJ1 to R HThe magnetic tunnel junction MTJ1 is written as R only when O1 is the same as O2. L In summary, the exclusive - OR operation is completed within the storage cell.

[0063] (4)IMP operation

[0064] As Figure 5 shown in the IMP operation mapping and calculation result diagram provided by the embodiment of the present application, when performing the IMP logical operation, both the read word line RWL and the read bit line RBL are not enabled, and SL is set to 0 V.

[0065] As Figure 5 shown in the operand value mapping table of the IMP operation, the operand 1 (Operant 1, O1) is represented by the voltages of the write bit line WBL and the inverted write bit line WBLB. When WBL / WBLB = (-1V, -1V), it means O1 = 0; when WBL / WBLB = (1V, -1V), it means O1 = 1. Similarly, the operand 2 (Operant 2, O2) is represented by the voltages of the left write word line WWL and the right write word line WWR. When WWL / WWR = (0V, 1V), it means O2 = 0; when WWL / WWR = (1V, 0V), it means O2 = 1.

[0066] After inputting different combinations of O1 and O2, the IMP operation results on the right side as shown in Figure 5 can be obtained. For example, when O1 = 0 and O2 = 0, the first carbon - based transistor M1 is turned on, while the second carbon - based transistor M2 is turned off, and at this time the write bit line WBL is -1V. Since SL is 0 V, an SOT current from right to left will be generated to flip the magnetic tunnel junction MTJ1 to R. L The magnetic tunnel junction MTJ1 is written as R only when O1 = 1 and O2 = 0. H In summary, the IMP logical operation is completed within the storage cell.

[0067] The above introduces the AND, OR, XOR, and IMP logical operations completed using the storage cell of the present application. For NAND, NOR, XNOR, and NIMP, only by changing the operand encoding method, they can also be easily implemented. Specifically, reference can be made to the encoding methods shown in Figure 6 、 Figure 7 、 Figure 8 and Figure 9 . For the specific working methods of Figures 6 - 9 , no further elaboration will be given here.

[0068] As described above, for the carbon-based MRAM storage cell provided by the present invention, both inputs are mapped to word line and bit line voltages, and logical operations are completed by writing different resistance states to the storage cell. Therefore, there is no requirement for the TMR value of the storage cell. In addition, the present application reconstructs the structure of the MRAM storage cell by using a 3T1M cell, which can implement full-array Boolean logic operations, and the operation results are stored back in the storage cell without the need for additional storage space and peripheral circuits, further simplifying the circuit design.

[0069] As Figure 10 shown in the structural schematic diagram of a carbon-based MRAM arithmetic storage matrix provided by an embodiment of the present application. It can be seen from Figure 10 that the carbon-based MRAM arithmetic storage matrix includes multiple carbon-based MRAM storage cells as Figure 1 shown. The multiple carbon-based MRAM storage cells are arranged in an m×n matrix form, where both m and n are integers greater than or equal to 1. Figure 10 Here, an n×n matrix is taken as an example for illustration.

[0070] In this arithmetic storage matrix, the read word line RWL, the left write word line WWL, and the right write word line WWR are all connected by columns, and the write bit line WBL, the inverted write bit line WBLB, the source line SL, and the read bit line RBL are all connected by rows. That is, in each row of this m×n matrix, the RWL, WWL, and WWR of the storage cells in each column are respectively connected together; while in each column of this m×n matrix, the WBL, WBLB, SL, and RBL of the storage cells in each row are respectively connected together.

[0071] As described above, in this arithmetic storage matrix, the input signal is mapped through the word line and bit line voltages. When two inputs are mapped to the word line and bit line voltages, all the storage cells in the entire array can be activated simultaneously. This design allows read and write operations to be performed on the entire array at the same time. Therefore, this parallel processing ability significantly improves the throughput of the operation. Compared with the traditional method where only two rows of data in the array can be accessed at a time, this method can complete more operations in a shorter time, thereby improving the overall computing efficiency. That is, the carbon-based MRAM arithmetic storage matrix provided by the embodiment of the present application has the advantage of high throughput in addition to the advantages of the carbon-based MRAM storage cell mentioned above.

[0072] As Figure 11 shown in the flowchart of the working method of a carbon-based MRAM storage cell provided by an embodiment of the present application. This method is based on the storage cell corresponding to Figure 1 and includes the following steps:

[0073] Step S110: Set the read word line RWL and the read bit line RBL to be both disabled, and set the source line SL to 0 V.

[0074] Set the read word line RWL and the read bit line RBL to be both disabled. This step disables the read operation to ensure that no accidental read occurs during the process of writing the inputs of the logical operation and performing the operation, interfering with the operation result.

[0075] Set the source line SL to 0 V because in this embodiment, the voltage of the source line SL controls the direction of the SOT current. The setting of 0 V prepares for the subsequent write operation. It determines the flow direction of the SOT current, thereby affecting the change in the resistance state of the magnetic tunnel junction MTJ1, and ultimately determining whether the result of the logical operation is 0 or 1.

[0076] Step S111: According to the type of Boolean logical operation to be performed, set the voltage combinations of the write bit line WBL and the inverted write bit line WBLB, as well as the voltage combinations of the left write word line WWL and the right write word line WWR.

[0077] Different Boolean logical operations (AND, OR, XOR, IMP, etc.) require different voltage combinations. The voltage combination of WBL and WBLB represents the first operand, and the voltage combination of WWL and WWR represents the second operand. These voltage combinations control the conduction states of the first carbon-based transistor M1 and the second carbon-based transistor M2, and further control the direction and magnitude of the SOT current, ultimately affecting the resistance state of the magnetic tunnel junction MTJ1.

[0078] Step S112: Change the resistance state of the magnetic tunnel junction according to the set voltage combinations.

[0079] This is the execution stage of the logical operation. The voltage combinations set in step S111 will generate a specific SOT current, which will change the resistance state (high resistance or low resistance) of the magnetic tunnel junction MTJ1. High resistance and low resistance represent the logical values "1" and "0" respectively. This change in the resistance state represents the result of the Boolean logical operation.

[0080] Step S113: Enable the read word line RWL and the read bit line RBL.

[0081] This step enables the read operation to prepare for reading the operation result.

[0082] Step S114: Obtain the corresponding Boolean logical operation result by reading the output signal of the third carbon-based transistor.

[0083] The output signal of the third carbon-based transistor reflects the resistance state (high resistance or low resistance) of the magnetic tunnel junction MTJ1, so that the result of the logical operation can be obtained.

[0084] Preferably, the above-mentioned Boolean logic operation types include at least one of AND, OR, XOR, IMP, NAND, NOR, XNOR, and NIMP.

[0085] Preferably, in the above step S111, according to the type of Boolean logic operation to be performed, setting the voltage combinations of the write bit line WBL and the inverted write bit line WBLB, and the voltage combinations of the left write word line WWL and the right write word line WWR includes: according to the type of Boolean logic operation to be performed, setting the voltage combinations of the write bit line WBL and the inverted write bit line WBLB, and the voltage combinations of the left write word line WWL and the right write word line WWR according to a preset voltage mapping table.

[0086] Preferably, before performing the logic operation in the embodiment of the present application, an initialization operation is performed on the magnetic tunnel junction to ensure the accuracy of the operation result. Here, the initialization operation refers to switching the resistance states of the magnetic tunnel junctions in all storage units to a known state, such as switching to a high-resistance or low-resistance state simultaneously.

[0087] As can be seen from the above, in the working method of the carbon-based MRAM storage unit provided by the present invention, both inputs are mapped to word line and bit line voltages, and the logic operation is completed by writing different resistance states to the storage unit. Therefore, there is no requirement for the TMR value of the storage unit. In addition, the present application reconstructs the structure of the MRAM storage unit using 3T1M cells, which can implement full-array Boolean logic operations, and the operation results are stored back in the storage unit without the need for additional storage space and peripheral circuits, further simplifying the circuit design. Finally, since both inputs are mapped to word line and bit line voltages, the entire memory and computing array can be activated, greatly increasing the operation throughput.

[0088] In the present invention, specific embodiments are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A carbon-based MRAM storage cell, characterized in that: The carbon-based MRAM storage cell includes: a first carbon-based transistor, a second carbon-based transistor, a third carbon-based transistor and a magnetic tunnel junction; The gate of the first carbon-based transistor is connected to the left write word line, the first end is connected to the write bit line, and the second end is connected to the first end of the magnetic tunnel junction; The gate of the second carbon-based transistor is connected to the right write word line, the first end is connected to the inverted write bit line, and the second end is connected to the first end of the magnetic tunnel junction; The gate of the third carbon-based transistor is connected to the read word line, the first end is connected to the third end of the magnetic tunnel junction, and the second end is connected to the read bit line; The second end of the magnetic tunnel junction is connected to the source line, the first end and the second end of the magnetic tunnel junction are located at the bottom electrode of the magnetic tunnel junction, and the third end of the magnetic tunnel junction is located at the top electrode of the magnetic tunnel junction.

2. The carbon-based MRAM storage cell according to claim 1, characterized in that: When the carbon-based MRAM storage unit performs a Boolean logic operation, a first logic operand in the Boolean logic operation is mapped to a voltage combination of the write bit line and the inverted write bit line, a second logic operand is mapped to a voltage combination of the left write word line and the right write word line, and a result of the Boolean logic operation is stored in the resistance state of the magnetic tunnel junction.

3. The carbon-based MRAM storage cell according to claim 1, characterized in that: The magnetic tunnel junction is a spin-orbit moment magnetic tunnel junction.

4. The carbon-based MRAM storage cell according to claim 3, characterized in that: The spin-orbit moment magnetic tunnel junction comprises a free layer, an insulating layer and a fixed layer stacked in sequence, the free layer is close to the bottom electrode, and the fixed layer is close to the top electrode.

5. The carbon-based MRAM storage cell according to claim 1, wherein: The first carbon-based transistor, the second carbon-based transistor and the third carbon-based transistor are PMOS or NMOS.

6. A carbon-based MRAM storage and computing matrix, characterized in that: The carbon-based MRAM storage-computing matrix comprises: a plurality of carbon-based MRAM storage cells according to any one of claims 1 to 5, wherein the plurality of carbon-based MRAM storage cells are arranged in an m×n matrix, where m and n are both integers greater than or equal to 1; in the matrix, a read word line, a left write word line, and a right write word line are all connected in columns, and a write bit line, an inverted write bit line, a source line, and a read bit line are all connected in rows.

7. A method for operating a carbon-based MRAM storage cell according to any one of claims 1 to 5, characterized in that: The method comprises: Set the read word line and read bit line to be disabled, and set the source line to 0 V; According to the type of Boolean logic operation to be performed, setting the voltage combination of the write bit line and the inverted write bit line, and the voltage combination of the left write word line and the right write word line; The resistance state of the magnetic tunnel junction is changed according to a set voltage combination; enabling the read word line and the read bit line; By reading the output signal of the third carbon-based transistor, the corresponding Boolean logic operation result is obtained.

8. The operating method of the carbon-based MRAM storage cell according to claim 7, characterized in that: The Boolean logic operation type includes at least one of AND, OR, XOR, IMP, NAND, NOR, XNOR, and NIMP.

9. The method for operating a carbon-based MRAM storage cell according to claim 7, wherein: The voltage combination of the write bit line and the inverted write bit line, and the voltage combination of the left write word line and the right write word line are set according to the type of Boolean logic operation to be performed, including: According to the type of Boolean logic operation to be performed, the voltage combination of the write bit line and the inverted write bit line, and the voltage combination of the left write word line and the right write word line are set according to a preset voltage mapping table.

10. The operating method of the carbon-based MRAM storage cell according to claim 7, characterized in that: The method further includes: before performing the logic operation, performing an initialization operation on the magnetic tunnel junction to ensure the accuracy of the operation result.

Images