Operation method of memory array and memory

Abstract

The invention provides an operation method of a storage array, the storage array comprises a plurality of storage units, each storage unit comprises a FeFET, the storage units in the same row share the same word line, and the storage units in the same column share the same source line, bit line and substrate line. The method comprises the following steps: applying a first programming voltage on a word line of a first target row, applying a first bias voltage on a source line and a bit line of a first target column, and placing a substrate line of the first target column at a floating potential so as to perform write operation on a first target storage unit; a turn-off voltage is applied to a word line of a second target row, a first bias voltage is applied to a substrate line of a second target column, and a source line and a bit line of the second target column are placed at a floating potential. According to the operation method provided by the invention, the write crosstalk of the FeFET device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and particularly to an operation method for a memory array and a memory. Background Art

[0002] A memory is a device for storing information. Usually, information is digitized and then stored using media such as electricity, magnetism, or optics. Ferroelectric memories mainly include ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memories. FeFET can achieve non-volatile storage characteristics in a single transistor cell, and has advantages such as high density, high speed, low power consumption, and compatibility with complementary metal-oxide-semiconductor (CMOS) processes.

[0003] The FeFET-based memory architecture has great potential in the field of embedded memories. However, when performing a write operation on FeEFTs in a memory array, other unselected devices on the same word line (WL) will be subject to a relatively serious write disturb effect. Therefore, there is an urgent need to design an operation method to reduce the write disturb of FeFET devices. Summary of the Invention

[0004] This application provides an operation method for a memory array and a memory, which can reduce the write disturb of FeFET devices.

[0005] In a first aspect, an operation method for a memory array is provided. The memory array includes a plurality of memory cells, each memory cell including a FeFET. Memory cells in the same row share the same word line, and memory cells in the same column share the same source line, the same bit line, and the same substrate line. The method includes: applying a first programming voltage to the word line of a first target row, applying a first bias voltage to the source line and the bit line of a first target column, and placing the substrate line of the first target column at a floating (FLT) potential to perform a write operation on a first target memory cell located at the first target row and the first target column, where the difference between the first bias voltage and a 0-volt voltage is less than a preset threshold; applying a turn-off voltage to the word line of a second target row to turn off the FeFETs of the memory cells in the second target row, applying the first bias voltage to the substrate line of the second target column, and placing the source line and the bit line of the second target column at a floating potential, where the second target row includes the remaining rows in the memory array other than the first target row, and the second target column includes the remaining columns in the memory array other than the first target column.

[0006] The present application provides an operation method for a memory array, which can make the selected memory cell in a first state, and the remaining unselected memory cells in the same row as the selected memory cell in a second state. Since the voltage on the ferroelectric layer of the FeFET in the second state is much smaller than the voltage on the ferroelectric layer of the FeFET in the first state, the write crosstalk of the FeFET device can be reduced.

[0007] The first target memory cell is the memory cell selected for the write operation. The FeFET includes a source (S), a gate (G), a drain (D), and a substrate (B). The gate includes a metal gate electrode, a ferroelectric layer, and a gate oxide layer. S and D are located above B. By applying a voltage to G, a channel can be formed between S and D.

[0008] In the present application, it is defined that the FeFET of the first target memory cell for the write operation is in a first state, that is, the voltage applied to the word line of the row where the first target memory cell is located is the first programming voltage, the voltage applied to the source line and the bit line of the column where the first target memory cell is located is the first bias voltage, and the substrate line of the column is placed at a floating potential. When the FeFET is in the first state, the electric potential points from the gate to the source and the drain, the channel does not participate in voltage division, and the voltage mainly falls on the gate. At this time, the voltage on the ferroelectric layer of the FeFET is relatively large, and polarization inversion can occur to complete state writing.

[0009] In this application, the remaining memory cells located in the same row as the first target memory cell are defined to be in the second state, that is, the voltage applied to the word line of the row where the remaining memory cells in the same row are located is the first programming voltage, the voltage applied to the substrate line of the column where they are located is the first bias voltage, and the source line and bit line of the column where they are located are placed at a floating potential. When the FeFET is in the second state, the electric potential points from the gate to the substrate, the channel is in the depletion region, and the depletion layer capacitance will share most of the voltage. At this time, the voltage on the ferroelectric layer is very small, about 1 / 10 of that in the first state, and polarization inversion will not occur. Therefore, the write crosstalk of the FeFET device can be reduced.

[0010] It should be understood that the FeFET included in each memory cell can be an N-type FeFET device or a P-type FeFET device. When the FeFET is an N-type FeFET device, the first programming voltage is a positive programming voltage, and 0 is written into the first target memory cell; when the FeFET is a P-type FeFET device, the first programming voltage is a negative programming voltage, and 1 is written into the first target memory cell.

[0011] The turn-off voltage and the first bias voltage are equal to or close to 0V. In a possible implementation, both the turn-off voltage and the first bias voltage are equal to 0V. At this time, the remaining unselected memory cells in the memory array other than the first target memory cell do not undergo polarization inversion because the WL voltage of the row where they are located is 0V. At the same time, the remaining unselected memory cells located in the same row as the selected first target memory cell are in the second state. Therefore, the voltage of the ferroelectric layer is very small and polarization inversion will not occur. Through the operation method provided in this application, the write crosstalk is effectively suppressed.

[0012] Combined with the first aspect, in some implementations of the first aspect, before applying the first programming voltage to the word line of the first target row, the method further includes: applying the first bias voltage to all the source lines, bit lines and substrate lines in the memory array, and applying a second programming voltage to all the word lines in the memory array, and the second programming voltage has the opposite polarity to the first programming voltage.

[0013] When the FeFET is an N-type FeFET device, the second programming voltage is a negative programming voltage, and 1 is written into the first target memory cell; when the FeFET is a P-type FeFET device, the first programming voltage is a positive programming voltage, and 0 is written into the first target memory cell.

[0014] When the FeFET is an N-type FeFET device, when performing a write "1" operation on a selected storage cell, first perform the same operation on the entire storage array, that is, connect all source lines (SL), bit lines (BL), and bulk lines (BuL) in the storage array to a first bias voltage, such as 0V, and connect all word lines (WL) to a negative programming voltage -V PGM , perform a write "1" operation on the storage cells in the entire storage array, and then perform the above write "0" operation on the unselected storage cells in the storage array. At this time, the unselected storage cells in the storage array can be regarded as the first target storage cells. It should be understood that the reason for performing two-step operations to write "1" to the selected storage cell is that for an N-type FeFET device, only by applying a positive programming voltage to the gate can the channel be in the depletion region, that is, the unselected storage cells in the same row as the selected storage cell are in the second state, reducing the write crosstalk of the FeFET device.

[0015] When the FeFET is a P-type FeFET device, when performing a write "0" operation on a selected storage cell, first perform the same operation on the entire storage array, that is, connect all SL, BL, and BuL in the storage array to a first bias voltage, such as 0V, and connect all WL to a positive programming voltage +V PGM , perform a write "0" operation on the storage cells in the entire storage array, and then perform the above write "1" operation on the unselected storage cells in the storage array. It should be understood that the reason for performing two-step operations to write "0" to the selected storage cell is that for a P-type FeFET device, only by applying a negative programming voltage to the gate can the channel be in the depletion region, that is, the unselected storage cells in the same row as the selected storage cell are in the second state, reducing the write crosstalk of the FeFET device.

[0016] The present application provides an operation method for a storage array, which considers different operations of writing 0 or 1 to a storage cell, and can make the selected storage cell in the first state, and the remaining unselected storage cells in the same row as the selected storage cell in the second state. Since the voltage on the ferroelectric layer of the FeFET in the second state is much smaller than the voltage on the ferroelectric layer of the FeFET in the first state, the write crosstalk of the FeFET device can be reduced.

[0017] In combination with the first aspect, in some implementation manners of the first aspect, when the FeFET is an N-type FeFET, the first programming voltage is positive, and the second programming voltage is negative; when the FeFET is a P-type FeFET, the first programming voltage is negative, and the second programming voltage is positive.

[0018] For an N-type FeFET device, only by applying a positive programming voltage to the gate can the channel be in the depletion region, that is, the unselected memory cells in the same row as the selected memory cell are in the second state, reducing the write crosstalk of the FeFET device. When the FeFET is an N-type FeFET, the first programming voltage is positive, and 0 is written into the first target memory cell; the second programming voltage is negative, and 1 is written into the first target memory cell.

[0019] For a P-type FeFET device, only by applying a negative programming voltage to the gate can the channel be in the depletion region, that is, the unselected memory cells in the same row as the selected memory cell are in the second state, reducing the write crosstalk of the FeFET device. When the FeFET is a P-type FeFET, the first programming voltage is negative, and 1 is written into the first target memory cell; the second programming voltage is positive, and 0 is written into the first target memory cell.

[0020] The present application provides an operation method for a memory array, which considers the situation of applying a programming voltage to the gate of different types of FeFETs and can reduce the write crosstalk of different types of FeFET devices.

[0021] Combined with the first aspect, in some implementation manners of the first aspect, the gates of the FeFETs in the same row share the same word line, the first poles of the FeFETs in the same column share the same source line, the second poles of the FeFETs in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line, where the first pole is the source and the second pole is the drain, or the first pole is the drain and the second pole is the source.

[0022] Exemplarily, the memory array includes M rows and N columns of memory cells, and each memory cell includes an FeFET. The gate of the FeFET in each memory cell is connected to WL, the source is connected to SL, the drain is connected to BL, and the substrate is connected to BuL. Among them, the gates of the FeFETs in the memory cells of the m-th row share a word line WLm, where 1 ≤ m ≤ M. The sources of the FeFETs in the memory cells of the n-th column share a source line SLn, the drains of the FeFETs in the memory cells of the n-th column share a bit line BLn, and the substrates of the memory cells in the n-th column share a substrate line BuLn, where 1 ≤ n ≤ N.

[0023] The present application provides an operation method for a memory array, which can perform a write operation on a 1T memory array including 4-port FeFETs, making the selected memory cell in the first state, and the remaining unselected memory cells in the same row as the selected memory cell in the second state. Since the voltage on the ferroelectric layer of the FeFET in the second state is much smaller than the voltage on the ferroelectric layer of the FeFET in the first state, the write crosstalk of the FeFET device can be reduced.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: applying a read voltage to the word line of the third target row, and applying a second bias voltage to the line connecting the drain of the FeFET in the third target column to read the value stored in the second target storage cell, where the second target storage cell is located in the third target row and the third target column.

[0025] Exemplarily, for an N-type FeFET, during a read operation, a read voltage V is applied to the WL of the row where the selected second target storage cell is located. read A positive second bias voltage +VDD is applied to the line connecting the drain of the FeFET of the second target storage cell. For example, the drain of the FeFET of the second target storage cell is connected to the BL of the third target column, that is, a positive second bias voltage +VDD is applied to the BL of the third target column. The line connecting the source of the FeFET in the third target column and the BuL of the third target column are connected to 0V; the WLs of the remaining unselected rows are connected to 0V, and the BLs, SLs, and BuLs of the remaining unselected columns are all connected to 0V.

[0026] For a P-type FeFET, during a read operation, a read voltage V is applied to the WL of the row where the selected second target storage cell is located. read A negative second bias voltage -VDD is applied to the line connecting the drain of the FeFET of the second target storage cell. For example, the drain of the FeFET of the second target storage cell is connected to the BL of the third target column, that is, a negative second bias voltage -VDD is applied to the BL of the third target column. The line connecting the source of the FeFET in the third target column and the BuL of the third target column are connected to 0V; the WLs of the remaining unselected rows are connected to 0V, and the BLs, SLs, and BuLs of the remaining unselected columns are all connected to 0V.

[0027] The current of the drain of the FeFET of the selected storage cell is read. If it is a high current, it represents that the read data is 1, and if it is a low current, it represents that the read data is 0. It should be understood that the high current can be a current higher than a preset threshold, and the low current can be a current lower than a preset threshold. In some possible application scenarios, the second bias voltage VDD can also be referred to as the operating voltage or the drain supply voltage.

[0028] The present application provides an operation method for a storage array, which can perform a read operation on a 1T storage array including 4-port FeFETs and reduce the read crosstalk of FeFET devices when the threshold voltage of the FeFET is positive.

[0029] In combination with the first aspect, in some implementations of the first aspect, each memory cell in the memory array further includes a logic transistor, the logic transistor is connected in series with the FeFET, the FeFETs of the memory cells in the same row share the same word line, and the logic transistors of the memory cells in the same row share the same selector word line (SWL). The method further includes: applying an enabling voltage to the word line selector line of the first target row to turn on the logic transistors of the memory cells in the first target row; applying the disabling voltage to the word line selector line of the second target row to turn off the logic transistors of the memory cells in the second target row.

[0030] Since each memory cell in the memory array includes an FeFET and a logic transistor, it can be referred to as a 2T (2 transistors, 2T) memory array.

[0031] Exemplarily, for an N-type FeFET, when performing a write "0" operation on a selected first target memory cell, a positive programming voltage +V is applied to the WL of the first target row PGM , the SWL of the first target row is connected to the enabling voltage +V UP , the SL and BL of the first target column are both connected to 0V, and the BuL of the first target column is placed at the FLT potential; the WL and SWL of the second target row are both connected to 0V, the SL and BL of the second target column are both placed at the FLT potential, and the BuL of the second target column is both connected to 0V. At this time, the FeFET of the selected first target memory cell is in the first state, so the ferroelectric layer can undergo polarization inversion to complete the state writing. Since the voltage of the WL of the memory cells on the second target row is 0V, the FeFETs do not undergo polarization inversion. The FeFETs of the remaining unselected memory cells on the same WL as the selected first target memory cell are in the second state, so the voltage of the ferroelectric layer is very small and no polarization inversion will occur.

[0032] Exemplarily, for an N-type FeFET, when performing a write "1" operation on a selected memory cell, first perform the same operation on the entire memory array, that is, connect all SLs, BLs, and BuLs in the memory array to 0V, and connect all SWLs to the enabling voltage +V UP , connect all WLs to the negative programming voltage -V PGM , perform a write "1" operation on the memory cells in the entire memory array, and then perform the above write "0" operation on the unselected memory cells in the memory array. It should be understood that the reason for performing two-step operations to write "1" to the selected memory cell is that for an N-type FeFET device, only by applying a positive programming voltage to the gate can the channel be in the depletion region, that is, the unselected memory cells in the same row as the selected memory cell are in the second state, reducing the write crosstalk of the FeFET device.

[0033] The present application provides an operation method for a storage array, which can perform a write operation on a 2T storage array including 4-port FeFETs, making the selected storage cells in a first state and the remaining unselected storage cells in the same row as the selected storage cells in a second state. Since the voltage on the ferroelectric layer of the FeFET in the second state is much smaller than the voltage on the ferroelectric layer of the FeFET in the first state, the write crosstalk of the FeFET device can be reduced.

[0034] In combination with the first aspect, in some implementation manners of the first aspect, the FeFET includes a first end and a second end, the logic transistor includes a third end and a fourth end, the second end of the FeFET is connected to the third end of the logic transistor, the gates of the FeFETs in the same row share the same word line, the first ends of the FeFETs in the same column share the same source line, the fourth ends of the logic transistors in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line.

[0035] The first end of the FeFET is the source and the second end is the drain, or the first end of the FeFET is the drain and the second end is the source.

[0036] The present application provides an operation method for a storage array, which can perform a write operation on a 2T storage array including 4-port FeFETs, making the selected storage cells in a first state and the remaining unselected storage cells in the same row as the selected storage cells in a second state. Since the voltage on the ferroelectric layer of the FeFET in the second state is much smaller than the voltage on the ferroelectric layer of the FeFET in the first state, the write crosstalk of the FeFET device can be reduced.

[0037] In combination with the first aspect, in some implementation manners of the first aspect, the method further includes: applying the turn-on voltage on the word line selection line of the fourth target row, and applying a second bias voltage on the line connecting the drain of the FeFET in the fourth target column to read the value stored in the third target storage cell, where the third target storage cell is located in the fourth target row and the fourth target column.

[0038] Exemplarily, the first end is the source and the second end is the drain. For an N-type FeFET, during a read operation, the SWL of the row where the selected storage cell is located is connected to the turn-on voltage +V UP , the WL is connected to 0V, the BL of the column where the selected storage cell is located is connected to the positive second bias voltage +VDD, the SL is connected to 0V, and the BuL is connected to 0V; the SWL and WL of the remaining unselected rows are both connected to 0V, and the BL, SL, and BuL of the remaining unselected columns are all connected to 0V.

[0039] Exemplarily, the first terminal is the source electrode and the second terminal is the drain electrode. For a P-type FeFET, during a read operation, the SWL of the row where the selected memory cell is located is connected to the turn-on voltage +V UP , the WL is connected to 0V, the BL of the column where the selected memory cell is located is connected to the negative second bias voltage -VDD, the SL is connected to 0V, and the BuL is connected to 0V; for the SWL and WL of the remaining unselected rows, both are connected to 0V, and for the BL, SL, and BuL of the remaining unselected columns, all are connected to 0V.

[0040] Read the current of the drain electrode of the FeFET of the selected memory cell. If it is a high current, it means the read data is 1, and if it is a low current, it means the read data is 0.

[0041] The present application provides an operation method for a memory array, which can perform a read operation on a 2T memory array including 4-port FeFETs, and reduce the read crosstalk of FeFET devices when the threshold voltage of the FeFET is positive or negative.

[0042] In a second aspect, a memory is provided, including: a memory array, the memory array includes a plurality of memory cells, each of the memory cells includes a FeFET, the memory cells located in the same row share the same word line, and the memory cells located in the same column share the same source line, the same bit line, and the same substrate line; a memory controller, configured to apply a first programming voltage to the word line of the first target row, apply a first bias voltage to the source line and the bit line of the first target column, and place the substrate line of the first target column at a floating potential to perform a write operation on the first target memory cell, the first target memory cell is located in the first target row and the first target column, and the difference between the first bias voltage and the 0-volt voltage is less than a preset threshold; and apply a turn-off voltage to the word line of the second target row to turn off the FeFET of the memory cells in the second target row, apply the first bias voltage to the substrate line of the second target column, and place the source line and the bit line of the second target column at a floating potential, the second target row includes the remaining rows in the memory array except the first target row, and the second target column includes the remaining columns in the memory array except the first target column.

[0043] In combination with the second aspect, in some implementation manners of the second aspect, the memory controller is further configured to apply the first bias voltage to all the source lines, bit lines, and substrate lines in the memory array, and apply a second programming voltage to all the word lines in the memory array, and the second programming voltage has a polarity opposite to that of the first programming voltage.

[0044] In combination with the second aspect, in some implementations of the second aspect, when the FeFET is an N-type FeFET, the first programming voltage is positive and the second programming voltage is negative; when the FeFET is a P-type FeFET, the first programming voltage is negative and the second programming voltage is positive.

[0045] In combination with the second aspect, in some implementations of the second aspect, the gates of the FeFETs in the same row share the same word line, the first poles of the FeFETs in the same column share the same source line, the second poles of the FeFETs in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line, where the first pole is the source and the second pole is the drain, or the first pole is the drain and the second pole is the source.

[0046] In combination with the second aspect, in some implementations of the second aspect, the memory controller is further configured to apply a read voltage to the word line of the third target row and apply a second bias voltage to the line connecting the drain of the FeFET in the third target column to read the value stored in the second target memory cell, where the second target memory cell is located in the third target row and the third target column.

[0047] In combination with the second aspect, in some implementations of the second aspect, each memory cell in the memory array further includes a logic transistor connected in series with the FeFET. The FeFETs of the memory cells in the same row share the same word line, and the logic transistors of the memory cells in the same row share the same word line selection line. The memory controller is further configured to: apply a turn-on voltage to the word line selection line of the first target row to turn on the logic transistors of the memory cells in the first target row; and apply the turn-off voltage to the word line selection line of the second target row to turn off the logic transistors of the memory cells in the second target row.

[0048] In combination with the second aspect, in some implementations of the second aspect, the FeFET includes a first end and a second end, the logic transistor includes a third end and a fourth end, the second end of the FeFET is connected to the third end of the logic transistor, the gates of the FeFETs in the same row share the same word line, the first ends of the FeFETs in the same column share the same source line, the fourth ends of the logic transistors in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line.

[0049] In combination with the second aspect, in some implementations of the second aspect, the storage controller is further configured to apply a second bias voltage to the line connecting the FeFET drain of the fourth target column to read the value stored in the third target storage cell, where the third target storage cell is located in the fourth target row and the fourth target column.

[0050] In a third aspect, an electronic device is provided, including a circuit board and a memory in the second aspect and any possible implementation of the second aspect. The memory is disposed on the circuit board and electrically connected to the circuit board. Description of the Drawings

[0051] Figure 1 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0052] Figure 2 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.

[0053] Figure 3 is a schematic structural diagram of a ferroelectric memory provided by an embodiment of the present application.

[0054] Figure 4 is a schematic structural diagram of a FeFET provided by an embodiment of the present application.

[0055] Figure 5 is a schematic structural diagram of a 4-port FeFET device provided by an embodiment of the present application.

[0056] Figure 6 is a schematic diagram of the first state and equivalent capacitance of an N-type FeFET provided by an embodiment of the present application.

[0057] Figure 7 is a schematic diagram of the second state and equivalent capacitance of an N-type FeFET provided by an embodiment of the present application.

[0058] Figure 8 is an exemplary flowchart of an operation method of a storage array provided by an embodiment of the present application.

[0059] Figure 9 is a schematic diagram of the architecture of a storage array provided by an embodiment of the present application.

[0060] Figure 10 is a schematic diagram of the architecture of another storage array provided by an embodiment of the present application.

[0061] Figure 11 is a schematic diagram of the first state and equivalent capacitance of a P-type FeFET provided by an embodiment of the present application.

[0062] Figure 12It is a schematic diagram of the second state and equivalent capacitance of a P-type FeFET provided by an embodiment of the present application. Detailed implementation manners

[0063] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0064] In the embodiments of the present application, words such as "exemplary" and "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0065] The business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions in the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0066] Reference to "one embodiment" or "some embodiments" etc. described in this specification means that specific features, structures or characteristics described in combination with the embodiment are included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "include", "comprise", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0067] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can mean: including the case where A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, at least one (item) of a, b, or c can mean: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0068] To facilitate the understanding of the embodiments of this application, some definitions involved in this application are briefly described first.

[0069] 1. Equivalent capacitance: It refers to the total equivalent capacitance value formed by combining multiple capacitors in a certain way when they are connected in a circuit. Equivalent capacitance is a simplified representation of the connection method of multiple capacitors, making circuit analysis more convenient.

[0070] 2. Ground (GND): GND refers to the ground pin, also known as the grounding pin. It is usually connected to the ground (ground potential) of the circuit as a reference potential point. The GND pin is used to provide the reference zero potential of the circuit to ensure the correct operation and reference of other signals in the circuit. In semiconductor memory cells, GND is usually used to connect to the ground of the circuit.

[0071] 3. Floating (FLT): It can also be called suspended or floating, etc. FLT usually represents the unselected state or the unwritten state of the memory cell. When the memory cell is in the unselected state, the FLT signal is applied to the relevant wires of the memory cell. The FLT signal is usually in a high-impedance state, that is, there is no clear voltage level or current flow, so that the memory cell maintains its original data state.

[0072] 4. Write disturb: The interference phenomenon that an unselected memory cell is affected because it shares the same word line (WL) with the selected memory cell. This unexpected voltage effect may cause the charge state in the memory cell of the unselected device to change, resulting in data instability or errors. Specifically, the memory cells in the unselected device may be wrongly written or overwritten, causing data damage or loss.

[0073] 5. NMOS Transistor: A field-effect transistor (FET) based on the N-type metal-oxide-semiconductor (NMOS) structure. The NMOS transistor consists of a P-type substrate and two N-type regions (source and drain). The working principle of the NMOS transistor is based on the control of the gate voltage. When a positive voltage is applied to the control gate, a channel is formed to connect the source and the drain, allowing current to pass through the NMOS transistor. At this time, the NMOS transistor is in the on state. Conversely, when a zero voltage or a negative voltage is applied to the control gate, the channel is cut off, and the current cannot pass through, and the NMOS transistor is in the off state.

[0074] 6. PMOS Transistor: A FET based on the P-type metal-oxide-semiconductor (PMOS) structure. The PMOS transistor consists of an N-type substrate and two P-type regions (source and drain). The working principle of the PMOS transistor is also based on the control of the gate voltage. When a negative voltage is applied to the control gate, a channel is formed to connect the source and the drain, allowing current to pass through the PMOS transistor. At this time, the PMOS transistor is in the on state. Conversely, when a positive voltage is applied to the control gate, the channel is cut off, and the current cannot pass through, and the PMOS transistor is in the off state.

[0075] 7. Carrier: A charged particle responsible for current transport in semiconductor materials. In semiconductors, there are mainly two types of carriers: electrons and holes.

[0076] 8. PN Junction: A structure formed by the direct contact of a P-type semiconductor and an N-type semiconductor. The majority carriers in the P-type semiconductor are holes (positive charges), and the majority carriers in the N-type semiconductor are electrons (negative charges). When the P-type semiconductor and the N-type semiconductor are connected by direct contact or short circuit, a PN junction is formed.

[0077] 9. Depletion Region: Also known as the depletion zone, blocking layer, or barrier region, it refers to a high-resistance region in the PN junction where the number of carriers is very small under the dual influence of drift motion and diffusion.

[0078] Memory is classified according to volatility into volatile memory and non-volatile memory. Volatile memory is usually used as memory or cache, while non-volatile memory is usually used as external storage. Volatile memory refers to the memory in which the stored information will disappear when the current or voltage is interrupted, such as common dynamic random access memory (DRAM), static random access memory (SRAM), etc. Non-volatile memory refers to the memory in which the stored information will not disappear when the current or voltage is interrupted, such as various types of read-only memory (ROM), flash memory, new memories such as magnetic random access memory (MRAM) or ferroelectric random access memory (FRAM), etc.

[0079] Ferroelectric memory mainly includes ferroelectric random access memory (FeRAM or FRAM) and ferroelectric field-effect transistor (FeFET) memory. As a new type of memory, ferroelectric memory has greatly improved performance such as power consumption and speed compared with traditional DRAM.

[0080] FeFET, such as the FeFET based on hafnium oxide (HfO2), can achieve non-volatile storage characteristics in a single transistor cell, and has advantages such as high density, high speed, low power consumption, and compatibility with CMOS process.

[0081] The negative-or (NOR) storage architecture based on FeFET has great potential in the field of embedded storage. However, when writing to the FeEFT in the storage array, other unselected devices on the same word line (WL) will be subject to relatively serious crosstalk effects. Therefore, designing a more suitable operation is of great significance for reducing the write crosstalk of FeFET devices.

[0082] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0083] The electronic device 100 includes a memory 110 and a circuit board (not shown in the figure). The memory 110 is disposed on the circuit board and electrically connected to the circuit board, and the circuit board may be a printed circuit board (PCB). The memory 110 includes at least one memory array 120 and a controller 130. Optionally, the electronic device 100 may further include other chips / stand-alone devices 140, and the other chips / stand-alone devices 140 may be a central processing unit (CPU), a power management chip, a communication chip, or the like.

[0084] Figure 2 It is a schematic structural diagram of another electronic device provided by an embodiment of the present application.

[0085] The electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or may also be a personal computer (PC), a server, a workstation, etc. The electronic device 200 includes a bus 205 and a system on chip (SoC) 210 connected to the bus 205. The SoC 210 can be used to process data, such as processing data of application programs, processing image data, and caching temporary data. In a possible implementation manner, the SoC 210 may include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and a first RAM 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (eflash), etc. The above AP 211, GPU 212, and first RAM 213 may be integrated in one die or may be separately provided in multiple dies. The electronic device 200 may further include a second RAM 220 connected to the SoC 210 through the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 can be used to store volatile data, such as temporary data generated by the SoC 210. The storage capacity of the second RAM 220 is generally larger than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213. In addition, the electronic device 200 may further include a communication chip 230 and / or a power management chip 240 connected to the SoC 210 through the bus 205. The communication chip 230 can be used for protocol stack processing, or for amplifying, filtering, etc. of analog radio frequency signals, or for implementing the above functions simultaneously. The power management chip 240 can be used to supply power to other chips. In one implementation manner, the SoC 210 and the second RAM 220 may be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster inter-chip data transmission rate.

[0086] Figure 3 It is a schematic structural diagram of the ferroelectric memory provided by the embodiment of the present application.

[0087] In one implementation manner, the ferroelectric memory 300 may be as Figure 2The first RAM 213 shown may also be the second RAM 220. The application scenarios of the ferroelectric memory 300 are not limited in this application. The ferroelectric memory 300 includes a storage array 310. The ferroelectric memory 300 may further include one or more circuit structures such as a decoder 320, a driver 330, a timing controller 340, a buffer 350, or an input / output driver 360. In one implementation, the storage array 310 includes a plurality of storage units 400 arranged in an array, and each storage unit 400 can be used to store 1 bit or multi-bit data. The storage array 310 may further include word lines (WLs), bit lines (BLs), source lines (SLs), and bulk lines (BuLs). Each storage unit 400 is electrically connected to a corresponding word line WL, bit line BL, source line SL, and bulk line BuL. Different storage units 400 can be electrically connected through WLs, BLs, SLs, or BuLs. One or more of the above WLs, BLs, SLs, and BuLs are used to select the storage unit 400 to be read or written in the storage array by receiving the control level output by the control circuit, so as to change the polarization direction of the ferroelectric layer in the storage unit 400, thereby implementing the read and write operations of data. For convenience, the above WLs, BLs, SLs, and BuLs are collectively referred to as signal lines in the embodiments of this application. The decoder 320 is used to implement the decoding of the addresses of the storage units 400. The decoder 320 is used to perform decoding according to the received addresses to determine the storage units 400 to be accessed. The driver 330 is used to control the levels of the signal lines according to the decoding results generated by the decoder 320, so as to implement the access to the specified storage unit 400. The buffer 350 is used to cache the read data. For example, a first-in first-out (FIFO) can be used for caching. The timing controller 340 is used to control the timing of the buffer 350 and to control the driver 330 to drive the signal lines in the storage array 310. The input / output driver 360 is used to drive transmission signals, such as driving the received data signals and driving the data signals to be sent, so that the data signals can be transmitted over a long distance. The above storage array 310, decoder 320, driver 330, timing controller 340, buffer 350, and input / output driver 360 can be integrated on one chip or can be separately integrated on multiple chips.

[0088] Figure 4 It is a schematic structural diagram of a FeFET provided by an embodiment of this application.

[0089] The FeFET provided by the embodiment of the present application includes a metal gate 410, a ferroelectric layer 420, a gate oxide layer 430, a source 440, a drain 450, and a substrate 470. A channel 460 can be formed between the source 440 and the drain 450. The metal gate 410, the ferroelectric layer 420, and the gate oxide layer 430 belong to the gate of the FeFET.

[0090] When the FeFET uses an NMOS transistor, the substrate 470 is P-type, and the source 440 and the drain 450 are N-type. When a positive voltage is applied to the control gate, the channel 460 is formed to connect the source 440 and the drain 150, enabling current to pass through the NMOS transistor. At this time, the NMOS transistor is in the on state. Conversely, when a zero voltage or a negative voltage is applied to the control gate, the channel 460 is truncated, and current cannot pass through, and the NMOS transistor is in the off state.

[0091] When the FeFET uses a PMOS transistor, the substrate 470 is N-type, and the source 440 and the drain 450 are P-type. When a negative voltage is applied to the control gate, the channel 460 is formed to connect the source 440 and the drain 150, enabling current to pass through the PMOS transistor. At this time, the PMOS transistor is in the on state. Conversely, when a positive voltage is applied to the control gate, the channel 460 is truncated, and current cannot pass through, and the PMOS transistor is in the off state.

[0092] Figure 4 The shown FeFET, compared with an ordinary field effect transistor (FET), integrates a ferroelectric layer 420 in the gate, enabling the transistor to store data in the polarization state of the ferroelectric layer 420. Each storage unit only requires one device to complete the storage function, uses a lower write voltage, and is easier to integrate into the CMOS process.

[0093] When both the upper and lower layers of a certain layer or a certain region in the FeFET are in the on state, the upper and lower layers can be regarded as two electrodes, and this layer or region can be equivalent to a capacitor. Exemplarily, the ferroelectric layer 420 can be equivalent to a capacitor C FE and the gate oxide layer 430 can be equivalent to a capacitor C IF .

[0094] Figure 5 is a schematic structural diagram of a 4-port FeFET device provided by the embodiment of the present application.

[0095] The semiconductor storage device can be a 4-port N-type FeFET device or a P-type FeFET device, and its gate (G), source (S), drain (D), and substrate (B) are respectively represented as G, S, D, and B. Figure 6 andFigure 7 Two bias states are respectively defined when the semiconductor memory device is an N-type FeFET device.

[0096] Figure 6 It is a schematic diagram of the first state and equivalent capacitance of an N-type FeFET provided by an embodiment of the present application.

[0097] Figure 6 (a) of is a schematic diagram of voltage signals applied to each port of the N-type FeFET in the first state. In the first state, a positive programming voltage +V is applied to G PGM , a first bias voltage is applied to S and D, and B is placed at the FLT potential. The difference between the first bias voltage and 0V is less than a preset threshold, that is, the first bias voltage is equal to or close to 0V. In the following embodiments, the case where the first bias voltage is equal to 0V is taken as an example for detailed description, and this example should not be construed as a limitation of the present application.

[0098] Exemplarily, in the first state, G = +V PGM , S = 0V, D = 0V, B = FLT. When the N-type FeFET is in the first state, the electric potential points from the gate to the source 440 and the drain 450, the channel 460 does not participate in voltage division, and the voltage mainly falls on the gate, and the voltage (V FE ) on the ferroelectric layer 420 is relatively large at this time. Figure 6 (b) of is a schematic diagram of the equivalent capacitance of the N-type FeFET in the first state. C FE represents the capacitance of the ferroelectric layer 420, C IF represents the capacitance of the gate oxide layer 430, C FE and C IF are in series.

[0099] Figure 7 It is a schematic diagram of the second state and equivalent capacitance of an N-type FeFET provided by an embodiment of the present application.

[0100] Figure 7 (a) of is a schematic diagram of voltage signals applied to each port of the N-type FeFET in the second state. In the second state, a positive programming voltage +V is applied to G PGM , S and D are placed at the FLT potential, and a first bias voltage is applied to B. The difference between the first bias voltage and 0V is less than a preset threshold, that is, the first bias voltage is equal to or close to 0V. In the following embodiments, the case where the first bias voltage is equal to 0V is taken as an example for detailed description, and this example should not be construed as a limitation of the present application.

[0101] Exemplarily, in the second state, G = +V PGM, S = FLT, D = FLT, B = 0V. When the N-type FeFET is in the second state, the electric potential points from the gate to the substrate 470, the channel 460 is in the depletion region, and the depletion layer capacitance will share most of the voltage. The voltage (V FE ) across the ferroelectric layer 420 is approximately 1 / 10 of that in the first state. Figure 7 Figure (b) of Figure 7 is a schematic diagram of the equivalent capacitance of the N-type FeFET in the second state. C FE represents the capacitance of the ferroelectric layer 420, C IF represents the capacitance of the gate oxide layer 430, C DEP represents the depletion layer capacitance, C FE , C IF and C DEP are in series.

[0102] In the operation method of the storage array provided by the embodiments of the present application, the selected storage unit is set to the first state, and the remaining unselected storage units in the same row as the selected storage unit are in the second state. Since the voltage across the ferroelectric layer 420 in the second state is approximately 1 / 10 of that in the first state, the write crosstalk of the FeFET device can be reduced.

[0103] Figure 8 Figure Figure 8 is an exemplary flowchart of an operation method of a storage array provided by the embodiments of the present application.

[0104] Figure 8 The method shown in Figure Figure 8 is to perform a write operation on the first target storage unit in the storage array. The storage array includes multiple storage units, and each storage unit includes Figure 4 the FeFET shown in Figure Figure 4 . Among them, the storage units in the same row share the same word line WL, and the storage units in the same column share the same source line SL, the same bit line BL, and the same substrate line BuL. The first target storage unit is located in the first target row and the first target column of the storage array.

[0105] 810, apply a first programming voltage to the word line of the first target row, apply a first bias voltage to the source line and the bit line of the first target column, and float the substrate line of the first target column to perform a write operation on the first target storage unit.

[0106] The difference between the first bias voltage and 0V is less than a preset threshold, that is, the first bias voltage is equal to or close to 0V.

[0107] At this time, the first target storage unit is in Figure 6 the first state shown in Figure Figure 6 , so the ferroelectric layer 420 of the first target storage unit can undergo polarization inversion to complete the state writing.

[0108] 820. Apply a turn-off voltage to the word line of the second target row to turn off the FeFETs of the memory cells in the second target row, apply a first bias voltage to the substrate line of the second target column, and place the source line and bit line of the second target column at a floating potential.

[0109] The second target row includes the remaining rows in the memory array except for the first target row, and the second target column includes the remaining columns in the memory array except for the first target column.

[0110] The turn-off voltage and the first bias voltage are equal to or close to 0V. In one possible implementation, both the turn-off voltage and the first bias voltage are equal to 0V. At this time, since the WL voltage of the row where the memory cells in the second target row are located is 0V, polarization inversion does not occur. At the same time, the remaining unselected memory cells in the same row as the selected first target memory cell are in the second state, so the voltage of the ferroelectric layer 420 is very small and polarization inversion does not occur. Through the operation method provided by this application, write crosstalk is effectively suppressed.

[0111] Figure 9 It is a schematic diagram of the architecture of a memory array provided by an embodiment of this application.

[0112] This memory array includes M rows and N columns of single-transistor (1T) memory cells. Each memory cell includes a FeFET as shown in Figure 4 where M and N are integers greater than or equal to 1. In this 1T memory array, the threshold voltage of the FeFET is positive. The threshold voltage of a transistor refers to the voltage difference between the gate and the source of the transistor. When the gate voltage is lower than the threshold voltage, the transistor is in the cut-off state and almost no drain current flows. When the gate voltage is higher than the threshold voltage, the transistor enters the conduction state and allows the drain current to flow.

[0113] The gate of the FeFET in each memory cell is connected to the word line (WL), the source is connected to the source line (SL), the drain is connected to the bit line (BL), and the substrate is connected to the bulk line (BuL). Among them, the gates of the FeFETs in the memory cells in the m-th row share a word line WLm, 1 ≤ m ≤ M. The sources of the FeFETs in the memory cells in the n-th column share a source line SLn, the drains of the FeFETs in the memory cells in the n-th column share a bit line BLn, and the substrates of the memory cells in the n-th column share a bulk line BuLn, 1 ≤ n ≤ N. It should be understood that the above connection structure is only an example. Due to the interchangeability of the source and the drain, the drain of the FeFET can also be connected to the SL, and the source of the FeFET can also be connected to the BL. The above example should not be construed as a limitation to this application.

[0114] Table 1 shows the read and write operation modes of the 1T memory array. Each memory cell in the memory array includes a 1T N-type FeFET device. Among them, the selected row is the row where the memory cell selected for write operation or read operation is located, and the non-selected row in the memory array is the unselected row. The selected column is the column where the memory cell selected for write operation or read operation is located, and the non-selected column in the memory array is the unselected column.

[0115] Table 1

[0116]

[0117] When writing "0" to the selected memory cell, a positive programming voltage +V can be applied to the WL of the row where the selected memory cell is located. PGM , the SL and BL of the column where it is located are both connected to 0V, and the BuL of the column where it is located is placed at the FLT potential. The WLs of the unselected rows are all connected to 0V, the SL and BL of the unselected columns are both placed at the FLT potential, and the BuLs of the unselected columns are all 0V. At this time, the FeFET of the selected memory cell is in the first state, so the ferroelectric layer 420 can undergo polarization reversal to complete state writing. The WL voltages of the remaining unselected rows are 0V, so no polarization reversal occurs. At the same time, the FeFETs of the remaining unselected memory cells in the same row as the selected memory cell are in the second state, so the voltage of the ferroelectric layer 420 is very small and no polarization reversal will occur. Through the operation method provided by this application, write crosstalk is effectively suppressed.

[0118] When writing "1" to the selected memory cell, first perform the same operation on the entire memory array, that is, connect all the SL, BL, and BuL in the memory array to 0V, and connect all the WLs to the negative programming voltage -V. PGM , perform the write "1" operation on the memory cells in the entire memory array, and then perform the above write "0" operation on the unselected memory cells in the memory array. It should be understood that the reason for performing two-step operations to write "1" to the selected memory cell is that for the N-type FeFET device, only by applying a positive programming voltage to the gate can the channel 460 be in the depletion region, that is, the unselected memory cell is in the second state, reducing the write crosstalk of the FeFET device.

[0119] During the read operation, a read voltage V is applied to the WL of the row where the selected memory cell is located. read, a positive second bias voltage +VDD is applied to the BL of the column where the selected storage cell is located, the SL is connected to 0V, and the BuL is connected to 0V; the WL of the unselected row is connected to 0V, and the BL, SL, and BuL of the unselected column are all connected to 0V. The current of the drain of the selected storage cell FeFET is read. If it is a high current, it means the read data is 1, and if it is a low current, it means the read data is 0. It should be understood that the high current can be a current higher than a preset threshold, and the low current can be a current lower than a preset threshold. In some possible application scenarios, VDD can also be referred to as the operating voltage or the drain supply voltage.

[0120] It should be understood that the connection to 0V voltage described in the embodiments of the present application is not strictly limited to only connecting to 0V voltage, and it can also be connected to a voltage close to 0V, such as 0.01V, 0.1V, or 0.05V voltage, etc.

[0121] Figure 10 is a schematic diagram of the architecture of another storage array provided by the embodiments of the present application.

[0122] The storage array includes M rows and N columns of 2T storage cells, and each storage cell includes a FeFET as shown in Figure 1 and a logic transistor. The FeFET and the logic transistor are connected in series, and M and N are integers greater than or equal to 1. In this 2T storage array, the threshold voltage of the FeFET can be positive or negative, and the threshold voltage of the logic transistor is positive. In this architecture, the threshold voltage of the FeFET can be negative, so the operating voltage is small.

[0123] The FeFET includes a first end and a second end, the logic transistor includes a third end and a fourth end. The second end of the FeFET is connected to the third end of the logic transistor. The first end of the FeFET is connected to the SL, and the fourth end of the logic transistor is connected to the BL. The gate of each FeFET is connected to the WL, and the substrate is connected to the BuL. The gate of each logic transistor is connected to the selector word line (SWL). The first end of the FeFET is the source and the second end is the drain, or the first end of the FeFET is the drain and the second end is the source. The following embodiments will describe the method provided by the present application with the first end as the source and the second end as the drain as an example, and this example should not be construed as a limitation to the present application.

[0124] Among them, the gates of the FeFETs located in the m-th row share a word line WLm, and the gates of the logic transistors located in the m-th row share a word line selection line SWLm, where 1 ≤ m ≤ M. The sources of the FeFETs located in the n-th column share a source line SLn, the logic transistors located in the n-th column share a bit line BLn, and the substrates of the FeFETs located in the n-th column share a substrate line BuLn, where 1 ≤ n ≤ N.

[0125] Table 2 shows the read and write operation modes of the 2T memory array. Each memory cell in the memory array includes an N-type FeFET and a logic transistor. Among them, the selected row is the row where the memory cell selected for write operation or read operation is located, and the unselected row in the memory array is the unselected row. The selected column is the column where the memory cell selected for write operation or read operation is located, and the unselected column in the memory array is the unselected column.

[0126] Table 2

[0127]

[0128] When writing "0" to the selected memory cell, a positive programming voltage +V is applied to the WL of the row where the selected memory cell is located. PGM The SWL of the row where it is located is connected to the turn-on voltage +V. UP The SL and BL of the column where it is located are both connected to 0V, and the BuL of the column where it is located is placed at the FLT potential; the WL and SWL of the remaining unselected rows are both connected to 0V, the SL and BL of the remaining unselected columns are both placed at the FLT potential, and the BuL of the remaining unselected columns are all connected to 0V. At this time, the FeFET of the selected memory cell is in the first state, so the ferroelectric layer 420 can undergo polarization reversal to complete state writing. The FeFETs of the memory cells on the remaining unselected rows do not undergo polarization reversal because the voltage of the WL is 0V. The FeFETs of the remaining unselected memory cells on the same WL as the selected memory cell are in the second state, so the ferroelectric layer voltage is very small and no polarization reversal occurs. Through the operation method provided by the present application, write crosstalk is effectively suppressed.

[0129] When writing "1" to the selected memory cell, first perform the same operation on the entire memory array, that is, connect all SL, BL, and BuL in the memory array to 0V, and connect all SWLs to the turn-on voltage +V. UP All WLs are connected to the negative programming voltage -V. PGM Perform a write "1" operation on the memory cells in the entire memory array, and then perform the above write "0" operation on the unselected memory cells in the memory array. It should be understood that the reason for performing two-step operations to write "1" to the selected memory cell is that for the N-type FeFET device, only by applying a positive programming voltage to the gate can the channel 460 be in the depletion region, that is, the unselected memory cell is in the second state, reducing the write crosstalk of the FeFET device.

[0130] During the read operation, the SWL of the row where the selected memory cell is located is connected to the turn-on voltage +V. UP, the WL is connected to 0V, the BL of the column where the selected memory cell is located is connected to a positive second bias voltage +VDD, the SL is connected to 0V, and the BuL is connected to 0V; for the unselected rows, both the SWL and WL are connected to 0V, and for the unselected columns, the BL, SL, and BuL are all connected to 0V. The current of the drain of the selected memory cell FeFET is read. If it is a high current, it means the read data is 1, and if it is a low current, it means the read data is 0. It should be understood that the high current can be a current higher than a preset threshold, and the low current can be a current lower than a preset threshold.

[0131] It should be understood that the connection to the 0V voltage described in the embodiments of the present application is not strictly limited to only the 0V voltage, and it can also be connected to a voltage close to 0V, such as 0.01V, 0.1V, or 0.05V voltage, etc.

[0132] Figure 11 and Figure 12 respectively define two bias states when the semiconductor memory device is a P-type FeFET device.

[0133] Figure 11 is a schematic diagram of the first state and equivalent capacitance of a P-type FeFET provided by an embodiment of the present application.

[0134] Figure 11 (a) of is a schematic diagram of the voltage signals applied to each port of the P-type FeFET in the first state. In the first state, a negative programming voltage -V is applied to G PGM , a first bias voltage is applied to S and D, and B is placed at the FLT potential. The difference between the first bias voltage and 0V is less than a preset threshold, that is, the first bias voltage is equal to or close to 0V. In the following embodiments, the example where the first bias voltage is equal to 0V is used for detailed description, and this example should not be construed as a limitation of the present application.

[0135] Exemplarily, in the first state, G = -V PGM , S = 0V, D = 0V, B = FLT. When the P-type FeFET is in the first state, the electric potential points from the gate to the source 440 and the drain 450, the channel 460 does not participate in voltage division, and the voltage mainly falls on the gate, and the voltage (V FE ) on the ferroelectric layer 420 is relatively large at this time. Figure 11 (b) of is a schematic diagram of the equivalent capacitance of the P-type FeFET in the first state. C FE represents the capacitance of the ferroelectric layer 420, C IF represents the capacitance of the gate oxide layer 430, C FE and C IF are in series.

[0136] Figure 12 is a schematic diagram of the second state and equivalent capacitance of a P-type FeFET provided by an embodiment of the present application.

[0137] Figure 12 (a) is a schematic diagram of the voltage signals applied to each port of the P-type FeFET in the second state. In the second state, a negative programming voltage -V is applied to G PGM , S and D are set to the FLT potential, and a first bias voltage is applied to B. The difference between the first bias voltage and 0V is less than a preset threshold, that is, the first bias voltage is equal to or close to 0V. In the following embodiments, the case where the first bias voltage is equal to 0V is taken as an example for detailed description, and this example should not be construed as a limitation to the present application.

[0138] Exemplarily, in the second state, G = -V PGM , S = FLT, D = FLT, B = 0V. When the P-type FeFET is in the second state, the electric potential points from the gate to the substrate 470, the channel 460 is in the depletion region, and the depletion layer capacitance will share most of the voltage. The voltage (V FE ) on the ferroelectric layer 420 at this time is about 1 / 10 of that in the first state. Figure 12 (b) is a schematic diagram of the equivalent capacitance of the P-type FeFET in the second state. C FE represents the capacitance of the ferroelectric layer 420, C IF represents the capacitance of the gate oxide layer 430, C DEP represents the depletion layer capacitance, C FE , C IF and C DEP are in series.

[0139] In the operation method of the storage array provided by the embodiments of the present application, the selected storage unit is set to the first state, and the remaining unselected storage units in the same row as the selected storage unit are in the second state. Since the voltage on the ferroelectric layer in the second state is about 1 / 10 of that in the first state, the write crosstalk of the FeFET device can be reduced.

[0140] Table 3 shows Figure 9 the read and write operation modes of the 1T storage array, where each storage unit in the storage array includes a 1T P-type FeFET device. Among them, the selected row is the row where the storage unit selected for the write operation or the read operation is located, and the unselected row in the storage array is the unselected row. The selected column is the column where the storage unit selected for the write operation or the read operation is located, and the unselected column in the storage array is the unselected column.

[0141] Table 3

[0142]

[0143] When writing a "1" to the selected storage unit, a negative programming voltage -V can be applied to the WL of the row where the selected storage unit is located PGM, the SL and BL of the column where it is located are both connected to 0V, and the BuL of the column where it is located is placed at the FLT potential. The WLs of the unselected rows are all connected to 0V, the SL and BL of the unselected columns are both placed at the FLT potential, and the BuLs of the unselected columns are all 0V. At this time, the selected memory cell is in the first state, so the ferroelectric layer 420 can undergo polarization reversal to complete state writing. The WL voltages of the remaining unselected rows are 0V, so no polarization reversal occurs. At the same time, the remaining unselected memory cells in the same row as the selected memory cell are in the second state, so the voltage of the ferroelectric layer 420 is very small and no polarization reversal occurs. Through the operation method provided by this application, write crosstalk is effectively suppressed.

[0144] When performing a write "0" operation on the selected memory cell, first perform the same operation on the entire memory array, that is, connect all the SL, BL, and BuL in the memory array to 0V, and connect all the WLs to the positive programming voltage +V PGM , perform a write "0" operation on the memory cells in the entire memory array, and then perform the above-mentioned write "1" operation on the unselected memory cells in the memory array. It should be understood that the reason for performing two-step operations to write "0" to the selected memory cell is that for P-type FeFET devices, only by applying a negative programming voltage to the gate can the channel 460 be in the depletion region, that is, the unselected memory cells are in the second state, reducing the write crosstalk of the FeFET device.

[0145] During the read operation, apply a read voltage V to the WL of the row where the selected memory cell is located read , apply a negative second bias voltage -VDD to the BL of the column where the selected memory cell is located, connect the SL to 0V, and connect the BuL to 0V; connect the WLs of the unselected rows to 0V, and connect the BL, SL, and BuL of the unselected columns to 0V. Read the current of the drain of the FeFET of the selected memory cell. If it is a high current, it means the read data is 1, and if it is a low current, it means the read data is 0. It should be understood that the high current can be a current higher than the preset threshold, and the low current can be a current lower than the preset threshold.

[0146] It should be understood that the 0V voltage described in the embodiments of this application is not strictly limited to only being able to connect to 0V voltage, and it can also be connected to a voltage close to 0V, such as 0.01V, 0.1V, or 0.05V voltage, etc.

[0147] As shown in Table 4 Figure 10 The read and write operation methods of the memory array, each memory cell in this memory array includes a P-type FeFET and a logic transistor. Among them, the selected row is the row where the memory cell selected for the write operation or the read operation is located, and the unselected rows in the memory array are the unselected rows. The selected column is the column where the memory cell selected for the write operation or the read operation is located, and the unselected columns in the memory array are the unselected columns.

[0148] Table 4

[0149]

[0150] When performing a write "1" operation on the selected storage cell, a negative programming voltage -V is applied to the WL of the row where the selected storage cell is located PGM , the SWL of the row where it is located is connected to the turn-on voltage +V UP , the SL and BL of the column where it is located are both connected to 0V, and the BuL of the column where it is located is placed at the FLT potential; the WL and SWL of the remaining unselected rows are both connected to 0V, the SL and BL of the remaining unselected columns are both placed at the FLT potential, and the BuL of the remaining unselected columns are all connected to 0V. At this time, the FeFET of the selected storage cell is in the first state, so the ferroelectric layer 420 can undergo polarization reversal to complete the state writing. The FeFETs of the storage cells on the remaining unselected rows do not undergo polarization reversal because the voltage of the WL is 0V. The FeFETs of the remaining unselected storage cells on the same WL as the selected storage cell are in the second state, so the ferroelectric layer voltage is very small and polarization reversal does not occur. Through the operation method provided by the present application, write crosstalk is effectively suppressed.

[0151] When performing a write "0" operation on the selected storage cell, first perform the same operation on the entire storage array, that is, connect all the SL, BL, and BuL in the storage array to 0V, and connect all the SWLs to the turn-on voltage +V UP , connect all the WLs to the positive programming voltage +V PGM , perform a write "0" operation on the storage cells in the entire storage array, and then perform the above write "1" operation on the unselected storage cells in the storage array. It should be understood that the reason for performing two-step operations to write "0" to the selected storage cell is that for a P-type FeFET device, only by applying a negative programming voltage to the gate can the channel 460 be in the depletion region, that is, the unselected storage cells are in the second state, reducing the write crosstalk of the FeFET device.

[0152] During the read operation, connect the SWL of the row where the selected storage cell is located to the turn-on voltage +V UP , connect the WL to 0V, connect the BL of the column where the selected storage cell is located to the negative second bias voltage -VDD, connect the SL to 0V, and connect the BuL to 0V; connect the SWL and WL of the unselected rows to 0V, and connect the BL, SL, and BuL of the unselected columns to 0V. Read the current of the drain of the FeFET of the selected storage cell. If it is a high current, it means the read data is 1, and if it is a low current, it means the read data is 0. It should be understood that the high current can be a current higher than a preset threshold, and the low current can be a current lower than a preset threshold.

[0153] It should be understood that the connection to the 0V voltage described in the embodiments of the present application is not strictly limited to only connecting to a voltage of 0V, and a voltage close to 0V can also be connected, such as 0.01V, 0.1V or 0.05V voltage, etc.

[0154] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0155] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center in a wired (such as coaxial cable, optical fiber) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as an optical disc), or a semiconductor medium (such as a solid-state drive (SSD)), etc.

[0156] As described above, the above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for operating a memory array, characterized in that, the memory array includes a plurality of memory cells, each memory cell includes a ferroelectric field-effect transistor FeFET, the memory cells in the same row share the same word line, the memory cells in the same column share the same source line, the same bit line and the same substrate line, and the method includes: applying a first programming voltage to the word line of the first target row, applying a first bias voltage to the source line and the bit line of the first target column, and floating the substrate line of the first target column to perform a write operation on the first target memory cell, the first target memory cell is located in the first target row and the first target column, and the difference between the first bias voltage and 0 V is less than a preset threshold; applying a turn-off voltage to the word line of the second target row to turn off the FeFETs of the memory cells in the second target row, applying the first bias voltage to the substrate line of the second target column, and floating the source line and the bit line of the second target column, the second target row includes the remaining rows in the memory array except the first target row, and the second target column includes the remaining columns in the memory array except the first target column.

2. The method according to claim 1, characterized in that, before applying the first programming voltage to the word line of the first target row, the method further includes: applying the first bias voltage to all the source lines, bit lines and substrate lines in the memory array, and applying a second programming voltage to all the word lines in the memory array, the second programming voltage has a polarity opposite to that of the first programming voltage.

3. The method according to claim 2, characterized in that, when the FeFET is an N-type FeFET, the first programming voltage is positive and the second programming voltage is negative; when the FeFET is a P-type FeFET, the first programming voltage is negative and the second programming voltage is positive.

4. The method according to any one of claims 1 to 3, characterized in that, the gates of the FeFETs in the same row share the same word line, the first poles of the FeFETs in the same column share the same source line, the second poles of the FeFETs in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line, the first pole is the source and the second pole is the drain, or, the first pole is the drain and the second pole is the source.

5. The method according to any one of claims 1 to 4, characterized in that, the method further includes: applying a read voltage to the word line of the third target row, and applying a second bias voltage to the line connecting the drain of the FeFET in the third target column to read the value stored in the second target memory cell, the second target memory cell is located in the third target row and the third target column.

6. The method according to any one of claims 1 to 3, characterized in that, Each memory cell in the memory array further includes a logic transistor, the logic transistor is connected in series with the FeFET, the FeFETs of the memory cells in the same row share the same word line, the logic transistors of the memory cells in the same row share the same word line selection line, and the method further includes: Applying an enabling voltage to the word line selection line of the first target row to turn on the logic transistors of the memory cells in the first target row; Applying the disabling voltage to the word line selection line of the second target row to turn off the logic transistors of the memory cells in the second target row.

7. The method according to claim 6, wherein, The FeFET includes a first end and a second end, the logic transistor includes a third end and a fourth end, the second end of the FeFET is connected to the third end of the logic transistor, the gates of the FeFETs in the same row share the same word line, the first ends of the FeFETs in the same column share the same source line, the fourth ends of the logic transistors in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line.

8. The method according to claim 6 or 7, wherein, The method further includes: Applying the enabling voltage to the word line selection line of the fourth target row, and applying a second bias voltage to the line connecting the drain of the FeFET in the fourth target column to read the value stored in the third target memory cell, the third target memory cell being located in the fourth target row and the fourth target column.

9. A memory, wherein, comprising: A memory array, the memory array includes a plurality of memory cells, each memory cell includes a ferroelectric field effect transistor FeFET, the memory cells in the same row share the same word line, and the memory cells in the same column share the same source line, the same bit line, and the same substrate line; A memory controller for applying a first programming voltage to the word line of the first target row, applying a first bias voltage to the source line and the bit line of the first target column, and placing the substrate line of the first target column at a floating potential to perform a write operation on the first target memory cell, the first target memory cell being located in the first target row and the first target column, and the difference between the first bias voltage and the 0-volt voltage is less than a preset threshold; And applying a disabling voltage to the word line of the second target row to turn off the FeFETs of the memory cells in the second target row, applying the first bias voltage to the substrate line of the second target column, and placing the source line and the bit line of the second target column at a floating potential, the second target row includes the remaining rows in the memory array except the first target row, and the second target column includes the remaining columns in the memory array except the first target column.

10. The memory according to claim 9, wherein, The memory controller is further configured to apply the first bias voltage to all the source lines, bit lines, and substrate lines in the memory array, and apply a second programming voltage to all the word lines in the memory array, the second programming voltage having a polarity opposite to that of the first programming voltage.

11. The memory according to claim 10, wherein, when the FeFET is an N-type FeFET, the first programming voltage is positive and the second programming voltage is negative; when the FeFET is a P-type FeFET, the first programming voltage is negative and the second programming voltage is positive.

12. The memory according to any one of claims 9 to 11, wherein, the gates of the FeFETs in the same row share the same word line, the first poles of the FeFETs in the same column share the same source line, the second poles of the FeFETs in the same column share the same bit line, the substrates of the FeFETs in the same column share the same substrate line, the first pole is the source and the second pole is the drain, or the first pole is the drain and the second pole is the source.

13. The memory according to any one of claims 9 to 12, wherein, the memory controller is further configured to apply a read voltage on the word line of the third target row, and apply a second bias voltage on the line connecting the drain of the FeFET in the third target column to read the value stored in the second target memory cell, and the second target memory cell is located in the third target row and the third target column.

14. The memory according to any one of claims 9 to 11, wherein, each memory cell in the memory array further includes a logic transistor, the logic transistor is connected in series with the FeFET, the gates of the FeFETs of the memory cells in the same row share the same word line, the logic transistors of the memory cells in the same row share the same word line selection line, and the memory controller is further configured to: apply an on voltage on the word line selection line of the first target row to turn on the logic transistor of the memory cell in the first target row; apply the off voltage on the word line selection line of the second target row to turn off the logic transistor of the memory cell in the second target row.

15. The memory according to claim 14, wherein, the FeFET includes a first end and a second end, the logic transistor includes a third end and a fourth end, the second end of the FeFET is connected to the third end of the logic transistor, the gates of the FeFETs in the same row share the same word line, the first ends of the FeFETs in the same column share the same source line, the fourth ends of the logic transistors in the same column share the same bit line, and the substrates of the FeFETs in the same column share the same substrate line.

16. The memory according to claim 14 or 15, wherein, the memory controller is further configured to apply a second bias voltage on the line connecting the drain of the FeFET in the fourth target column to read the value stored in the third target memory cell, and the third target memory cell is located in the fourth target row and the fourth target column.

17. An electronic device, wherein, it includes a circuit board and the memory according to any one of claims 9 to 16, and the memory is disposed on the circuit board and electrically connected to the circuit board.

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