NAND flash memory, memory and electronic equipment

Abstract

The invention discloses an NAND flash memory, a memory and electronic equipment. Data of a plurality of pages can be read at the same time under the same face in the NAND, the saturation current of each page can be different, and / or the time for reading the data of each page can be different, so that the data recorded by each page is different, the total current of a reading circuit is different, and the voltage drop speed of a discharge capacitor CSO is different. When the NAND flash memory reads data of a plurality of pages, the voltage comparison unit can be used for detecting the relation between the voltage of the discharge capacitor CSO and the comparison voltage so as to accurately read data recorded in each page, and confusion between the read data and the pages is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of storage chips, and particularly to a NAND flash memory, a memory, and an electronic device. Background Art

[0002] A non-and (NAND) flash memory is a non-volatile storage device that uses NAND gate circuits to store data. The NAND flash memory has advantages such as high storage density, fast data read and write speeds, low power consumption, and long lifespan, and can be widely applied to various electronic devices, such as solid state disks (SSDs), universal serial bus (USB) flash drives, memory cards, mobile devices, etc.

[0003] Data reading and writing are the most typical scenarios in the application process of NAND flash memories. Among them, data reading (read operation) is the most important usage scenario for users, so improving the reading performance and power consumption of NAND memories is of great significance. The read operation of NAND memories can be divided into a pre-charging process, an evaluation process, and a discharging process. The time delay of each process is continuously reduced with the improvement of the manufacturer's process, circuit design, and manufacturing capabilities until it reaches an extreme value. With the iterative update of the media of NAND memories, the decrease in read time delay gradually becomes slow, resulting in NAND memories being unable to meet the requirements of future storage scenarios for low power consumption and high performance. Summary of the Invention

[0004] To solve the above problems, embodiments of the present application provide a NAND flash memory, a memory, and an electronic device. When reading data of multiple pages simultaneously on the same plane, making the saturation current of each page different and / or the time for reading data of each page different can accurately read out the data recorded on each page and avoid confusion between the read data and the pages. In addition, the present application also provides a memory and an electronic device corresponding to the NAND flash memory.

[0005] For this purpose, the following technical solutions are adopted in the embodiments of the present application:

[0006] First aspect, an embodiment of the present application provides a NAND flash memory, including: a voltage control unit including a plurality of first output ports and a plurality of second output ports, where the plurality of first output ports are all used to output a first electrical signal, and the plurality of second output ports are all used to output a second electrical signal; a NAND array including a plurality of sub-blocks, each sub-block including a plurality of pages, and the plurality of pages are respectively electrically connected to the plurality of first output ports and are used to read or write data when receiving the first electrical signal; an asynchronous unit electrically connected between the plurality of first output ports and the plurality of sub-blocks, or electrically connected to the gates of the sub-block selection transistors in the plurality of pages of the plurality of sub-blocks and the gates of the double-gate MOS transistors in the plurality of pages of the plurality of sub-blocks, and is used to make the saturation currents of the target double-gate MOS transistors for simultaneously reading data of a plurality of pages different and / or make the conduction times of each page for simultaneously reading data of a plurality of pages different; a plurality of discharge capacitors C SO , where the first ends of the plurality of discharge capacitors are respectively electrically connected to the plurality of second output ports, and the second ends of the plurality of discharge capacitors are grounded; a voltage comparison unit including a plurality of input ports, where the plurality of input ports are respectively electrically connected to the plurality of second output ports and are used to compare the magnitudes of the voltages received by the plurality of input ports with a comparison voltage and output a comparison result.

[0007] In this embodiment, when reading data of a plurality of pages simultaneously under the same plane in the NAND memory, the saturation current of each page can be made different and / or the time for reading data of each page can be made different, so that the data recorded on each page is different, the total current of the reading circuit is different, and the voltage drop speeds of the discharge capacitors C SO are different. When the NAND flash memory reads data of a plurality of pages, the voltage comparison unit can be used to detect the relationship between the voltage of the discharge capacitor C SO and the comparison voltage, so as to accurately read out the data recorded on each page and avoid confusion between the read data and the pages.

[0008] In one embodiment, the discharge capacitor is in a discharging state when the data recorded by the target double-gate MOS transistor in the page to which it is electrically connected is "1"; the discharge capacitor is in a charging state when the data recorded by the target double-gate MOS transistor in the page to which it is electrically connected is "0".

[0009] In this embodiment, when the data recorded by the target double-gate MOS transistor is "1", the circuit where the target double-gate MOS transistor and the discharge capacitor are located is turned on, allowing the discharge capacitor to discharge, so that the voltage of the discharge capacitor decreases. When the data recorded by the target double-gate MOS transistor is "0", the circuit where the target double-gate MOS transistor and the discharge capacitor are located is turned off, allowing the discharge capacitor to be in a charging state, so that the voltage of the discharge capacitor is maintained. The voltage comparison unit can accurately read the data recorded on each page according to the voltages of multiple discharge capacitors at different times, avoiding confusion between the read data and the pages.

[0010] In one embodiment, the voltage comparison unit is specifically configured to compare the voltages received by the multiple input ports at multiple latch time points with the comparison voltage to obtain multiple sub-output results; the NAND flash memory further includes: a decoding unit, configured to compare the multiple sub-output results with a preset result to determine whether the data recorded by the target double-gate MOS transistors of each page when simultaneously reading multiple pages is "0" or "1"; the preset result records the sub-output results corresponding to different latch time points for the data recorded by the multiple target double-gate MOS transistors read simultaneously.

[0011] In this embodiment, due to the different saturation currents of the target double-gate MOS transistors of multiple pages read simultaneously or the different times for reading the data of each page, the voltages of multiple discharge capacitors at different times by the voltage comparison unit are different. The decoding unit can compare the voltages of multiple discharge capacitors at different times with the data recorded by each target double-gate MOS transistor according to its pre-stored table, so as to accurately read the data recorded on each page, avoiding confusion between the read data and the pages.

[0012] In one embodiment, the relationship between the number M of the multiple latch time points and the number N of pages read simultaneously is: M ≥ (2 N - 1); M and N are positive integers greater than or equal to 2.

[0013] In this embodiment, the number M of latch time points set by the voltage comparison unit shall not be less than (2 N - 1), to avoid insufficient number of latch times, resulting in the inability to distinguish the voltages of multiple discharge capacitors when the data recorded by the target double-gate MOS transistors of multiple pages read simultaneously are different.

[0014] In one embodiment, there is at least one latch time point between different discharge durations; the discharge duration refers to the duration during which the voltage of the discharge capacitor electrically connected to the target double-gate MOS transistor of multiple pages read simultaneously decreases to the comparison voltage.

[0015] In one embodiment, when the conduction times of the respective pages of the multiple pages read simultaneously are different, the time difference between the conduction times of two adjacent pages is less than or equal to the duration for the voltage of the discharge capacitor to drop to the comparison voltage.

[0016] In this embodiment, when the asynchronous unit makes the times for reading the data of each page different, the delayed time is less than or equal to the duration for the voltage of the discharge capacitor to drop to the comparison voltage, avoiding completely asynchronous reading of two pages.

[0017] In one embodiment, the voltage control unit is further configured to electrically connect the multiple first output ports to the multiple second output ports respectively when stopping outputting the first electrical signal and the second electrical signal.

[0018] In this embodiment, after the voltage control unit stops outputting the first electrical signal and the second electrical signal, each first output port can be electrically connected to a second output port to form a reading circuit, enabling the discharge capacitor C SO to discharge to read data.

[0019] In one embodiment, the voltage control unit is further configured to convert the current of the second output port from a first value to a second value.

[0020] In this embodiment, after the multiple first output ports are electrically connected to the multiple second output ports respectively, the voltage control unit can change the current value of the second output port to reduce the current flowing into the NAND array 420, protecting the NAND array.

[0021] In a second aspect, an embodiment of the present application provides a memory, including: a circuit board, at least one NAND flash memory as various possible implementations of the first aspect, the NAND flash memory being fixed and electrically connected to the circuit board for storing data.

[0022] In a third aspect, an embodiment of the present application provides an electronic device, including: at least one memory as various possible implementations of the second aspect, at least one processor, the processor being electrically connected to the at least one memory for writing data to the at least one memory and / or reading data from the at least one memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following briefly introduces the drawings required for the description of the embodiments or the prior art.

[0024] Figure 1 It is a schematic structural diagram of a double-gate MOS transistor of a NAND memory in the related art;

[0025] Figure 2Schematic diagram of the structure of a NAND memory in the related art;

[0026] Figure 3 Schematic diagram of the path for reading the data of page 1 of sub-block 0 of the NAND memory in the related art;

[0027] Figure 4 Schematic diagram of the structure of the first NAND memory provided in the embodiments of the present application;

[0028] Figure 5 In the embodiments of the present application, the discharge capacitor C SO Schematic diagram of the relationship between the voltage drop rate and the current in the reading circuit;

[0029] Figure 6 Schematic diagram of the structure of the second NAND memory provided in the embodiments of the present application;

[0030] Figure 7 In the embodiments of the present application, the discharge capacitor C SO Schematic diagram of the relationship between the voltage drop rate and the current in the reading circuit;

[0031] Figure 8 Schematic diagram of the structure of the third NAND memory provided in the embodiments of the present application. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0033] In this article, the term "and / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The symbol " / " in this article represents an "or" relationship between associated objects. For example, A / B represents A or B.

[0034] In the specification and claims of this article, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first response message and the second response message are used to distinguish different response messages, rather than to describe the specific order of response messages.

[0035] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.

[0036] In the description of the embodiments of the present application, unless otherwise specified, "a plurality of" means two or more. For example, a plurality of processing units means two or more processing units, etc.; a plurality of elements means two or more elements, etc.

[0037] NAND memory adopts a double-gate transistor design. A traditional metal-oxide-semiconductor field-effect transistor (MOSFET) includes a source, a drain, a gate, and a body. A storage unit inside NAND adds a floating gate in the insulating layer of the traditional MOS transistor to store charges. By applying a large voltage difference between the gate and the body, electrons or holes can be injected into the floating gate to achieve write and erase operations. The amount of stored charge will change the threshold voltage V of the transistor. TH . Different threshold voltages V TH represent different information storage states, so each storage unit stores one or more (bit) bits of data. When the voltage applied to the gate is greater than the threshold voltage V TH , the channel will be inverted. If there is a voltage difference between the source and the drain at this time, a current path will be formed. Otherwise, there will be no current path. Based on this, the magnitude of the threshold voltage V of the transistor can be judged, and the stored data can be read out. TH

[0038] Figure 1 is a schematic structural diagram of a double-gate MOS transistor of a NAND memory in the related art. As Figure 1 shown, NAND memory can change the threshold voltage V of the double-gate MOS transistor by the amount of charge stored on the floating gate. TH . After applying a read voltage V read to the gate of NAND memory, if the read voltage V read is greater than the threshold voltage V formed by the charge in the floating gate TH , a controllable transconductance effect in the double-gate MOS transistor will be triggered, causing the channel between the source and the drain to conduct and allowing current to pass through the channel. When the read voltage V read is greater than the threshold voltage V TH , when the double-gate MOS transistor of the storage unit is in the on state, it means that the data recorded in the storage unit is "1". On the contrary, when the read voltage V read is less than the threshold voltage V TH , when the double-gate MOS transistor of the storage unit is in the off state, it indicates that the data recorded in the storage unit is "0".

[0039] In NAND memory, the granularity of the read operation is in units of "pages". A page usually contains multiple memory cells. When NAND memory performs a read operation, it first selects the word line (WL) of the target page and connects the WL to the source output (SO) node through the bit line (BL).

[0040] As Figure 2 shown, NAND memory includes a read circuit. The voltage control unit of the read circuit applies an appropriate read voltage V read to the BL. After the voltage is applied to the BL, the charge state of the memory cell affects the voltage on the BL. If the threshold voltage V TH formed by the charge state of the memory cell is greater than the read voltage V read on the BL, the read voltage V read on the BL will change. The read circuit amplifies and encodes the changed voltage according to the change of the read voltage V read on the BL and outputs the data information in a detected manner. Therefore, NAND memory can quickly read and transfer the data in the memory cell by detecting the voltage change of the discharge capacitor C SO .

[0041] The process of NAND memory reading a single page can be divided into a precharge phase, an evaluate phase, and a discharge phase.

[0042] In the precharge phase, the voltage control unit charges the WL and the BL so that the voltages formed by the discharge capacitor C SO at the BL and SO nodes are V BL and V SO , and V BL <V SO .

[0043] In the evaluate phase, since the voltage V SO of the discharge capacitor C SO at the SO node is greater than the voltage V BL of the BL, if the memory cell is in the on state (data is "1"), the discharge capacitor C SO will discharge and discharge until the voltage V SO of the discharge capacitor C SO is less than the comparison voltage V THSA . If the memory cell is in the off state (data is "0"), the discharge capacitor C SO will not discharge, and the voltage V SO of the discharge capacitor C SOwill always be greater than the comparison voltage V THSA The voltage comparison unit inside the NAND memory can obtain the voltage V of the discharging capacitor C at the SO node at a "latch" time point SO of SO and determine whether the read data is "1" or "0" by comparing the magnitude between the voltage V SO and the comparison voltage V THSA . The voltage comparison unit saves and stores the read data in the data buffer area.

[0044] During the discharging process, the voltage control unit discharges the WL and BL to complete this read operation.

[0045] Under the same plane, reading data from multiple pages in the NAND memory needs to be executed serially. As Figure 3 shown, taking the data of page 1 of sub-block (string) 0 as an example, when the NAND memory needs to read the target storage unit, it processes through the row address decoder and applies the voltages output by the boosting and voltage control circuits to each WL. The sub-block selection transistor is applied with a positive voltage Vpass to make it conduct, enabling the BL to access the storage units under sub-block 0. At the same time, other non-selected sub-block selection transistors are set to a low voltage (such as 0V) to prevent the non-selected sub-block selection transistors from conducting and interfering with the read result.

[0046] After applying the read voltage V read to the WL2 where the target storage unit is located, the storage unit on WL2 can be activated and selected for reading. The gates of other storage units are set to a high voltage V pass to make the transistors connected in series on other sub-blocks conduct, ensuring that the conduction state of the entire sub-block is determined by the conduction state of the read storage unit. If the data written to the target storage unit is "0", it indicates that the threshold voltage V TH of the target storage unit is greater than the read voltage V read , and the target storage unit is in the off state, and almost no current passes through the storage unit string. If the data written to the target storage unit is "1", it indicates that the threshold voltage V TH of the target storage unit is greater than the read voltage V read , and the target storage unit is in the on state, and there is current passing through the storage unit string, making the current I cell . After the NAND memory completes the reading of page 1, it discharges the WL and BL. If the NAND memory needs to read the page on sub-block 1, the above process will be repeated, only need to turn off the sub-block selection transistor 0 and turn on the sub-block selection transistor 1.

[0047] When a NAND memory performs a read operation, independent operations can be carried out between different planes and different logical unit numbers (LUNs). This means that in a NAND memory chip, multiple planes and multiple LUNs can perform read operations simultaneously. In the same plane, different pages can be read in a serial manner. Serial reading means reading the pages one by one in sequence, rather than reading multiple pages simultaneously. When the NAND memory reads a page, it is necessary to recharge and discharge the BL again to read the data. However, the repeated recharge and discharge process limits the read performance and increases the read power consumption. If two sub-blocks are opened simultaneously and the currents conducted by the two sub-blocks are close to the same and the slopes of the voltage V SO of the node SO decreasing are close to the same, there may be two cases of "01" and "10" that cannot be distinguished, resulting in confusion between the data read and the page.

[0048] To solve the drawbacks existing in the related art, the embodiments of the present application provide a new NAND memory, a memory, and an electronic device. In order to improve the speed of reading data, the NAND memory can add an asynchronous unit. The asynchronous unit can make the saturation current of each page different, can make the time for reading the data of each page different, can make the saturation current of each page different, and can make the time for reading the data of each page different. When the NAND memory reads the data of multiple pages simultaneously under the same plane, it can make the saturation current of each page different and / or the time for reading the data of each page different, so that the data recorded on each page is different, the total current of the reading circuit is different, and the voltage of the discharge capacitor C SO decreases at different speeds. When the NAND flash reads the data of multiple pages, it can use a voltage comparison unit to detect the relationship between the voltage of the discharge capacitor C SO at multiple latch time points and the comparison voltage, so as to accurately read the data recorded on each page and avoid confusion between the data read and the page. The following asynchronous unit can be called a "current limiting unit", a "time control unit", and a "current limiting and time control unit" according to its own functions.

[0049] Figure 4 FIG. 13 is a schematic structural diagram of the first NAND memory provided in the embodiments of the present application. As Figure 4 shown, the NAND memory 400 includes a reading circuit 410, a NAND array 420, and a current limiting unit 430. The CMOS circuit 410 includes a voltage control unit 411, a voltage comparison unit 412, a data cache unit 413, a decoding unit 414, and multiple discharge capacitors C SO . The NAND array 420 includes multiple sub-blocks.

[0050] The voltage control unit 411 includes a plurality of first output ports and a plurality of second output ports. The plurality of first output ports are respectively connected to each sub-block of the NAND array 420 through lines, and the lines between the voltage control unit 411 and the plurality of sub-blocks are "BL". Each sub-block includes a plurality of sub-block selection transistors. The drain of each sub-block selection transistor is respectively connected to a BL, and the source of each sub-block selection transistor is connected in series with the double-gate MOS transistors of a plurality of memory cells. The gates of the double-gate MOS transistors of each memory cell are connected to an external read unit through lines, and the lines between the gates of the double-gate MOS transistors of each memory cell and the external read unit are "WL".

[0051] The plurality of second output ports of the voltage control unit 411 are respectively connected to the plurality of input ports of the voltage comparison unit 412. One end of a plurality of discharge capacitors C SO is respectively connected to the line between the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412, and the other ends of the plurality of discharge capacitors C SO are grounded. Let the node of the line connecting the discharge capacitor C SO to the line between the second output port of the voltage control unit 411 and the input port of the voltage comparison unit 412 be the SO node.

[0052] The voltage control unit 411 is used to convert the electrical energy provided by the power supply into a suitable voltage, finely regulate the voltage applied to the WL, such as the read voltage V read , through the voltage V pass , etc., and provide voltages for the BL, WL, and the discharge capacitor C SO . During the data reading process of the NAND memory 400, the voltage control unit 411 charges the discharge capacitor C SO in the pre-charge stage, controls the voltage of the SO node, and can stop power supply in the evaluation stage, connect the line where a SO node is located to a BL to form a read loop, and can clamp the voltage of the SO node to prevent its voltage from being too low.

[0053] In the embodiment of the present application, the voltage applied by the voltage control unit 411 to each BL of the NAND array 420 is VBL, the voltage applied to each input port of the voltage comparison unit 412 of the read circuit 410 is VSO, and VSO > VBL. After the voltage control unit 411 electrically connects the plurality of first output ports and the plurality of second output ports respectively, it can change the current value of the second output port and convert the current of the second output port from a first value to a second value. The voltage control unit 411 changes the current when the discharge capacitor C SO discharges, reduces the current flowing into the NAND array 420, and realizes the protection of the NAND array 420.

[0054] The reading circuit 410 may further include a reading unit, which is configured to parse the input address signal to determine the index, page, block, or other location information of the target storage unit to be operated. The reading unit transmits the parsed location information to the NAND array 420, causing the sub-block selection transistors inside the corresponding sub-blocks in the NAND array 420 to conduct, so that the circuit where the target storage unit is located is conducted. In addition, the address decoding unit 413 is further configured to generate appropriate operation signals according to the parsed location information and the selection result of the target storage unit to control the charge and discharge, erasure, or other related operations of the target storage unit.

[0055] In the embodiment of the present application, when the NAND array 420 performs a reading operation on the storage units managed by more than one sub-block at the same time, the reading unit may parse more than one input address information at the same time, and transmit more than one parsed location to the NAND array 420 to control the select gates of more than one target storage unit.

[0056] The current limiting unit 430 may be disposed between each BL and each sub-block, or at the gates of the sub-block selection transistors inside each sub-block and the gates of the double-gate MOS transistors of each storage unit, and is configured to limit the saturation current of each page of storage units by regulating the gate voltage, threshold voltage, resistance value of the series resistance, resistance value of the equivalent resistance, etc. of the double-gate MOS transistors of each page of storage units, so that the saturation currents of each page are different. The saturation current refers to the current in the double-gate MOS transistors of each storage unit of the page, the sub-block selection transistor where the page is located, the BL, and the discharge capacitor C SO in the reading circuit where it is located.

[0057] Taking the example that the NAND flash memory 400 reads the data of the storage units of two pages at the same time, let the two pages be page 0 and page 1 respectively. Assume that the storage units of page 0 are connected to the sub-block selection transistor 0 and BL0, the storage units of page 1 are connected to the sub-block selection transistor 1 and BL1, and the saturation current I cell0 of the double-gate MOS transistor of the storage units of page 0 is greater than the saturation current I cell1 of the double-gate MOS transistor of the storage units of page 1.

[0058] During the evaluation process, if the data of the storage units of page 0 is "1" and the data of the storage units of page 1 is "1", the double-gate MOS transistor of the storage units of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell0 , and the double-gate MOS transistor of the storage units of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell1 . Therefore, the total current on the reading circuit when the data is "11" is Icell0 +I cell1 。

[0059] When the data in the storage unit of page 0 is "1" and the data in the storage unit of page 1 is "0", the double-gate MOS transistor in the storage unit of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell0 , and the double-gate MOS transistor in the storage unit of page 1 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "10" is I cell0 。

[0060] When the data in the storage unit of page 0 is "0" and the data in the storage unit of page 1 is "1", the double-gate MOS transistor in the storage unit of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, and the double-gate MOS transistor in the storage unit of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell1 . Therefore, the total current on the read circuit when the data is "01" is I cell1 。

[0061] When the data in the storage unit of page 0 is "0" and the data in the storage unit of page 1 is "0", the double-gate MOS transistor in the storage unit of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, and the double-gate MOS transistor in the storage unit of page 1 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "00" is 0

[0062] In the embodiments of the present application, the total current on the read circuit is different, and the slope of the voltage of the discharge capacitor C SO dropping from the voltage V SO to the comparison voltage V THSA is different. As Figure 5 shown, the total current on the read circuit has four cases: I cell0 +I cell1 , I cell0 , I cell1 , and 0. The total current on the read circuit when the data is "11" is I cell0 +I cell1 , and the voltage drop rate of the discharge capacitor C SO is the fastest, and the slope is also the largest. Since the saturation current I cell0 is greater than the saturation current I cell1 , so when the data is "10", the discharge capacitor CSO has a voltage drop rate greater than that of the discharge capacitor C when the data is "01" SO 's voltage drop rate, that is, the discharge capacitor C when the data is "10" SO has a slope of voltage change greater than that of the discharge capacitor C when the data is "01" SO 's slope of voltage change. When the data is "00", the total current on the reading circuit is 0, and the voltage of the discharge capacitor C SO remains unchanged.

[0063] The voltage comparison unit 412 is used to receive the discharge capacitor voltage V of the discharge capacitor C SO and compare the discharge capacitor voltage V SO with the comparison voltage V SO . In the embodiments of the present application, the voltage comparison unit 412 can set M latch time points. The relationship between the number M of multiple latch time points and the number N of pages read simultaneously is: M≥(2 THSA -1); M and N are positive integers greater than or equal to 2. N -1); M, N are positive integers greater than or equal to 2.

[0064] The NAND flash memory 400 can be divided into single level cell (SLC), multi level cell (MLC), triple level cell (TLC), quad level cell (QLC), etc. according to the number of bits stored in the storage unit.

[0065] SLC is a type of flash memory. Each storage unit can only store 1 bit (0 or 1). When reading data of a page in the SLC, a read voltage V read is applied to the storage unit. Therefore, the relationship between the number M of latch time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1).

[0066] Each storage unit of the MLC can store multiple bits, usually 2 bits. When reading data of a page in the MLC, an X1 read voltage V read is applied to the storage unit. Therefore, the relationship between the number M of latch time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M≥(2 N -1)×X1. Wherein, X1 is 1 or 2. The value of X1 is related to the type of page read.

[0067] Each storage unit of the TLC can store more bits, usually 3 bits. When reading data of a page in the TLC, an X2 read voltage Vread , so the relationship between the number M of latch time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M ≥ (2 N - 1) × X2. Wherein, X2 is 1, 2, 3 or 4. The value of X2 is related to the type of the read page.

[0068] Each storage cell of QLC can store more bits, usually 4 bits. When reading data of a page in QLC, an X3 read voltage V is applied to the storage cell read , so the relationship between the number M of latch time points set by the voltage comparison unit 412 and the number N of pages read simultaneously is: M ≥ (2 N - 1) × X3. Wherein, X3 is 1, 2, 3, 4, 5, 6, 7 or 8. The value of X3 is related to the type of the read page.

[0069] The voltage comparison unit 412 is used to compare the voltage V of the SO node with a specific comparison voltage V SO within a specific time, and digitize and latch the result. In the embodiment of the present application, the voltage comparison unit 412 can detect the comparison result of each latch time point and input the comparison result into the data cache unit 413. In one case, when the voltage comparison unit 412 determines that the voltage V of the discharge capacitor at a latch time point THSA is greater than the comparison voltage V SO , it outputs "fail". In another case, when the voltage comparison unit 412 determines that the voltage V of the discharge capacitor at a latch time point THSA is equal to or less than the comparison voltage V SO , it outputs "pass". THSA

[0070] There is at least one latch time point between different discharge durations. The discharge duration refers to the duration during which the voltage of the discharge capacitor electrically connected to the target double-gate MOS transistor of multiple pages read simultaneously drops to the comparison voltage. Preferably, the first latch time point among the M latch time points can be set as the time point when the voltage of the discharge capacitor C SO when the data is "11" drops to the comparison voltage V THSA . The Mth latch time point among the M latch time points can be set as the time point when the voltage of the discharge capacitor C SO when the data is "01" drops to the comparison voltage V THSA . The 2nd to N - 1th latch time points among the M latch time points are between the first latch time point and the Mth latch time point.

[0071] Such as Figure 5As shown, the voltage comparison unit 412 sets 3 latch time points. The first latch time point can be set to the time point when the voltage of the discharge capacitor C SO drops to the comparison voltage V THSA when the data is "11". The second latch time point can be set to the time point when the voltage of the discharge capacitor C SO drops to the comparison voltage V THSA when the data is "10". The third latch time point can be set to the time point when the voltage of the discharge capacitor C SO drops to the comparison voltage V THSA when the data is "01".

[0072] The results output by the voltage comparison unit 412 are shown in Table 1. When the data is "11", the voltage comparison unit 412 outputs "pass" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "10", the voltage comparison unit 412 outputs "fail" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "01", the voltage comparison unit 412 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "pass" at the third latch time point. When the data is "00", the voltage comparison unit 412 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "fail" at the third latch time point.

[0073] Table 1 Results output by the voltage comparison unit for different data at three latch time points

[0074] Page 0 Page 1 The first latch The second latch The third latch 1 1 pass pass pass 1 0 fail pass pass 0 1 fail fail pass 0 0 fail fail fail

[0075] The data cache unit 413 is coupled to the voltage comparison unit 412, and is used to store the results latched by the voltage comparison unit 412 multiple times, and perform data transmission with the decoding unit 414. In the embodiment of the present application, the data cache unit 413 temporarily caches the data read by the NAND flash memory 400 from the NAND array 420, so as to transmit the read data to the host or the processor later. The decoding unit 414 is coupled to the data cache unit 413, and is used to read the comparison results of the voltage comparison unit 412 cached by the data cache unit 413, and analyze whether the data of each page is "0" or "1" according to the comparison results.

[0076] The decoding unit 414 is used to perform operations and processing on the results latched by the data storage unit 413 multiple times, so as to obtain the original data of the read storage unit. In the embodiment of the present application, the decoding unit 414 prestores the preset results in Table 1, and it can be defined that when the comparison results of the three latch time points are all "pass", the data of page 0 is "1" and the data of page 1 is "1". The NAND flash memory 400 can be defined that when the comparison result of the first latch time point is "fail", and the comparison results of the second latch time point and the third latch time point are "pass", the data of page 0 is "1" and the data of page 1 is "0". The NAND flash memory 400 can be defined that when the comparison results of the first latch time point and the second latch time point are "fail", and the comparison result of the third latch time point is "pass", the data of page 0 is "0" and the data of page 1 is "1". The NAND flash memory 400 can be defined that when the comparison results of the three latch time points are all "fail", the data of page 0 is "0" and the data of page 1 is "0".

[0077] When the decoding unit 414 receives that all three results are "pass", the output data is "11". When the decoding unit 414 receives that the first result is "fail" and the second and third results are both "pass", the output data is "10". When the decoding unit 414 receives that the first and second results are both "fail" and the third result is "pass", the output data is "01". When the decoding unit 414 receives that all three results are "fail", the output data is "00". Or, if "pass" is regarded as logic "1" and "fail" is regarded as logic "0", then the result of the first page is the logical OR operation of the first and second latch results, and the result of the second page is the logical OR operation of the first and third latch results.

[0078] In the embodiment of the present application, when the NAND flash memory 400 simultaneously processes multiple pages on the same plane, it can change the saturation current of the double-gate MOS transistors of the storage units of each page, so that the saturation currents of each page are different, so that the data recorded on each page is different, and the total current of the reading circuit is different, so that the voltage drop speed of the discharge capacitor C SO is different. When the NAND flash memory 400 reads the data of multiple pages, it can use the voltage comparison unit to detect the relationship between the voltage of the discharge capacitor C SO and the comparison voltage at multiple latch time points, so as to accurately read the data recorded on each page and avoid confusion between the read data and the pages.

[0079] Figure 6This is a schematic structural diagram of the second NAND memory provided in the embodiments of the present application. As Figure 6 shown, compared with the structure of the NAND memory 400, the structure of the NAND memory 600 replaces the current limiting unit 430 with a timing control unit 630.

[0080] The timing control unit 630 is used to stagger the discharge time of each page. For example, by changing the application time of the read voltage V read , by adding additional switches to adjust the time when different pages start to enter the evaluation stage, etc., so that the storage units of each page start to enter the evaluation stage and read data at different times. In the embodiments of the present application, the timing control unit 630 can be connected to each sub-block selection transistor, and by sending a control signal to the sub-block selection transistor, the sub-block selection transistor is turned on to enable the storage units of the pages corresponding to different sub-blocks to read data at different times. Optionally, the NAND memory 600 can be provided with a switching transistor on each WL. The timing control unit 630 is respectively connected to each switching transistor, and by sending a control signal to the switching transistor, the switching transistor is turned on to enable the storage units of different pages to read data at different times.

[0081] Taking the example of the NAND flash 400 reading the data of the storage units of two pages simultaneously, let the two pages be page 0 and page 1 respectively. Assume that the storage unit of page 0 is connected to the sub-block selection transistor 0 and BL0, and the storage unit of page 1 is connected to the sub-block selection transistor 1 and BL1. The saturation current I cell of the double-gate MOS transistors of the storage units of the two pages is the same, and the time difference between the application of the read voltage V read of the double-gate MOS transistors of the storage units of the two pages is a set time T. Wherein, the duration of the set time T is equal to or less than the time for the storage unit of page 0 to read data.

[0082] During the evaluation process, the timing control unit 630 preferentially turns on the sub-block selection transistor where page 0 is located, and after waiting for the set time T, then turns on the sub-block selection transistor where page 1 is located. If the data of the storage unit of page 0 is "1" and the data of the storage unit of page 1 is "1", the double-gate MOS transistor of the storage unit of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell , and the double-gate MOS transistor of the storage unit of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell . Therefore, the total current on the read circuit when the data is "11" changes from I cell to 2I cell after the time T.

[0083] When the data in the storage cell of page 0 is "1" and the data in the storage cell of page 1 is "0", the double-gate MOS transistor in the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell , and the double-gate MOS transistor in the storage cell of page 1 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the reading circuit when the data is "10" is always I cell .

[0084] When the data in the storage cell of page 0 is "0" and the data in the storage cell of page 1 is "1", the double-gate MOS transistor in the storage cell of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, and the double-gate MOS transistor in the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell . Therefore, the total current on the reading circuit when the data is "01" changes from 0 to I after time T cell .

[0085] When the data in the storage cell of page 0 is "0" and the data in the storage cell of page 1 is "0", the double-gate MOS transistor in the storage cell of page 0 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, and the double-gate MOS transistor in the storage cell of page 1 is in the off state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the reading circuit when the data is "00" is always 0.

[0086] Since the total current on the reading circuit is different, the slope of the voltage of the discharge capacitor C SO dropping from the voltage V SO to the comparison voltage V THSA is not the same. As Figure 7 shown, when the total current on the reading circuit when the data is "11" is I cell , the voltage drop rate of the discharge capacitor C SO is relatively fast and the slope is relatively large. When the total current on the reading circuit when the data is "11" becomes 2I cell , the voltage drop rate of the discharge capacitor C SO increases, and the slope increases on the original basis. When the total current on the reading circuit when the data is "10" is always I cell , so the voltage drop rate of the discharge capacitor C SO remains unchanged and the slope also remains unchanged. When the total current on the reading circuit when the data is "01" is 0, the discharge capacitor C SOThe voltage remains unchanged. When the data is "01", the total current on the read circuit becomes I cell When it is, the discharge capacitor C SO The voltage of starts to drop, and the dropping speed is the same as that of the discharge capacitor C when the data is "10" SO The voltage dropping speed is the same, and the slope is also the same. When the data is "00", the total current on the read circuit is 0, and the voltage of the discharge capacitor C SO remains unchanged.

[0087] The voltage comparison unit 612 sets 3 latch time points. The first latch time point can be set to the time point when the voltage of the discharge capacitor C when the data is "11" SO drops to the comparison voltage V THSA The second latch time point can be set to the time point when the voltage of the discharge capacitor C when the data is "10" SO drops to the comparison voltage V THSA The third latch time point can be set to the time point when the voltage of the discharge capacitor C when the data is "01" SO drops to the comparison voltage V THSA The time point.

[0088] The results output by the voltage comparison unit 612 are shown in Table 2. When the data is "11", the voltage comparison unit 612 outputs "pass" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "10", the voltage comparison unit 612 outputs "fail" at the first latch time point, "pass" at the second latch time point, and "pass" at the third latch time point. When the data is "01", the voltage comparison unit 612 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "pass" at the third latch time point. When the data is "00", the voltage comparison unit 612 outputs "fail" at the first latch time point, "fail" at the second latch time point, and "fail" at the third latch time point.

[0089] Table 2 Results output by the voltage comparison unit for different data at three latch time points

[0090] Page 0 Page 1 The first latch The second latch The third latch 1 1 pass pass pass 1 0 fail pass pass 0 1 fail fail pass 0 0 fail fail fail

[0091] The decoding unit 614 prestores the preset results in Table 2. When it can be defined that the comparison results of all three latch time points are "pass", the data of page 0 is "1" and the data of page 1 is "1". The NAND flash memory 600 can be defined that when the comparison result of the first latch time point is "fail" and the comparison results of the second and third latch time points are "pass", the data of page 0 is "1" and the data of page 1 is "0". The NAND flash memory 600 can be defined that when the comparison results of the first and second latch time points are "fail" and the comparison result of the third latch time point is "pass", the data of page 0 is "0" and the data of page 1 is "1". The NAND flash memory 600 can be defined that when the comparison results of all three latch time points are "fail", the data of page 0 is "0" and the data of page 1 is "0".

[0092] When the decoding unit 614 receives that all three results are "pass", the output data is "11". When the decoding unit 614 receives that the first result is "fail" and the second and third results are both "pass", the output data is "10". When the decoding unit 614 receives that the first and second results are both "fail" and the third result is "pass", the output data is "01". When the decoding unit 614 receives that all three results are "fail", the output data is "00".

[0093] In the embodiment of the present application, the NAND flash memory 600 can simultaneously change the time for reading the data recorded in the storage units of each page for multiple pages on the same plane, so that the data recorded in each page is different and the total current of the reading circuit is different, making the voltage drop speed of the discharge capacitor C SO different. When the NAND flash memory 600 reads the data of multiple pages, it can use the voltage comparison unit to detect the relationship between the voltage of the discharge capacitor C SO at multiple latch time points and the comparison voltage, so as to accurately read out the data recorded in each page and avoid confusion between the read data and the pages.

[0094] Figure 8 FIG. 14 is a schematic structural diagram of a third NAND memory provided in the embodiment of the present application. As Figure 8 shown, compared with the structure of the NAND memory 400, the structure of the NAND memory 800 is to replace the current limiting unit 430 with a current limiting and timing unit 830.

[0095] The current-limiting and timing control unit 830 has the functions of the current-limiting unit 430 and the timing control unit 630, and is used to limit the saturation current of each page, make the saturation currents of each page different, and stagger the discharge times of each page, so that the storage units of each page read data at different times.

[0096] Taking the example of the NAND flash memory 800 reading the data of the storage units of four pages simultaneously, let the four pages be page 0, page 1, page 2, and page 3 respectively.

[0097] The current-limiting and timing control unit 830 can make all or part of the saturation currents of the double-gate MOS transistors of the storage units of the four pages different, and make all or part of the times when the double-gate MOS transistors of the storage units of the four pages apply the read voltage different. For example, the current-limiting and timing control unit 830 makes the saturation current of the double-gate MOS transistor of the storage unit of page 0 the same as that of the double-gate MOS transistor of the storage unit of page 1, makes the saturation current of the double-gate MOS transistor of the storage unit of page 2 the same as that of the double-gate MOS transistor of the storage unit of page 3, and makes the saturation current of the double-gate MOS transistor of the storage unit of page 0 different from that of the double-gate MOS transistor of the storage unit of page 2. The current-limiting and timing control unit 830 makes the time when the double-gate MOS transistor of the storage unit of page 0 applies the read voltage the same as the time when the double-gate MOS transistor of the storage unit of page 2 applies the read voltage, makes the time when the double-gate MOS transistor of the storage unit of page 1 applies the read voltage the same as the time when the double-gate MOS transistor of the storage unit of page 3 applies the read voltage, and makes the time when the double-gate MOS transistor of the storage unit of page 0 applies the read voltage different from the time when the double-gate MOS transistor of the storage unit of page 1 applies the read voltage. And for other situations, the present application does not give examples one by one here.

[0098] Assume that the magnitude relationship of the saturation currents of the double-gate MOS transistors of the storage units of the four pages is I cell0 >I cell1 >I cell2 >I cell3 , and the times when the double-gate MOS transistors of the storage units of the four pages apply the read voltage differ by a set time T in sequence.

[0099] During the evaluation process, the current-limiting and timing control unit 830 preferentially turns on the sub-block selection transistor where page 0 is located, and after waiting for the set time T, then turns on the sub-block selection transistor where page 1 is located. And so on, until the sub-block selection transistor where page 1 is located is turned on.

[0100] When the data in the storage cells of the four pages is "1111", the dual-gate MOS transistor in the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor in the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor in the storage cell of page 2 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor in the storage cell of page 3 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the read circuit when the data is "1111" changes sequentially to I cell0 、I cell0 +I cell1 、I cell0 +I cell1 +I cell2 and I cell0 +I cell1 +I cell2 +I cell3 .

[0101] When the data in the storage cells of the four pages is "1110", the dual-gate MOS transistor in the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor in the storage cell of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor in the storage cell of page 2 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor in the storage cell of page 3 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "1110" changes sequentially to I cell0 、I cell0 +I cell1 and I cell0 +I cell1 +I cell2 .

[0102] When the data in the storage cells of the four pages is "1101", the dual-gate MOS transistor in the storage cell of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell0, the dual-gate MOS transistor of the storage cell on page 1 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the storage cell on page 2 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on page 3 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, when the data is "1101", the total current on the read circuit changes sequentially to I cell0 、I cell0 +I cell1 and I cell0 +I cell1 +I cell3 .

[0103] If the data of the storage cells on the four pages is "1100", the dual-gate MOS transistor of the storage cell on page 0 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the storage cell on page 1 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the storage cell on page 2 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on page 3 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. Therefore, when the data is "1100", the total current on the read circuit changes sequentially to I cell0 and I cell0 +I cell1 .

[0104] If the data of the storage cells on the four pages is "1011", the dual-gate MOS transistor of the storage cell on page 0 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell0 , the dual-gate MOS transistor of the storage cell on page 1 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on page 2 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the storage cell on page 3 is in the on state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, when the data is "1011", the total current on the read circuit changes sequentially to I cell0, I cell0 +I cell2 and I cell0 +I cell2 +I cell3 。

[0105] When the data of the storage units of the four pages is "1010", the double-gate MOS transistor of the storage unit of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell0 , the double-gate MOS transistor of the storage unit of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, the double-gate MOS transistor of the storage unit of page 2 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell2 , the double-gate MOS transistor of the storage unit of page 3 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the reading circuit when the data is "1010" changes sequentially to I cell0 and I cell0 +I cell2 。

[0106] When the data of the storage units of the four pages is "1001", the double-gate MOS transistor of the storage unit of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell0 , the double-gate MOS transistor of the storage unit of page 1 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, the double-gate MOS transistor of the storage unit of page 2 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0, the double-gate MOS transistor of the storage unit of page 3 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the reading circuit when the data is "1001" changes sequentially to I cell0 and I cell0 +I cell3 。

[0107] When the data of the storage units of the four pages is "1000", the double-gate MOS transistor of the storage unit of page 0 is in the on state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell0, the dual-gate MOS transistor of the storage cell on Page 1 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on Page 2 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on Page 3 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "1000" is always I cell0 .

[0108] If the data of the storage cells of the four pages is "0111", the dual-gate MOS transistor of the storage cell on Page 0 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on Page 1 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the storage cell on Page 2 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the storage cell on Page 3 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the read circuit when the data is "0111" changes sequentially to I cell1 、I cell1 +I cell2 and I cell1 +I cell2 +I cell3 .

[0109] If the data of the storage cells of the four pages is "0110", the dual-gate MOS transistor of the storage cell on Page 0 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor of the storage cell on Page 1 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor of the storage cell on Page 2 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor of the storage cell on Page 3 is in the conducting state, and the current flowing through the channel between the source and the drain in the dual-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "0110" changes sequentially to I cell1 、and I cell1 +I cell2 .

[0110] When the data in the storage cells of four pages is "0101", the dual-gate MOS transistor in the storage cell of page 0 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 1 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor in the storage cell of page 2 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 3 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the read circuit when the data is "0101" changes sequentially to I cell1 and I cell1 +I cell3 .

[0111] When the data in the storage cells of four pages is "0100", the dual-gate MOS transistor in the storage cell of page 0 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 1 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell1 , the dual-gate MOS transistor in the storage cell of page 2 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 3 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "0100" has been changing sequentially to I cell2 .

[0112] When the data in the storage cells of four pages is "0011", the dual-gate MOS transistor in the storage cell of page 0 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 1 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is 0. The dual-gate MOS transistor in the storage cell of page 2 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell2 , the dual-gate MOS transistor in the storage cell of page 3 is in the conducting state, and the current flowing through the channel between the source and drain in the dual-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the read circuit when the data is "0011" changes sequentially to I cell2 and I cell2 +I cell3 .

[0113] When the data in the storage units of the four pages is "0001", the double-gate MOS transistors in the storage unit of page 0 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 1 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 2 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 3 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is the saturation current I cell3 . Therefore, the total current on the read circuit when the data is "0001" is always I cell3 .

[0114] When the data in the storage units of the four pages is "0000", the double-gate MOS transistors in the storage unit of page 0 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 1 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 2 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. The double-gate MOS transistors in the storage unit of page 3 are in the conducting state, and the current flowing through the channel between the source and the drain in the double-gate MOS transistor is 0. Therefore, the total current on the read circuit when the data is "0000" is always 0.

[0115] The total current on the read circuit is different, and the slope of the voltage of the discharge capacitor C SO dropping from the voltage V SO to the comparison voltage V THSA is different. Among them, the greater the total current, the greater the slope of the voltage change of the discharge capacitor C SO . The voltage comparison unit 812 can detect the comparison results at multiple latch time points and input the multiple comparison results into the data cache unit 813. The data cache unit 813 temporarily caches the data read by the NAND flash 800 from the NAND array 820 for subsequent transmission of the read data to the host or the processor. The decoding unit 814 can read the comparison results of the voltage comparison unit 812 cached in the data cache unit 813 and analyze whether the data of each page is "0" or "1" according to the comparison results.

[0116] In an embodiment of the present application, the NAND flash memory 800 can change the saturation current of the dual-gate MOS transistors of the memory cells of each page for multiple pages on the same plane at the same time, so that the saturation currents of each page are different, and can also change the time for reading the data recorded by the memory cells of each page, so that the data recorded by each page is different and the total current of the reading circuit is different, making the voltage drop rates of the discharge capacitor C SO different. When the NAND flash memory 800 reads the data of multiple pages, the voltage comparison unit can be used to detect the relationship between the voltage of the discharge capacitor C SO at multiple latch time points and the comparison voltage, so as to accurately read the data recorded by each page and avoid confusion between the read data and the pages.

[0117] An embodiment of the present application provides a memory, which includes a circuit board and at least one NAND flash memory. The NAND flash memory is fixed and electrically connected to the circuit board for storing data. The NAND flash memory can be the NAND flash memory as Figures 4 - 8 shown. Since the memory includes the NAND flash memory as Figures 4 - 8 shown, the memory has all or at least some of the advantages of the NAND flash memory. Among them, the memory can be an SSD, a USB flash drive, a memory card, a mobile device, etc.

[0118] An embodiment of the present application provides an electronic device, which includes at least one memory and at least one processor. The at least one processor is electrically connected to the at least one memory for writing data into the at least one memory and / or reading data from the at least one memory. Since the memory includes the NAND flash memory as Figures 4 - 8 shown, the electronic device has all or at least some of the advantages of the NAND flash memory. Among them, the electronic device can be a smart phone, a laptop computer, a tablet computer, a desktop computer, a server, a storage system, a base station, a drone, an outdoor cabinet, etc.

[0119] The number of each component, the positional relationship of each component, the type of each component, the shape of each component, etc. of the memory provided by the embodiment of the present application are not limited to the above embodiments. Any technical solution implemented under the principle of the present application is within the protection scope of this solution. Any one or more embodiments or illustrations in the specification, and the technical solutions combined in a suitable manner are within the protection scope of this solution.

[0120] The number of each component, the positional relationship of each component, the type of each component, the shape of each component, etc. of the electronic device provided by the embodiment of the present application are not limited to the above embodiments. Any technical solution implemented under the principle of the present application is within the protection scope of this solution. Any one or more embodiments or illustrations in the specification, and the technical solutions combined in a suitable manner are within the protection scope of this solution.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application. Those of ordinary skill in the art should understand that although the present application has been described in detail with reference to the foregoing embodiments, it is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the various embodiments of the present application.

Claims

1. A NAND flash memory (400, 600, 800), characterized in that, comprising: A voltage control unit (411, 611, 811) including a plurality of first output ports and a plurality of second output ports, wherein the plurality of first output ports are all used for outputting a first electrical signal, and the plurality of second output ports are all used for outputting a second electrical signal; A NAND array (420, 620, 820) including a plurality of sub-blocks, each sub-block including a plurality of pages, and the plurality of pages are respectively electrically connected to the plurality of first output ports for reading or writing data when receiving the first electrical signal; An asynchronous unit (430, 630, 830) electrically connected between the plurality of first output ports and the plurality of sub-blocks, or electrically connected to the gates of the sub-block selection transistors in the plurality of pages of the plurality of sub-blocks and the gates of the double-gate MOS transistors in the plurality of pages of the plurality of sub-blocks, for making the saturation currents of the target double-gate MOS transistors for simultaneously reading a plurality of pages different and / or making the conduction times of the respective pages for simultaneously reading a plurality of pages different; Multiple discharge capacitors (C SO ), a first end of each of the multiple discharge capacitors is electrically connected to the multiple second output ports respectively, and a second end of each of the multiple discharge capacitors is grounded; A voltage comparison unit (412, 612, 812) including a plurality of input ports, and the plurality of input ports are respectively electrically connected to the plurality of second output ports for comparing the magnitudes of the voltages received by the plurality of input ports with a comparison voltage and outputting a comparison result.

2. The NAND flash memory according to claim 1, characterized in that, The discharge capacitor is in a discharge state when the data recorded by the target double-gate MOS transistor in the page to which it is electrically connected is "1"; the discharge capacitor is in a charging state when the data recorded by the target double-gate MOS transistor in the page to which it is electrically connected is "0".

3. The NAND flash memory according to claim 1 or 2, characterized in that, The voltage comparison unit is specifically configured to compare the magnitudes of the voltages received by the plurality of input ports with the comparison voltage at a plurality of latch time points to obtain a plurality of sub-output results; The NAND flash memory further includes: A decoding unit (414, 614, 814) for comparing the plurality of sub-output results with a preset result to determine whether the data recorded by the target double-gate MOS transistors in the respective pages for simultaneously reading a plurality of pages is "0" or "1"; the preset result records the sub-output results at different latch time points corresponding to the data recorded by the plurality of target double-gate MOS transistors read simultaneously.

4. The NAND flash memory according to claim 3, characterized in that, The relationship between the number M of the multiple latching time points and the number N of pages read simultaneously is: M ≥ (2 N - 1); M and N are positive integers greater than or equal to 2.

5. The NAND flash memory according to claim 3 or 4, characterized in that, There is at least one latch time point between different discharge durations; the discharge duration refers to the duration during which the voltage of the discharge capacitor electrically connected to the target double-gate MOS transistor of the plurality of pages read simultaneously drops to the comparison voltage.

6. The NAND flash memory according to any one of claims 1-5, characterized in that, When the conduction times of the respective pages of simultaneously reading multiple pages are different, the time difference between the conduction times of two adjacent pages is less than or equal to the duration for the voltage of the discharge capacitor to drop to the comparison voltage.

7. The NAND flash memory according to any one of claims 1-6, wherein, the voltage control unit is further configured to electrically connect the plurality of first output ports to the plurality of second output ports respectively when stopping outputting the first electrical signal and the second electrical signal.

8. The NAND flash memory according to claim 7, wherein, the voltage control unit is further configured to convert the current of the second output port from a first value to a second value.

9. A memory, wherein, it includes: a circuit board, at least one NAND flash memory according to any one of claims 1-8, the NAND flash memory being fixed and electrically connected to the circuit board for storing data.

10. An electronic device, wherein, it includes: at least one memory according to claim 9, at least one processor, the processor being electrically connected to the at least one memory for writing data to the at least one memory and / or reading data from the at least one memory.

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