Output driver, non-volatile memory device, and memory controller

Abstract

An output driver, a non-volatile memory device, and a memory controller are provided. The output driver includes: a selection circuit configured to selectively output a first pull-up driving signal or a pulse signal in response to a first control signal; a first pull-up driver circuit configured to provide a first power supply voltage to the first node in response to a first pull-up driving signal or a pulse signal; a second pull-up driver circuit configured to provide a second power supply voltage to the first node in response to a second pull-up driving signal; a first decoupling capacitor having a first terminal electrically connected to the second node and a second terminal electrically connected to a line to which a third power supply voltage is applied; a capacitance optimization circuit configured to change a capacitance of a decoupling capacitor having a first terminal electrically connected to a third node to which the first power supply voltage is applied in response to a second control signal; and a pull-down driver circuit configured to provide a third power supply voltage to the first node in response to a pull-down driving signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0180105, filed on Dec. 12, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to an electronic device, and more particularly, to an output driver circuit for an integrated circuit including a memory device and a memory controller. Background Art

[0003] Memory devices are used to store data and are generally classified into volatile memory devices and non-volatile memory devices. As an example of a non-volatile memory device, a flash memory device may be used in a cellular phone, a digital camera, a portable digital assistant (PDA), a portable computer device, a fixed computer device, and other devices. In a non-volatile memory device, an output driver for outputting a data signal may include a pull-up driver and a pull-down driver each including a plurality of transistors. Summary of the Invention

[0004] The inventive concept provides an output driver, an interface circuit, a non-volatile memory device, and a memory controller for enhancing power integrity (PI) and signal integrity (SI) of an output driver.

[0005] According to an aspect of the inventive concept, there is provided an output driver including: a selection circuit configured to output a first pull-up driving signal or a pulse signal according to a first control signal; a first pull-up driver circuit configured to send a first power voltage to a first node connected to a data pin based on the first pull-up driving signal or the pulse signal of the selection circuit; a second pull-up driver circuit configured to send a second power voltage having a second level to the first node based on a second pull-up driving signal, the second level being less than a first level of the first power voltage; a first decoupling capacitor connected to a second node to which the second power voltage is applied and a line to which a third power voltage having a third level is applied, the third level being lower than the first level and the second level; a capacitance optimization circuit configured to change a capacitance of a decoupling capacitor between a third node to which the first power voltage is applied and the line to a first capacitance or greater based on a second control signal; and a pull-down driver circuit configured to provide the third power voltage to the first node based on a pull-down driving signal.

[0006] According to another aspect of the inventive concept, there is provided a non-volatile memory device including: a memory cell array; a control logic circuit configured to output a plurality of control signals based on a command signal; and a data input / output circuit configured to: generate a plurality of driving signals based on a clock signal and internal data output from the memory cell array, and output data based on the plurality of control signals and the plurality of driving signals. The data input / output circuit includes: a multiplexer configured to output a first pull-up driving signal or a pulse signal according to a first control signal; a first pull-up driver including a first electrode connected to a third node to which a first power voltage is applied, a second electrode connected to a first node connected to a data pin, and a gate electrode to which the first pull-up driving signal and the pulse signal are selectively applied; a second pull-up driver including a first electrode connected to a second node to which a second power voltage having a second level is applied, a second electrode connected to the first node, and a gate electrode to which a second pull-up driving signal is applied, the second level being lower than a first level of the first power voltage; a first decoupling capacitor connected to a line to which a third power voltage having a third level is applied and the second node, the third level being lower than the first level and the second level; a second decoupling capacitor connected to the third node and the line; a third decoupling capacitor connected to a fourth node and the line; a switch configured to connect the third node to the fourth node or electrically disconnect the third node from the fourth node according to a second control signal; a pull-down driver including a first electrode connected to the first node, a second electrode connected to the line, and a gate electrode to which a pull-down driving signal is applied; and an equalizer configured to output a pulse signal based on a sixth control signal.

[0007] According to another aspect of the inventive concept, there is provided a memory controller including: a processor configured to receive data and a command signal, output a plurality of control signals based on the command signal, and output a clock signal and data; and a memory interface circuit configured to generate a plurality of driving signals based on the data and the clock signal, and output internal data based on the plurality of control signals and the plurality of driving signals. The memory interface circuit includes: a multiplexer configured to output a first pull-up driving signal or a pulse signal according to a first control signal; a first pull-up driver including a first electrode connected to a third node to which a first power supply voltage is applied, a second electrode connected to a first node connected to a data pin, and a gate electrode to which the first pull-up driving signal and the pulse signal are applied; a second pull-up driver including a first electrode connected to a second node to which a second power supply voltage having a second level is applied, a second electrode connected to the first node, and a gate electrode to which a second pull-up driving signal is applied, the second level being lower than a first level of the first power supply voltage; a first decoupling capacitor connected to a line to which a third power supply voltage having a third level is applied and the second node, the third level being lower than the first level and the second level; a second decoupling capacitor connected to the third node and the line; a third decoupling capacitor connected to a fourth node and the line; a switch configured to connect the third node to the fourth node or electrically disconnect the third node from the fourth node according to a second control signal; a pull-down driver including a first electrode connected to the first node, a second electrode connected to the line, and a gate electrode to which a pull-down driving signal is applied; and an equalizer configured to output a pulse signal based on a sixth control signal.

[0008] According to another aspect of the inventive concept, there is provided an interface circuit including: a pre-driver circuit configured to output a plurality of driving signals based on internal data and a clock signal, and an output driver circuit configured to output data based on a plurality of received control signals and the plurality of driving signals. The output driver circuit includes: a multiplexer configured to output a first pull-up driving signal or a pulse signal according to a first control signal, a first pull-up driver including a first electrode connected to a third node to which a first power voltage is applied, a second electrode connected to a first node connected to a data pin, and a gate electrode to which the first pull-up driving signal or the pulse signal is applied; a second pull-up driver including a first electrode connected to a second node to which a second power voltage having a second level is applied, a second electrode connected to the first node, and a gate electrode to which a second pull-up driving signal is applied, the second level being lower than a first level of the first power voltage; a first decoupling capacitor connected to a line to which a third power voltage having a third level is applied and the second node, the third level being lower than the first level and the second level; a second decoupling capacitor connected to the third node and the line; a third decoupling capacitor connected to a fourth node and the line; a switch configured to: connect the third node to the fourth node or electrically disconnect the third node from the fourth node according to a second control signal; a pull-down driver including a first electrode connected to the first node, a second electrode connected to the line, and a gate electrode to which a pull-down driving signal is applied; and an equalizer configured to output a pulse signal based on a sixth control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a diagram illustrating an output driver according to an embodiment.

[0011] Figure 2 is a diagram illustrating a capacitance optimization circuit according to an embodiment.

[0012] Figure 3 is a circuit diagram of an output driver according to an embodiment.

[0013] Figure 4 and Figure 5 is for explaining Figure 3 the first termination and the second termination of the output driver.

[0014] Figure 6 is for explaining Figure 3 the third termination of the output driver.

[0015] Figure 7 is a circuit diagram of an output driver according to an embodiment.

[0016] Figure 8 is a diagram for explaining the first termination and the second termination of the output driver Figure 7 .

[0017] Figure 9 is a diagram for explaining Figure 7 the third termination of the output driver

[0018] Figure 10 is a circuit diagram of an output driver according to an embodiment.

[0019] Figure 11 is a diagram for explaining Figure 10 the first termination of the output driver

[0020] Figure 12 is a diagram for explaining Figure 10 the second termination of the output driver

[0021] Figure 13 is a diagram for explaining Figure 10 the third termination of the output driver

[0022] Figure 14 is a circuit diagram of an output driver according to an embodiment.

[0023] Figure 15 is a diagram showing an output driver according to an embodiment.

[0024] Figure 16 is a block diagram of an interface circuit according to an embodiment.

[0025] Figure 17 is a diagram of a non - volatile memory according to an embodiment.

[0026] Figure 18 is a block diagram of a storage system according to an embodiment.

[0027] Figure 19 is a block diagram showing at least a part of an electronic system according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a diagram showing an output driver 100 according to an embodiment. The output driver 100 may include a selection circuit 110, a first pull - up driver circuit 120, a second pull - up driver circuit 130, a first decoupling capacitor DECAP1, a capacitance optimization circuit 140, and a pull - down driver circuit 150.

[0030] The selection circuit 110 may receive a first pull-up drive signal PU1 and a pulse signal SPS, and may perform a selection operation according to the received first control signal CTL1 to output the first pull-up drive signal PU1 or the pulse signal SPS. The first pull-up drive signal PU1 may be generated and output by an external pre-driver. The pre-driver (or pre-driver circuit) will be described below with reference to Figure 16 which will be described. The pulse signal SPS is a signal having a pulse width, and may be generated and output by an equalization circuit. The equalization circuit may be included in the output driver 100, or may be provided outside the output driver 100. The first control signal CTL1 may be generated and output by an external control logic.

[0031] The first pull-up driver circuit 120 may send a first power supply voltage VDDQ1 to a first node N1 based on the first pull-up drive signal PU1 or the pulse signal SPS selected by the selection circuit 110. The first node N1 may be a node connected to a data pin DQ_PIN. Data may be output to the outside through the data pin DQ_PIN. The first power supply voltage VDDQ1 may also be supplied to the output driver 100 through a first power supply voltage pin VDDQ1_PIN. A "pin" in the inventive concept may also be referred to as a "pad". The first power supply voltage VDDQ1 may be a power supply voltage defined in a memory standard such as the JEDEC standard (JESD) and the Open NAND Flash Interface (ONFI). For example, in some embodiments, a first level of the first power supply voltage VDDQ1 may be a constant 1.2 [V]. The first power supply voltage VDDQ1 may be used as each of a channel voltage required to perform data communication between the output driver 100 and the outside and an on-chip voltage required to operate a semiconductor chip including the output driver 100.

[0032] The second pull-up driver circuit 130 may send the second power supply voltage VDDQ2 to the first node N1 based on the second pull-up driving signal PU2. The second pull-up driving signal PU2 may be generated and output by an external pre-driver. The second power supply voltage VDDQ2 may also be supplied to the output driver 100 through the second power supply voltage pin VDDQ2_PIN. The second power supply voltage VDDQ2 may be a power supply voltage defined in a memory standard. In one embodiment, the second power supply voltage VDDQ2 may have a second level that is the same as or lower than the first level of the first power supply voltage VDDQ1. For example, the second level of the second power supply voltage VDDQ2 may be a constant 1.2 [V] that is the same as the first level of the first power supply voltage VDDQ1. Optionally, the second level of the second power supply voltage VDDQ2 may be 0.6 [V] that is lower than the first level of the first power supply voltage VDDQ1. However, the embodiments are not limited thereto. The second level of the second power supply voltage VDDQ2 may be changed according to termination (also known as terminal, termination, or end) corresponding to an interface method. For example, the termination may include low tap termination (LTT), center tap termination (CTT), power isolation low tap termination (PI-LTT), etc. defined in a memory standard. In LTT and CTT, both the first level and the second level may be 1.2 [V], while in PI-LTT, the first level may be 1.2 [V] and the second level may be 0.6 [V]. However, the embodiments are not limited thereto. The second power supply voltage VDDQ2 may be used as a channel voltage required to perform data communication between the output driver 100 and the outside.

[0033] Among multiple terminations supported by the output driver 100, the current termination may be determined based on a command signal input from the outside. In one embodiment, among LTT, CTT, and PI-LTT, PI-LTT may be the default, but is not limited thereto. In terms of power consumption, PI-LTT consumes the least, LTT consumes more power than PI-LTT, and CTT consumes more power than PI-LTT and LTT. On the other hand, in terms of signal transmission capabilities such as signal-to-noise ratio (SNR), PI-LTT is the worst, LTT is better than PI-LTT, and CTT is better than PI-LTT and LTT.

[0034] The first decoupling capacitor DECAP1 can perform a function of assisting power integrity (PI) regarding each of a plurality of terminations. The first decoupling capacitor DECAP1 can be connected to a second node N2 and a line to which a third power supply voltage VSSQ is applied. The second node N2 can be connected to a second power supply voltage pin VDDQ2_PIN, and a second power supply voltage VDDQ2 can be applied to the second node N2. The third power supply voltage VSSQ can be a power supply voltage defined in a memory standard. In one embodiment, the third power supply voltage VSSQ can have a third level, the third level can be lower than a first level of a first power supply voltage VDDQ1 and also lower than a second level of a second power supply voltage VDDQ2. For example, the third power supply voltage VSSQ can correspond to ground, and the third level of the third power supply voltage VSSQ can be 0 [V]. However, the embodiment is not limited thereto. The third power supply voltage VSSQ can be constant. The third power supply voltage VSSQ can be used as a channel voltage required to perform data communication between the output driver 100 and the outside. The first decoupling capacitor DECAP1 can have a first capacitance. The capacitance can be proportional to the area of the decoupling capacitor (e.g., the decoupling capacitor DECAP or the first decoupling capacitor DECAP1). In one embodiment, the first capacitance can correspond to the size of the second pull-up driver circuit 130.

[0035] The capacitance optimization circuit 140 can change the capacitance of the decoupling capacitor DECAP included in the capacitance optimization circuit 140 to the first capacitance or greater based on a second control signal CTL2. The second control signal CTL2 can be generated and output by control logic. The decoupling capacitor DECAP can perform a function of assisting PI regarding some terminations and on-chip regions. The decoupling capacitor DECAP can be connected between a line to which the third power supply voltage VSSQ is supplied and a third node N3. The third node N3 can be connected to a first power supply voltage pin VDDQ1_PIN, and a first power supply voltage VDDQ1 can be applied to the third node N3. Embodiments of the capacitance optimization circuit 140 are described more fully below with reference to Figure 2 The pull-down driver circuit 150 can send the third power supply voltage VSSQ to the first node N1 based on a pull-down driving signal PD.

[0036] According to the above embodiments, the decoupling capacitor DECAP included in the capacitance optimization circuit 140 is optimized, and channel equalization is implemented using the pulse signal SPS. Therefore, the PI and signal integrity (SI) with respect to the output driver 100 can be more robust. Additionally, according to the above embodiments, a plurality of pull-up drivers are designed such that the first power supply voltage VDDQ1 and the second power supply voltage VDDQ2 are respectively applied, and decoupling capacitors (e.g., decoupling capacitor DECAP or first decoupling capacitor DECAP1) having the capacitance required by each pull-up driver are designed according to the termination. Therefore, the PI and SI of the output driver 100 and the integration level of the output driver 100 are improved.

[0037] Figure 2 is a diagram showing the capacitance optimization circuit 140 according to an embodiment. Referring to Figure 1 and Figure 2 , the capacitance optimization circuit 140 may include a second decoupling capacitor DECAP2, a third decoupling capacitor DECAP3, and a switch SWT. The second decoupling capacitor DECAP2 may be connected to the line to which the third power supply voltage VSSQ is supplied and the third node N3. In one embodiment, the second decoupling capacitor DECAP2 may include a first terminal connected to the third node N3 and a second terminal connected to the line to which the third power supply voltage VSSQ is supplied. As shown, the first power supply voltage VDDQ1 may be applied to the third node N3.

[0038] According to some embodiments, the second decoupling capacitor DECAP2 may have a second capacitance. The second capacitance may have a capacity sufficient to support the channel voltage required to transfer data through the data pin DQ_PIN. The second capacitance may be greater than or equal to the first capacitance of the first decoupling capacitor DECAP1. In one embodiment, the second capacitance may correspond to the size of the first pull-up driver circuit 120, and the first capacitance may correspond to the size of the second pull-up driver circuit 130. For example, when the size of the first pull-up driver circuit 120 is larger than the size of the second pull-up driver circuit 130, the second capacitance may be greater than the first capacitance. And, when the size of the first pull-up driver circuit 120 is the same as the size of the second pull-up driver circuit 130, the second capacitance may be equal to the first capacitance.

[0039] The third decoupling capacitor DECAP3 may be connected to the line to which the third power supply voltage VSSQ is supplied and the fourth node N4. In one embodiment, the third decoupling capacitor DECAP3 may include a first terminal connected to the fourth node N4 and a second terminal connected to the line to which the third power supply voltage VSSQ is supplied. The logic circuit 201 may be connected to the fourth node N4. The logic circuit 201 may be a circuit configured to perform various functions included in the output driver 100 and / or a circuit disposed outside the output driver 100 in a semiconductor chip including the output driver 100 to perform various functions. The third decoupling capacitor DECAP3 may have a third capacitance. The third capacitance may be a capacity required for the on-chip area.

[0040] The switch SWT may selectively connect the third node N3 to the fourth node N4 based on the second control signal CTL2. When the third node N3 and the fourth node N4 are connected to each other, the second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 may be connected in parallel. At this time, the combined capacitance of the second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 connected in parallel may be the sum of the second capacitance and the third capacitance. The third node N3 and the fourth node N4 may also be electrically disconnected. In one embodiment, the switch SWT may be implemented as a transistor (such as, a metal-oxide semiconductor field effect transistor (MOSFET), a transmission gate, or a bipolar junction transistor (BJT)), but is not limited thereto.

[0041] Figure 3 is a detailed circuit diagram of an output driver 300 according to an embodiment. Referring to Figure 3 , the output driver 300 may include a selection circuit 310, a first pull-up driver circuit 320, a second pull-up driver circuit 330, a first decoupling capacitor DECAP1, a capacitance optimization circuit 340, and a pull-down driver circuit 350. The selection circuit 310 may be implemented as a 2-to-1 multiplexer (MUX); the multiplexer may output a first pull-up drive signal PU1 or a pulse signal SPS to the first pull-up driver circuit 320 according to the value of the first control signal CTL1.

[0042] The first pull-up driver circuit 320 may include a first N-type transistor NTR1. The first N-type transistor NTR1 may include a first electrode (i.e., the first current-carrying terminal), a second electrode (i.e., the second current-carrying terminal), and a gate electrode. The first electrode of the first N-type transistor NTR1 may be connected to the third node N3, and the first power supply voltage VDDQ1 may be applied to the first electrode of the first N-type transistor NTR1. The second electrode of the first N-type transistor NTR1 may be connected to the first node N1. The first pull-up drive signal PU1 or the pulse signal SPS output from the selection circuit 310 may be applied to the gate electrode of the first N-type transistor NTR1. When the first pull-up drive signal PU1 or the pulse signal SPS output from the selection circuit 310 has a conductive level, the first N-type transistor NTR1 may be turned on, and the first node N1 and the third node N3 may be electrically connected to each other. When the first pull-up drive signal PU1 or the pulse signal SPS output from the selection circuit 310 has a cut-off level, the first N-type transistor NTR1 may be turned off, and the first node N1 and the third node N3 may be electrically disconnected from each other.

[0043] The second pull-up driver circuit 330 may include a second N-type transistor NTR2. The second N-type transistor NTR2 may include a first electrode (i.e., the first current-carrying terminal), a second electrode (i.e., the second current-carrying terminal), and a gate electrode. The first electrode of the second N-type transistor NTR2 may be connected to the second node N2, the second power supply voltage VDDQ2 may be applied to the first electrode of the second N-type transistor NTR2, and the first electrode of the second N-type transistor NTR2 may be connected to the second node N2. The second electrode of the second N-type transistor NTR2 may be connected to the first node N1. The second pull-up drive signal PU2 may be input to the gate electrode of the second N-type transistor NTR2. When the second pull-up drive signal PU2 has a conductive level, the second N-type transistor NTR2 may be turned on, and the first node N1 and the second node N2 may be electrically connected to each other. When the second pull-up drive signal PU2 has a cut-off level, the second N-type transistor NTR2 may be turned off, and the first node N1 and the second node N2 may be electrically disconnected from each other. The second N-type transistor NTR2 may be referred to as the second pull-up driver. The transistors included in each of the first pull-up driver circuit 320 and the second pull-up driver circuit 330 may be referred to as pull-up drivers.

[0044] As described above with reference to Figure 2As described above, the capacitance optimization circuit 340 may include a second decoupling capacitor DECAP2, a third decoupling capacitor DECAP3, and a switch SWT. The pull-down driver circuit 350 may include a first transistor TR1 and a second transistor TR2. As shown, the first transistor TR1 and the second transistor TR2 may be electrically connected in series. A first pull-down drive signal PD1 may be input to the gate electrode of the first transistor TR1, and a second pull-down drive signal PD2 may be input to the gate electrode of the second transistor TR2. The first transistor TR1 and the second transistor TR2 may each be an N-type, but are not limited thereto. When both the first pull-down drive signal PD1 and the second pull-down drive signal PD2 have a conductive level, the first transistor TR1 and the second transistor TR2 may be turned on, and the line to which the third power supply voltage VSSQ is supplied and the first node N1 may be connected to each other.

[0045] According to the above-described embodiment, the first pull-up driver circuit 320 and the second pull-up driver circuit 330 are designed such that the first power supply voltage VDDQ1 and the second power supply voltage VDDQ2 are separately input. Therefore, the entire decoupling capacitor can also be separately designed in the output driver 300 to have a capacitance suitable for each of the first pull-up driver circuit 320 and the second pull-up driver circuit 330, and the capacitor optimization circuit 340 can also be designed. As a result, without significantly changing the internal design structure of the output driver 300, the on-chip PI can be robust in the PI-LTT.

[0046] Figure 4 and 5 are diagrams for explaining Figure 3 the first termination and the second termination of the output driver 300. Referring to Figure 4 and Figure 5, in one embodiment, the first termination may be an LTT, and the second termination may be a CTT. In the LTT or CTT, the first level of the first power supply voltage VDDQ1 and the second level of the second power supply voltage VDDQ2 may both be 1.2 [V] as defined in the memory standard. Meanwhile, the selection circuit 310 may output a first pull-up drive signal PU1 to the first pull-up driver circuit 320. The first pull-up driver circuit 320 may connect the first node N1 to the third node N3 during the pull-up period PUP. The second pull-up driver circuit 330 may connect the first node N1 to the second node N2 during the pull-up period PUP. The switch SWT of the capacitor optimization circuit 340 may be turned off in response to the off level of the second control signal CTL2, and the third node N3 and the fourth node N4 may be electrically disconnected from each other. In this case, when a pulse signal is input, the second decoupling capacitor DECAP2 may assist the PI related to channel equalization in the PI-LTT. The third decoupling capacitor DECAP3 may assist the PI regarding the on-chip area. The second capacitance of the second decoupling capacitor DECAP2 may be greater than or equal to the first capacitance.

[0047] Referring to Figure 4 , during the pull-up period PUP, both the first pull-up drive signal PU1 and the second pull-up drive signal PU2 may have a conductive level (e.g., logic high level), and both the first pull-down drive signal PD1 and the second pull-down drive signal PD2 may have a cut-off level (e.g., logic low level). In this case, the first N-type transistor NTR1 and the second N-type transistor NTR2 may be turned on, the first transistor TR1 and the second transistor TR2 may be turned off, and the level of the voltage applied to the first node N1 may increase. Therefore, the data signal output through the data pin DQ_PIN may have an output high level (e.g., the high-level output voltage (or voltage output high) (VOH) defined in the memory standard). Meanwhile, during the pull-down period PDP, both the first pull-up drive signal PU1 and the second pull-up drive signal PU2 may have a cut-off level, and both the first pull-down drive signal PD1 and the second pull-down drive signal PD2 may have a conductive level. In this case, the first N-type transistor NTR1 and the second N-type transistor NTR2 may be turned off, the first transistor TR1 and the second transistor TR2 may be turned on, and the level of the voltage applied to the first node N1 may decrease. Therefore, the data signal output through the data pin DQ_PIN may have an output low level (e.g., the low-level output voltage (or voltage output low) (VOL) defined in the memory standard). In this way, the data signal output through the data pin DQ_PIN may be a periodic signal that swings between the output high level and the output low level. At this time, the swing width SW of the data signal and the center level between the output high level and the output low level may be different according to the LTT or CTT.

[0048] In one embodiment, the first capacitor may correspond to the size of the active region of the second pull-up driver (e.g., the second N-type transistor NTR2). The second capacitor may correspond to the size of the active region of the first pull-up driver (e.g., the first N-type transistor NTR1). For example, when the size of the active region of the first N-type transistor NTR1 is larger than the size of the active region of the second N-type transistor NTR2, the second capacitor of DECAP2 may be larger than the first capacitor of DECAP1. Optionally, when the size of the active region of the first N-type transistor NTR1 is the same as the size of the active region of the second N-type transistor NTR2, the second capacitor may be equal to the first capacitor.

[0049] Referring to Figure 5 , in one embodiment, the output driver 300 may be operable as an LTT or a CTT according to the resistance of each of the first resistor R1 and the second resistor R2 corresponding to the drain-to-source resistance of the first N-type transistor NTR1 and the second N-type transistor NTR2, respectively. For example, when the resistance of each of the first resistor R1 and the second resistor R2 is designed to be relatively large, the output driver 300 shown in Figure 4 and Figure 5 may support a CTT; however, when the resistance of each of the first resistor R1 and the second resistor R2 is designed to be relatively small, the output driver 300 shown in Figure 4 and Figure 5 may support an LTT.

[0050] Figure 6 is a diagram for explaining the third termination of the output driver 300 of Figure 3 Referring to Figure 6, in one embodiment, the third termination may be a PI-LTT. In the PI-LTT, according to the memory standard, the first level of the first power supply voltage VDDQ1 may be 1.2 [V], and the second level of the second power supply voltage VDDQ2 may be 0.6 [V]. The selection circuit 310 may output a pulse signal SPS to the first pull-up driver circuit 320. During the pull-up period PUP, the first pull-up driver circuit 320 may connect the first node N1 to the third node N3 during a first period P1 corresponding to the pulse width of the pulse signal SPS, and electrically disconnect the first node N1 and the third node N3 during a second period P2 after the first period P1 has passed. The second pull-up driver circuit 330 may connect the first node N1 to the second node N2 during the pull-up period PUP. Meanwhile, the third node N3 and the fourth node N4 may be connected to each other through the turned-on switch SWT. The second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 may be connected in parallel. At this time, the capacitance of the decoupling capacitor DECAP may be the sum of the second capacitance of DECAP2 and the third capacitance of DECAP3. The second decoupling capacitor DECAP2 may additionally assist with PI regarding the on-chip area. That is, the second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 connected in parallel may assist with PI regarding the on-chip area.

[0051] Referring to Figure 6 , for example, during the pull-up period PUP, the second N-type transistor NTR2 may be turned on, the first transistor TR1 and the second transistor TR2 may be turned off, and the level of the voltage applied to the first node N1 may increase. Meanwhile, during the first period P1 of the pull-up period PUP, the first N-type transistor NTR1 may be turned on together with the second N-type transistor NTR2. Therefore, during the first period P1 of the pull-up period PUP, the level of the voltage applied to the first node N1 may increase significantly due to the combination of the first power supply voltage VDDQ1 and the second power supply voltage VDDQ2. As a result, the value of the resistance (e.g., Ron) defined in the memory standard may be maintained, and the impedance regarding the data pin DQ_PIN may be appropriately matched.

[0052] Meanwhile, during the second period P2 of the pull-up period PUP, unlike the second N-type transistor NTR2, the first N-type transistor NTR1 may be turned off. Therefore, compared with the first period P1, the level of the voltage applied to the first node N1 during the second period P2 of the pull-up period PUP may decrease, but may be at a high level. During the pull-down period PDP, the first N-type transistor NTR1 and the second N-type transistor NTR2 may be turned off, the first transistor TR1 and the second transistor TR2 may be turned on, and the level of the voltage applied to the first node N1 may decrease.

[0053] Figure 7 is a circuit diagram of an output driver 400 according to an embodiment. Referring to Figure 7 , the output driver 400 may include a selection circuit 410, a first pull-up driver circuit 420, a second pull-up driver circuit 430, a first decoupling capacitor DECAP1, a capacitance optimization circuit 440, and a pull-down driver circuit (or pull-down circuit) 450. The selection circuit 410, the first decoupling capacitor DECAP1, the capacitance optimization circuit 440, and the pull-down driver circuit 450 may be the same as the selection circuit, the first decoupling capacitor, the capacitance optimization circuit, and the pull-down driver circuit described above.

[0054] In addition, the first pull-up driver circuit 420 may include a first N-type transistor NTR1 and a first P-type transistor PTR1. The first N-type transistor NTR1 is the same as that referred to above with reference to Figures 3 to 6 . The first P-type transistor PTR1 may "gate" the first power supply voltage VDDQ1 based on a third control signal CTL3; the first P-type transistor PTR1 may include a first electrode, a second electrode, and a gate electrode. The first electrode of the first P-type transistor PTR1 may be connected to the third node N3, and the first power supply voltage VDDQ1 may be applied to the first electrode of the first P-type transistor PTR1. The second electrode of the first P-type transistor PTR1 may be connected to the first electrode of the first N-type transistor NTR1. The third control signal CTL3 may be applied to the gate electrode of the first P-type transistor PTR1. The third control signal CTL3 may be generated and output by a control logic circuit. When the third control signal CTL3 has a conductive level (for a PMOS device), the first P-type transistor PTR1 may be turned on, and the third node N3 and the first electrode of the first N-type transistor NTR1 may be connected to each other to support the pull-up function.

[0055] The second pull-up driver circuit 430 may include a second N-type transistor NTR2, a second P-type transistor PTR2, and a third N-type transistor NTR3. The second N-type transistor NTR2 is the same as that referred to above with reference to Figures 3 to 6 . The second P-type transistor PTR2 may gate the second power supply voltage VDDQ2 based on a fourth control signal CTL4 in LTT or CTT. The second P-type transistor PTR2 may include a first electrode, a second electrode, and a gate electrode. The first electrode of the second P-type transistor PTR2 may be connected to the second node N2, and the second power supply voltage VDDQ2 may be applied to the first electrode of the second P-type transistor PTR2. The second electrode of the second P-type transistor PTR2 may be connected to the first electrode of the second N-type transistor NTR2. The fourth control signal CTL4 may be input to the gate electrode of the second P-type transistor PTR2. In one embodiment, in PI-LTT, the fourth control signal CTL4 may have a cut-off level.

[0056] The third N-type transistor NTR3 can "gate" the second power supply voltage VDDQ2 in the PI-LTT based on the fifth control signal CTL5. The third N-type transistor NTR3 can include a first electrode, a second electrode, and a gate electrode. The first electrode of the third N-type transistor NTR3 can be connected to the second node N2, and the second electrode of the third N-type transistor NTR3 can be connected to the first electrode of the second N-type transistor NTR2. The fifth control signal CTL5 can be input to the gate electrode of the third N-type transistor NTR3. In one embodiment, the fifth control signal CTL5 can have a cut-off level in the LTT and the CTT. According to the above embodiment, the power consumption of the output driver 400 can be controlled by implementing power gating.

[0057] Figure 8 is for explaining Figure 7 a diagram of the first termination and the second termination of the output driver 400. Referring to Figure 8 FIG. , the first termination according to the embodiment can be the LTT, and the second termination can be the CTT. In the LTT or the CTT, the first pull-up drive signal PU1 and the third control signal CTL3 can be input to the first pull-up driver circuit 420, and the second pull-up drive signal PU2, the fourth control signal CTL4, and the fifth control signal CTL5 can be input to the second pull-up driver circuit 430. At this time, the fifth control signal CTL5 can have a cut-off level. The first pull-down signal PD1 and the second pull-down signal PD2 can be input to the pull-down driver circuit 450. At the same time, the third node N3 and the fourth node N4 can be electrically disconnected by the turned-off switch SWT.

[0058] During the pull-up period PUP, the first pull-up driver circuit 420 can connect the first node N1 to the third node N3. During the pull-up period PUP, the second pull-up driver circuit 430 can connect the first node N1 to the second node N2. The pull-down circuit 450 can electrically disconnect the first node N1 and the line to which the third power supply voltage VSSQ is applied. During the pull-down period PDP, the pull-down circuit 450 can connect the first node N1 to the line to which the third power supply voltage VSSQ is applied. The first pull-up driver circuit 420 and the second pull-up driver circuit 430 can electrically disconnect the first node N1, the second node N2, and the third node N3.

[0059] Figure 9 is for explaining Figure 7 a diagram of the third termination of the output driver 400. Referring to Figure 9, the third termination according to an embodiment may be a PI-LTT. In the PI-LTT, the pulse signal SPS and the third control signal CTL3 may be input to the first pull-up driver circuit 420, and the second pull-up drive signal PU2, the fourth control signal CTL4, and the fifth control signal CTL5 may be input to the second pull-up driver circuit 430. At this time, the first N-type transistor NTR1 may be turned on only during the period when the pulse signal SPS is input, and the third control signal CTL3 may have an on level only when the pulse signal SPS is input. The fourth control signal CTL4 may have an off level. The third node N3 and the fourth node N4 may be connected to each other through the turned-on switch SWT, and the second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 may be connected in parallel.

[0060] During the first period P1 of the pull-up period PUP, the first pull-up driver circuit 420 may connect the first node N1 to the third node N3. The first period may be the period when the pulse signal SPS is input. During the second period P2 after the first period P1 of the pull-up period PUP, the first pull-up driver circuit 420 may electrically disconnect the first node N1 and the third node N3. During the pull-up period PUP, the second pull-up driver circuit 430 may connect the first node N1 to the second node N2, and the pull-down circuit 450 may electrically disconnect the first node N1 and the line to which the third power supply voltage VSSQ is applied. During the pull-down period PDP, the pull-down circuit 450 may connect the first node N1 to the line to which the third power supply voltage VSSQ is applied. The first pull-up driver circuit 420 and the second pull-up driver circuit 430 may electrically disconnect the first node N1, the second node N2, and the third node N3.

[0061] Figure 10 is a circuit diagram of the output driver 500 according to an embodiment. Referring to Figure 10 , the output driver 500 may include a selection circuit 510, a first pull-up driver circuit 520, a second pull-up driver circuit 530, a first decoupling capacitor DECAP1, a capacitance optimization circuit 540, and a pull-down driver circuit (or pull-down circuit) 550. The output driver 500 may support all the first to third terminations (e.g., LTT, CTT, and PI-LTT). The selection circuit 510, the first decoupling capacitor DECAP1, the capacitance optimization circuit 540, and the pull-down driver circuit 550 may be the same as the above-described selection circuit, first decoupling capacitor, capacitance optimization circuit, and pull-down driver circuit.

[0062] The first pull-up driver circuit 520 may include a first N-type transistor NTR1 and a first P-type transistor PTR1. The first N-type transistor NTR1 is the same as that referred to above with reference to Figures 3 to 6The same as described. The first P-type transistor PTR1 may include a first electrode, a second electrode, and a gate electrode. The first electrode of the first P-type transistor PTR1 may be connected to the first electrode of the first N-type transistor NTR1 and the third node N3. The second electrode of the first P-type transistor PTR1 may be connected to the first node N1. The third pull-up drive signal PU3 may be applied to the gate electrode of the first P-type transistor PTR1. In one embodiment, the first N-type transistor NTR1 may be a pull-up driver for supporting LTT, and the first P-type transistor PTR1 may be a pull-up driver for supporting CTT.

[0063] The second pull-up driver circuit 530 may include a second N-type transistor NTR2 and a second P-type transistor PTR2. The second N-type transistor NTR2 is the same as that described above with reference to Figures 3 to 6 The same as described. The second P-type transistor PTR2 may include a first electrode, a second electrode, and a gate electrode. The first electrode of the second P-type transistor PTR2 may be connected to the first electrode of the second N-type transistor NTR2 and the second node N2. The second electrode of the second P-type transistor PTR2 may be connected to the first node N1. The fourth pull-up drive signal PU4 may be applied to the gate electrode of the second P-type transistor PTR2. In one embodiment, the second N-type transistor NTR2 may be a pull-up driver for supporting LTT, and the second P-type transistor PTR2 may be a pull-up driver for supporting CTT.

[0064] According to the above embodiments, multiple terminations (e.g., the first to the third terminations) can all be supported, thereby reducing the time and cost required for mass-producing products that match the memory standard and providing user convenience and high satisfaction.

[0065] Figure 11 is a diagram for explaining Figure 10 the first termination of the output driver 500. Referring to Figure 11 , the first termination according to an embodiment may be LTT. In LTT, the first pull-up drive signal PU1 and the third pull-up drive signal PU3 may be input to the first pull-up driver circuit 520, and the second pull-up drive signal PU2 and the fourth pull-up drive signal PU4 may be input to the second pull-up driver circuit 530. At this time, both the third pull-up drive signal PU3 and the fourth pull-up drive signal PU4 may have a cut-off level. The first pull-down signal PD1 and the second pull-down signal PD2 may be input to the pull-down driver circuit 550. At the same time, the third node N3 and the fourth node N4 may be electrically disconnected through the turned-off switch SWT.

[0066] During the pull-up period PUP, the first N-type transistor NTR1 may connect the first node N1 to the third node N3, and the second N-type transistor NTR2 may connect the first node N1 to the second node N2. The pull-down circuit 550 may electrically disconnect the first node N1 and the line to which the third power supply voltage VSSQ is applied. Conversely, during the pull-down period PDP, the pull-down circuit 550 may connect the first node N1 to the line to which the third power supply voltage VSSQ is applied. The first N-type transistor NTR1 and the second N-type transistor NTR2 may electrically disconnect the first node N1, the second node N2, and the third node N3.

[0067] Figure 12 is a diagram for explaining Figure 10 the second termination of the output driver 500. Referring to Figure 12 , the second termination according to an embodiment may be CTT. In CTT, the first pull-up drive signal PU1 and the third pull-up drive signal PU3 may be input to the first pull-up driver circuit 520, and the second pull-up drive signal PU2 and the fourth pull-up drive signal PU4 may be input to the second pull-up driver circuit 530. At this time, the second pull-up drive signal PU2 may have a cut-off level. The first pull-down drive signal PD1 and the second pull-down drive signal PD2 may be input to the pull-down driver circuit 550. Meanwhile, the third node N3 and the fourth node N4 may be electrically disconnected by the turned-off switch SWT.

[0068] During the pull-up period PUP, the first P-type transistor PTR1 may connect the first node N1 to the third node N3, and the second P-type transistor PTR2 may connect the first node N1 to the second node N2. The pull-down circuit 550 may electrically disconnect the first node N1 and the line to which the third power supply voltage VSSQ is applied. Conversely, during the pull-down period PDP, the pull-down circuit 550 may connect the first node N1 to the line to which the third power supply voltage VSSQ is applied. The first P-type transistor PTR1 and the second P-type transistor PTR2 may electrically disconnect the first node N1, the second node N2, and the third node N3.

[0069] Figure 13 is a diagram for explaining Figure 10 the third termination of the output driver 500. Referring to Figure 13, the third termination according to an embodiment may be PI-LTT. In PI-LTT, a pulse signal SPS may be input to the first pull-up driver circuit 520, and a second pull-up drive signal PU2 and a fourth pull-up drive signal PU4 may be input to the second pull-up driver circuit 530. At this time, the first N-type transistor NTR1 may be turned on only during the period when the pulse signal SPS is input. Both the third pull-up drive signal PU3 and the fourth pull-up drive signal PU4 may have a cut-off level. The second decoupling capacitor DECAP2 and the third decoupling capacitor DECAP3 may be connected in parallel through the turned-on switch SWT.

[0070] During a first period P1 of the pull-up period PUP, the first N-type transistor NTR1 may connect the first node N1 to the third node N3. During a second period P2 of the pull-up period PUP, the first N-type transistor NTR1 may electrically disconnect the first node N1 and the third node N3. During the pull-up period PUP, the second N-type transistor NTR2 may connect the first node N1 to the second node N2, and the pull-down circuit 550 may electrically disconnect the first node N1 and the line to which the third power supply voltage VSSQ is applied. However, during the pull-down period PDP, the pull-down circuit 550 may connect the first node N1 to the line to which the third power supply voltage VSSQ is applied. The first N-type transistor NTR1 and the second N-type transistor NTR2 may electrically disconnect the first node N1, the second node N2, and the third node N3.

[0071] Figure 14 is a circuit diagram of an output driver 600 according to an embodiment. Referring to Figure 14 , the output driver 600 may include a selection circuit 610, a first pull-up driver circuit 620, a second pull-up driver circuit 630, a first decoupling capacitor DECAP1, a capacitance optimization circuit 640, and a pull-down driver circuit 650. The output driver 600 may support all first terminations to third terminations (e.g., LTT, CTT, and PI-LTT). The selection circuit 610, the first decoupling capacitor DECAP1, the capacitance optimization circuit 640, and the pull-down driver circuit 650 may be the same as the selection circuit, the first decoupling capacitor, the capacitance optimization circuit, and the pull-down driver circuit described above.

[0072] The first pull-up driver circuit 620 may include a first N-type transistor NTR1, a first P-type transistor PTR1, and a second P-type transistor PTR2. The first N-type transistor NTR1 is the same as that described above with reference to Figures 3 to 6 The first P-type transistor PTR1 is the same as that described above with reference to Figures 7 to 9 The second P-type transistor PTR2 is the same as that described above with reference to Figures 10 to 13is the same as the first P-type transistor PTR1 described above. The second pull-up driver circuit 630 may include a second N-type transistor NTR2, a third P-type transistor PTR3, a third N-type transistor NTR3, and a fourth P-type transistor PTR4. The second N-type transistor NTR2 is the same as that described above with reference to Figures 3 to 6 above. The third P-type transistor PTR3 and the third N-type transistor NTR3 are the same as the second P-type transistor PTR2 and the third N-type transistor NTR3 described above with reference to Figures 7 to 9 above, respectively. The fourth P-type transistor PTR4 is the same as the second P-type transistor PTR2 described above with reference to Figures 10 to 13 above. The transistors included in each of the first pull-up driver circuit 620 and the second pull-up driver circuit 630 may be referred to as pull-up drivers.

[0073] Figure 15 is a diagram illustrating an output driver 700 according to an embodiment. Referring to Figure 15 , the output driver 700 may include a selection circuit 710, a first pull-up driver circuit 720, a second pull-up driver circuit 730, a first decoupling capacitor DECAP1, a capacitance optimization circuit 740, a pull-down driver circuit 750, and an equalization circuit 760. The selection circuit 710, the first pull-up driver circuit 720, the second pull-up driver circuit 730, the first decoupling capacitor DECAP1, the capacitance optimization circuit 740, and the pull-down driver circuit 750 are the same as those described above with reference to Figure 1 above.

[0074] The equalization circuit 760 may output a pulse signal SPS based on a sixth control signal CTL6 so as to cancel the characteristics of the low-pass filter of the channel and amplify the high-frequency components of the data output to the outside. The sixth control signal CTL6 may be generated and output by control logic. The equalization circuit 760 may be referred to as an equalizer. In one embodiment, the equalization circuit 760 may be implemented as a feed-forward equalizer (FFE). However, the equalization circuit 760 is not limited thereto, and in other embodiments, it may also be implemented as an equalizer such as decision feedback equalization (DFE), continuous-time linear equalization (CTLE), etc. In one embodiment, the equalization circuit 760 may operate or stop operating as needed in PI-LTT.

[0075] According to the above embodiments, separating the power regarding the equalization path can result in providing an equalizer that is robust to SI, optimizing the capacitance required by the output driver 700, and allocating, as power, the additional space and capacitors to be ensured by the output driver 700 to the on-chip area of the semiconductor chip including the output driver 700 according to the optimized capacitors. Additionally, according to the above embodiments, equalization can be achieved while maintaining the resistance (e.g., Ron) of the pull-up driver at a value defined in the memory standard (e.g., 37.5 Ω), and thus, SI can be robust without increasing the input / output capacitance (Cio) and chip size. Additionally, according to the above embodiments, equalization is achieved in the PI-LTT due to the transistors included in the first pull-up driver circuit 720, and thus, the number of transistors required to achieve equalization can be reduced, thereby reducing the size and power consumption of the semiconductor chip.

[0076] Figure 16 is a block diagram of the interface circuit 1 according to an embodiment. Referring to Figure 16 , the interface circuit 1 can communicate with the outside. The interface circuit 1 can include a pre-driver circuit 10 and an output driver circuit 11. The pre-driver circuit 10 can output a plurality of driving signals DSs based on the internal data IDATA and the clock signal CLK. The internal data IDATA can be, for example, data stored in a plurality of memory cells. The clock signal CLK can be, for example, a data strobe signal and can be output from the memory cell array. The plurality of driving signals DSs can include a pull-up driving signal and a pull-down driving signal.

[0077] The output driver circuit 11 can output data DATA based on the plurality of driving signals DSs and the plurality of control signals CTLs received from the outside. The data can be sent to the outside through the data pin DQ_PIN and the channel. As described in the embodiments shown above with reference to Figures 1 to 15 , some embodiments of the inventive concept can be applied to the output driver circuit 11.

[0078] Figure 17 is a diagram of the non-volatile memory 200 according to an embodiment. Referring to Figure 17 , the non-volatile memory 200 can include a memory cell array 210, a control logic (or control logic circuit) 220, a voltage generator 230, a row decoder 240, and a page buffer circuit (or page buffer) 250. In alternative or additional embodiments, the non-volatile memory 200 can include a data input / output (I / O) circuit and / or an I / O interface 260.

[0079] The memory cell array 210 may include a plurality of memory cells and be connected to word lines WL, string selection lines SSL, ground selection lines GSL, and a plurality of bit lines BL. For example, the memory cell array 210 may be connected to a row decoder 240 via word lines WL, string selection lines SSL, and ground selection lines GSL, and connected to a page buffer circuit 250 via a plurality of bit lines BL. The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz (hereinafter, generally referred to as "BLK"), where z is an integer greater than zero (0). For example, each of the plurality of memory blocks BLK may have a three-dimensional (3D) structure (or a vertical structure). That is, each memory block BLK may include a structure extending in a first direction to a third direction. For example, each memory block BLK may include a plurality of NAND strings extending in a third direction. In one embodiment, the plurality of NAND strings may be separated from each other by a predetermined distance in a first direction and a second direction. The plurality of memory blocks BLK may be selected by the row decoder 240. For example, the row decoder 240 may select a memory block corresponding to a block address from the plurality of memory blocks BLK.

[0080] Each memory cell included in the memory cell array 210 may store at least one bit. For example, each memory cell may be a single-level cell (SLC) configured to store one (1) bit of data. For another example, each memory cell may be a multi-level cell (MLC) configured to store two (2) bits of data. For yet another example, each memory cell may be a triple-level cell (TLC) configured to store three (3) bits of data. For yet another example, each memory cell may be a quad-level cell (or quadruple-level cell) (QLC) configured to store four (4) bits of data. However, the inventive concept is not limited in this regard. That is, the memory cells included in the memory cell array 210 may be configured to store more than four (4) bits of data.

[0081] The plurality of memory blocks BLK may include at least one of a single-level cell block including SLCs, a multi-level cell block including MLCs, a triple-level cell block including TLCs, and a quad-level cell block including QLCs. That is, among the plurality of memory blocks BLK included in the memory cell array 210, some memory blocks may be SLC blocks, and other memory blocks may be MLC blocks, TLC blocks, and / or QLC blocks.

[0082] In one embodiment, the memory cell array 210 may be configured to place a plurality of memory cells in an erased state when an erase voltage is applied to the memory cell array 210. Optionally or additionally, the memory cell array 210 may be configured to place a plurality of memory cells in a programmed state when a program voltage is applied to the memory cell array 210. In this case, each memory cell may have an erased state or at least one programmed state according to the threshold voltage. That is, the state of each memory cell may include an erased state and at least one programmed state, and the predetermined state of each memory cell may be an erased state or a predetermined programmed state.

[0083] The control logic 220 may control various operations in the non-volatile memory 200. For example, the control logic 220 may write data to the memory cell array 210 and / or output various control signals for reading data from the memory cell array 210 based on the command CMD, the address ADDR, and the control signal CTRL.

[0084] The various control signals output from the control logic 220 may be provided to the voltage generator 230, the row decoder 240, and the page buffer circuit 250. The control logic 220 may provide the voltage control signal CTRL_vol to the voltage generator 230.

[0085] In some embodiments, the control logic 220 may further include a cell counter (not shown). The cell counter may count the number of memory cells falling within a predetermined threshold voltage range according to the data sensed by the page buffer circuit 250. The cell counter may generate a memory cell count value indicating the number of memory cells. In one embodiment, the counted memory cells may be referred to as OFF cells. In an alternative or additional embodiment, the counted memory cells may be referred to as ON cells.

[0086] The voltage generator 230 may be electrically connected to the memory cell array 210 through a plurality of word lines WL. The voltage generator 230 may generate various voltages for performing a program operation, a read operation, and an erase operation on the memory cell array 210 based on the voltage control signal CTRL_vol. The voltage generator 230 may generate a word line voltage VWL (e.g., a program voltage, a verify voltage, a read voltage, and an erase voltage).

[0087] The program voltage, the verify voltage, the read voltage, and the erase voltage that may be generated by the voltage generator 230 may be provided to the selected word lines among the plurality of word lines WL. The selected word lines may be at least one word line selected by the row address X-ADDR. The selected word lines may be referred to as selected word lines.

[0088] During an erase operation, the voltage generator 230 may apply an erase voltage to the wells and / or common source lines of the memory block. Optionally or additionally, the voltage generator 230 may apply an erase permission voltage (e.g., ground voltage) to the word lines WL of the memory block or the word lines WL corresponding to some sub-blocks based on the erase address. During an erase verification operation, the voltage generator 230 may apply an erase verification voltage to the word lines WL of a memory block or apply the erase verification voltage on a per-word-line basis.

[0089] During a programming operation, the voltage generator 230 may apply a programming voltage to the selected word lines among a plurality of word lines WL, and apply a programming pass voltage to the unselected word lines among the plurality of word lines WL. During a programming verification operation, the voltage generator 230 may apply a programming verification voltage to the selected word lines, and apply a verification pass voltage to the unselected word lines. During a normal read operation, the voltage generator 230 may apply a read voltage to the selected word lines, and apply a read pass voltage to the unselected word lines. During a data recovery read operation, the voltage generator 230 may apply a read pass voltage to the selected word lines, and apply a read voltage to at least one word line adjacent to the selected word line. Optionally or additionally, the voltage generator 230 may apply a read voltage to the selected word lines, and apply a read voltage to at least one word line adjacent to the selected word line. The word lines adjacent to the selected word line may be referred to as adjacent word lines.

[0090] The row decoder 240 may select a predetermined word line from the word lines WL in response to the row address X-ADDR received from the control logic 220. For example, during a programming operation, the row decoder 240 may provide a programming voltage to the selected word line. Optionally or additionally, the row decoder 240 may select some of the string select lines SSL and / or some of the ground select lines GSL in response to the row address X-ADDR received from the control logic 220.

[0091] The page buffer circuit 250 may be connected to the memory cell array 210 through a plurality of bit lines BL. The page buffer circuit 250 may select some bit lines from the plurality of bit lines BL in response to the column address Y-ADDR received from the control logic 220. During a verification operation (e.g., an erase verification operation and / or a programming verification operation) and / or a read operation, the page buffer circuit 250 may operate as a sense amplifier and sense the data stored in the selected memory cells through the selected bit lines. Further, during a programming operation, the page buffer circuit 250 may operate as a write driver and input the desired data into the memory cell array 210. The page buffer circuit 250 may include a plurality of page buffers. For example, each page buffer may be connected to at least one bit line.

[0092] The page buffer circuit 250 may store data read from the memory cell array 210 and / or store data to be stored in the memory cell array 210. The page buffer circuit 250 may include a plurality of page buffers respectively connected to a plurality of bit lines BL. The plurality of page buffers may be positioned to respectively correspond to the plurality of bit lines BL. Each page buffer may include a plurality of latches. Hereinafter, the page buffer circuit 250 may be defined as including a page buffer connected to each bit line BL. However, in some embodiments, the term may be defined differently. For example, one page buffer may be set to correspond to a plurality of bit lines BL, and a unit of components arranged to correspond to each bit line BL may be defined as a page buffer unit. In one embodiment, the control logic 220, the voltage generator 230, the row decoder 240, and the page buffer circuit 250 may be included in the peripheral circuit. In one example, the data I / O circuit 260 may be connected to the page buffer 250 through data lines DLs, and may provide data DQ to the page buffer 250 and / or output the data DQ to the outside based on a plurality of control signals CTLs received from the control logic 220. As described in the embodiments illustrated above with reference to Figures 1 to 16 As described in the embodiments shown in, some embodiments of the inventive concept may be applied to the data I / O circuit and / or the I / O interface 260.

[0093] Figure 18 is a block diagram of a storage system 2000 according to an embodiment. Referring to Figure 18 , the storage system 2000 may include a host 2100 and a storage device 2200. In one embodiment, the storage device 2200 may include a storage controller 2210 and a non-volatile memory (e.g., NVM 2220). In alternative or additional embodiments, the host 2100 may include a host controller 2110 and a host memory 2120. The host memory 2120 may be used as a buffer memory configured to temporarily store data to be sent to the storage device 2200 and / or data sent from the storage device 2200.

[0094] The storage device 2200 may include a storage medium configured to store data in response to a request from the host 2100. For example, the storage device 2200 may include at least one of an SSD, an embedded memory, and a removable external memory. For example, when the storage device 2200 is an SSD, the storage device 2200 may be a device compliant with the NVMe standard. Optionally or additionally, when the storage device 2200 is an embedded memory or an external memory, the storage device 2200 may be a device compliant with the Universal Flash Storage (UFS) standard or the Embedded Multimedia Card (eMMC) standard. Each of the host 2100 and the storage device 2200 may generate a packet according to an adopted standard protocol and send the packet.

[0095] When the NVM 2220 of the storage device 2200 may include flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. Optionally or additionally, the storage device 2200 may include various other types of non-volatile memory. For example, the storage device 2200 may include, but is not limited to, magnetic (or magnetoresistive) RAM (random access memory) (MRAM), spin transfer torque MRAM (STT-MRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (FRAM), phase change RAM (PRAM), and resistive RAM (RRAM).

[0096] According to an embodiment, the host controller 2110 and the host memory 2120 may be implemented as separate semiconductor chips. Optionally or additionally, in some embodiments, the host controller 2110 and the host memory 2120 may be integrated into the same semiconductor chip. For example, the host controller 2110 may include any one of a plurality of modules included in an application processor. For another example, the application processor may be implemented as a system on a chip (SoC). Optionally or additionally, the host memory 2120 may be an embedded memory included in the application processor, or a non-volatile memory or memory module external to the application processor.

[0097] The host controller 2110 may manage operations of storing data (e.g., write data) in a buffer region of the host memory 2120 in the non-volatile memory 2220 and / or storing data (e.g., read data) in the non-volatile memory 2220 in the buffer region.

[0098] The storage controller 2210 may include a host interface (IF) 2211, a memory interface 2212, and a CPU 2213. In one embodiment, the storage controller 2210 may further include a flash translation layer (FTL) 2214, a packet manager 2215, a buffer memory 2216, an ECC engine 2217, and an advanced encryption standard (AES) engine 2218. The storage controller 2210 may further include a working memory (not shown) in which the FTL 2214 is loaded. The CPU 2213 may execute the FTL 2214 to control write operations and read operations on the NVM 2220.

[0099] The host interface 2211 can send packets to and / or receive packets from the host 2100. Packets sent from the host 2100 to the host interface 2211 can include commands and / or data to be written to the non-volatile memory 2220. Packets sent from the host interface 2211 to the host 2100 can include responses to commands and / or data read from the non-volatile memory 2220. The memory interface 2212 can send data to be written to the non-volatile memory 2220 and / or receive data read from the non-volatile memory 2220. The memory interface 2212 can be configured to conform to one or more standard protocols (such as but not limited to, Toggle and / or Open NAND Flash Interface (ONFI)). As described in the embodiments shown above with reference to Figures 1 to 16 Some embodiments of the inventive concept can be applied to the memory interface 2212, as described in the embodiments shown above.

[0100] The FTL 2214 can perform various functions (such as but not limited to, address mapping operations, wear leveling operations, and garbage collection operations). The address mapping operation can refer to an operation of converting a logical address received from the host 2100 into a physical address for physically storing data in the non-volatile memory 2220. The wear leveling operation can refer to a technique for preventing excessive degradation of a specific block by allowing blocks of the non-volatile memory 2220 to be used evenly. For example, the wear leveling operation can be implemented using a firmware technique for balancing the erase counts of physical blocks. The garbage collection operation can refer to a technique for ensuring available capacity in the non-volatile memory 2220 by erasing an existing block after copying valid data of the existing block to a new block.

[0101] The packet manager 2215 can generate packets according to the protocol of the interface connected to the host 2100, and / or parse various types of information from the packets received from the host 2100. Optionally or additionally, the buffer memory 2216 can temporarily store data to be written to the NVM 2220 and / or data to be read from the NVM 2220. Although in some embodiments, the buffer memory 2216 can be a component included in the storage controller 2210, the buffer memory 2216 can be external to the storage controller 2210.

[0102] The ECC engine 2217 can perform error detection and correction operations on the read data read from the NVM 2220. For example, the ECC engine 2217 can generate parity bits for the write data to be written to the NVM 2220, and the generated parity bits can be stored in the NVM 2220 together with the write data. During the process of reading data from the NVM 2220, the ECC engine 2217 can correct the errors in the read data by using the parity bits read from the NVM 2220 together with the read data, and output the error-corrected read data. The AES engine 2218 can perform at least one of an encryption operation and a decryption operation on the data input to the storage controller 2210 by using a symmetric key algorithm.

[0103] Figure 19 is a block diagram showing at least a part of an electronic system according to an embodiment. Refer to Figure 19, the electronic system 1000 can be implemented as, but not limited to, a laptop computer, a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device. Additionally, the electronic system 1000 can be implemented as a server or a personal computer. The electronic system 1000 can include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, volatile memories 1500a and 1500b, flash memories 1600a and 1600b, I / O devices 1700a and 1700b, and an application processor (AP) 1800 (hereinafter referred to as "AP"). The camera 1100 can capture still images or moving images according to the user's control. The audio processor 1300 can process audio data included in content stored in one or more of the flash memories 1600a and 1600b or provided from a network. The modem 1400 can be configured to modulate and transmit signals to send / receive wired / wireless data, and can demodulate the modulated signals at the receiving end to recover the original signals. The I / O devices 1700a and 1700b can include devices that provide digital input and / or output functions. The AP 1800 can control all or some of the operations of the electronic system 1000. The AP 1800 can control the display 1200 to display a part of the content. When user input is received through the I / O devices 1700a and 1700b, the AP 1800 can perform control operations corresponding to the user input. The AP 1800 can optionally include an accelerator 1820, which is a dedicated circuit for artificial intelligence (AI) data calculation. The volatile memory 1500b can additionally reside in the accelerator 1820. The accelerator 1820 can be a functional block that performs specific functions of the AP 1800. The accelerator 1820 can include a graphics processing unit (GPU), a neural processing unit (NPU), and a data processing unit (DPU). The GPU can be a block dedicated to processing graphics data. The NPU can be a block for professionally performing AI calculations and inferences. The DPU can be a block dedicated to data transfer.

[0104] The AP 1800 can control the volatile memories 1500a and 1500b through commands and mode register settings (e.g., MRS) compliant with JEDEC (Joint Electron Device Engineering Council) standards. Optionally, the AP 1800 can set the DRAM interface protocol to use company-specific functions (such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions). The controller 1810 included in the AP 1800 can correspond to the memory controller 110 described above with reference to Figure 1 description.

[0105] The volatile memories 1500a and 1500b, which may include DRAM, may have relatively smaller latency and bandwidth than the I / O devices 1700a and 1700b or the flash memories 1600a and 1600b. The volatile memories 1500a and 1500b may be initialized at a power-on time point of the electronic system 1000 and may be used as a temporary storage location for an operating system and application data loaded therewith, or may be used as an execution space for various software codes. In the volatile memories 1500a and 1500b, addition / subtraction / multiplication / division operations, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. Additionally, functions for inference may be performed by the volatile memories 1500a and 1500b.

[0106] The flash memories 1600a and 1600b may store pictures taken by the camera 1100 or data transmitted through a data network. Each of the flash memories 1600a and 1600b may include a memory controller 1610 and a flash memory array 1620; one or more operations of the flash memory array 1620 may be controlled by the memory controller 1610. The flash memories 1600a and 1600b may have a larger capacity than the volatile memories 1500a and 1500b. As described in the embodiments referred to above Figures 1 to 18 as shown in the embodiments, some embodiments of the inventive concept may be applied to at least one of the volatile memories 1500a and 1500b, the flash memories 1600a and 1600b, and the I / O devices 1700a and 1700b.

[0107] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An output driver, comprising: A selection circuit configured to: selectively output a first pull-up driving signal or a pulse signal in response to a received first control signal; A first pull-up driver circuit configured to: provide a first power supply voltage to a first node electrically connected to the data pin in response to a first pull-up driving signal or a pulse signal received from the selection circuit; a second pull-up driver circuit configured to: provide a second power supply voltage having a second level to the first node in response to a second pull-up driving signal, the second level being less than or equal to a first level of the first power supply voltage; a first decoupling capacitor having a first terminal electrically connected to a second node to which a second power supply voltage is applied and a second terminal electrically connected to a line to which a third power supply voltage is applied, the third power supply voltage having a third level lower than the first level and the second level; a capacitance optimization circuit configured to: in response to a received second control signal, change a capacitance of a decoupling capacitor having a first terminal electrically connected to a third node to which a first power supply voltage is applied; as well as The pull-down driver circuit is configured to provide a third power supply voltage to the first node in response to a pull-down driving signal.

2. The output driver according to claim 1, wherein: The capacitance optimization circuit includes: a second decoupling capacitor electrically connected between the third node and the line; a third decoupling capacitor electrically connected between a fourth node and the line, the fourth node being electrically connected to the logic circuit; and The switch is configured to electrically connect the third node to the fourth node based on the second control signal.

3. The output driver according to claim 2, wherein: The capacitance of the first decoupling capacitor corresponds to the size of the second pull-up driver circuit, and the capacitance of the second decoupling capacitor corresponds to the size of the first pull-up driver circuit.

4. The output driver according to claim 1, wherein: The first pull-up driver circuit includes a first N-type transistor having a first electrode to which a first power supply voltage is applied, a second electrode electrically connected to a first node, and a gate electrode to which a first pull-up driving signal and a pulse signal are selectively applied one at a time.

5. The output driver according to claim 4, wherein: The first pull-up driver circuit also includes a second P-type transistor including a first electrode electrically connected to the first electrode of the first N-type transistor, a second electrode electrically connected to the first node, and a gate electrode to which a third pull-up driving signal is applied.

6. The output driver according to claim 1, wherein: The second pull-up driver circuit includes a second N-type transistor including a first electrode to which a second power supply voltage is applied, a second electrode electrically connected to the first node, and a gate electrode to which a second pull-up driving signal is applied.

7. The output driver according to claim 6, wherein: The second pull-up driver circuit also includes a fourth P-type transistor including a first electrode electrically connected to the first electrode of the second N-type transistor, a second electrode electrically connected to the first node, and a gate electrode to which a fourth pull-up driving signal is applied.

8. The output driver according to claim 1, in, The selection circuit is configured to output a first pull-up drive signal to the first pull-up driver circuit; wherein the first pull-up driver circuit is configured to electrically connect the first node to the third node during the pull-up period; wherein the second pull-up driver circuit is configured to electrically connect the first node to the second node during the pull-up period; and The second level is equal to the first level.

9. The output driver according to claim 1, in, The selection circuit is configured to output a pulse signal to the first pull-up driver circuit; wherein the first pull-up driver circuit is configured to: in the pull-up period, electrically connect the first node to the third node during a first period corresponding to a pulse width of the pulse signal, and electrically disconnect the first node and the third node during a second period after the first period has elapsed; wherein the second pull-up driver circuit is configured to electrically connect the first node to the second node during the pull-up period; wherein the second level is lower than the first level; and The first capacitance is smaller than the capacitance of the decoupling capacitor.

10. A non-volatile memory device comprising: A memory cell array having a plurality of memory cells in the memory cell array; a control logic circuit configured to output a plurality of control signals in response to the command signal; as well as A data input / output circuit is configured to generate a plurality of drive signals based on a clock signal and internal data output from a memory cell array, and output data based on the plurality of control signals and the plurality of drive signals, the data input / output circuit comprising: a multiplexer configured to output the received first pull-up driving signal or the received pulse signal according to the first control signal; a first pull-up driver including a first electrode electrically connected to a third node to which a first power supply voltage is applied, a second electrode electrically connected to a first node connected to a data pin, and a gate electrode to which a first pull-up driving signal and a pulse signal are selectively applied one at a time; a second pull-up driver including a first electrode electrically connected to a second node to which a second power supply voltage having a second level lower than a first level of the first power supply voltage is applied, a second electrode electrically connected to the first node, and a gate electrode to which a second pull-up driving signal is applied; a first decoupling capacitor having a first capacitance electrically connected to a line to which a third power supply voltage of a third level is applied and to a second node, the third level being lower than the first level and the second level; a second decoupling capacitor electrically connected to the third node and the line, the second decoupling capacitor having a second capacitance greater than or equal to the first capacitance; a third decoupling capacitor having a third capacitance electrically connected to a fourth node and the line; a switch configured to selectively connect the third node to the fourth node or electrically disconnect the third node from the fourth node according to a second control signal; a pull-down driver including a first electrode connected to the first node, a second electrode connected to the line, and a gate electrode to which a pull-down driving signal is applied; and The equalizer is configured to output a pulse signal based on a sixth control signal.

11. The nonvolatile memory device according to claim 10, wherein: When the multiplexer selectively outputs the first pull-up drive signal: The first pull-up driver is configured to electrically connect the first node to the third node during a pull-up period; a second pull-up driver configured to electrically connect the first node to the second node during a pull-up period; and The switch is configured to electrically disconnect the third node from the fourth node.

12. The nonvolatile memory device according to claim 10, wherein: When the multiplexer selectively outputs a pulse signal: The first pull-up driver is configured to: in the pull-up period, electrically connect the first node to the third node during a first period corresponding to a pulse width of the pulse signal, and electrically disconnect the first node from the third node during a second period after the first period has elapsed; The second pull-up driver is configured to: electrically connect the first node to the second node during the pull-up period; and The switch is configured to electrically connect the third node to the fourth node.

13. The nonvolatile memory device according to claim 10, wherein: The data input / output circuit also includes: a third pull-up driver including a first electrode electrically connected to the first electrode of the first pull-up driver, a second electrode electrically connected to the first node, and a gate electrode to which a third pull-up driving signal is applied, and having a type different from that of the first pull-up driver; and a fourth pull-up driver including a first electrode electrically connected to the first electrode of the second pull-up driver, a second electrode electrically connected to the first node, and a gate electrode to which a fourth pull-up drive signal is applied, and having the same type as that of the third pull-up driver; and The type of the first pull-up driver is the same as the type of the second pull-up driver.

14. The non-volatile memory device according to any one of claims 10 to 13, wherein: The first capacitance corresponds to a size of an active area of ​​the second pull-up driver, and the second capacitance corresponds to a size of an active area of ​​the first pull-up driver.

15. A memory controller comprising: A processor configured to: receive data and a command signal from outside the memory controller, output a plurality of control signals based on the command signal, and output a clock signal and data; as well as A memory interface circuit is configured to generate a plurality of drive signals based on data and a clock signal, and output internal data based on the plurality of control signals and the plurality of drive signals, the memory interface circuit comprising: a multiplexer configured to output a first pull-up driving signal or a pulse signal according to a first control signal; a first pull-up driver including a first electrode electrically connected to a third node to which a first power supply voltage is applied, a second electrode electrically connected to a first node connected to a data pin, and a gate electrode to which a first pull-up driving signal and a pulse signal are selectively applied one at a time; a second pull-up driver including a first electrode electrically connected to a second node to which a second power supply voltage having a second level lower than a first level of the first power supply voltage is applied, a second electrode electrically connected to the first node, and a gate electrode to which a second pull-up driving signal is applied; a first decoupling capacitor electrically connected to a line to which a third power supply voltage of a third level is applied and to a second node and having a first capacitance, the third level being lower than the first level and the second level; a second decoupling capacitor electrically connected to the third node and the line and having a second capacitance greater than or equal to the first capacitance; a third decoupling capacitor electrically connected to the fourth node and the line and having a third capacitance; a switch configured to: connect the third node to the fourth node or electrically disconnect the third node from the fourth node according to a second control signal; a pull-down driver including a first electrode electrically connected to the first node, a second electrode electrically connected to the line, and a gate electrode to which a pull-down driving signal is applied; and The equalizer is configured to output a pulse signal based on a sixth control signal.

16. The memory controller of claim 15, in, The multiplexer is configured to output a first pull-up drive signal; Wherein, the first pull-up driver is configured to: during the pull-up period, electrically connect the first node to the third node; wherein the second pull-up driver is configured to: during the pull-up period, electrically connect the first node to the second node; and The switch is configured to electrically disconnect the third node from the fourth node.

17. The memory controller according to claim 15, in, The multiplexer is configured to output a pulse signal; wherein the first pull-up driver is configured to: during the pull-up period, electrically connect the first node to the third node during a first period corresponding to a pulse width of the pulse signal, and electrically disconnect the first node from the third node during a second period after the first period has elapsed; wherein the second pull-up driver is configured to: during the pull-up period, electrically connect the first node to the second node; and The switch is configured to connect the third node to the fourth node.

18. The memory controller of claim 15, wherein: The memory interface circuit also includes: a third pull-up driver including a first electrode electrically connected to the first electrode of the first pull-up driver, a second electrode electrically connected to the first node, and a gate electrode to which a third pull-up driving signal is applied, and having a type different from that of the first pull-up driver; and a fourth pull-up driver including a first electrode electrically connected to the first electrode of the second pull-up driver, a second electrode electrically connected to the first node, and a gate electrode to which a fourth pull-up drive signal is applied, and having the same type as that of the third pull-up driver; and The type of the first pull-up driver is the same as the type of the second pull-up driver.

19. The memory controller of claim 15, wherein: The memory interface circuit also includes: a fifth pull-up driver including a first electrode electrically connected to the third node, a second electrode electrically connected to the first electrode of the first pull-up driver, and a gate electrode to which a third control signal is applied; a sixth pull-up driver including a first electrode electrically connected to the second node, a second electrode electrically connected to the first electrode of the second pull-up driver, and a gate electrode to which a fourth control signal is applied, and having the same type as that of the fifth pull-up driver; and The seventh pull-up driver includes a first electrode electrically connected to the second node, a second electrode electrically connected to the first electrode of the second pull-up driver, and a gate electrode to which the fifth control signal is applied, and has a type different from that of the sixth pull-up driver.

20. The memory controller of any one of claims 15 to 19, wherein: The first capacitance corresponds to a size of an active area of ​​the second pull-up driver, and the second capacitance corresponds to a size of an active area of ​​the first pull-up driver.

Images