Wafer level fan-out package method for high step stacked chip gap protection

Abstract

The application relates to a wafer-level fan-out packaging method for high-step stacked chip gap protection, which comprises the following steps: stacked chip pre-treatment; preparation of a glass carrier plate and a TMV chip; assembly welding; plastic packaging and debonding; and ball mounting of the packaging body. The structure obtained by the packaging method is combined with advanced packaging processes such as 3D printing gap sealing, TMV double-sided wiring, RDL-first and laser ball mounting and traditional fan-out redistribution, screen plate ball mounting and other processes, solves the problems of uneven glue coating and missing ball mounting plane of high-step stacked chips, adopts the RDL-first process, avoids the problem that the high-step surface cannot be spin-coated with photoresist, improves the wiring precision, guarantees the radio frequency performance of the stacked chips, reduces the packaging process difficulty, effectively reduces the thermal shock of the stacked chips in the redistribution process, and finally realizes low loss of the packaging body under 30GHz high frequency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit packaging technology, in particular to a wafer-level fan-out package method for gap protection of high-step stacked chips. BACKGROUND

[0002] Wafer-level fan-out package technology is an advanced semiconductor packaging technology that allows the redistribution layer (RDL) to extend beyond the chip edge, thereby providing higher pin density and wiring flexibility. Wafer-level molding is the basis of fan-out, which combines bare dies into a reconstituted wafer through temporary bonding, molding, and carrier removal steps to construct a finished chip with a larger area and more I / Os. The molding process mainly uses resin material.

[0003] With the development of the wireless communication field, radio frequency devices need to have the characteristics of low loss, large bandwidth, and high reliability. For example, radio frequency switches, antennas, power amplifiers, and other radio frequency devices. Due to the incompatibility of the front-end CMOS factory with resin materials and the need for functional debugging of the components, the upper chip and lower chip component gold ball stacking process needs to be completed in the CMOS factory, and the stacked component functional debugging needs to be completed before the molding process in the back-end packaging factory to form a high-reliability shell. However, the stacking gap of the components will increase the dielectric constant when it enters the molding material, resulting in greater signal loss. In addition, the input and output ports of the stacked chips are located on the GaAs substrate, and there is a large height difference between the silicon cover plate and the GaAs substrate, forming a process "high step". The large height difference of the surface will cause uneven glue coating, incomplete glue coating, bubble formation, and defects at the step, etc. in the fan-out wafer-level package. Moreover, the step height is usually greater than 300 μm, making it extremely difficult to use copper pillars as the input and output ports. Therefore, there is an urgent need to develop a wafer-level fan-out package method for gap protection of high-step stacked chips. SUMMARY

[0004] To solve the above technical problems, the present application provides a wafer-level fan-out package method for gap protection of high-step stacked chips, which is applied to the packaging of high-frequency radio frequency devices and has strong process compatibility, and includes the following steps:

[0005] Step S11: Pre-treatment of stacked chips, sealing the gap of the stacked chips to form a cavity, and placing solder balls on the pads of the stacked chips through laser solder ball placement technology;

[0006] Step S12: Apply a temporary bonding layer on a glass carrier and complete the preparation of the redistribution layer (RDL-first), and at the same time, prepare a TMV chip with a double-sided redistribution layer and place solder balls on the bottom of the TMV chip;

[0007] Step S13: the TMV chip is welded to the re-distribution layer of the glass carrier through the bottom solder ball, and the stacked chip is flip-chip soldered to the top of the TMV chip through the solder ball;

[0008] Step S14: the wafer-level plastic packaging is performed on the welded assembly to form a reconstituted wafer, and then the glass carrier is peeled off through laser debonding;

[0009] Step S15: the re-distribution layer pad exposed after the plastic packaging of the reconstituted wafer is ball-mounted, and the fan-out structure of the package is completed.

[0010] In an embodiment of the present application, in the step S11:

[0011] The gap sealant adopts epoxy resin or thermal conductive glue with a viscosity greater than 1000 Pa·s, and the edge sealing is performed through a 3D printing device or a dispensing machine, and the nozzle inner diameter is smaller than the minimum distance from the pad to the step;

[0012] The laser ball mounting selects a tin-lead alloy solder ball, the reflow peak temperature is 183℃, the solder ball diameter matches the pad diameter, and the ball mounting plane is accurately controlled through laser.

[0013] In an embodiment of the present application, in the step S12:

[0014] The temporary bonding layer of the glass carrier is a photocuring resin, the substrate of the TMV chip is a Core material, the ABF film is covered on both ends of the through hole, and the conductive through hole is formed through electroplating;

[0015] The TMV chip bottom solder ball is a tin-silver alloy, the reflow temperature is 240-260℃, and the ratio of the solder ball height to the diameter is 2:3.

[0016] In an embodiment of the present application, in the step S13:

[0017] The welding of the TMV chip and the glass carrier adopts a hot-press welding technology, and the reflow temperature is 250℃;

[0018] The reflow temperature of the welding of the stacked chip and the TMV chip is lower than the welding temperature of the TMV chip, and a tin-lead alloy solder ball is selected, and the reflow temperature is 183℃.

[0019] In an embodiment of the present application, in the step S14:

[0020] The plastic packaging adopts a cavity smaller than the size of the glass carrier, and the diameter of the reconstituted wafer after the plastic packaging is 3-5μm smaller than the glass carrier;

[0021] The additional laser debonding realizes the separation of the glass carrier and the re-distribution layer by degrading the photocuring resin.

[0022] In one embodiment of the present invention, in step S15:

[0023] The ball placement uses SAC305 material and is achieved through stencil ball placement. The reflow temperature is 245℃, the ball diameter is 120μm, and the melting point is 217-221℃.

[0024] The signal return loss of the package is less than -20dB at 30GHz, and the differential loss is less than -0.2dB.

[0025] In one embodiment of the present invention, the height of the TMV chip is greater than the height of the high step of the stacked chip, and its double-sided redistribution layer is passivated and protected by electroless nickel-palladium-gold plating.

[0026] In one embodiment of the present invention, the stacked chip includes a silicon-based chip and a gallium arsenide chip, and a high-step structure with a height difference greater than 300 μm is formed by stacking gold balls.

[0027] In one embodiment of the invention, the material of the solder balls is configured with a reflow temperature gradient according to the soldering sequence, wherein the melting point of the TMV chip solder balls is higher than that of the stacked chip solder balls.

[0028] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The wafer-level fan-out packaging method of the present invention utilizes 3D printing to seal the gaps of the stacked chips, ensuring that the solder gaps of the stacked chips form cavities, effectively preventing the infiltration of molding compound and causing RF signal transmission loss. Simultaneously, laser balling is used to ball the pads of the stacked chips, compensating for the incompatibility of traditional balling methods with high-step stacked chips. TMV via modules are used to bring out the pads of the stacked chips, reducing the process difficulty of methods such as copper pillar growth. The RDL-first method is used to complete the rewiring requirement, solving the problem that photoresist cannot be spin-coated on the surface of high-step stacked chips, and effectively reducing the thermal shock to the stacked chips during the rewiring process. Attached Figure Description

[0029] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0030] Figure 1 This is a flowchart of the wafer-level fan-out packaging method for high-step stacked chip gap protection according to the present invention;

[0031] Figure 2 This is a front view of the high-step stacked chip described in this invention;

[0032] Figure 3 This is a top view of the high-step stacked chip described in this invention;

[0033] Figure 4This is a schematic diagram of the stacked chip gap sealing and laser ball-planting structure described in this invention;

[0034] Figure 5 This is a schematic diagram of the structure of the glass carrier plate after rewiring according to the present invention;

[0035] Figure 6 This is a schematic diagram of the TMV component structure after rewiring according to the present invention;

[0036] Figure 7 This is a schematic diagram of the bonding of the stacked chip, TMV component, and glass substrate described in this invention;

[0037] Figure 8 This is a schematic diagram of the encapsulation structure after the adhesive component is encapsulated and the glass substrate is debonded, as described in this invention.

[0038] Figure 9 This is a schematic diagram of the encapsulated body after ball implantation as described in this invention;

[0039] Figure 10 This is a simulation diagram of the high-frequency signal return loss of the package described in this invention;

[0040] Figure 11 This is a simulation diagram of the high-frequency signal loss of the package described in this invention.

[0041] As shown in the figure, the markings are: 101-silicon-based chip, 102-gallium arsenide chip, 103-gold ball, 201-pad, 301-sealant, 302-ball placement, 401-glass substrate, 402-pad II, 501-TMV chip, 502-rewiring layer, 503-bottom solder ball, 601-stacked chip package structure. Detailed Implementation

[0042] like Figure 1 As shown, this embodiment provides a wafer-level fan-out packaging method for protecting the gaps in high-step stacked chips. This wafer-level fan-out packaging method is applied to the packaging of high-frequency radio frequency devices and has strong process compatibility. It includes the following steps:

[0043] Step S11: Fabrication and gap sealing of high-step stacked chips

[0044] 1. Pre-processing of stacked chips: such as Figure 2 , 3 As shown, the high-step stacked chip consists of an upper silicon-based chip 101 with dimensions of 2.1 mm in length, 0.8 mm in width, and 0.1 mm in height, and a lower gallium arsenide chip 102 with dimensions of 1.37 mm in length, 0.58 mm in width, and 0.25 mm in height. The two chips are bonded together by gold balls 103, forming a gap of 0.05 mm.

[0045] 2. Gap sealing: Use epoxy adhesive with a viscosity of 1200 Pa·s, such as...Figure 4 As shown, 3D printing equipment is used to seal the gaps and edges of stacked chips with high steps to form cavities. The nozzle inner diameter is 0.08mm (less than the minimum distance of 0.1mm from the pad to the step) to ensure that the colloid does not cover the pads, thus forming a protective cavity.

[0046] 3. Laser Ball Placement: Solder balls 302 are placed onto the stacked chip pads 201 using laser ball placement. The solder balls are made of a tin-lead alloy material, with a tin mass fraction of 63% and a lead mass fraction of 37%, and a reflow peak temperature of 183℃. There is a 300μm high step between the pads and the top of the stacked chip. The pad diameter is only 100μm, and the ball diameter is 100μm.

[0047] Step S12: Fabrication of glass substrate and TMV chip

[0048] 1. Glass substrate treatment: such as Figure 5 As shown, after coating a 12-inch glass substrate 401 with a light-curing resin as a temporary bonding adhesive, RDL-first layer wiring is performed, and a ball pad II 402 with a diameter of 120μm is reserved in the first layer.

[0049] 2. TMV chip fabrication:

[0050] The TMV chip 501 is fabricated using Core material as a substrate and ABF film is laminated over both ends of the via. Its dimensions are 1.11 mm long, 1.36 mm wide, and 0.45 mm high. The bottom pad size is 160 μm, and the top pad size is 160 μm.

[0051] Double-sided rewiring: such as Figure 6 As shown, the TMV chip 501 first performs top-side wiring. After the wiring is completed, the pads are protected by electroplating. A 5μm thick nickel-palladium-gold redistribution layer 502 is electroplated on the top surface of the TMV. Then, bottom-side wiring is performed. After the wiring is completed, electroplating ball placement is required. The opening of the ball placement metal layer is 87μm. According to the opening diameter, the composition of the electroplated ball is Cu 5μm high, Ni 3μm high, and SnAg 52μm high. After reflow, tin-silver bottom solder balls 503 with a ball height of 60μm and a ball diameter of 90μm are formed. The reflow temperature is 240-260℃.

[0052] Step S13: Component welding and assembly

[0053] 1. TMV chip soldering:

[0054] like Figure 7 As shown, flux is applied to the corresponding pads on the glass substrate, and the bottom of the TMV is soldered to the top pad of the glass substrate using hot press welding technology. A reliable connection is formed by reflowing at 250°C in a reflow oven.

[0055] 2. Stacked chip soldering:

[0056] Flux is applied to the corresponding pad positions on the top surface of the TMV, and the stacked chip pads are soldered to the top pads of the TMV using hot press soldering technology. A reliable connection is formed by reflowing at a high temperature of 183°C in a reflow oven.

[0057] Step S14: Encapsulation and Debonding

[0058] 1. Wafer-level molding:

[0059] like Figure 8 As shown, the welded components will be encapsulated as a whole. The 12-inch glass substrate has a diameter of 300μm, and a 297μm diameter disc will be formed on top of the glass wafer through wafer-level encapsulation.

[0060] 2. Laser debonding:

[0061] After encapsulation, laser debonding is used to degrade the coated photocurable resin by laser irradiation, separating the glass substrate and exposing the bottom reserved solder pad II502.

[0062] Step S15: Package ball placement and performance verification

[0063] 1. Ball planting:

[0064] like Figure 9 As shown, ball-mounting was performed on the encapsulated assembly. SAC305 material was selected, with a composition of 96.5% tin, 3% silver, and 0.5% copper by mass. Stencil ball-mounting was used, with a maximum reflow temperature of 245℃ and a ball melting point of 217-221℃. The ball height was 50μm and the diameter was 120μm. Finally, the high-step stacked chip package structure 601 was obtained through dicing.

[0065] 2. Performance Testing:

[0066] Simulation results show that the package achieves a signal return loss of -20dB (1% reflected power) and a differential loss of -0.2dB (95.5% transmission efficiency) at 30GHz, significantly outperforming traditional wire bonding schemes (loss 1.5-2.5dB / mm). (See attached diagram) Figure 10 , Figure 11 (High-frequency signal simulation diagram).

[0067] Specifically, simulation results of the wafer-level fan-out packaging method described in this embodiment show that the return loss at 30GHz is -20dB, indicating minimal signal reflection from the RF chip package and good impedance matching of the transmission line or device. The reflected power is only 1% of the incident power, indicating minimal signal reflection and high transmission efficiency. The differential loss at 30GHz is -0.2dB, indicating very low power loss after the signal passes through the device or transmission line. The output power is approximately 95.5% of the input power, demonstrating high signal transmission efficiency. This proves that this packaging solution is well-suited for high-frequency, high-precision applications of RF chips, facilitating its application in the packaging of high-frequency RF devices such as 5G communication and millimeter-wave radar.

[0068] Compared to traditional packaging solutions, such as wire bonding, which simply connects stacked chips to the redistribution layer carrier without achieving the effect of repackaging stacked chips, wire bonding exhibits typical losses of approximately 1.5-2.5 dB / mm at high frequencies, such as 30 GHz. This is unacceptable in high-frequency, high-precision applications.

[0069] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A wafer-level fan-out packaging method for protecting the gaps in high-step stacked chips, wherein the wafer-level fan-out packaging method is applied to the packaging of high-frequency radio frequency devices and has strong process compatibility, characterized in that, Includes the following steps: Step S11: Pre-processing of stacked chips, sealing the gaps between stacked chips to form cavities, and placing solder balls onto the pads of stacked chips using laser ball placement technology; Step S12: Coat a temporary bonding layer on a glass substrate and complete the fabrication of the redistribution layer. At the same time, fabricate a TMV chip with double-sided redistribution layers and place solder balls on its bottom. Step S13: The TMV chip is soldered to the redistribution layer of the glass substrate using bottom solder balls, and the stacked chip is flip-chip soldered to the top of the TMV chip using solder balls; Step S14: The welded components are encapsulated at the wafer level to form a reconstructed wafer, and then the glass substrate is peeled off by laser debonding; Step S15: Ball-mounting is performed on the exposed redistribution layer pads of the reconstructed wafer after molding to complete the fan-out structure of the package.

2. The wafer-level fan-out packaging method according to claim 1, characterized in that, In step S11: The sealant for the gaps uses epoxy resin or thermally conductive adhesive with a viscosity greater than 1000 Pa·s. The edges are sealed using 3D printing equipment or a dispensing machine, and the inner diameter of the nozzle used is smaller than the minimum distance from the pad to the step. Laser ball placement uses tin-lead alloy solder balls with a reflow peak temperature of 183℃. The diameter of the solder balls matches the diameter of the pads, and the placement plane is precisely controlled by laser.

3. The wafer-level fan-out packaging method according to claim 1, characterized in that, In step S12: The temporary bonding layer of the glass substrate is a photocurable resin, the substrate of the TMV chip is a Core material, the two ends of the through hole are covered with ABF film, and conductive through holes are formed by electroplating. The TMV chip has tin-silver alloy solder balls at the bottom, a reflow temperature of 240-260℃, and a solder ball height to diameter ratio of 2:

3.

4. The wafer-level fan-out packaging method according to claim 1, characterized in that, In step S13: The TMV chip is welded to the glass substrate using thermocompression welding technology, with a reflow temperature of 250°C. The reflow temperature for soldering the stacked chip and the TMV chip is lower than the soldering temperature of the TMV chip. Tin-lead alloy solder balls are used, and the reflow temperature is 183°C.

5. The wafer-level fan-out packaging method according to claim 1, characterized in that, In step S14: The molding process uses a cavity smaller than the glass carrier plate size, and the diameter of the reconstructed disc after molding is 3-5 μm smaller than that of the glass carrier plate. Another method is laser debonding, which separates the glass substrate from the redistribution layer by degrading the photocurable resin.

6. The wafer-level fan-out packaging method according to claim 1, characterized in that, In step S15: The ball placement uses SAC305 material and is achieved through stencil ball placement. The reflow temperature is 245℃, the ball diameter is 120μm, and the melting point is 217-221℃. The signal return loss of the package is less than -20dB at 30GHz, and the differential loss is less than -0.2dB.

7. The wafer-level fan-out packaging method according to claim 1, characterized in that: The height of the TMV chip is greater than the height of the high step of the stacked chip, and its double-sided redistribution layer is passivated and protected by electroless nickel-palladium-gold plating.

8. The wafer-level fan-out packaging method according to claim 1, characterized in that: The stacked chip includes silicon-based chips and gallium arsenide chips, which are stacked with gold balls to form a high-step structure with a height difference greater than 300 μm.

9. The wafer-level fan-out packaging method according to claim 1, characterized in that: The materials of the solder balls are configured with reflow temperature steps according to the welding sequence, wherein the melting point of the TMV chip solder balls is higher than that of the stacked chip solder balls.

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