Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. The lower electrode is formed in the first wiring layer. In a second wiring layer over the first wiring layer, two wirings having a thickness greater than that of the lower electrode are formed. A dielectric film and an upper electrode are formed over the lower electrode between the first wiring layer and the second wiring layer. A resistor element is formed over the two wirings. The lower electrode, the dielectric film, and the upper electrode are used as capacitor elements.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-208796, filed on December 11, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device including capacitor elements and resistor elements formed in a multilayer wiring layer and a method for manufacturing the same.

[0004] In recent semiconductor devices, the number of wiring layers has been increasing. By providing capacitor elements and resistor elements between the wiring layers, an increase in the planar size of the semiconductor device can be suppressed, and miniaturization of the semiconductor device can be promoted.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-191182

[0007] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2023-58091

[0008] Patent Document 1 discloses a capacitor element having a lower electrode, a capacitor dielectric film, and an upper electrode laminated thereon in this order. The lower electrode is formed in a wiring layer and is formed by the same manufacturing steps as those for forming the wiring.

[0009] Patent Document 2 discloses a technique for forming a resistor element made of a material such as silicon chromium (SiCr) between a lower wiring layer and an upper wiring layer. Summary of the Invention

[0010] As in Patent Document 1, for example, capacitor elements are used in high-precision analog circuits that require high relative accuracy. When using the wiring in the same wiring layer as the lower electrode of the capacitor element, the relative accuracy varies depending on the configuration of the wiring, and the characteristics of the capacitor element change. Therefore, there are limitations on the wiring that can be used for the lower electrode. Relative accuracy refers to the magnitude of characteristic variations between multiple elements formed in the same semiconductor substrate. Good relative accuracy means that the characteristic variations between multiple elements are small enough to meet the requirements of high-precision analog circuits.

[0011] In addition, as the resistor element in Patent Document 2, a conductive film with a thickness of approximately 10 nm is used. The resistor element is formed between the upper wiring layer and the lower wiring layer. During the patterning of the upper wiring formed in the upper wiring layer, over-etching is performed, but the thicker the upper wiring, the longer the over-etching time becomes. Therefore, if the thickness of the upper wiring is large and the thickness of the interlayer dielectric film formed on the resistor element is small, there is a risk that the over-etching will reach the resistor element.

[0012] In this case, there is a risk that the thickness of the resistor element decreases or a part of the resistor element disappears, changing the characteristics of the resistor element. Therefore, the placement of the resistor element is restricted. In particular, the shorter the distance between the multiple wiring layers, the more likely the above problems occur.

[0013] Therefore, when a capacitor element and a resistor element are provided between wiring layers, a technique for improving the relative accuracy of the capacitor element and maintaining the characteristics of the resistor element is required to improve the performance of the semiconductor device and ensure the reliability of the semiconductor device.

[0014] From the description of this specification and the drawings, other objects and novel features will become apparent.

[0015] The typical embodiments disclosed in this application will be briefly described as follows.

[0016] In one embodiment, a semiconductor device includes a first wiring formed in a first wiring layer; a second wiring and a third wiring, each formed in a second wiring layer located above the first wiring layer and having a greater thickness than the first wiring; a first dielectric film and a first conductive film formed between the first wiring layer and the second wiring layer and above the first wiring; and a second conductive film formed above the second wiring and the third wiring. The first wiring, the first dielectric film, and the first conductive film serve as a capacitor element, and the second conductive film serves as a first resistor element electrically connected to the second wiring and the third wiring.

[0017] In one embodiment, a method of manufacturing a semiconductor device includes: a step of forming a first interlayer dielectric film over a semiconductor substrate; a step of forming a first wiring and a first dielectric film and a first conductive film sequentially laminated over the first wiring over the first interlayer dielectric film; a step of forming a second interlayer dielectric film covering the first wiring, the first dielectric film, and the first conductive film; a step of forming a second wiring and a third wiring over the second interlayer dielectric film; a step of forming a third interlayer dielectric film covering the second wiring and the third wiring; and a step of forming a second conductive film over the third interlayer dielectric film. The thickness of the first wiring is smaller than the thickness of each of the second wiring and the third wiring, and the first wiring, the first dielectric film, and the first conductive film are used as a capacitor element, and the second conductive film is used as a first resistor element electrically connected to the second wiring and the third wiring.

[0018] According to one embodiment, the performance of the semiconductor device can be improved and the reliability of the semiconductor device can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional view showing a semiconductor device according to a first embodiment.

[0020] Figure 2 is a cross-sectional view showing a main part of a semiconductor device according to a first embodiment.

[0021] Figure 3 is a view showing Figure 2 parameters of each component in

[0022] Figure 4 is a cross-sectional view showing manufacturing steps of a semiconductor device according to a first embodiment.

[0023] Figure 5 is a view showing Figure 4 manufacturing steps after

[0024] Figure 6 is a view showing Figure 5 manufacturing steps after

[0025] Figure 7 is a view showing Figure 6 manufacturing steps after

[0026] Figure 8 is a view showing Figure 7 manufacturing steps after

[0027] Figure 9 is a view showing Figure 8 manufacturing steps after

[0028] Figure 10 is a main part cross-sectional view showing Figure 9 the subsequent manufacturing steps.

[0029] Figure 11 is a main part cross-sectional view showing Figure 10 the subsequent manufacturing steps.

[0030] Figure 12 is a main part cross-sectional view showing Figure 11 the subsequent manufacturing steps.

[0031] Figure 13 is a main part cross-sectional view showing Figure 12 the subsequent manufacturing steps.

[0032] Figure 14 is a main part cross-sectional view showing Figure 13 the subsequent manufacturing steps.

[0033] Figure 15 is a main part cross-sectional view for explaining problems during the manufacturing steps.

[0034] Figure 16 is a main part cross-sectional view for explaining problems during the manufacturing steps.

[0035] Figure 17 is data for explaining the relative accuracy of a capacitor element and a resistor element.

[0036] Figure 18 is a main part cross-sectional view showing a semiconductor device according to the second embodiment.

[0037] Figure 19 is a cross-sectional view showing a semiconductor device according to the third embodiment. Detailed Description of the Embodiment

[0038] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description is omitted. Further, in the following embodiments, unless particularly necessary, the description of the same or similar components will not be repeated in principle.

[0039] In addition, in the present application, the X direction, the Y direction, and the Z direction are described as being perpendicular to each other and orthogonal to each other. The Z direction is orthogonal to the upper surface of the semiconductor substrate SUB. In the present application, the Z direction is described as the vertical direction, the height direction, or the thickness direction of a specific structure.

[0040] First Embodiment

[0041] Structure of the Semiconductor Device

[0042] As Figure 1 shown, the semiconductor device includes a semiconductor substrate SUB, a plurality of transistors 1Q, a multilayer wiring layer formed on the semiconductor substrate SUB, and capacitor elements MIM and resistor elements RS1 formed between the wiring layers.

[0043] The multilayer wiring layer has a plurality of wiring layers. In the first embodiment, the plurality of wiring layers include a wiring layer WL1, a wiring layer WL2, a wiring layer WL3, a wiring layer WL4, a wiring layer WL5, and a wiring layer WL6. The wiring layer WL6 is the uppermost wiring layer of the multilayer wiring layer. The wiring layer WL1 includes a plurality of wirings M1. The wiring layer WL2 includes a plurality of wirings M2. The wiring layer WL3 includes a plurality of wirings M3. The wiring layer WL4 includes a plurality of wirings M4. The wiring layer WL5 includes a plurality of wirings M5. The wiring layer WL6 includes a plurality of wirings M6.

[0044] The semiconductor substrate SUB is made of, for example, p-type single crystal silicon. In the semiconductor substrate SUB, a plurality of element isolation portions are formed, and the plurality of element isolation portions define regions for forming a plurality of semiconductor elements. Further, in the semiconductor substrate SUB, a well region into which p-type or n-type impurities are introduced is formed. In the well region, a source region and a drain region into which p-type or n-type impurities are introduced are formed. Above the well region, a gate electrode is formed through a gate dielectric film. In Figure 1 this, as semiconductor elements, transistors 1Q are formed as MOSFETs (metal oxide semiconductor field effect transistors). The transistor 1Q includes a gate dielectric film, a gate electrode, a source region, and a drain region.

[0045] Above the semiconductor substrate SUB, an interlayer dielectric film IL0 is formed to cover the plurality of transistors 1Q. The interlayer dielectric film IL0 includes, for example, a silicon oxide film. In the interlayer dielectric film IL0, a plurality of plugs PG are formed to connect to the semiconductor substrate SUB. Each of the plurality of plugs PG is buried in a hole formed in the interlayer dielectric film IL0 and includes a laminated film including, for example, a titanium nitride film and a tungsten film. Above the interlayer dielectric film IL0, a plurality of wirings M1 are formed to connect to the plurality of plugs PG.

[0046] An interlayer dielectric film IL1 is formed above the interlayer dielectric film IL0 to cover the plurality of wirings M1. The interlayer dielectric film IL1 includes, for example, a silicon oxide film. A plurality of vias V1 are formed in the interlayer dielectric film IL1 to connect to the plurality of wirings M1. The plurality of vias V1 are buried in holes formed in the interlayer dielectric film IL1 and include a laminated film including, for example, a titanium nitride film and a tungsten film. A plurality of wirings M2 are formed above the interlayer dielectric film IL1 to connect to the plurality of vias V1.

[0047] The interlayer dielectric film IL2 is formed over the interlayer dielectric film IL1 so as to cover the plurality of wirings M2. The interlayer dielectric film IL2 includes, for example, a silicon oxide film. In the interlayer dielectric film IL2, a plurality of vias V2 are formed so as to connect to the plurality of wirings M2. The plurality of vias V2 are buried in holes formed in the interlayer dielectric film IL2 and include a laminated film including, for example, a titanium nitride film and a tungsten film. Over the interlayer dielectric film IL2, a plurality of wirings M3 are formed so as to connect to the plurality of vias V2.

[0048] The interlayer dielectric film IL3 is formed over the interlayer dielectric film IL2 so as to cover the plurality of wirings M3. The interlayer dielectric film IL3 includes, for example, a silicon oxide film. In the interlayer dielectric film IL3, a plurality of vias V3 are formed so as to connect to the plurality of wirings M3. The plurality of vias V3 are buried in holes formed in the interlayer dielectric film IL3 and include a laminated film including, for example, a titanium nitride film and a tungsten film. Over the interlayer dielectric film IL3, a plurality of wirings M4 are formed so as to connect to the plurality of vias V3.

[0049] The plurality of wirings M4 have the lower electrode BE of the capacitor element MIM. The dielectric film IF1 is formed over the lower electrode BE. The dielectric film IF1 is, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film, or a laminated film obtained by appropriately laminating these films. The upper electrode UE is formed over the dielectric film IF1. The upper electrode UE is a conductive film including, for example, a titanium nitride film. The dielectric film IF1 and the upper electrode UE are formed between the wiring layer WL4 and the wiring layer WL5. The lower electrode BE, the dielectric film IF1, and the upper electrode UE serve as the capacitor element MIM.

[0050] The interlayer dielectric film IL4 is formed over the interlayer dielectric film IL3 so as to cover the plurality of wirings M4 and the capacitor element MIM. The interlayer dielectric film IL4 includes, for example, a silicon oxide film. In the interlayer dielectric film IL4, a plurality of vias V4 are formed so as to connect to the plurality of wirings M4. Further, in the interlayer dielectric film IL4, a plurality of vias V4 that connect to the upper electrode UE of the capacitor element MIM are also formed. The plurality of vias V4 are buried in holes formed in the interlayer dielectric film IL4 and include a laminated film including, for example, a titanium nitride film and a tungsten film. Over the interlayer dielectric film IL4, a plurality of wirings M5 are formed so as to connect to the plurality of vias V4.

[0051] The interlayer dielectric film IL5a is formed over the interlayer dielectric film IL4 so as to cover the plurality of wirings M5. The interlayer dielectric film IL5a includes, for example, a silicon oxide film. In the interlayer dielectric film IL5a, local vias LV1 and local vias LV2 are formed so as to connect to different wirings M5, respectively. The local vias LV1 and the local vias LV2 are buried in holes formed in the interlayer dielectric film IL5a and include a laminated film including, for example, a titanium nitride film and a tungsten film.

[0052] On the interlayer dielectric film IL5a, the resistor element RS1 is formed so as to be connected to the local vias LV1 and LV2. That is, the resistor element RS1 is electrically connected to two different wirings M5 via the local vias LV1 and LV2. The resistor element RS1 is a conductive film. The resistor element RS1 includes at least one of a silicon chromium film (SiCr film), a silicon chromium film introduced with carbon (SiCrC film), a nickel chromium film (NiCr film), a titanium nitride film (TiN film), and a tantalum nitride film (TaN film).

[0053] The interlayer dielectric film IL5b is formed on the interlayer dielectric film IL5a so as to cover the resistor element RS1. The interlayer dielectric film IL5b includes, for example, a silicon oxide film. A plurality of vias V5 are formed in the interlayer dielectric film IL5b and the interlayer dielectric film IL5a so as to be connected to the plurality of wirings M5. The plurality of vias V5 are buried in the holes formed in the interlayer dielectric film IL5b and the interlayer dielectric film IL5a, and include a laminated film including, for example, a titanium nitride film and a tungsten film. A plurality of wirings M6 are formed on the interlayer dielectric film IL5b so as to be connected to the plurality of vias V5.

[0054] Figure 2 is Figure 1 An enlarged cross-sectional view of a portion where the capacitor element MIM and the resistor element RS1 are formed. Figure 3 is a cross-sectional view showing the same portion as Figure 2 In Figure 3 some components and some hatching are omitted to facilitate the explanation of the thickness of each wiring and other features.

[0055] As Figure 2 shown, the wiring M4 includes a lower barrier metal film BM4a, a conductive film CF4 formed on the lower barrier metal film BM4a, and an upper barrier metal film BM4b formed on the conductive film CF4. The wiring M5 includes a lower barrier metal film BM5a, a conductive film CF5 formed on the lower barrier metal film BM5a, and an upper barrier metal film BM5b formed on the conductive film CF5. The wiring M6 includes a lower barrier metal film BM6a, a conductive film CF6 formed on the lower barrier metal film BM6a, and an upper barrier metal film BM6b formed on the conductive film CF6.

[0056] The configurations of the wirings M1, M2, and M3 are similar to the configuration of the wiring M4. That is, each of the wirings M1, M2, and M3 has a barrier metal film similar to the lower barrier metal film BM4a, a conductive film similar to the conductive film CF4, and a barrier metal film similar to the upper barrier metal film BM4b.

[0057] The lower barrier metal film BM4a, the lower barrier metal film BM5a, and the lower barrier metal film BM6a each include a titanium film and a titanium nitride film formed on the titanium film. The conductive film CF4, the conductive film CF5, and the conductive film CF6 each include an aluminum film or an aluminum alloy film added with copper or silicon. The upper barrier metal film BM4b, the upper barrier metal film BM5b, and the upper barrier metal film BM6b each include a titanium nitride film.

[0058] The thickness T5 of the wiring M5 is greater than the thickness T4 of the wiring M4. The thickness T6 of the wiring M6 is greater than the thickness T5 of the wiring M5. The wiring layer WL6 is generally used for routing power. To suppress voltage drop, the thickness T6 of the wiring M6 is set to be greater than the thickness of other wirings such as the wiring M4.

[0059] The thickness T4 of the wiring M4 is, for example, 220 nm or greater than 220 nm and 360 nm or less than 360 nm. The thickness of the upper barrier metal film BM4b is, for example, 50 nm or greater than 50 nm and 70 nm or less than 70 nm. The thickness of the conductive film CF4 is, for example, 130 nm or greater than 130 nm and 230 nm or less than 230 nm. The thickness of the lower barrier metal film BM4a is, for example, 40 nm or greater than 40 nm and 60 nm or less than 60 nm.

[0060] The thickness T5 of the wiring M5 is, for example, 550 nm or greater than 550 nm and 690 nm or less than 690 nm. The thickness of the upper barrier metal film BM5b is, for example, 60 nm or greater than 60 nm and 80 nm or less than 80 nm. The thickness of the conductive film CF5 is, for example, 450 nm or greater than 450 nm and 550 nm or less than 550 nm. The thickness of the lower barrier metal film BM5a is, for example, 40 nm or greater than 40 nm and 60 nm or less than 60 nm.

[0061] The thickness T6 of the wiring M6 is, for example, 1000 nm or greater than 1000 nm and 1640 nm or less than 1640 nm. The thickness of the upper barrier metal film BM6b is, for example, 60 nm or greater than 60 nm and 80 nm or less than 80 nm. The thickness of the conductive film CF6 is, for example, 900 nm or greater than 900 nm and 1500 nm or less than 1500 nm. The thickness of the lower barrier metal film BM6a is, for example, 40 nm or greater than 40 nm and 60 nm or less than 60 nm.

[0062] The thickness of the dielectric film IF1 is, for example, 20 nm or greater than 20 nm and 50 nm or less than 50 nm. The thickness of the upper electrode UE is, for example, 50 nm or greater than 50 nm and 150 nm or less than 150 nm. The thickness of the resistor element RS1 is, for example, 5 nm or greater than 5 nm and 20 nm or less than 20 nm.

[0063] The distance L56 between the wiring layer WL5 and the wiring layer WL6 is longer than the distance L45 between the wiring layer WL4 and the wiring layer WL5. The distances between the wiring layer WL1 and the wiring layer WL2, between the wiring layer WL2 and the wiring layer WL3, and between the wiring layer WL3 and the wiring layer WL4 are the same as the distance L45.

[0064] The distance L45 is, for example, 250 nm or greater than 250 nm and 350 nm or less than 350 nm. The distance L45 corresponds to the thickness of the portion of the interlayer dielectric film IL4 located above the wiring M4, and corresponds to the height of the via V4 that electrically connects the wiring M4 and the wiring M5.

[0065] The distance L56 is, for example, 500 nm or greater than 500 nm and 650 nm or less than 650 nm. The distance L56 corresponds to the sum of the thicknesses of the portion of the interlayer dielectric film IL5a located above the wiring M5 and the portion of the interlayer dielectric film IL5b located above the wiring M5, and corresponds to the height of the via V5 that electrically connects the wiring M5 and the wiring M6.

[0066] The distance between the upper electrode UE and the wiring layer WL5 (wiring M5) L5m is, for example, 50 nm or greater than 50 nm and 280 nm or less than 280 nm. The distance L5m corresponds to the thickness of the portion of the interlayer dielectric film IL4 located above the upper electrode UE, and corresponds to the height of the via V4 that electrically connects the upper electrode UE and the wiring M5.

[0067] The distance between the resistor element RS1 and the wiring layer WL5 (wiring M5) L5r is, for example, 200 nm or greater than 200 nm and 230 nm or less than 230 nm. The distance L5r corresponds to the thickness of the portion of the interlayer dielectric film IL5a located above the wiring M4, and corresponds to the heights of the local vias LV1 and LV2 that electrically connect the resistor element RS1 and the wiring M5.

[0068] The distance between the resistor element RS1 and the wiring layer WL6 (wiring M6) L6r is, for example, 250 nm or greater than 250 nm and 445 nm or less than 445 nm. The distance L6r corresponds to the thickness of the portion of the interlayer dielectric film IL5b located above the resistor element RS1.

[0069] It should be noted that the distances L45, L56, L5m, L5r, and L6r are distances in the direction (Z direction) orthogonal to the upper surface of the semiconductor substrate SUB.

[0070] Method for manufacturing a semiconductor device

[0071] As Figure 4As shown, first, a semiconductor substrate SUB is prepared. Next, a plurality of element isolation regions are formed in the semiconductor substrate SUB. Each of the plurality of element isolation regions can be formed by forming a trench in the semiconductor substrate SUB and filling the trench with a dielectric film such as a silicon oxide film. Next, a well region is formed by introducing a p-type or n-type impurity into the semiconductor substrate SUB. Next, a transistor 1Q is formed on the semiconductor substrate as a semiconductor element. For example, a gate electrode is formed over the well region through a gate dielectric film, and a source region and a drain region are formed by introducing a p-type or n-type impurity into the well region.

[0072] Next, for example, by a CVD (chemical vapor deposition) method, an interlayer dielectric film IL0 is formed over the semiconductor substrate SUB to cover the transistor 1Q. Next, a polishing process is performed on the upper surface of the interlayer dielectric film IL0 by a CMP (chemical mechanical polishing) method. Next, a plurality of plugs PG are formed in the interlayer dielectric film IL0.

[0073] To form the plurality of plugs PG, first, holes are formed in the interlayer dielectric film IL0 by photolithography and anisotropic etching processes. Next, for example, by a CVD method, a titanium nitride film and a tungsten film are sequentially formed over the interlayer dielectric film IL0 to fill the holes. Next, the titanium nitride film and the tungsten film located outside the holes are removed by a CMP process. In this way, the plurality of plugs PG are formed.

[0074] As Figure 5 shown, a wiring layer WL1, a wiring layer WL2, and a wiring layer WL3 are sequentially formed over the interlayer dielectric film IL0. First, a lower barrier metal film is formed over the interlayer dielectric film IL0. The lower barrier metal film is a laminated film including a titanium film formed by, for example, a sputtering method and a titanium nitride film formed over the titanium film by, for example, a sputtering method. Next, a conductive film such as an aluminum film or an aluminum alloy film is formed over the lower barrier metal film by, for example, a sputtering method. Then, an upper barrier metal film such as a titanium nitride film is formed over the conductive film by, for example, a sputtering method.

[0075] Next, the upper barrier metal film, the conductive film, and the lower barrier metal film are patterned by photolithography and anisotropic etching processes to form a plurality of wirings M1.

[0076] Next, an interlayer dielectric film IL1 is formed over the interlayer dielectric film IL0 by, for example, a CVD method. Then, a polishing process is performed on the upper surface of the interlayer dielectric film IL1 by a CMP method. Next, a plurality of vias V1 are formed in the interlayer dielectric film IL1.

[0077] To form a plurality of vias V1, first, holes are formed in the interlayer dielectric film IL1 by lithography and anisotropic etching processes. Next, a titanium nitride film and a tungsten film are sequentially formed over the interlayer dielectric film IL1 by, for example, a CVD method so as to fill the holes. Then, a polishing process is performed by a CMP method to remove the titanium nitride film and the tungsten film located outside the holes. In this way, a plurality of vias V1 are formed.

[0078] Thereafter, by a method similar to the method of forming the wiring M1, the interlayer dielectric film IL1, and the via V1, the wiring M2, the interlayer dielectric film IL2, the via V2, the wiring M3, the interlayer dielectric film IL3, and the via V3 are formed.

[0079] As Figure 6 shown, first, a lower barrier metal film BM4a is formed over the interlayer dielectric film IL3. The lower barrier metal film BM4a is a laminated film including a titanium film formed by, for example, a sputtering method and a titanium nitride film formed over the titanium film by, for example, a sputtering method. Next, a conductive film CF4 such as an aluminum film or an aluminum alloy film is formed over the lower barrier metal film BM4a by, for example, a sputtering method. Then, an upper barrier metal film BM4b such as a titanium nitride film is formed over the conductive film CF4 by, for example, a sputtering method. Next, a dielectric film IF1 is formed over the upper barrier metal film BM4b by, for example, a CVD method. Next, a conductive film CFm such as a titanium nitride film is formed over the dielectric film IF1 by, for example, a sputtering method.

[0080] As Figure 7 shown, by selectively patterning the conductive film CFm and the dielectric film IF1, the conductive film CFm patterned as the upper electrode UE of the capacitor element MIM is formed.

[0081] First, a resist pattern RP1 is formed over the conductive film CFm. The resist pattern RP1 has an opening pattern that selectively covers a part of the conductive film CFm. Next, by performing an anisotropic etching process using the resist pattern RP1 as a mask, the conductive film CFm and the dielectric film IF1 exposed from the resist pattern RP1 are removed. The left conductive film CFm is formed as the upper electrode UE. Thereafter, the resist pattern RP1 is removed by ashing.

[0082] As Figure 8 shown, by selectively patterning the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a, a plurality of wirings M4 are formed such that the dielectric film IF1 and the upper electrode UE are left over the upper barrier metal film BM4b. The plurality of wirings M4 include the lower electrode BE of the capacitor element MIM.

[0083] First, a resist pattern RP2 is formed over the upper barrier metal film BM4b. The resist pattern RP2 has an opening pattern that selectively covers the regions where the dielectric film IF1 and the upper electrode UE are formed over the upper barrier metal film BM4b. Next, by using the resist pattern RP2 as a mask, an anisotropic etching process is performed to remove the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a that are exposed from the resist pattern RP2. The upper left barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a are formed as a plurality of wirings M4. Thereafter, the resist pattern RP2 is removed by ashing.

[0084] Although not shown in the figure, patterning may also be performed using a hard mask instead of the resist pattern RP2. First, a dielectric film such as a silicon nitride film is formed over the upper barrier metal film BM4b, for example, by a CVD method. Next, the resist pattern RP2 is formed over the dielectric film. Then, by using the resist pattern RP2 as a mask, an anisotropic etching process is performed to remove the dielectric film that is exposed from the resist pattern RP2. The left dielectric film is formed as a hard mask. Thereafter, the resist pattern RP2 is removed by ashing.

[0085] The hard mask has the same opening pattern as the resist pattern RP2. By using the hard mask to perform an anisotropic etching process, the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a that are exposed from the hard mask are removed. The upper left barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a are formed as a plurality of wirings M4.

[0086] Patterning using a resist pattern or a hard mask processed using a resist pattern is not limited to forming the wiring M4, and can also be performed for forming the wiring M1, the wiring M2, the wiring M3, the wiring M5, or the wiring M6.

[0087] Therefore, through Figures 6 to 8 the manufacturing steps shown, a plurality of wirings M4, the dielectric film IF1, and the upper electrode UE (which are sequentially laminated over the lower electrode BE) are formed over the interlayer dielectric film IL3.

[0088] As Figure 9 shown, the interlayer dielectric film IL4 is formed over the interlayer dielectric film IL3, for example, by a CVD method, so as to cover the plurality of wirings M4 including the lower electrode BE, the dielectric film IF1, and the upper electrode UE. Next, a polishing process is performed on the upper surface of the interlayer dielectric film IL4 by a CMP method. Next, a plurality of vias V4 are formed in the interlayer dielectric film IL4. The method of forming the vias V4 is similar to the method of forming the vias V1.

[0089] As Figure 10As shown, first, a plurality of wirings M5 are formed over the interlayer dielectric film IL4. The method of forming the wiring M5 is similar to the method of forming the wiring M4. However, the thicknesses of the upper barrier metal film BM5b, the conductive film CF5, and the lower barrier metal film BM5a are different from the thicknesses of the upper barrier metal film BM4b, the conductive film CF4, and the lower barrier metal film BM4a, respectively.

[0090] Next, the interlayer dielectric film IL5a is formed over the interlayer dielectric film IL4, for example, by a CVD method, so as to cover the plurality of wirings M5. Next, a polishing process is performed on the upper surface of the interlayer dielectric film IL5a by a CMP method.

[0091] As Figure 11 shown, first, the local vias LV1 and the local via LV2 are formed in the interlayer dielectric film IL5a. The method of forming the local vias LV1 and the local via LV2 is similar to the method of forming the via V1. The local vias LV1 and the local via LV2 are formed so as to be connected to different wirings M5, respectively. Next, the conductive film CFr is formed over the interlayer dielectric film IL5a, for example, by a sputtering method.

[0092] As Figure 12 shown, by selectively patterning the conductive film CFr, the resistor element RS1 connected to the local vias LV1 and the local via LV2 is formed.

[0093] First, the resist pattern RP3 is formed over the conductive film CFr. The resist pattern RP3 has an opening pattern that selectively covers a part of the conductive film CFr. Next, by using the resist pattern RP3 as a mask, an anisotropic etching process is performed to remove the exposed conductive film CFr. The left conductive film CFr is formed as the resistor element RS1. Subsequently, the resist pattern RP3 is removed by ashing.

[0094] As Figure 13 shown, first, the interlayer dielectric film IL5b is formed over the interlayer dielectric film IL5a, for example, by a CVD method, so as to cover the resistor element RS1. Next, a polishing process is performed on the upper surface of the interlayer dielectric film IL5b by a CMP method.

[0095] Next, a plurality of vias V5 are formed in the interlayer dielectric film IL5b and the interlayer dielectric film IL5a. The method of forming the via V5 is similar to the method of forming the via V1. However, the diameter, thickness of the titanium nitride film, and thickness of the tungsten film in the via V5 are different from the diameter, thickness of the titanium nitride film, and thickness of the tungsten film in the via V1.

[0096] As Figure 14As shown, first, the lower barrier metal film BM6a is formed over the interlayer dielectric film IL5b. The lower barrier metal film BM6a is a laminated film including, for example, a titanium film formed over the interlayer dielectric film IL5b by sputtering and a titanium nitride film formed over the titanium film by sputtering. Next, a conductive film CF6 such as an aluminum film or an aluminum alloy film is formed over the lower barrier metal film BM6a by sputtering, for example. Then, an upper barrier metal film BM6b such as a titanium nitride film is formed over the conductive film CF6 by sputtering, for example.

[0097] Thereafter, by selectively patterning the upper barrier metal film BM6b, the conductive film CF6, and the lower barrier metal film BM6a, a plurality of wirings M6 are formed. Thus, the Figure 1 and Figure 2 structure shown is obtained.

[0098] To pattern the plurality of wirings M6, first, a resist pattern is formed over the upper barrier metal film BM6b. The resist pattern has an opening pattern that selectively covers a part of the upper barrier metal film BM6b. Next, by performing an anisotropic etching process using the resist pattern as a mask, the exposed upper barrier metal film BM6b, the conductive film CF6, and the lower barrier metal film BM6a are removed. The upper barrier metal film BM6b, the conductive film CF6, and the lower barrier metal film BM6a are formed into a plurality of wirings M6. Thereafter, the resist pattern is removed by ashing.

[0099] Main features of the semiconductor device

[0100] Formation position of the resistor element RS1

[0101] Theoretically, the resistor element RS1 can be formed between wiring layers, but in the first embodiment, the resistor element RS1 is formed between the wiring layer WL6 and the wiring layer WL5. The reason is explained below using Figure 15 and Figure 16 To form the resistor element RS1 between wiring layers, the following first condition, second condition, and third condition must be satisfied.

[0102] As Figure 15 shown, the first condition is that the over-etch amount OE1 of the anisotropic etching process performed when forming the resistor element RS1 is less than the distance L5r. That is, the over-etching during the patterning of the conductive film CFr does not reach the wiring M5.

[0103] Returning to the reference Figure 12, a resistor element RS1 is formed by performing an anisotropic etching process on the conductive film CFr using the resist pattern RP3 as a mask. At this time, since the etching uniformity varies in the same semiconductor substrate SUB, over-etching is performed so as not to leave unnecessary conductive film CFr. Therefore, the portion of the interlayer dielectric film IL5a exposed from the resistor element RS1 is also etched. The over-etching amount OE1 is, for example, 100 nm or greater than 100 nm and 120 nm or less than 120 nm.

[0104] The second condition is that the over-etching amount OE2 of the anisotropic etching process performed when forming the wiring M6 is less than the distance L6r. That is, the over-etching during the patterning of the wiring M6 does not reach the conductive film CFr.

[0105] For example, the wiring M6 is formed by performing an anisotropic etching process using the resist pattern RP4 as a mask. Here, over-etching is performed so as not to leave unnecessary lower barrier metal film BM6a, etc. Therefore, the portion of the interlayer dielectric film IL5b exposed from the wiring M6 is also etched. The amount of over-etching OE2 is, for example, 60 nm or greater than 60 nm and 80 nm or less than 80 nm.

[0106] As Figure 16 shown, the third condition is to consider the variation in the polishing amount of the CMP method. After forming the interlayer dielectric film, polishing is performed on the upper surface of the interlayer dielectric film, but the uniformity of the polishing amount is different in the same semiconductor substrate SUB. Therefore, when the polishing amount exceeds the set value, it is necessary to consider the amount of over-polishing.

[0107] In order to form the resistor element RS1 between the wiring layers, it is necessary to divide the formation of the interlayer dielectric film into two parts, such as the interlayer dielectric film IL5a and the interlayer dielectric film IL5b. Therefore, since the polishing process by the CMP method is performed twice, it is necessary to calculate the amount of over-polishing for both times.

[0108] When performing the polishing process on the upper surface of each of the interlayer dielectric film IL5a and the interlayer dielectric film IL5b, the over-polishing amount 1 and the over-polishing amount 2 are calculated. For example, if the distance L5r is set to 230 nm, 15% of the distance L5r is calculated as the over-polishing amount 1 (34.5 nm). In addition, if the distance L6r is set to 250 nm, 15% of the distance L6r is calculated as the over-polishing amount 2 (37.5 nm).

[0109] Therefore, considering the first condition, the second condition, and the third condition, it is necessary to separately consider approximately 250 nm as the minimum manufacturing margin between the resistor element RS1 and the wiring layer WL6 and between the resistor element RS1 and the wiring layer WL5.

[0110] As a comparative example, consider the case where the resistor element RS1 is formed between the wiring layer WL4 and the wiring layer WL5. As the semiconductor device is miniaturized, the value of the distance L45 becomes smaller. Therefore, there may be a case where the resistor element RS1 cannot be formed between the wiring layer WL4 and the wiring layer WL5. In addition, even if the resistor element RS1 can be formed, the distance between the resistor element RS1 and the wiring layer WL4 and the distance between the resistor element RS1 and the wiring layer WL5 are short. Therefore, in the case of unexpected defects other than the defects related to the first condition, the second condition, and the third condition, it is difficult to make a design change or take measures. That is, in the comparative example, it is difficult to stably manufacture the resistor element RS1.

[0111] As described above, in the first embodiment, the resistor element RS1 is formed between the wiring layer WL5 and the wiring layer WL6, and the wiring layer WL6 has the longest distance L56 among these layers. Since the resistor element RS1 can be formed with a sufficient manufacturing margin, the characteristics of the resistor element RS1 can be maintained and the reliability of the semiconductor device can be ensured.

[0112] The formation position of the capacitor element MIM

[0113] Figure 17 is data on the relative accuracy of a plurality of capacitor elements MIM formed on the same semiconductor substrate SUB that has been studied by the inventors of the present application. Figure 17 The vertical axis of the graph in shows the Pelgrom coefficient of the capacitor element MIM. The smaller the value of the Pelgrom coefficient, the better the relative accuracy, and the smaller the characteristic variation between the plurality of capacitor elements MIM. The error range is calculated as 3σ of the variation that appears in a plurality of semiconductor substrates SUB.

[0114] The upper surface of the upper barrier metal film is not a completely flat surface, but has irregularities formed thereon. The appearance of these irregularities is due not only to the accuracy of the film formation process of the upper barrier metal film, but also to the irregular surface shape of the lower layer film. Therefore, the fewer the irregularities in the lower layer film, the less likely it is that irregularities will appear in the film that becomes the upper layer. In addition, the fewer the irregularities in the upper barrier metal film, the fewer the irregularities that appear in the dielectric film IF1 and the upper electrode UE formed on the upper barrier metal film. Therefore, the relative accuracy of the capacitor element MIM can be improved.

[0115] Comparing Sample 5 and Sample 4, the thicknesses of the upper barrier metal films of both are the same, and the thicknesses of the conductive films are also the same, but the thickness of the lower barrier metal film of Sample 4 is greater than that of Sample 5. Therefore, the greater the thickness of the lower barrier metal film, the fewer the irregularities that appear in the conductive film and the upper barrier metal film that become the upper layer, and the relative accuracy of the capacitor element MIM is improved.

[0116] In addition, when comparing Sample 5 and Sample 3, the thicknesses of the upper barrier metal films are the same for both, and the thicknesses of the lower barrier metal films are the same. However, the thickness of the conductive film of Sample 3 is smaller than that of Sample 5. Therefore, the smaller the thickness of the conductive film, the fewer irregularities appear in the upper barrier metal film, and the relative accuracy is improved. The result of Sample 2 is almost the same as that of Sample 3.

[0117] Therefore, by comparing Sample 5 and Sample 1, it can be seen that the smaller the thickness of the conductive film and the larger the thickness of the lower barrier metal film, the more effectively the relative accuracy of the capacitor element MIM can be improved. For example, by setting the thickness of the conductive film CF4 to 230 nm or less than 230 nm and setting the thickness of the lower barrier metal film BM4a to 40 nm or more than 40 nm, the relative accuracy of the capacitor element MIM can be more effectively improved.

[0118] The thickness of each wiring is mainly the thickness of a conductive film such as an aluminum film or an aluminum alloy film. Therefore, in the first embodiment, the conductive film CF4 with a thickness smaller than that of the conductive film CF5 and the conductive film CF6 is applied. That is, among the wirings formed in the multilayer wiring layer, the wiring M4 with the smallest thickness is used as the lower electrode BE of the capacitor element MIM. This allows the relative accuracy of the capacitor element MIM to be improved, thereby improving the performance of the semiconductor device.

[0119] Other features regarding the formation positions of the resistor element RS1 and the capacitor element MIM

[0120] The resistor element RS1 and the capacitor element MIM are arranged so as not to overlap each other in a plan view. In other words, the resistor element RS1 is arranged not to be formed directly above the capacitor element MIM.

[0121] During the formation of the interlayer dielectric film IL4, the upper surface of the interlayer dielectric film IL4 is planarized by a polishing process using the CMP method. However, directly above the capacitor element MIM, due to the thickness of the dielectric film IF1 and the thickness of the upper electrode UE, the upper surface of the interlayer dielectric film IL4 is higher than that directly above another wiring M4. Therefore, even after the polishing process, the upper surface of the interlayer dielectric film IL4 located directly above the capacitor element MIM may not be completely planarized.

[0122] In this case, directly above the capacitor element MIM, the convex shape of the upper surface of the interlayer dielectric film IL4 can be reflected in the interlayer dielectric film IL5a, and the upper surface of the interlayer dielectric film IL5a can also have a convex shape. If the resistor element RS1 is formed on the upper surface of the interlayer dielectric film IL5a including such a convex shape, it is difficult to form the resistor element RS1 with a uniform thickness. This can cause variations in the characteristics of the resistor element RS1. If the resistor element RS1 and the capacitor element MIM are formed so as not to overlap each other in a plan view, such risks can be eliminated.

[0123] Preferably, the resistor element RS1 and the capacitor element MIM are formed between different wiring layers. For example, consider the case where the resistor element RS1 and the capacitor element MIM are formed in the wiring layer WL5. If the resistor element RS1 is formed first, since the wiring M4 serving as the lower electrode BE of the capacitor element MIM is covered with the interlayer dielectric film IL5a, additional processes such as partially opening a part of the wiring M4 are required, thus complicating the manufacturing steps.

[0124] On the other hand, if the capacitor element MIM is formed first, it is necessary to completely cover the upper electrode UE of the capacitor element MIM with the interlayer dielectric film IL5a. This is because if the upper electrode UE is exposed from the interlayer dielectric film IL5a, it can be scraped off during the patterning of the resistor element RS1. Then, it is necessary to lengthen the distance L5r, but as the distance L5r is lengthened, the distance L6r becomes shorter, which can expose the resistor element RS1 to over-etching. To eliminate such risks, lengthening the distance L6r results in a longer distance L56 between the wiring layer WL6 and the wiring layer WL5, making it difficult to miniaturize the semiconductor device. In addition, during the formation of the via V5, the depth of the hole becomes larger and the aspect ratio becomes higher, making it difficult to properly fill the hole with a tungsten film or the like.

[0125] Second Embodiment

[0126] The following description will mainly explain the differences from the first embodiment, and the description of the points overlapping with the first embodiment will be omitted.

[0127] As Figure 18 shown, in the second embodiment, the conductive film CFm that serves as the upper electrode UE in the first embodiment is used as the resistor element RS2 electrically connected to different wirings M5. The resistor element RS2 is connected to one via V4, and one via V4 is connected to one wiring M5. In addition, the resistor element RS2 is connected to another via V4, and another via V4 is connected to another wiring M5.

[0128] As Figure 17As shown, similar to the capacitor element MIM, for the resistor element RS2, the smaller the thickness of the conductive film and the larger the thickness of the lower barrier metal film, the higher the relative accuracy that can be achieved. Therefore, in the second embodiment, among the wirings formed in the multilayer wiring layer, the dielectric film IF1 and the resistor element RS2 are formed on the wiring M4 having the minimum thickness. Therefore, it is possible to improve the relative accuracy of the resistor element RS2 and enhance the performance of the semiconductor device.

[0129] Similar to the upper electrode UE, the resistor element RS2 is formed between the wiring layer WL5 and the wiring layer WL4, but the wiring M4 on which the resistor element RS2 is formed is different from the wiring M4 on which the upper electrode UE is formed. In other words, the resistor element RS2 is positioned so as not to overlap with the capacitor element MIM in a plan view. In addition, the resistor element RS2 and the upper electrode UE can be formed in the same manufacturing step. Therefore, an increase in manufacturing cost can be suppressed. It should be noted that although the thickness of each of the resistor element RS2 and the upper electrode UE is the same, their respective lengths, planar shapes, and planar areas are different from each other.

[0130] In the first embodiment, the resistor element RS1 and the capacitor element MIM are formed so as not to overlap with each other in a plan view, and for the same reason, the resistor element RS1 and the resistor element RS2 are formed so as not to overlap with each other in a plan view.

[0131] Third Embodiment

[0132] The following description mainly explains the differences from the first embodiment, and the description of aspects overlapping with the first embodiment is omitted.

[0133] In the first embodiment, the wiring M4 is used as the lower electrode BE, and the upper electrode UE and the dielectric film IF1 are formed between the wiring layer WL5 and the wiring layer WL4. As Figure 19 shown, in the third embodiment, the wiring M3 is used as the lower electrode BE, and the upper electrode UE and the dielectric film IF1 are formed between the wiring layer WL4 and the wiring layer WL3.

[0134] In other words, the distance between the resistor element RS1 and the capacitor element MIM in the third embodiment is longer than the distance between the resistor element RS1 and the capacitor element MIM in the first embodiment.

[0135] The heat generated by the resistor element RS1 can change the characteristics of the capacitor element MIM. Similarly, the heat generated by the capacitor element MIM can change the characteristics of the resistor element RS1. By increasing the distance between the resistor element RS1 and the capacitor element MIM, these characteristic changes can be suppressed.

[0136] It is also possible to use the wiring M2 as the lower electrode BE, and form the upper electrode UE and the dielectric film IF1 between the wiring layer WL3 and the wiring layer WL2. In addition, it is possible to use the wiring M1 as the lower electrode BE, and form the upper electrode UE and the dielectric film IF1 between the wiring layer WL2 and the wiring layer WL1. That is to say, it is sufficient if there is one or more other wiring layers between the wiring layer in which the wiring electrically connected to the resistor element RS1 is formed and the wiring layer in which the lower electrode BE of the capacitor element MIM is formed.

[0137] Similarly, the concept applicable to the resistor element RS2 of the second embodiment can also be applied to the capacitor element MIM of the third embodiment. That is to say, the resistor element RS2 can be formed between the wiring layer WL4 and the wiring layer WL3, between the wiring layer WL3 and the wiring layer WL2, or between the wiring layer WL2 and the wiring layer WL1.

[0138] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A multi-layer wiring layer is formed on the semiconductor substrate, the multi-layer wiring layer includes a first wiring layer and a second wiring layer located on the first wiring layer; a first wiring formed in the first wiring layer; a second wiring formed in the second wiring layer, the thickness of the second wiring being greater than the thickness of the first wiring; a third wiring formed in the second wiring layer, wherein the thickness of the third wiring is greater than the thickness of the first wiring; a first dielectric film formed between the first wiring layer and the second wiring layer, the first dielectric film being formed on the first wiring; a first conductive film formed between the first wiring layer and the second wiring layer, the first conductive film being formed on the first dielectric film; as well as a second conductive film formed on the second wiring and on the third wiring; wherein the first wiring, the first dielectric film, and the first conductive film function as a capacitor element, and The second conductive film functions as a first resistor element electrically connected to the second wiring and the third wiring.

2. The semiconductor device according to claim 1, comprising: a first interlayer dielectric film covering the second wiring and the third wiring; a first via hole formed in the first interlayer dielectric film so as to be connected to the second wiring; as well as a second via hole formed in the first interlayer dielectric film so as to be connected to the third wiring, The second conductive film is formed over the first interlayer dielectric film so as to be connected to the first via hole and the second via hole.

3. The semiconductor device according to claim 2, wherein the multi-layer wiring layer includes a third wiring layer located above the second wiring layer, The semiconductor device comprises: a second interlayer dielectric film formed on the first interlayer dielectric film so as to cover the second conductive film; as well as a fourth wiring formed in the third wiring layer and formed over the second interlayer dielectric film, the thickness of the fourth wiring being greater than the thickness of the second wiring, In a direction orthogonal to an upper surface of the semiconductor substrate, a distance between the third wiring layer and the second wiring layer is longer than a distance between the second wiring layer and the first wiring layer.

4. The semiconductor device according to claim 3, The distance between the third wiring layer and the second wiring layer is 500 nm or greater.

5. The semiconductor device according to claim 4, The second conductive film includes at least one of a SiCr film, a SiCrC film, a NiCr film, a TiN film, and a TaN film.

6. The semiconductor device according to claim 1, The first wiring comprises: First barrier metal film; a third conductive film formed on the first barrier metal film; as well as A second barrier metal film is formed on the third conductive film. The thickness of the first barrier metal film is 40 nm or greater. wherein the thickness of the third conductive film is 230 nm or less, and The thickness of the second barrier metal film is 50 nm or greater.

7. The semiconductor device according to claim 6, wherein the first barrier metal film comprises a TiN film and a Ti film, wherein the third conductive film comprises an Al film or an Al alloy film, wherein the second barrier metal film comprises a TiN film, and The first conductive film includes a TiN film.

8. The semiconductor device according to claim 6, comprising: a fifth wiring and a sixth wiring, each of which is formed in the second wiring layer and each has a thickness greater than the thickness of the first wiring; as well as a fourth conductive film formed between the first wiring layer and the second wiring layer, wherein the fourth conductive film functions as a second resistor element electrically connected to the fifth wiring and the sixth wiring.

9. The semiconductor device according to claim 1, wherein the first resistor element and the capacitor element are arranged so as not to overlap each other in a plan view.

10. The semiconductor device according to claim 1, At least one wiring layer is provided between the first wiring layer and the second wiring layer.

11. A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor substrate; (b) after step (a), forming a first interlayer dielectric film on the semiconductor substrate; (c) after (b), forming a first wiring on the first interlayer dielectric film, and forming a first dielectric film and a first conductive film sequentially laminated on the first wiring; (d) after (c), forming a second interlayer dielectric film over the first interlayer dielectric film so as to cover the first wiring, the first dielectric film, and the first conductive film; (e) after the step (d), forming a second wiring and a third wiring on the second interlayer dielectric film; (f) after (e), forming a third interlayer dielectric film over the second interlayer dielectric film so as to cover the second wiring and the third wiring; (g) after (f), forming a first via hole in the third interlayer dielectric film so as to be connected to the second wiring, and forming a second via hole in the third interlayer dielectric film so as to be connected to the third wiring; and (h) after (g), forming a second conductive film over the third interlayer dielectric film so as to be connected to the first via hole and the second via hole, wherein the thickness of the first wiring is smaller than the thickness of the second wiring and the thickness of the third wiring, wherein the first wiring, the first dielectric film, and the first conductive film function as a capacitor element, and The second conductive film functions as a resistor element electrically connected to the second wiring and the third wiring.

12. The method according to claim 11, comprising: (i) after step (h), forming a fourth interlayer dielectric film on the third interlayer dielectric film so as to cover the second conductive film; as well as (j) after the step (i), forming a fourth wiring on the fourth interlayer dielectric film, The sum of the thickness of the portion of the third interlayer dielectric film located above the second wiring or the third wiring and the thickness of the portion of the fourth interlayer dielectric film located above the second wiring or the third wiring is greater than the thickness of the portion of the second interlayer dielectric film located above the first wiring.

13. The method according to claim 12, comprising: (k) between (b) and (c), performing a first polishing process on the upper surface of the first interlayer dielectric film by a CMP method; (l) between (d) and (e), performing a second polishing process on the upper surface of the second interlayer dielectric film by a CMP method; (m) between (f) and (g), performing a third polishing process on the upper surface of the third interlayer dielectric film by a CMP method; and (n) Between (i) and (j), a fourth polishing process is performed on the upper surface of the fourth interlayer dielectric film by a CMP method.

14. The method according to claim 13, The sum of the thickness of the portion of the third interlayer dielectric film located above the second wiring or above the third wiring and the thickness of the portion of the fourth interlayer dielectric film located above the second wiring or above the third wiring is 500 nm or greater.

15. The method according to claim 13, wherein said (j) comprises: (j1) forming a first barrier metal film, a third conductive film, and a second barrier metal film on the fourth interlayer dielectric film; as well as (j2) after (j1), selectively patterning the first barrier metal film, the third conductive film, and the second barrier metal film to form the fourth wiring, In the (j2), the portion of the fourth interlayer dielectric film exposed from the fourth wiring is etched using an anisotropic etching process.

16. The method according to claim 13, wherein said (h) comprises: (h1) forming a second conductive film on the third interlayer dielectric film; as well as (h2) after (h1), selectively patterning the second conductive film to form the first resistor element connected to the first via hole and the second via hole, In (h2), the portion of the third interlayer dielectric film exposed from the first resistor element is etched using an anisotropic etching process.

17. The method according to claim 11, wherein said (c) comprises: (c1) forming a third barrier metal film, a fourth conductive film, a fourth barrier metal film, the first dielectric film and the first conductive film in sequence on the first interlayer dielectric film; (c2) after (c1), selectively patterning the first dielectric film and the first conductive film; as well as (c3) after (c2), selectively patterning the third barrier metal film, the fourth conductive film, and the fourth barrier metal film to form the first wiring so that the first dielectric film and the first conductive film are left on the fourth barrier metal film, wherein the thickness of the third barrier metal film is 40 nm or greater, wherein the thickness of the fourth conductive film is 230 nm or less, and The thickness of the fourth barrier metal film is 50 nm or greater.

18. The method according to claim 11, comprising: (o) between (d) and (e), forming a third via hole and a fourth via hole in the second interlayer dielectric film, wherein in said (c), a fifth wiring is formed on said first interlayer dielectric film, and a second dielectric film and a fifth conductive film are sequentially formed on said fifth wiring, wherein in the (d), the second interlayer dielectric film is formed so as to cover the fifth wiring, the second dielectric film, and the fifth conductive film, wherein in (e), a sixth wiring connected to the third via hole and a seventh wiring connected to the fourth via hole are formed on the second interlayer dielectric film, wherein the third via hole and the fourth via hole are formed so as to be connected to the fifth conductive film, and wherein the fifth conductive film functions as a second resistor element electrically connected to the sixth wiring and the seventh wiring.

19. The method according to claim 11, wherein the first resistor element and the capacitor element are arranged so as not to overlap each other in a plan view.

20. The method according to claim 11, comprising: (p) between (d) and (e), forming an eighth wiring on the second interlayer dielectric film; as well as (q) between (p) and (e), forming a fifth interlayer dielectric film on the second interlayer dielectric film so as to cover the eighth wiring, wherein in said (e), said second wiring and said third wiring are formed on said fifth interlayer dielectric film, wherein in said (f), said third interlayer dielectric film is formed on said fifth interlayer dielectric film, and The thickness of the eighth wiring is smaller than the thickness of the second wiring and the thickness of the third wiring.

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