Output control circuit and Class-AB operational amplifier

Abstract

The invention discloses an output control circuit and a Class-AB type operational amplifier, and the output control circuit comprises a first output tube, a second output tube, a first conversion unit, a first switch unit, a clamping unit, a second switch unit and a third switch unit. The first conversion unit converts an input signal into a first control signal for controlling the on-off of the first switch unit; the clamping unit generates a second control signal based on the on-off of the first switch unit and the first voltage; the second switch unit controls connection and disconnection between the first voltage and the first output tube based on a second control signal; the third switch unit controls connection and disconnection between the second voltage and the second output tube based on the first control signal. According to the output control circuit and the Class-AB type operational amplifier, conversion from an input signal of a low-voltage domain to a second control signal of a high-voltage domain is realized during high-voltage power-on, so that the first output tube and the second output tube are controlled, and the Class-AB type operational amplifier is in a high-resistance state during power-on.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to an output control circuit and a Class-AB operational amplifier. Background Art

[0002] As Figure 1 shown, the first output transistor MP and the second output transistor MN constitute the output stage circuit of a Class-AB operational amplifier, and the first inverter NV1, the second inverter NV2, the transistor M4, and the transistor M5 constitute the control circuit of the output stage circuit.

[0003] The basic principle is as Figure 2 shown. When the first voltage VDD is powered on, the input signal Vcont is initially low. After passing through the first inverter NV1, the first control signal n1 is high level, the transistor M5 is turned on, pulling down the control terminal of the second output transistor MN, so the second output transistor MN is turned off. After the first control signal n1 passes through the second inverter NV2, the second control signal n2 is low level, the transistor M4 is turned on, pulling up the voltage of the control terminal of the first output transistor MP, so the first output transistor MP is turned off.

[0004] As the first voltage VDD increases, the input signal Vcont becomes high, the first control signal n1 flips to low level, the transistor M5 is turned off, the control terminal of the second output transistor MN is not controlled by the transistor M5, the second output transistor MN becomes normal operation, the second control signal n2 flips to high level, the transistor M4 is turned off, the control terminal of the first output transistor MP is not controlled by the transistor M4, and the first output transistor MP operates normally.

[0005] It should be noted that in the actual application scenario, since the input signal Vcont is a low-voltage signal and the first voltage VDD is a high-voltage signal, only a low-voltage second control signal n2 can be generated after the input signal Vcont is converted by the first inverter NV1 and the second inverter NV2. When the low-voltage second control signal n2 and the high-voltage first voltage VDD act on the transistor M4, it is easy to cause damage to the transistor M4. Therefore, the low-voltage input signal Vcont cannot be used as the initial control signal.

[0006] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of implication that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0007] The object of the present invention is to provide an output control circuit and a Class-AB operational amplifier that can still use a low-voltage input signal as the initial control signal for the output stage circuit of the Class-AB operational amplifier.

[0008] To achieve the above object, a specific embodiment of the present invention provides an output control circuit, including: a first output transistor and a second output transistor. The second end of the first output transistor is connected to the second end of the second output transistor. The first end of the first output transistor is connected to a first voltage located in a first voltage domain. The second end of the second output transistor is connected to a second voltage. The output control circuit further includes: a first conversion unit, a first switching unit, a clamping unit, a second switching unit, and a third switching unit.

[0009] The first conversion unit is used to convert an input signal located in a second voltage domain into a first control signal; the first switching unit is connected to the first conversion unit and the second voltage, and the first switching unit controls its own on / off based on the first control signal; the clamping unit is connected to the first switching unit and the first voltage, and the clamping unit is used to generate a second control signal located in the first voltage domain based on the on / off of the first switching unit and the first voltage.

[0010] The second switching unit is connected to the clamping unit, the first voltage, and the control end of the first output transistor to control the on / off between the first voltage and the control end of the first output transistor based on the second control signal; the third switching unit is connected to the first conversion unit, the second voltage, and the control end of the second output transistor to control the on / off between the second voltage and the control end of the second output transistor based on the first control signal.

[0011] In one or more embodiments of the present invention, the first conversion unit includes a first inverter. The input end of the first inverter is used to receive the input signal, and the output end of the first inverter is used to output the first control signal.

[0012] In one or more embodiments of the present invention, the first switching unit includes a first transistor and a biasing unit. The control end of the first transistor is used to receive the first control signal. The first end of the first transistor is connected to the biasing unit, and the second end of the first transistor is connected to the clamping unit.

[0013] In one or more embodiments of the present invention, the biasing unit includes a current source and a current mirror. The current source is connected to the current mirror to provide an input current to the current mirror. The current mirror is simultaneously connected to the first end of the first transistor and the second voltage to provide a biasing current to the first transistor.

[0014] In one or more embodiments of the present invention, the clamping unit includes a diode or a triode. The cathode of the diode is connected to the first voltage, the anode of the diode is connected to the first switching unit. The base and the collector of the triode are connected and connected to the first switching unit, and the emitter of the triode is connected to the first voltage.

[0015] In one or more embodiments of the present invention, the clamping unit also includes a resistance unit, a first end of the resistance unit is connected to the cathode of the diode, and a second end of the resistance unit is connected to the anode of the diode, or a first end of the resistance unit is connected to the emitter of the transistor, and a second end of the resistance unit is connected to the base and collector of the transistor.

[0016] In one or more embodiments of the present invention, the output control circuit further includes a second conversion unit and a third conversion unit, the second conversion unit is used to convert the first control signal into a third control signal, the first switch unit controls its own on and off based on the third control signal, the third conversion unit is powered by the first voltage and the third voltage, the third conversion unit is used to receive the second control signal and output a fourth control signal based on the first voltage and the third voltage, and the second switch unit controls the on and off between the first voltage and the control end of the first output tube based on the fourth control signal.

[0017] In one or more embodiments of the present invention, the second conversion unit includes a second inverter, the input end of the second inverter is connected to the output end of the first conversion unit to receive the first control signal, the output end of the second inverter is used to output the third control signal, and the third conversion unit 70 includes a third inverter, the input end of the third inverter is used to receive the second control signal, and the output end of the third inverter is used to output the fourth control signal.

[0018] In one or more embodiments of the present invention, the output control circuit further includes a voltage generating circuit, the voltage generating circuit is used to generate a third voltage, and the voltage difference between the first voltage and the third voltage is used to turn on the second switch unit.

[0019] The invention also discloses a Class-AB operational amplifier, comprising the output control circuit.

[0020] Compared with the prior art, the output control circuit and the Class-AB operational amplifier of the present invention, when the high voltage is powered on, realize the conversion from the input signal in the low voltage domain to the second control signal in the high voltage domain through the clamping unit in cooperation with the first switch unit, and then control the first output tube and the second output tube through the second switch unit and the third switch unit, so that the output of the Class-AB operational amplifier is in a high impedance state when powered on. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is the circuit schematic diagram of the output control circuit in the prior art.

[0023] Figure 2 It is the signal waveform diagram in the application scenario.

[0024] Figure 3 It is the circuit schematic diagram of the output control circuit in the first embodiment.

[0025] Figure 4 It is the circuit schematic diagram of the output control circuit in the second embodiment.

[0026] Figure 5 It is the circuit schematic diagram of the voltage generation circuit in the second embodiment. Detailed implementation manners

[0027] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0028] "Coupled" or "connected" or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0029] In the detailed description of the specification, reference is made to the accompanying drawings which form a part hereof, in which like reference numerals always refer to like components, and which are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense.

[0030] The various operations in the specification may be described sequentially as a number of discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0031] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0032] Various components and devices may be referred to or shown herein in the singular form (e.g., "transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0033] The specification describes the use of the phrase "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc., used with respect to the embodiments of the present disclosure are synonymous.

[0034] Embodiment 1

[0035] As Figure 3 shown, an output control circuit in an embodiment of the present invention includes: a first output transistor MP and a second output transistor MN. The second end of the first output transistor MP is connected to the second end of the second output transistor MN. The first end of the first output transistor MP is connected to a first voltage VDD in a first voltage domain. The second end of the second output transistor MN is connected to a second voltage VSS. The output control circuit further includes: a first conversion unit 10, a first switch unit 20, a clamping unit 30, a second switch unit 40, and a third switch unit 50. In one embodiment, the second voltage VSS is a ground voltage or a reference voltage of other magnitude.

[0036] The first conversion unit 10 is used to convert the input signal Vcont located in the second voltage domain into a first control signal n1; the first switch unit 20 is connected to the first conversion unit 10 and the second voltage VSS, and the first switch unit 20 controls its own on / off based on the first control signal n1; the third switch unit 50 is connected to the first conversion unit 10, the second voltage VSS, and the control terminal of the second output transistor MN to control the on / off between the second voltage VSS and the control terminal of the second output transistor MN based on the first control signal n1.

[0037] The clamping unit 30 is connected to the first switch unit 20 and the first voltage VDD. The clamping unit 30 is used to generate a second control signal n2 located in the first voltage domain based on the on / off of the first switch unit 20 and the first voltage VDD; the second switch unit 40 is connected to the clamping unit 30, the first voltage VDD, and the control terminal of the first output transistor MP to control the on / off between the first voltage VDD and the control terminal of the first output transistor MP based on the second control signal n2.

[0038] In an embodiment, the first voltage domain can be considered as a high-voltage range, and its maximum voltage can be considered to be 36V or a voltage of other magnitudes, that is, the first voltage VDD can be powered up to a maximum value of 36V, and VDD - 5V is also within the high-voltage range; the second voltage domain can be considered as a low-voltage range, and its maximum voltage can be considered to be 5V or a voltage of other magnitudes.

[0039] Specifically, as Figure 3 shown, in an embodiment, the first conversion unit 10 includes a first inverter NV1. The input terminal of the first inverter NV1 is used to receive the input signal Vcont, and the output terminal of the first inverter NV1 is used to output the first control signal n1.

[0040] The first switch unit 20 includes a first transistor M1 and a biasing unit. The control terminal of the first transistor M1 is used to receive the first control signal n1. The first end of the first transistor M1 is connected to the biasing unit, and the biasing unit is used to provide a biasing current for the first transistor M1. The second end of the first transistor M1 is connected to the clamping unit 30. In an embodiment, the first transistor M1 is a high-voltage transistor.

[0041] The bias unit includes a current source A and a current mirror. The current source A is connected to the current mirror to provide an input current to the current mirror, and the current mirror is simultaneously connected to the first end of the first transistor M1 and the second voltage VSS to provide a bias current to the first transistor M1. In one embodiment, the current mirror includes a second transistor M2 and a third transistor M3. The control terminal of the second transistor M2 is connected to the second end of the second transistor M2, the current source A, and the control terminal of the third transistor M3. The first end of the second transistor M2 and the first end of the third transistor M3 are connected to the second voltage VSS, and the second end of the third transistor M3 is connected to the first end of the first transistor M1. The second transistor M2 receives the input current generated by the current source A, and the third transistor M3 mirrors the input current to generate a bias current. In one embodiment, the current source A can be composed of a transistor or a current mirror, and the control signal of the current source A can be generated synchronously with the input signal Vcont, that is, the current source A is turned on only when there is an input signal Vcout, so as to save circuit power consumption when the input signal Vcont is not generated.

[0042] The clamping unit 30 includes a diode D1 and a resistor unit R1. The cathode of the diode D1 is connected to the first voltage VDD, the first end of the resistor unit R1 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the first switch unit 20, and the second end of the resistor unit R1 is connected to the anode of the diode D1. In other embodiments, a triode can also be used to replace the diode. The base and collector of the triode are connected and connected to the second end of the first transistor M1, and the emitter of the triode is connected to the first voltage VDD.

[0043] The second switch unit 40 includes a fourth transistor M4. The control terminal of the fourth transistor M4 is connected to the anode of the diode D1, the second end of the resistor unit R1, and the second end of the first transistor M1. The first end of the fourth transistor M4 is connected to the first voltage VDD, and the second end of the fourth transistor M4 is connected to the control terminal of the first output transistor MP.

[0044] The third switch unit 50 includes a fifth transistor M5. The control terminal of the fifth transistor M5 is connected to the output terminal of the first inverter NV1. The first end of the fifth transistor M5 is connected to the second voltage VSS, and the second end of the fifth transistor M5 is connected to the control terminal of the second output transistor MN.

[0045] This application also discloses a Class-AB operational amplifier, including the above output control circuit.

[0046] The first output transistor MP and the second output transistor MN form the output stage circuit of a Class-AB operational amplifier. When the first voltage VDD is powered on, the input signal Vcont is initially at a low level in the second voltage domain. After passing through the first inverter NV1, a first control signal n1 at a high level in the second voltage domain is generated. The first transistor M1 is turned on, and the diode D1 clamps the voltage at the second terminal of the first transistor M1 to generate a second control signal n2 at a low level in the first voltage domain (as low as VDD - 5V in one embodiment), ensuring that the fourth transistor M4 is turned on, thereby raising the voltage at the control terminal of the first output transistor MP. The first output transistor MP is turned off. Since the first control signal n1 is at a high level, the fifth transistor M5 is turned on, and the control terminal of the second output transistor MN is pulled low, turning off the second output transistor MN, and further realizing a high-impedance state at the node where the second terminal of the first output transistor MP is connected to the second terminal of the second output transistor MN.

[0047] As the first voltage VDD increases, the input signal Vcont flips to a high level in the second voltage domain. After passing through the first inverter NV1, a first control signal n1 at a low level in the second voltage domain is generated. The first transistor M1 is turned off, and the second terminal of the first transistor M1 is connected to the first voltage VDD through the resistor unit R1. At this time, a second control signal n2 at a high level in the first voltage domain is generated at the second terminal of the first transistor M1 (the high-level second control signal n2 is VDD in one embodiment), causing the fourth transistor M4 to turn off. The control terminal of the first output transistor MP is at the normal operating voltage, and the first output transistor MP operates normally. Since the first control signal n1 is at a low level, the fifth transistor M5 is turned off, and the control terminal of the second output transistor MN is at the normal operating voltage, and the second output transistor MN operates normally.

[0048] As can be seen from the above, through the diode D1 and the resistor unit R1 of the clamping unit 30, the input signal Vcont that flips in the low voltage domain can be converted into a second control signal n2 that follows the flip in the high voltage domain.

[0049] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, and the second output transistor MN are N-channel MOS transistors, and the fourth transistor M4 and the first output transistor MP are P-channel MOS transistors; the first ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first output transistor MP, and the second output transistor MN are source electrodes, the second ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first output transistor MP, and the second output transistor MN are drain electrodes, and the control ends of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first output transistor MP, and the second output transistor MN are gate electrodes.

[0050] Embodiment 2

[0051] As Figure 4 shown, on the basis of Embodiment 1, the output control circuit further includes a second conversion unit 60 and a third conversion unit 70. The second conversion unit 60 is configured to convert the first control signal n1 into a third control signal n3. The first switch unit 20 controls its own on / off based on the third control signal n3. The third conversion unit 70 is powered by the first voltage VDD and the third voltage VCC. In one embodiment, the third voltage VCC = VDD - 5V. In other embodiments, the third voltage VCC may be a voltage of other magnitudes. The third conversion unit 70 is configured to receive the second control signal n2 and output a fourth control signal n4 based on the first voltage VDD and the third voltage VCC. The second switch unit 40 controls the on / off between the first voltage VDD and the control end of the first output transistor MP based on the fourth control signal n4.

[0052] Specifically, the second conversion unit 60 includes a second inverter NV2. The input end of the second inverter NV2 is connected to the output end of the first conversion unit 10 to receive the first control signal n1, and the output end of the second inverter NV2 is configured to output the third control signal n3. The third conversion unit 70 includes a third inverter NV3. The input end of the third inverter NV3 is configured to receive the second control signal n2, and the output end of the third inverter NV3 is configured to output the fourth control signal n4.

[0053] When the first voltage VDD is powered on, the input signal Vcont is initially at a low level in the second voltage domain. After passing through the first inverter NV1, a first control signal n1 at a high level in the second voltage domain is generated. At this time, the fifth transistor M5 is turned on, the control terminal of the second output transistor MN is pulled low, and the second output transistor MN is turned off. The high-level first control signal n1 passes through the second inverter NV2 to generate a third control signal n3 at a low level in the second voltage domain. The first transistor M1 is turned off, and the second terminal of the first transistor M1 is connected to the first voltage VDD through the resistor unit R1. At this time, a second control signal n2 at a high level in the first voltage domain is generated at the second terminal of the first transistor M1 (in one embodiment, the high-level second control signal n2 is VDD). The high-level second control signal n2 passes through the third inverter NV3 to generate a fourth control signal n4 at a low level in the first voltage domain (in one embodiment, the low-level fourth control signal n4 is VCC, and VCC = VDD - 5V), ensuring that the fourth transistor M4 is turned on, thereby raising the voltage at the control terminal of the first output transistor MP. The first output transistor MP is turned off, and both the first output transistor MP and the second output transistor MN are turned off, thus achieving a high-impedance state at the node where the second terminal of the first output transistor MP is connected to the second terminal of the second output transistor MN.

[0054] As the first voltage VDD increases, the input signal Vcont flips to a high level in the second voltage domain. After passing through the first inverter NV1, a first control signal n1 at a low level in the second voltage domain is generated. The fifth transistor M5 is turned off, the control terminal of the second output transistor MN is at the normal operating voltage, and the second output transistor MN operates normally. The low-level first control signal n1 passes through the second inverter NV2 to generate a third control signal n3 at a high level in the second voltage domain. The first transistor M1 is turned on, and the diode D1 clamps the voltage at the second terminal of the first transistor M1 to generate a second control signal n2 at a low level in the first voltage domain (in one embodiment, the low-level second control signal n2 is VDD - 5V). The low-level second control signal n2 passes through the third inverter NV3 to generate a fourth control signal n4 at a high level in the first voltage domain (in one embodiment, the high-level fourth control signal n4 is VDD). At this time, the fourth transistor M4 is turned off, the control terminal of the first output transistor MP is at the normal operating voltage, and the first output transistor MP operates normally.

[0055] The input signal Vcont, the first control signal n1, and the third control signal n3 are low-voltage signals that flip between high and low levels within the low-voltage domain. The second control signal n2 and the fourth control signal n4 are high-voltage signals that flip between high and low levels within the high-voltage domain.

[0056] The third inverter NV3 enables the fourth control signal n4 to flip between the first voltage VDD in the first voltage domain and the third voltage VCC, realizing the conduction and cutoff of the fourth transistor M4. The third inverter NV3 isolates the clamping unit 30 from the control terminal of the fourth transistor M4, making the voltage on the control terminal of the fourth transistor M4 more stable and avoiding the influence caused by the jitter of the second control signal n2 during power-on.

[0057] In one embodiment, the output control circuit further includes a voltage generation circuit for generating the third voltage VCC, and the second switch unit 40 is turned on by the voltage difference between the first voltage VDD and the third voltage VCC.

[0058] As Figure 5 shown, the voltage generation circuit includes a transistor M6 and a resistor R2. The control terminal and the second terminal of each transistor M6 are connected and the transistors M6 are connected in series. The series-connected transistors M6 are connected between the first voltage VDD and the first end of the resistor R2 to generate the third voltage VCC at the first end of the resistor R2, and the second end of the resistor R2 is connected to the second voltage VSS. The transistor M6 and the resistor R2 can each be one or more, and the number of the transistor M6 and the resistor R2 can be selected according to actual needs to obtain the required third voltage VCC.

[0059] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0060] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An output control circuit, characterized in that: include: The first output tube and the second output tube, the second end of the first output tube is connected to the second end of the second output tube, the first end of the first output tube is connected to a first voltage in a first voltage domain, and the second end of the second output tube is connected to a second voltage, and the output control circuit further includes: A first conversion unit, configured to convert an input signal in a second voltage domain into a first control signal; A first switch unit, connected to the first conversion unit and the second voltage, wherein the first switch unit controls its own on and off based on a first control signal; A clamping unit connected to the first switch unit and the first voltage, wherein the clamping unit is used to generate a second control signal in the first voltage domain based on the on / off state of the first switch unit and the first voltage; a second switch unit connected to the clamp unit, the first voltage and the control end of the first output tube to control the on-off between the first voltage and the control end of the first output tube based on a second control signal; and The third switch unit is connected to the first conversion unit, the second voltage and the control end of the second output tube to control the connection between the second voltage and the control end of the second output tube based on the first control signal.

2. The output control circuit according to claim 1, characterized in that: The first conversion unit includes a first inverter, an input end of the first inverter is used to receive an input signal, and an output end of the first inverter is used to output a first control signal.

3. The output control circuit according to claim 1, characterized in that: The first switch unit includes a first transistor and a bias unit, the control end of the first transistor is used to receive a first control signal, the first end of the first transistor is connected to the bias unit, and the second end of the first transistor is connected to the clamp unit.

4. The output control circuit according to claim 3, characterized in that: The bias unit includes a current source and a current mirror, wherein the current source is connected to the current mirror to provide an input current to the current mirror, and the current mirror is simultaneously connected to the first terminal of the first transistor and the second voltage to provide a bias current to the first transistor.

5. The output control circuit according to claim 1, characterized in that: The clamping unit includes a diode or a triode, the cathode of the diode is connected to the first voltage, the anode of the diode is connected to the first switch unit, the base and collector of the triode are connected and connected to the first switch unit, and the emitter of the triode is connected to the first voltage.

6. The output control circuit according to claim 5, characterized in that: The clamping unit also includes a resistor unit, a first end of the resistor unit is connected to the cathode of the diode, and a second end of the resistor unit is connected to the anode of the diode, or a first end of the resistor unit is connected to the emitter of the transistor, and a second end of the resistor unit is connected to the base and collector of the transistor.

7. The output control circuit according to claim 1, characterized in that: The output control circuit also includes a second conversion unit and a third conversion unit, the second conversion unit is used to convert the first control signal into a third control signal, the first switch unit controls its own on and off based on the third control signal, the third conversion unit is powered by the first voltage and the third voltage, the third conversion unit is used to receive the second control signal and output a fourth control signal based on the first voltage and the third voltage, and the second switch unit controls the on and off between the first voltage and the control end of the first output tube based on the fourth control signal.

8. The output control circuit according to claim 7, characterized in that: The second conversion unit includes a second inverter, the input end of the second inverter is connected to the output end of the first conversion unit to receive the first control signal, the output end of the second inverter is used to output the third control signal, and the third conversion unit includes a third inverter, the input end of the third inverter is used to receive the second control signal, and the output end of the third inverter is used to output the fourth control signal.

9. The output control circuit according to claim 7, characterized in that: The output control circuit further includes a voltage generating circuit, wherein the voltage generating circuit is used to generate a third voltage, and a voltage difference between the first voltage and the third voltage is used to turn on the second switch unit.

10. A Class-AB operational amplifier, characterized in that: The invention comprises the output control circuit as claimed in any one of claims 1 to 9.

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