Dual-channel TIADC Sampling Time Mismatch Error Estimation and Calibration Method and Device

Abstract

The present invention specifically discloses a method and device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which relates to the technical field of high-speed analog-to-digital conversion. On the one hand, the method of the present invention performs data transformation on the output signal of the sub-analog-to-digital converter serving as a reference. On the other hand, it performs mismatch delay on the output signal of the sub-analog-to-digital converter to be calibrated, then multiplies the imaginary part of the transformed signal by the delayed signal and then calculates the mean value. After that, it performs iteration of the estimated parameters and adjustment of the mismatch parameters to obtain more appropriate mismatch parameters for the next round of calibration; in this way, through multiple rounds of calibration, the sampling time mismatch error τ is effectively estimated from the output signal of the dual-channel TIADC, and then calibration is achieved. The present invention can accurately estimate the sampling time mismatch error τ, thereby effectively suppressing the spurious signals caused by the sampling time mismatch clock skew, improving the dynamic performance of the system, and reducing the signal distortion caused by the sampling time mismatch.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed analog-to-digital conversion, and specifically relates to: 1. A method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC; 2. A device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC using this method. Background Art

[0002] A TIADC (Time-Interleaved Analog To Digital Converter) performs time-interleaved sampling on an analog input signal through multiple relatively low-speed sub-ADCs, and theoretically can increase the sampling rate without reducing the conversion accuracy.

[0003] Refer to Figure 1 , which shows a dual-channel TIADC, including: 2 sub-analog-to-digital converters sub_ADC1 to sub_ADC2, a clock network Clock, and a multiplexer MUX. Among them, sub_ADC1 and sub_ADC2 are relatively low-speed and sample the test signal V in in a time-interleaved manner. The number of interleaved channels is 2; if the overall sampling rate of the dual-channel TIADC is Fs, then the 2 sub-analog-to-digital converters are respectively driven by sampling clocks with an equal phase difference (180°) and a frequency of Fs / 2 to sample V in , and finally the quantization results of the 2 sub-analog-to-digital converters are sequentially output through the MUX (the quantization result of sub_ADC1 is y1[n], and the quantization result of sub_ADC2 is y2[n], n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the nth sampling point in N) to obtain the final digital output y[n]. Ideally, this dual-channel TIADC can double the overall sampling rate without affecting the conversion accuracy, thereby breaking the design limit between the sampling rate and the conversion accuracy faced by traditional single-channel ADCs.

[0004] However, in the actual chip design and manufacturing process, due to factors such as the uncertainty errors in the layout design and chip manufacturing, the above-mentioned dual-channel TIADC has inter-channel parameter mismatch problems, such as offset, gain, and sampling time mismatch. Among them, the sampling time mismatch will introduce error spur components in the output spectrum, seriously affecting the dynamic performance. Therefore, it is necessary to calibrate the sampling time mismatch existing in the above-mentioned dual-channel TIADC. Summary of the Invention

[0005] Based on this, it is necessary to propose a method and device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC system to address the problem of the need for calibration of the sampling time mismatch existing in the prior art dual-channel TIADC system in the background technology.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention discloses a method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which is used to estimate and calibrate the sampling time mismatch τ of Sub_ADC2 with Sub_ADC1 as a reference. Among them, Sub_ADC1 and Sub_ADC2 represent two sub-analog-to-digital converters of the dual-channel TIADC.

[0008] The method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC includes:

[0009] Taking T s as a period, periodically obtaining the output signals of Sub_ADC1 and Sub_ADC2 multiple times; among them, T s represents the sampling period of the dual-channel TIADC;

[0010] Based on the obtained y 1,i [n] and y 2,i [n], perform the i-th round of calibration; among them, y 1,i [n] and y 2,i [n] respectively represent the output signals of Sub_ADC1 and Sub_ADC2 at the i-th time; n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the n-th sampling point in N; i ≥ 1;

[0011] Among them, the method for the i-th round of calibration includes:

[0012] S100, perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°;

[0013] According to the mismatch parameter C_τ i of the i-th round, perform digital correction on y 2,i [n] to delay the overall signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n];

[0014] S200, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n];

[0015] S300, calculate p i [0] to p i The average value avg of [N] i ;

[0016] S400, use avg i as the iteration parameter, and iterate the estimated parameter C_err i-1 in the (i - 1)-th round to obtain the estimated parameter C_err i in the i-th round;

[0017] S500, add T i to C_err s to obtain the mismatch parameter C_τ i+1 in the (i + 1)-th round;

[0018] where, when i = 1, C_τ1 takes 0, and C_err i-1 takes 0;

[0019] where, if C_τ i has converged, the calibration is completed, and C_err i is used as τ to calibrate the output signal of Sub_ADC2; otherwise, the calibration is not completed, and the (i + 1)-th round of calibration is performed.

[0020] The implementation of the method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC is based on the method or process of the embodiments of the present disclosure.

[0021] In a second aspect, the present invention discloses a device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which uses the method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC disclosed in the first aspect.

[0022] The device for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC includes: a signal acquisition module and an error estimation and calibration module.

[0023] The signal acquisition module is used to periodically acquire the output signals of Sub_ADC1 and Sub_ADC2 multiple times with T s as a period. The error estimation and calibration module is used to perform the i-th round of calibration based on the acquired y 1,i [n], y 2,i [n].

[0024] Among them, the error estimation and calibration module includes: a data conversion sub-module, a digital correction sub-module, a product calculation sub-module, an average calculation sub-module, an estimation sub-module, and an adjustment sub-module.

[0025] The data conversion sub-module is used to process y 1,i[n] Perform data conversion to obtain the imaginary part Im_y 1,i [n] that contains phase information delayed by 90°; the digital correction sub-module is used to i perform digital correction on y 2,i [n] according to the mismatch parameter C_τ i in the i-th round to delay the overall signal phase by C_τ 2_call,i and obtain the corrected output signal y 1,i [n]; the product calculation sub-module is used to multiply Im_y 2_call,i [n] by y i [n] to obtain the multiplication result p i [n]; the average calculation sub-module is used to calculate the average value avg i of p i [0] to p i [N]; the estimation sub-module is used to use avg i-1 as the iteration parameter and perform iteration on the estimation parameter C_err i in the (i - 1)-th round to obtain the estimation parameter C_err i in the i-th round; the adjustment sub-module is used to add C_err s to T i+1 to obtain the mismatch parameter C_τ

[0026] in the (i + 1)-th round.

[0027] The implementation of this TIADC sampling time mismatch calibration device is based on the method or process of the embodiments of the present disclosure.

[0028] In a third aspect, the present invention discloses a computer program product, including a computer program. When the computer program is executed by a processor, it implements the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in the first aspect.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. On the one hand, the present invention performs data transformation on the output signal of the sub-analog-to-digital converter used as a reference, and on the other hand, performs mismatch delay on the output signal of the sub-analog-to-digital converter to be calibrated. Then, it multiplies the imaginary part of the transformed signal by the delayed signal and then calculates the average value. After that, it performs iteration of the estimation parameter and adjustment of the mismatch parameter to obtain a more appropriate mismatch parameter for the next round of calibration. In this way, through multiple rounds of calibration, the sampling time mismatch error τ is effectively estimated from the output signal of the dual-channel TIADC, and then calibration is achieved. Through simulation verification, the present invention can accurately estimate the sampling time mismatch error τ, thereby effectively suppressing the spurious signals caused by the sampling time mismatch clock skew, improving the dynamic performance of the system, and reducing the signal distortion caused by the sampling time mismatch.

[0030] 2. The present invention utilizes the mathematical characteristics of signals and can be implemented without complex additional hardware circuits. It can be achieved only by using relatively simple digital signal processing methods or steps. While ensuring the accuracy of the estimation of the sampling time mismatch error τ, it reduces the dependence on additional hardware, thereby reducing the hardware cost and circuit complexity.

[0031] 3. The method of the present invention can be designed based on digital circuits, and thus has good stability and reliability in the face of process, voltage, and temperature (PVT) variations.

[0032] 4. The method of the present invention can quickly and accurately correct the sampling time mismatch; compared with existing methods, the method of the present invention has a faster convergence speed and requires fewer total sampling points to achieve convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is the structural diagram of the existing dual-channel TIADC mentioned in the background art;

[0035] Figure 2 It is the data flow diagram of the method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC provided in Embodiment 1 of the present invention;

[0036] Figure 3 It is the simulation result provided in Embodiment 2 of the present invention Figure 1 ;

[0037] Figure 4 It is the simulation result provided in Embodiment 2 of the present invention Figure 2 ;

[0038] Figure 5 It is the simulation result provided in Embodiment 2 of the present invention Figure 3 。 DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, rather than all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0040] It should be noted that when a component is referred to as "installed on" another component, it can be directly on the other component or there can also be an intermediate component. When a component is considered to be "arranged on" another component, it can be directly arranged on the other component or there may be an intermediate component at the same time. When a component is considered to be "fixed to" another component, it can be directly fixed to the other component or there may be an intermediate component at the same time.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used in the specification of this invention herein are only for the purpose of describing specific embodiments and are not intended to limit the invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0042] Embodiment 1

[0043] Please refer to Figure 2 , Figure 2 which is the data flow diagram of the sampling time mismatch error estimation and calibration method for the dual-channel TIADC proposed for Embodiment 1, and actually also shows the brief process of the sampling time mismatch error estimation and calibration method for the dual-channel TIADC.

[0044] As described in the background art, Figure 2 Sub_ADC1 and Sub_ADC2 in [[ ]] represent the two sub-analog-to-digital converters of the dual-channel TIADC. Among them, the sampling periods of Sub_ADC1 and Sub_ADC2 are the same, both being T s . That is to say, T s is actually the sampling period of the dual-channel TIADC.

[0045] It should be noted that this method estimates and calibrates the sampling time mismatch τ of Sub_ADC2 with Sub_ADC1 as the reference. That is to say, τ is relative to Sub_ADC1 for Sub_ADC2.

[0046] As Figure 2 shown, a sampling time mismatch error estimation and calibration method for a dual-channel TIADC specifically includes:

[0047] Taking T s as a period, obtaining the output signals of Sub_ADC1 and Sub_ADC2 periodically and multiple times;

[0048] It should be noted that, as mentioned in the background art, Sub_ADC1 and Sub_ADC2 sample the test signal V in to obtain the corresponding output signals. Among them, V inIt can be a single-tone signal or a multi-tone signal.

[0049] Based on the acquired y 1,i [n], y 2,i [n] performs the i-th round of calibration; i ≥ 1;

[0050] Among them, y 1,i [n], y 2,i [n] respectively represent the output signals of Sub_ADC1 and Sub_ADC2 in the i-th time; n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the n-th sampling point in N.

[0051] Since the principle of each round of calibration is similar, taking the i-th round of calibration as an example for illustration - its method specifically includes:

[0052] S100, performs data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°.

[0053] According to the mismatch parameter C_τ of the i-th round i performs digital correction on y 2,i [n] to delay the overall signal phase by C_τ i , and obtains the corrected output signal y 2_call,i [n].

[0054] On the one hand, S100 aims to obtain Im_y 1,i [n] from y 1,i [n] - which contains the phase information delayed by 90° and is used for subsequent signal processing. On the other hand, it aims to make y 2,i [n] achieve an overall delay of the signal phase by C_τ i and is used for subsequent signal processing.

[0055] In this Embodiment 1:

[0056] 1. It is recommended to use the Hilbert transform to perform data conversion on y 1,i [n], which can convert a real signal into a complex signal and delay the phase of the signal frequency component by 90° (reflected in the imaginary part of the complex signal).

[0057] 2. It is recommended to use an interpolation delay filter to perform digital correction on y 2,i [n], which completes the overall delay of the signal phase of y 2,i [n] by C_τ i through steps such as interpolation and delay filtering. Among them, C_τ iAs the configuration parameters used by the interpolation delay filter during the i-th round of calibration; that is, y 2,i [n] passes through the interpolation delay filter with configuration parameters C_τ i to obtain the signal phase with an overall delay of C_τ i of y 2_call,i [n].

[0058] In addition, it should be noted that when i = 1, C_τ1 takes 0, that is, in fact, during the first round of calibration, y 2_call,1 [n] is the same as y2[n].

[0059] Of course, other devices or digital circuits can also be used to implement the process of S100, but it should be ensured that the processing effect meets the requirements.

[0060] S200, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n].

[0061] That is, the calculation formula for p i [n] is:

[0062] p i [n] = Im_y 1,i [n] × y 2_call,i [n].

[0063] S300, calculate the mean value avg i of p i [0] to p i [N].

[0064] Since n ranges from 0 to N, there are p i [0] to p i [N], so take the mean value of them.

[0065] That is, the calculation formula for avg i is:

[0066] avg i = (p i [0] + … + p i [N]) / N.

[0067] S400, use avg i as the iteration parameter and iterate the estimated parameter C_err i-1 in the (i - 1)-th round to obtain the estimated parameter C_err i in the i-th round.

[0068] Among them, C_err iThe calculation formula is as follows:

[0069] C_err i = C_err i-1 - μ * avg i ;

[0070] Where μ represents the iteration coefficient, which is a preset value.

[0071] Then, S400 actually updates and calculates C_err i once based on avg i-1 and μ to obtain C_err i .

[0072] In this Embodiment 1:

[0073] It is recommended to use an LMS adaptive engine filter to iterate C_err i-1 , and it implements the above calculation process based on the LMS algorithm. Among them, avg i and μ are used as the configuration parameters of the LMS adaptive engine filter during the i-th round of calibration. That is to say, C_err i-1 is processed by the LMS adaptive engine filter with configuration parameters avg i and μ to obtain C_err i .

[0074] In addition, it should be noted that when i = 1, C_err i-1 takes 0.

[0075] Of course, other devices or digital circuits can also be used to implement the process of S400, but it should be ensured that the processing effect meets the requirements.

[0076] S500, add C_err i to T s to obtain the mismatch parameter C_τ i+1 of the (i + 1)-th round;

[0077] Since there is T 1,i in y 2,i [n] and y s [n], if only C_err i is used to update the mismatch parameter, the calibration result will be unsatisfactory; therefore, it is selected to add C_err i to T s to obtain the mismatch parameter C_τ i+1 of the (i + 1)-th round, that is, C_τ i+1 = C_err i + T s . In this way, during the (i + 1)-th round of calibration, y 2_call,i+1 [n] compared with y2,i+1 For [n], the signal phase will be delayed by C_τ as a whole i+1 , so as to perform subsequent signal processing.

[0078] For S200, S300, and S500, they are all simple numerical calculation processes and can all be implemented in the way of digital circuits, which will not be elaborated here.

[0079] Since multiple calibrations are performed - the current calibration will produce a pre - adjustment for the next calibration, after a certain number of calibrations, the estimated parameters and mismatch parameters will gradually converge, the mean value of the multiplication result will tend to 0, and τ will be gradually corrected by the mismatch parameters and tend to the estimated parameters. That is to say, if C_τ i has converged, the calibration is completed and C_err i is used as τ to calibrate the output signal of Sub_ADC2; otherwise, the calibration is not completed and the (i + 1)-th round of calibration is performed.

[0080] Specifically, if C_τ i has converged, then the estimated τ (i.e., C_err i ) is used to calibrate y 2,i [n] to obtain y 2_call,i [n], and then together with y 1,i [n] is input into the MUX, and the MUX will sequentially output the quantization results of two sub - analog - to - digital converters to obtain the final digital output y i [n].

[0081] To facilitate the understanding of the signal change in the above - mentioned method, in this Embodiment 1, V in is taken as a cosine signal for illustration:

[0082] First, let V in =cos(2πf in t), where f in represents the signal frequency of V in , and t represents time.

[0083] Assume that there is a sampling - time mismatch τ between Sub_ADC2 and Sub_ADC1, then there is:

[0084] y 1,i [n]=cos[2πf in (2nT s )];

[0085] y 2,i [n]=cos[2πf in [(2n + 1)T s +τ)]]。

[0086] Next, on the one hand, for y1,i [n] performs Hilbert transform to obtain its complex representation, and takes the imaginary part Im_y of the signal 1,i [n] = sin[2πf in (2nT s )]; on the other hand, an interpolation delay filter with configuration parameter C_τ i is used to process y 2,i [n], and we get: y 2_cal,i [n] = cos[2πf in [(2n + 1)T s + τ - C_τ i )]];

[0087] After that, multiply Im_y 1,i [n] by y 2_call,i [n], and we get:

[0088]

[0089] Then, take the average of p i [0] to p i [N], and we get:

[0090]

[0091] For avg i , the sin function is a periodic function: the integral value within one period is zero; then, when N is large enough (e.g., > 100), the average value of the sin function accumulated over multiple periods tends to zero, that is, avg i tends to 0. Then, in this case, the first term of avg i tends to zero, leaving only the second term related to τ. Therefore, avg i can be approximated as:

[0092]

[0093] Then, as the multi-round calibration progresses, when the estimated parameters and mismatch parameters gradually converge, the mean value of the multiplication result tends to 0, that is, it is considered that: the estimated parameters converge to the same value as τ, thus causing the mean value of the multiplication result to tend to 0.

[0094] Although the above example uses a cosine signal belonging to the single-tone signal category, the working mechanism of the method is still common for multi-tone signals.

[0095] Example 2

[0096] This Example 2 conducts simulation verification on the method provided in Example 1 to illustrate its effectiveness and superiority.

[0097] In this Embodiment 2, MATLAB software is used to model the dual-channel TIADC. Input signals, sampling frequencies, time mismatches and other parameters are set externally, and then the situations before and after processing using the method of Embodiment 1 are compared; among them, N is taken as 2 8 = 256.

[0098] 1. Refer to Figure 3 , which shows the comparison of the output signal spectra before and after calibrating the single-tone signal. It can be seen that the spurs caused by the sampling time mismatch are well suppressed, indicating that the calibration is successful; the SNDR (signal-to-noise and distortion ratio) index is increased from 38.74 dB to 62.08 dB; the SFDR (spurious-free dynamic range) is increased from 38.76 dB to 88.53 dB.

[0099] 2. Refer to Figure 4 , which shows the comparison of the output signal spectra before and after calibrating the multi-tone signal. It can be seen that all the spurs caused by the sampling time mismatch are well suppressed, indicating that the calibration is successful.

[0100] 3. Refer to Figure 5 , which shows the convergence curve of the estimated parameters. It can be seen that when the estimated parameters finally converge, only about 3600 sampling points (specifically 3584 samples in Figure 5 ) are consumed to complete the calibration of the sampling time mismatch.

[0101] For comparison:

[0102] Ⅰ. Han Le Duc proposed a full-digital feedforward background calibration method for sampling time mismatch of sub-sampled time-interleaved analog-to-digital converters (TIADC) based on polyphase decomposition in 2017, which requires collecting 5000 sampling points to complete the calibration of the sampling time mismatch;

[0103] Ⅱ. Han Niu proposed an efficient spurious-free aliasing spectrum calibration technique method for time-interleaved analog-to-digital converters (TIADC) in 2020, which requires collecting 4000 sampling points to complete the calibration of the sampling time mismatch.

[0104] It can be seen that the method of Embodiment 1 requires fewer sampling points and less calibration time, and has an advantage in speed.

[0105] Embodiment 3

[0106] This Embodiment 3 discloses a device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which uses the method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC provided in Embodiment 1.

[0107] This dual-channel TIADC sampling time mismatch error estimation and calibration device includes: a signal acquisition module and an error estimation and calibration module.

[0108] The signal acquisition module is configured to: take T s as a period and periodically acquire the output signals of Sub_ADC1 and Sub_ADC2 multiple times. The error estimation and calibration module is configured to: perform the i-th round of calibration based on the acquired y 1,i [n], y 2,i [n].

[0109] Specifically, the error estimation and calibration module includes: a data conversion sub-module, a digital correction sub-module, a product calculation sub-module, an averaging calculation sub-module, an estimation sub-module, and an adjustment sub-module.

[0110] The data conversion sub-module is configured to: perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing 90° phase-delayed information; the digital correction sub-module is configured to: perform digital correction on y i [n] according to the mismatch parameter C_τ 2,i in the i-th round to delay the overall signal phase by C_τ i and obtain the corrected output signal y 2_call,i [n]; the product calculation sub-module is configured to: multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n]; the averaging calculation sub-module is configured to: calculate the average value avg i of p i [0] to p i [N]; the estimation sub-module is configured to: use avg i as the iteration parameter and perform iteration on the estimation parameter C_err i-1 in the (i - 1)-th round to obtain the estimation parameter C_err i in the i-th round; the adjustment sub-module is configured to: add C_err i to T s to obtain the mismatch parameter C_τ i+1 in the (i + 1)-th round.

[0111] Of course, a judgment module can also be added to the error estimation and calibration module, which is configured to judge whether C_τ i has converged and timely feedback the calibration progress.

[0112] Example 4

[0113] Embodiment 4 discloses a computer device, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are implemented.

[0114] Embodiment 4 also discloses a readable storage medium. Computer program instructions are stored in the readable storage medium. When the computer program instructions are read and run by a processor, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are executed.

[0115] Embodiment 4 also discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are implemented.

[0116] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0117] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which is used to estimate and calibrate the sampling time mismatch τ of Sub_ADC2 with Sub_ADC1 as a reference; Sub_ADC1 and Sub_ADC2 represent two sub-analog-to-digital converters of the dual-channel TIADC; characterized in that, It includes: Taking T s as a period, obtaining the output signals of Sub_ADC1 and Sub_ADC2 periodically for multiple times; where T s represents the sampling period of the dual-channel TIADC; Based on the obtained y 1,i [n], y 2,i [n] perform the i-th round of calibration; where y 1,i [n], y 2,i [n] respectively represent the output signals of Sub_ADC1 and Sub_ADC2 at the i-th time; n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the n-th sampling point in N; i ≥ 1; Among them, the method for the i-th round of calibration includes: S100, for y 1,i [n] performs data conversion to obtain the imaginary part Im_y 1,i [n] that contains the phase information delayed by 90°; According to the mismatch parameter C_τ in the i-th round i for y 2,i [n] perform digital correction to delay the overall signal phase by C_τ i to obtain the corrected output signal y 2_call,i [n]; S200, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n]; S300, calculate p i [0] to p i The mean value avg of i ; S400, take avg i as the iteration parameter, and iterate on the estimated parameter C_err i-1 in the (i - 1)-th round to obtain the estimated parameter C_err i ; S500, add C_err i to T s to obtain the mismatch parameter C_τ for the (i + 1)-th round i+1 ; Among them, if C_τ i has converged, the calibration is completed, and C_err i is used as τ to calibrate the output signal of Sub_ADC2; otherwise, the calibration is not completed, and the (i + 1)-th round of calibration is performed.

2. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that In S100, the Hilbert transform is used to perform data conversion on y 1,i [n].

3. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that In S100, an interpolation delay filter is used to digitally correct y 2,i [n]. Among them, C_τ i is used as the configuration parameter of the interpolation delay filter during the i-th round of calibration.

4. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, wherein In S200, p i The calculation formula of [n] is: p i [n]=Im_y 1,i [n]×y 2_call,i [n]; In S300, the calculation formula for avg i is as follows: avg i = (p i [0] + … + p i [N]) / N。 5. The method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC according to claim 1, wherein In S400, C_err i The calculation formula is as follows: C_err i = C_err i-1 - μ * avg i ; In the formula, μ represents the iteration coefficient.

6. The method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC according to claim 5, characterized in that, In S400, the LMS adaptive engine filter is used to iterate on C_err i-1 ; Among them, avg i and μ are configuration parameters used by the LMS adaptive engine filter during the i-th round of calibration.

7. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that Sub_ADC1 and Sub_ADC2 sample the test signal V in to obtain the corresponding output signals; V in is a single-tone signal or a multi-tone signal.

8. A dual-channel TIADC sampling time mismatch error estimation and calibration device, characterized in that, The dual-channel TIADC sampling time mismatch error estimation and calibration method described in any one of claims 1-7 above is used. The dual-channel TIADC sampling time mismatch error estimation and calibration device includes: A signal acquisition module, which is used to acquire the output signals of Sub_ADC1 and Sub_ADC2 periodically and multiple times with T s as a period. And Error estimation and calibration module, which is used to perform the i-th round of calibration based on the acquired y 1,i [n], y 2,i [n] for the i-th round of calibration; Among them, the error estimation and calibration module includes: a data conversion sub-module, a digital correction sub-module, a product calculation sub-module, an averaging calculation sub-module, an estimation sub-module, and an adjustment sub-module. The data conversion sub-module is used to perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] that contains the phase information with a 90° delay; The digital correction sub-module is used to perform digital correction on y i [n] according to the mismatch parameter C_τ in the i-th round 2,i so as to delay the overall signal phase by C_τ i and obtain the corrected output signal y 2_call,i [n]; The product calculation sub-module is used to multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n]; The average calculation sub-module is used to calculate the average value avg of p i [0] to p i [N]; i ; The estimator submodule is used to take avg i as an iterative parameter and iterate on the estimated parameter C_err i-1 in the (i - 1)-th round to obtain the estimated parameter C_err i ; The adjustment sub-module is used to add C_err i to T s to obtain the mismatch parameter C_τ for the (i + 1)-th round i+1 .

9. The dual-channel TIADC sampling time mismatch error estimation and calibration device according to claim 8, characterized in that The error estimation and calibration module further includes: A judgment module, which is used to judge whether C_τ i has converged.

10. A computer program product, characterized in that, It includes a computer program; when the computer program is executed by a processor, it implements the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method described in any one of claims 1-7.

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