Successive approximation analog-to-digital converter design method and system for second-order Sallen Key filtering

Abstract

The invention discloses a second-order Sallen Key filtering successive approximation analog-to-digital converter design method and system, and relates to the technical field of analog-to-digital conversion. Comprising the steps that a second-order Sallen Key low-pass filter is selected, and the gain and the quality factor of an operational amplifier are determined; obtaining a second-order Sallen Key low-pass filter topological structure which comprises a resistor R1, a resistor R2, a capacitor C1, a capacitor C2 and an operational amplifier used for unity gain configuration; obtaining a transfer function according to the parameters of the second-order Sallen Key low-pass filter; determining a capacitance value, and then obtaining a resistance value based on the capacitance value and a second-order Sallen Key low-pass filter design formula; obtaining the minimum gain bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and the signal amplitude; and obtaining a DAC architecture, and obtaining a digital-to-analog converter DAC according to the SAR ADC precision index. By optimizing the structure and parameters of the filter, the anti-aliasing performance and the signal conversion precision of the ADC are improved, and the power consumption and the cost are reduced at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and particularly to a design method and system for a successive approximation analog-to-digital converter with second-order Sallen Key filtering. Background Art

[0002] Traditional SAR ADCs (successive approximation analog-to-digital converters) have some limitations in design and performance, especially in front-end filtering and signal processing. Generally, these ADCs rely on simple RC filters or even lack dedicated front-end filtering circuits, resulting in poor anti-aliasing performance. Due to insufficient anti-aliasing ability, high-frequency noise and interference are likely to mix into the signal, thus reducing the signal quality. In addition, due to the lack of a high-performance filtering circuit, the high-frequency components in the input signal may not be effectively filtered out, resulting in distortion of the sampled signal, which in turn affects the conversion accuracy.

[0003] Another problem is that the front-end circuit of traditional SAR ADCs performs poorly when processing a wide range of input signals, with a limited dynamic range. Especially in high-precision applications, this limitation is more obvious and cannot meet the requirements for a wide dynamic range and high precision. At the same time, the insufficient noise suppression ability will also lead to an increase in quantization noise and thermal noise, thereby reducing the signal-to-noise ratio (SNR) and further affecting the overall performance of the system.

[0004] In addition, the input impedance design of traditional SAR ADCs may not be well matched with the signal source, which will cause signal reflection or attenuation, further affecting the signal quality and conversion accuracy. Signal reflection not only introduces additional noise but also may cause signal distortion, especially in high-frequency applications, this problem is more prominent. Summary of the Invention

[0005] The object of the present invention is to provide a design method and system for a successive approximation analog-to-digital converter with second-order Sallen Key filtering, which can provide excellent anti-aliasing performance and signal integrity, thus ensuring the accuracy of the sampled signal.

[0006] According to the first aspect of the embodiments of the present disclosure, a design method for a successive approximation analog-to-digital converter with second-order Sallen Key filtering is provided, including the following steps:

[0007] Analyze the design requirements of the SAR ADC to determine the design needs, determine the cut-off frequency according to the sampling frequency of the SAR ADC and the Nyquist theorem, select a second-order Sallen Key low-pass filter, and determine the gain and quality factor of the operational amplifier;

[0008] Obtain the topology of the second-order Sallen Key low-pass filter, which includes resistor R 1 and resistor R 2, capacitor C 1 , capacitor C 2 , an operational amplifier for unity-gain configuration;

[0009] Obtain the transfer function according to the parameters of the second-order Sallen Key low-pass filter;

[0010] Determine the capacitance value, and then obtain the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter;

[0011] Obtain the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and signal amplitude;

[0012] Obtain the DAC architecture, and obtain the digital-to-analog converter DAC according to the accuracy index of the SAR ADC.

[0013] In one embodiment, the cut-off frequency f of the second-order Sallen Key low-pass filter c is:

[0014]

[0015] where R 1 , R 2 , C 1 , C 2 are the parameter values in the topology of the second-order Sallen Key low-pass filter. The cut-off frequency is usually set slightly higher than the maximum frequency of the input signal, but much lower than half of the sampling frequency to avoid aliasing.

[0016] In one embodiment, the transfer function of the second-order Sallen Key low-pass filter is:

[0017]

[0018] where ω 0 = 2πf c is the cut-off angular frequency, Q is the quality factor, and K is the gain. For a second-order Sallen Key low-pass filter with unity gain (K = 1), the transfer function simplifies to:

[0019]

[0020] The way to obtain the quality factor Q is:

[0021]

[0022] In one embodiment, in the topology of the second-order Sallen Key low-pass filter, select C 1 = C 2 = C and R 1 = R2 = R, then:

[0023]

[0024] Based on the required cut-off angular frequency ω 0 , the values of R and C are obtained;

[0025] At this time, the second-order Sallen Key low-pass filter is in a state similar to a voltage follower, and the amplification factor is approximately equal to 1, which neither affects the magnitude of the input signal nor can produce the effect of impedance isolation.

[0026] In one embodiment, the gain-bandwidth product (GBW) of the operational amplifier is at least 10 times the cut-off frequency; the slew rate SR of the operational amplifier ≥ 2πf c V pp , where V pp is the peak voltage to avoid distortion when a large signal is input.

[0027] In one embodiment, the DAC architecture uses a capacitive DAC. KT / C noise is the thermal noise in the capacitive DAC, mainly caused by the thermal fluctuations of the charge on the capacitor during the sampling process. The acquisition method is as follows:

[0028]

[0029] where V n is the noise voltage (RMS value), k is the Boltzmann constant (1.38×10 -23 J / K), T is the absolute temperature (unit: K), C is the capacitance value (unit: F). KT / C noise limits the dynamic range and signal-to-noise ratio of the DAC. For high-precision DACs, KT / C noise is an important design constraint.

[0030] In one embodiment, a segmented capacitive array is adopted according to the SAR ADC accuracy index. A bridging capacitor is used to connect the high-order capacitive array and the low-order capacitive array. The voltages at both ends of the bridging capacitor satisfy a two-fold relationship to meet the linearity requirement.

[0031] According to the second aspect of the embodiments of the present disclosure, a second-order Sallen Key filtering successive approximation analog-to-digital converter design system is provided, including:

[0032] A selection module analyzes the SAR ADC design specifications to determine the design requirements, determines the cut-off frequency according to the sampling frequency of the SAR ADC and the Nyquist theorem, selects a second-order Sallen Key low-pass filter, and determines the amplifier gain and quality factor;

[0033] Topology module, obtaining the topology of a second-order Sallen Key low-pass filter, which includes resistor R 1 and resistor R 2 and capacitor C 1 and capacitor C 2 and an operational amplifier for unity-gain configuration;

[0034] Function module, obtaining the transfer function according to the parameters of the second-order Sallen Key low-pass filter;

[0035] Parameter module, determining the capacitance value, and then obtaining the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter;

[0036] Operation module, obtaining the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and signal amplitude;

[0037] Design module, obtaining the DAC architecture and obtaining the digital-to-analog converter DAC according to the accuracy index of the SAR ADC.

[0038] According to the third aspect of the embodiments of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program running on the memory. When the processor executes the program, the method for designing a successive approximation analog-to-digital converter with second-order Sallen Key filtering is implemented.

[0039] According to the fourth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method for designing a successive approximation analog-to-digital converter with second-order Sallen Key filtering is implemented.

[0040] The above technical solutions adopted by the present invention, compared with the prior art, have the following advantages: 1. The Sallen Key filter has a simple structure and only requires one operational amplifier, two resistors, and two capacitors to achieve second-order filtering. A low-pass filter can be designed by adjusting the component parameters. Adding it at the front end of the SAR ADC can effectively reduce the influence of input noise on the accuracy of the SAR ADC.

[0041] 2. Adding a Sallen Key filter at the sampling front end of the SAR ADC can reduce the influence of the SAR ADC on the previous-stage circuit and produce an isolation effect. The input impedance of the Sallen-Key filter is relatively high, and the load effect on the previous-stage circuit is small. Integrating the Sallen-Key filter and the SAR ADC on the same chip can improve the system integration and reduce the production cost. Description of the Drawings

[0042] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The illustrative embodiments and descriptions thereof of this application are used to explain this application and do not constitute an improper limitation of this application.

[0043] Figure 1 It is a design circuit diagram of a SAR ADC based on a second-order Sallen Key filter. Detailed implementation manners

[0044] The present disclosure will be further described below in conjunction with the accompanying drawings and embodiments.

[0045] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0046] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary implementation manners according to this application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0047] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of methods and systems according to various embodiments of the present disclosure. It should be noted that each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, the program segment, or the part of code may include one or more executable instructions for implementing the logical functions specified in each embodiment. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the flowchart and / or block diagram, as well as the combinations of blocks in the flowchart and / or block diagram, may be implemented using a dedicated hardware-based system for performing the specified functions or operations, or may be implemented using a combination of dedicated hardware and computer instructions.

[0048] In order to prove the effectiveness of the method proposed by the present invention, the following examples are selected for calculation. The design problem of a SAR ADC based on a second-order Sallen Key filter involves a total of nine design variables, including the cut-off frequency fc, the gain K, the quality factor Q, the capacitance values C1, C2, the resistance values R1, R2, the SAR ADC accuracy N, and the KT / C noise.

[0049] Embodiment 1:

[0050] This embodiment provides a design method for a successive approximation analog-to-digital converter with a second-order Sallen Key filter, including the following steps:

[0051] Step 1: Analyze the design requirements of the SAR ADC to determine the design needs. For example, the accuracy of the SAR ADC is 14 bits. Determine the cut-off frequency f according to the sampling frequency of the SAR ADC and the Nyquist theorem c = 10 kHz, design a second-order Sallen Key low-pass filter, and determine the operational amplifier gain K = 1 and the quality factor = 0.5;

[0052] Step 2: Obtain the topology of the second-order Sallen Key low-pass filter, which includes a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, and an operational amplifier for unity-gain configuration. The specific circuit structure is as Figure 1 shown;

[0053] Step 3: Obtain the transfer function according to the parameters of the second-order Sallen Key low-pass filter as:

[0054]

[0055] Step 4: Determine the capacitance value, and then obtain the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter;

[0056] Specifically, select the capacitance value C 1 = C 2 = 1 nF, substitute it into Equation (4) to get:

[0057]

[0058] According to the cut-off frequency formula (1), substitute fc = 10 kHz and C 1 = C 2 = 1 nF to get:

[0059]

[0060] Therefore

[0061] R 1 R 2 = (15.915 kΩ) 2 (11)

[0062] R 1 = R 2 = 15.915 kΩ, and the standard value 16 kΩ can be selected.

[0063] Step 5: Obtain the minimum gain-bandwidth product and slew rate of the required operational amplifier based on the cut-off frequency and signal amplitude;

[0064] Specifically, select an operational amplifier with a high enough bandwidth to ensure good performance near the cut-off frequency; the gain-bandwidth product (GBW) of the operational amplifier should be at least 10 times the cut-off frequency, i.e., GBW ≥ 10×f c = 100 kHz. To leave a margin, an operational amplifier with GBW ≥ 1 MHz can be selected; assuming the amplitude of the SAR ADC input signal V pp = 5 V, the required slew rate SR ≥ 2πf c V pp = 2π×10 4 ×5 ≈ 0.314 V / us, and an operational amplifier with SR ≥ 1 V / us can be selected.

[0065] In summary, a general-purpose operational amplifier Texas Instruments TL072 with GBW = 3 MHz and SR = 13 V / us can be selected.

[0066] Step 6: Obtain the DAC architecture and get the digital-to-analog converter DAC according to the SAR ADC accuracy index;

[0067] Specifically, design a two-stage digital-to-analog converter DAC according to the SAR ADC accuracy index of 14 bits, divide the capacitor array into the upper 7 bits and the lower 7 bits, and connect them with a bridging capacitor in the middle.

[0068] The smallest capacitor in the capacitor array is 1C, there are 7 bits each for the high and low bits, the largest capacitor is 64C, and the bridging capacitor Cs = 1C. The unit capacitor multiplexing design can facilitate the layout and wiring of the layout, and at the same time it is also convenient to calculate whether the circuit linearity is guaranteed.

[0069] The SAR ADC control timing is as follows:

[0070] 1) Sampling: SIN and VIN are closed, SM7~SM1 are closed to connect CM7~CM1 to the input, S0 is closed, the voltage of the upper plate of the capacitor is connected to VCM, both input terminals of the operational amplifier are connected to VCM, and SL7~SL1 make the lower plates of CL7~CL1 grounded;

[0071] 2) Hold: S0 is disconnected, SIN is connected to VREF, SM7~SM1 and SL7~SL1 are all grounded, (VREF is not actually connected to the circuit), but the charge is redistributed, and the voltage V X of the positive input terminal of the operational amplifier changes;

[0072] 3) Charge redistribution: MSB is connected to VREF, and SM7 is connected to CM7;

[0073] 4) The second-highest bit is connected to VREF, equivalent to V X Plus 1 / 4 VREF, and then compared with the input to obtain the value of the second-highest bit.

[0074] 5) Compare each bit sequentially one by one, and finally obtain the converted output.

[0075] In addition, assuming that this capacitive DAC operates at room temperature (T = 300K) and the minimum unit capacitance C = 1 fF, the KT / C noise is:

[0076]

[0077] Cutoff frequency verification:

[0078]

[0079] Quality factor verification:

[0080]

[0081] In summary, the Sallen-Key filter can provide a smooth and low-noise signal, and the Sallen Key filter has excellent anti-aliasing performance, simple structure, low power consumption, low cost, easy integration, etc. This design is particularly suitable for application scenarios that require high precision, low noise, and low power consumption, such as sensor interfaces, portable devices, and industrial control systems. By reasonably designing the parameters of the filter and the SAR ADC, the overall performance of the system can be significantly improved.

[0082] Embodiment 2:

[0083] This embodiment provides a successive approximation analog-to-digital converter design system with second-order Sallen Key filtering, including:

[0084] A selection module analyzes the design requirements of the SAR ADC design specifications, determines the cutoff frequency according to the sampling frequency of the SAR ADC and the Nyquist theorem, selects a second-order Sallen Key low-pass filter, and determines the amplifier gain and quality factor;

[0085] A topology module obtains the topology structure of the second-order Sallen Key low-pass filter, which includes resistor R 1 , resistor R 2 , capacitor C 1 , capacitor C 2 , and an operational amplifier for unity gain configuration;

[0086] A function module obtains the transfer function according to the parameters of the second-order Sallen Key low-pass filter;

[0087] A parameter module determines the capacitance value and then obtains the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter;

[0088] An operation module obtains the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and the signal amplitude;

[0089] A design module obtains the DAC architecture and gets the digital-to-analog converter DAC according to the accuracy index of the SAR ADC.

[0090] Embodiment 3:

[0091] An electronic device includes a memory, a processor, and a computer program running on the memory. When the processor executes the program, it implements the above-mentioned design method of a successive approximation analog-to-digital converter with second-order Sallen Key filtering, including:

[0092] Analyze the design requirements of the SAR ADC design index, determine the cut-off frequency according to the sampling frequency of the SAR ADC and the Nyquist theorem, select a second-order Sallen Key low-pass filter, and determine the gain and quality factor of the operational amplifier;

[0093] Obtain the topology structure of the second-order Sallen Key low-pass filter, which includes resistor R 1 , resistor R 2 , capacitor C 1 , capacitor C 2 , and an operational amplifier for unity-gain configuration;

[0094] Obtain the transfer function according to the parameters of the second-order Sallen Key low-pass filter;

[0095] Determine the capacitance value, and then obtain the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter;

[0096] Obtain the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and the signal amplitude;

[0097] Obtain the DAC architecture and get the digital-to-analog converter DAC according to the accuracy index of the SAR ADC.

[0098] Embodiment 4:

[0099] A computer-readable storage medium stores a computer program, and when the program is executed by a processor, it implements the above-mentioned design method of a successive approximation analog-to-digital converter with second-order Sallen Key filtering, including:

[0100] Analyze the design specifications of the SAR ADC to determine the design requirements. Determine the cut-off frequency according to the sampling frequency of the SAR ADC and the Nyquist theorem. Select a second-order Sallen Key low-pass filter and determine the gain and quality factor of the operational amplifier.

[0101] Obtain the topology of the second-order Sallen Key low-pass filter, which includes resistor R 1 、resistor R 2 、capacitor C 1 、capacitor C 2 、and an operational amplifier for unity-gain configuration.

[0102] Obtain the transfer function according to the parameters of the second-order Sallen Key low-pass filter.

[0103] Determine the capacitance value, and then obtain the resistance value based on the capacitance value and the design formula of the second-order Sallen Key low-pass filter.

[0104] Obtain the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cut-off frequency and the signal amplitude.

[0105] Obtain the DAC architecture and obtain the digital-to-analog converter (DAC) according to the accuracy index of the SAR ADC.

[0106] Those skilled in the art should understand that the above-mentioned modules or steps of the present disclosure can be implemented by a general-purpose computer device. Optionally, they can be implemented by program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. The present disclosure is not limited to any specific combination of hardware and software.

[0107] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

[0108] Although the specific implementation manners of the present disclosure are described above in conjunction with the accompanying drawings, it is not a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that based on the technical solutions of the present disclosure, various modifications or deformations that can be made by those skilled in the art without creative efforts are still within the protection scope of the present disclosure.

Claims

1. A method for designing a successive approximation analog-to-digital converter for a second-order Sallen Key filter, characterized in that: The following steps are involved: Analyze the SAR ADC design indicators to determine the design requirements, determine the cutoff frequency based on the SAR ADC sampling frequency and Nyquist theorem, select the second-order Sallen Key low-pass filter, and determine the operational amplifier gain and quality factor; Obtain a second-order Sallen Key low-pass filter topology including a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, and an operational amplifier configured in unity gain; The transfer function is obtained based on the parameters of the second-order Sallen Key low-pass filter; Determine the capacitor value, and then find the resistor value based on the capacitor value and the second-order Sallen Key low-pass filter design formula; The minimum gain-bandwidth product and slew rate of the required operational amplifier are obtained according to the cutoff frequency and signal amplitude; The DAC architecture is obtained, and the digital-to-analog converter DAC is obtained according to the SAR ADC accuracy index.

2. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: The cutoff frequency f of the second-order Sallen Key low-pass filter c for: Wherein R1, R2, C1, C2 are parameter values ​​in the second-order Sallen Key low-pass filter topology.

3. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: The transfer function of a second-order Sallen Key low-pass filter is: Where ω0=2πf c is the cutoff frequency, Q is the quality factor, and K is the gain. For a second-order Sallen Key low-pass filter with unity gain (K = 1), the transfer function is simplified to: The quality factor Q is obtained as follows:

4. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: In the second-order Sallen Key low-pass filter topology, select C1=C2=C and R1=R2=R, then: The values ​​of R and C are obtained based on the required cutoff angular frequency ω0.

5. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: The gain bandwidth product of the operational amplifier is at least 10 times the cut-off frequency; the slew rate SR of the operational amplifier is ≥ 2πf c V pp , where V pp is the peak voltage.

6. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: The DAC architecture uses a capacitive DAC, which is obtained as follows: Where V n is the noise voltage, k is the Boltzmann constant, T is the absolute temperature, C is the capacitance value, and KT / C noise limits the dynamic range and signal-to-noise ratio of the DAC.

7. The method for designing a second-order Sallen Key filtered successive approximation analog-to-digital converter according to claim 1, characterized in that: According to the SAR ADC accuracy index, a segmented capacitor array is used, and a bridge capacitor is used to connect the high-order capacitor array and the low-order capacitor array. The voltage across the bridge capacitor satisfies a two-fold relationship to meet the linearity requirement.

8. A second-order Sallen Key filtered successive approximation analog-to-digital converter design system, characterized in that: include: Select the module, analyze the SAR ADC design indicators to determine the design requirements, determine the cutoff frequency based on the SAR ADC sampling frequency and Nyquist theorem, select the second-order Sallen Key low-pass filter, and determine the amplifier gain and quality factor; A topology module, which obtains a second-order Sallen Key low-pass filter topology structure, which includes a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, and an operational amplifier configured in unity gain; Function module, which obtains the transfer function according to the parameters of the second-order Sallen Key low-pass filter; The parameter module determines the capacitance value, and then obtains the resistance value based on the capacitance value and the second-order Sallen Key low-pass filter design formula; An operation module obtains the minimum gain-bandwidth product and slew rate of the required operational amplifier according to the cutoff frequency and the signal amplitude; Design the module, obtain the DAC architecture, and obtain the digital-to-analog converter DAC based on the SAR ADC accuracy index.

9. An electronic device comprising a memory, a processor and a computer program stored and running on the memory, characterized in that: When the processor executes the program, the method for designing a successive approximation analog-to-digital converter for a second-order Sallen Key filter is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, a successive approximation analog-to-digital converter design method for a second-order Sallen Key filter is implemented.

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