Partial common-mode level-based switching method for SAR-ADC

Abstract

A partial common mode level-based switching method for SAR-ADC relates to the technical field of integrated circuits, in a sampling stage, an input signal is sampled to a top plate of a capacitor array, and bottom plates of a highest weight bit capacitor and a second highest weight bit capacitor are connected to a common mode level Vcm; in the conversion phase, the MSB decision is directly made by comparing the differences between the differential inputs. Since the operation of the highest weight bit capacitor and the operation of the second highest weight bit capacitor are differential, the common mode remains unchanged. For the cycle of the remaining bits, the bits in the corresponding capacitor array will be discharged to Gnd. For an n-bit ADC, this operation is repeated n-3 times until the last bit is determined. Compared with a back-switching method, the common mode change can be improved while good energy efficiency of the switch and the logic controller is maintained.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a switching method based on a partial common-mode level for a SAR-ADC. Background Art

[0002] High-speed (>500 MS / s sampling rate) and low-to-medium resolution (5 to 7 bits) ADCs are widely used in ultra-wideband communication systems. A successive approximation register (SAR) ADC is a power-efficient architecture, and its core structure mainly includes a capacitive DAC, a comparator, a successive approximation register, and switching control logic, etc. Figure 1 The structural block diagram of a traditional successive approximation type ADC is shown. Due to its fully dynamic operation, simple structure, and advantages in technology scaling, with the development of modern nano-CMOS technology and advanced circuit solutions, SAR-ADCs can achieve high speed and become a competitive solution for such applications.

[0003] Due to its conversion linearity, speed, and energy efficiency, the capacitive digital-to-analog converter (DAC) adopts a switched approach. Several switching techniques have been proposed to improve the power efficiency of capacitive DACs. For low-speed applications (<1 MS / s), such as sensor networks and implantable biomedical devices, the SAR-ADC can benefit from advanced switching techniques because its switching energy occupies a large part of the power consumption. However, if the SAR-ADC is designed for high speed, its power is dominated by the digital part, i.e., the SAR controller. Typically, the switching energy accounts for less than 15% of the total ADC power consumption. Therefore, the method of mainly reducing the switching energy is not very effective for high-speed SARs. Some existing monotonic and switchback switching methods, such as the techniques mentioned in the references "C.-C. Liu, et al., “A 10-bit 50-MS / s SAR-ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010" and "G.-Y. Huang, et al., “10-bit 30-MS / s SAR-ADC using a switchback switching method,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 3, pp. 584-588, Mar. 2013", simplify the control logic of the SAR conversion and achieve good high-speed energy efficiency, but they all suffer from common-mode variations during the bit cycle. The common-mode variations in the comparator are more critical because it causes dynamic offset, noise, and input parasitic variations, which significantly affect the speed and accuracy of the comparison. The switchback switching method reduces the common-mode level variation by 50% compared to the monotonic switching method. However, due to the switchback switching operation being purely single-ended, it still causes a larger common-mode level variation compared to traditional switches. Figure 2 Shows the switching process of the traditional switchback method. Summary of the Invention

[0004] The object of the present invention is to propose a switching method based on partial common-mode levels for SAR-ADCs, which can not only maintain the good energy efficiency of the switch and the logic controller, but also improve the common-mode variations compared to the switchback method.

[0005] The technical solution adopted by the present invention to achieve its invention purpose is a switching method based on a partial common-mode level for a SAR-ADC. The P-terminal capacitor array and the N-terminal capacitor array of the SAR-ADC are each composed of a binary-weighted capacitor array and a capacitor equal in value to the LSB capacitor, and the method includes the following steps:

[0006] (1) Sampling stage: The input signals Vip and Vin are respectively sampled onto the top plates of the capacitors in the P-terminal capacitor array and the N-terminal capacitor array. The bottom plates of the capacitors with the highest weight bit and the second-highest weight bit in the P-terminal capacitor array and the N-terminal capacitor array are both connected to the common-mode level Vcm, and the bottom plates of the remaining capacitors are connected to the reference voltage Vref;

[0007] (2) Charge locking at the instant of sampling disconnection and the first comparison. If Vop > Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref;

[0008] If Vop < Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd;

[0009] where Vop is the voltage of the P-terminal capacitor array and Von is the voltage of the N-terminal capacitor array;

[0010] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0011] (3) Second comparison: If Vop > Von at this time, the bottom plate of the capacitor with the second-highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the second-highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref;

[0012] If Vop < Von at this time, the bottom plate of the capacitor with the second-highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the second-highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd;

[0013] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0014] (4) Third comparison: If Vop > Von at this time, the bottom plate of the capacitor with the third-highest weight bit in the P-terminal capacitor array is switched from the reference voltage Vref to the ground level Gnd;

[0015] If Vop < Von at this time, the bottom plate of the third highest weighted capacitor in the N-terminal capacitor array switches from the reference voltage Vref to the ground level Gnd;

[0016] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0017] (5) Subsequent comparison: According to the method of the third comparison, the switching of the remaining capacitors in the binary weighted capacitor array is cyclically completed, thereby completing the entire successive approximation comparison process.

[0018] Furthermore, Vcm = 1 / 2Vref.

[0019] The beneficial effects of the present invention are as follows:

[0020] While maintaining the good energy efficiency of the switch and the logic controller, compared with the back-off method, it can improve the common-mode variation, and the design complexity and digital overhead of the controller are not significant. Description of the Drawings

[0021] Figure 1 is the structural block diagram of a traditional successive approximation ADC;

[0022] Figure 2 is the schematic flow diagram of the traditional back-off method;

[0023] Figure 3 is the schematic flow diagram of the embodiment of the present invention;

[0024] Figure 4 is the schematic diagram of the energy consumption of the traditional back-off method;

[0025] Figure 5 is the schematic diagram of the energy consumption of the embodiment of the present invention. Detailed Embodiments

[0026] In order to be able to more clearly understand the above objects, features, and advantages of the present invention, the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0027] Figure 3 Disclosed is a switching method based on a partial common-mode level for a SAR-ADC of the present invention. The P-terminal capacitor array and the N-terminal capacitor array of the SAR-ADC are both composed of 1 binary weighted capacitor array and 1 capacitor equal in value to the LSB capacitor, and include the following steps:

[0028] (1) During the sampling phase, the input signals Vip and Vin are respectively sampled onto the top plates of the capacitors in the P-terminal capacitor array and the N-terminal capacitor array. The bottom plates of the capacitors with the highest weight bit and the second highest weight bit in the P-terminal capacitor array and the N-terminal capacitor array are both connected to the common-mode level Vcm, and the bottom plates of the remaining capacitors are connected to the reference voltage Vref;

[0029] (2) At the moment when the sampling is disconnected, charge locking occurs and the first comparison is made. If Vop > Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref;

[0030] If Vop < Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd;

[0031] where Vop is the voltage of the P-terminal capacitor array and Von is the voltage of the N-terminal capacitor array;

[0032] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0033] (3) Second comparison: If Vop > Von at this time, the bottom plate of the capacitor with the second highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the second highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref;

[0034] If Vop < Von at this time, the bottom plate of the capacitor with the second highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the second highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd;

[0035] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0036] (4) Third comparison: If Vop > Von at this time, the bottom plate of the capacitor with the third highest weight bit in the P-terminal capacitor array is switched from the reference voltage Vref to the ground level Gnd;

[0037] If Vop < Von at this time, the bottom plate of the capacitor with the third highest weight bit in the N-terminal capacitor array is switched from the reference voltage Vref to the ground level Gnd;

[0038] The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array;

[0039] (5)Subsequent comparison: According to the method of the third comparison, the switching of the remaining capacitors in the binary weighted capacitor array is cyclically completed, thereby completing the entire successive approximation comparison process.

[0040] In this embodiment, Vcm = 1 / 2Vref.

[0041] In the sampling stage of the present invention, the input signal is sampled onto the top plates of the capacitor array, and the bottom plates of the highest weight bit and the second highest weight bit capacitors are both connected to the common mode level Vcm; in the conversion stage, the MSB decision is directly made by comparing the difference between the differential inputs. Since the operations of the highest weight bit and the second highest weight bit capacitors are differential, their common mode remains unchanged. For the remaining bit cycles, the corresponding bits in the capacitor array will be discharged to Gnd. For an n-bit ADC, this operation is repeated n - 3 times until the last bit is determined. Although the operation of the LSB is single-ended and will cause a common mode change, the amount is much smaller than the back-off method, as Figure 5 shown, the maximum change amount is Vref / 8, which is 50% lower than the Figure 4 back-off method shown. In addition, since only the highest weight bit and the second highest weight bit capacitors are involved in the switching based on Vcm, the design complexity and digital overhead of the controller are not significant.

[0042] For an n-bit SAR-ADC, the average switching energy of the method proposed by the present invention can be derived as:

[0043]

[0044] where C is the unit capacitance and Vref is the reference voltage.

[0045] For a 10-bit case including sampling reset energy, the total energy consumed by the monotonic and slewing switches is and while the energy consumed by the method proposed by the present invention is which includes the energy of the Vcm input during sampling

Claims

1. A switching method based on partial common mode level for SAR-ADC, wherein the P-terminal capacitor array and the N-terminal capacitor array of the SAR-ADC are each composed of a binary weighted capacitor array and a capacitor with a value equal to the LSB capacitor, characterized in that: It includes the following steps: (1) Sampling stage: The input signals Vip and Vin are respectively sampled onto the top plates of the capacitors in the P-terminal capacitor array and the N-terminal capacitor array. The bottom plates of the capacitors with the highest and the second-highest weight bits in the P-terminal capacitor array and the N-terminal capacitor array are both connected to the common-mode level Vcm, and the bottom plates of the remaining capacitors are connected to the reference voltage Vref; (2) Charge locking at the instant of sampling disconnection and the first comparison: If Vop > Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref; If Vop < Von at this time, the bottom plate of the capacitor with the highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd; where Vop is the voltage of the P-terminal capacitor array and Von is the voltage of the N-terminal capacitor array; The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array; (3) Second comparison: If Vop > Von at this time, the bottom plate of the capacitor with the second-highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd, and the bottom plate of the capacitor with the second-highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref; If Vop < Von at this time, the bottom plate of the capacitor with the second-highest weight bit in the P-terminal capacitor array is switched from the common-mode level Vcm to the reference voltage Vref, and the bottom plate of the capacitor with the second-highest weight bit in the N-terminal capacitor array is switched from the common-mode level Vcm to the ground level Gnd; The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array; (4) Third comparison: If Vop > Von at this time, the bottom plate of the capacitor with the third-highest weight bit in the P-terminal capacitor array is switched from the reference voltage Vref to the ground level Gnd; If Vop < Von at this time, the bottom plate of the capacitor with the third-highest weight bit in the N-terminal capacitor array is switched from the reference voltage Vref to the ground level Gnd; The remaining capacitors remain in their original states; the comparator completes the comparison of the voltage Vop of the P-terminal capacitor array and the voltage Von of the N-terminal capacitor array; (5) Subsequent comparisons: According to the method of the third comparison, the switching of the remaining capacitors in the binary weighted capacitor array is cyclically completed, thus completing the entire successive approximation comparison process.

2. The switching method based on partial common mode level for SAR-ADC according to claim 1, characterized in that: Vcm = 1 / 2Vref.

Images