Semiconductor structure, memory chip

Abstract

A semiconductor structure, a memory chip. The semiconductor structure comprises: a first well region; a first active region located in the first well region and extending along a first direction; a second active region located in the first well region and extending along the first direction, the first active region is closer to a side edge of the first well region relative to the second active region in a second direction; a gate located on the first well region and contacting the first active region and the second active region; wherein, in the first direction, the gate has a first length on the first active region, the gate has a second length on the second active region, and the first length is less than the second length. The semiconductor structure has good performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a memory chip. Background Technology

[0002] The layout of DRAM (Dynamic Random Access Memory) includes memory cell areas (arrays), sensing amplifiers (SAs), and word line drivers (SWDs). The word line drivers are primarily responsible for providing the drive voltage to enable the word lines of the memory. Word line drivers consist of a large number of repeating drive cells, each containing a large number of transistors. Mismatched performance among some transistors can lead to low device reliability. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0004] First well region;

[0005] The first active region is located in the first well region and extends along the first direction;

[0006] The second active region is located in the first well region and extends along the first direction. In the second direction, the first active region is closer to the side edge of the first well region than the second active region.

[0007] The gate is located on the first well region and is in contact with the first active region and the second active region;

[0008] In the first direction, the gate has a first length in the first active region and a second length in the second active region, wherein the first length is less than the second length.

[0009] In some embodiments, in the second direction, the gate has a first width in the first active region and a second width in the second active region, the second width being equal to the first width.

[0010] In some embodiments, in the second direction, the gate has a first width in the first active region and a second width in the second active region, the second width being smaller than the first width.

[0011] In some embodiments, the first active region includes an extension, the second active region includes a recess, the extension is embedded in the recess, and in a second direction, the width of the extension is greater than the width of the recess.

[0012] In some embodiments, a second well region is further included, which is located on both sides of the first well region in the second direction, wherein the ion doping type of the second well region is different from that of the first well region.

[0013] In some embodiments, a mixed well region is provided between the first well region and the second well region, the mixed well region including the ion doping type of the first well region and the ion doping type of the second well region.

[0014] In some embodiments, the hybrid well region is the overlapping region of the first well region and the second well region.

[0015] In some embodiments, the gate further includes a first protrusion located outside the first active region, wherein the length of the first protrusion is greater than the first length in the first direction.

[0016] In some embodiments, the gate further includes a second protrusion located between the first active region and the second active region, wherein, in the first direction, the length of the second protrusion is greater than the second length.

[0017] In some embodiments, in the first direction, the first protrusion protrudes beyond the edge of the first active region, and the second protrusion protrudes beyond the edge of the first active region.

[0018] In some embodiments, in the first direction, the length of the first protrusion is equal to the length of the second protrusion.

[0019] In some embodiments, the gate includes a first gate and a second gate, the first gate and the second gate being disposed in parallel on the first active region and the second active region.

[0020] In some embodiments, the first protrusion on the first gate and the first protrusion on the second gate extend in opposite directions, and the second protrusion on the first gate and the second protrusion on the second gate extend in opposite directions.

[0021] In some embodiments, the gate and the first active region form a first transistor, the gate and the second active region form a second transistor, the first transistor and the second transistor are transistors of the same type, the first length is the channel length of the first transistor, the second length is the channel length of the second transistor, the first width is the channel width of the first transistor, and the second width is the channel width of the second transistor.

[0022] According to a second aspect of the present disclosure, a memory chip is provided, including the semiconductor structure described above.

[0023] In summary, this disclosure provides a semiconductor structure and a memory chip. The semiconductor structure includes a first active region and a second active region, with a gate located on both regions, thereby forming a first transistor and a second transistor, respectively. Furthermore, since the first active region is closer to the side edge of the first well region than the second active region, the first transistor is closer to the side edge of the first well region. Additionally, in a first direction, the length of the gate on the first active region is shorter than the length of the gate on the second active region, meaning the channel length of the first transistor is smaller. This reduced channel length increases the transistor's drive current, thereby improving the driving capability of the first transistor. This allows the driving capability of the first transistor to match that of the second transistor, thus reducing the impact on device reliability. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of a driving unit according to an exemplary embodiment;

[0025] Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0026] Figure 3 This is yet another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0027] Figure 4 This is illustrated according to an exemplary embodiment. Figure 3 Cross-sectional view along the AA direction;

[0028] Figure 5 This is yet another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0029] Figure 6 This is yet another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0030] Figure 7 This is a schematic diagram illustrating a first active region and a second active region according to an exemplary embodiment;

[0031] Figure 8 This is a cross-sectional view of a first active region and a second active region according to an exemplary embodiment;

[0032] Figure 9 This is yet another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0033] Figure 10 This is illustrated according to an exemplary embodiment. Figure 9Cross-sectional view in the BB direction;

[0034] Figure 11 This is yet another schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0035] Figure 12 This is a schematic diagram of a memory chip according to an exemplary embodiment. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0037] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0038] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0039] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0041] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0042] In Dynamic Random Access Memory (DRAM), the activation and deactivation of memory cells are controlled by word lines, which are controlled by sub-wordline drivers (SWDs). As chip technology advances, the demand for miniaturization of devices increases. Simultaneously, the sheer number of driver cells and transistors causes some transistors to be positioned closer to the side edges of the well region, leading to performance mismatches.

[0043] like Figure 1 As shown, Figure 1 The diagram shows a circuit of a driving unit for a word line driver. This driving unit may include a first NMOS transistor N1, a second NMOS transistor N2, and a PMOS transistor P1. The drain of PMOS transistor P1 is connected to the word line WL and is used to drive the memory array connected to the word line WL. The source of PMOS transistor P1 receives the word line select signal PXID. The gate of PMOS transistor P1 receives the word line turn-on voltage MWLB and uses MWLB as its gate control voltage, controlling whether the word line is turned on by controlling whether the word line select signal PXID is passed.

[0044] like Figure 1 As shown, the gate of the first NMOS transistor N1 receives the word line open-gate voltage MWLB and uses it as its gate control voltage. The drain of the first NMOS transistor N1 is connected to the word line WL, and its source is grounded to VSS. The word line WL can be turned off by connecting its drain and source to grounded VSS. The gate of the second NMOS transistor N2 receives the word line select complement signal PXIB. The drain of the second NMOS transistor N2 is connected to the word line WL, and its source is grounded to VSS. The word line WL can be turned off by connecting its drain and source to grounded VSS. To turn on the word line WL, the word line open-gate voltage MWLB needs to be low, the word line select signal PXID needs to be high, and the word line select complement signal PXIB needs to be low. In this situation, PMOS transistor P1 is turned on, first NMOS transistor N1 and second NMOS transistor N2 are turned off, and word line WL is turned on.

[0045] like Figure 1As shown, the word line driver's driving unit includes a PMOS and a pair of NMOS transistors, i.e., a 2N1P structure. This pair of NMOS transistors is located on either side of the PMOS. The applicant's research revealed a difference in driving capability between the transistors closer to and farther from the NMOS in the PMOS, leading to low device reliability. Further research by the applicant found that during PMOS formation, the active region closer to the NMOS is doped with more ions, while the active region farther from the NMOS is doped with fewer ions, resulting in a difference in driving capability between the two transistors.

[0046] Given the increasing miniaturization of memory devices, the applicant has improved the channel length of the two transistors, thereby reducing the difference in driving capability between them, while also ensuring the miniaturization of the memory devices.

[0047] like Figure 2 As shown, this disclosure provides a semiconductor structure 100, which may include a first well region 101, in which a first active region 103 and a second active region 104 are located. The first active region 103 and the second active region 104 may be separated by an isolation structure. The first active region 103 and the second active region 104 may extend along a first direction (X direction), and the first active region 103 and the second active region 104 may be arranged along a second direction (Y direction). The first active region 103 and the second active region 104 may have the same structure. The first active region 103 and the second active region 104 may have a regular structure, for example. In the second direction, the first active region 103 is closer to the side edge of the first well region 101, and the second active region 104 is farther away from the side edge of the first well region 101, that is, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104.

[0048] like Figure 2As shown, a gate 105 is also present in the first well region 101. The gate 105 can be located on the first active region 103 and the second active region 104, that is, the gate 105 is in contact with both the first active region 103 and the second active region 104. The gate 105 can extend along a second direction, thereby extending to the outside of the first active region 103 and the second active region 104. In the first direction, since the gate 105 has a certain length, the gate 105 has a first length L1 in the first active region 103 and a second length L2 in the second active region 104. The first length L1 can be less than the second length L2. In this embodiment, the gate 105 can be divided into two parts, the first part being located, for example, on the first active region 103, and the second part being located, for example, on the second active region 104. The first part has a length of L1 in the first direction, and the second part has a length of L2 in the second direction. The first part changes from the first length L1 between the first active region 103 and the second active region 104 to the second length L2 of the second part, thereby realizing that the same gate 105 has different lengths in the first active region 103 and the second active region 104.

[0049] like Figure 2As shown in the embodiments of this disclosure, the first active region 103 and the second active region 104 are formed before the first well region 101. That is, the first active region 103 and the second active region 104 can be formed in the substrate first, and then the substrate is ion-doped to form the first well region 101, so that the first active region 103 and the second active region 104 can be located in the first well region 101. The first well region 101 is, for example, an N-type well region, and the doping ions in the first well region 101 are N-type, such as one or more of phosphorus ions, arsenic ions, and antimony ions. Since the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104 in the second direction, the ion doping concentration in the first active region 103 will be greater than the ion doping concentration in the second active region 104 during N-type ion doping. At this time, if the gate 105 has the same length in the first active region 103 and the second active region 104 in the first direction, that is, the channel length of the first transistor (formed by the gate 105 and the first active region 103) is equal to the channel length of the second transistor (formed by the gate 105 and the second active region 104), the driving capability of the first transistor is worse than that of the second transistor. In this embodiment, due to the well proximity effect, the driving capability of the first transistor is less than that of the second transistor, meaning there is a performance difference between the two transistors. In this embodiment, the first length L1 of the gate 105 on the first active region 103 is less than the second length L2 of the gate 105 on the second active region 104, thereby reducing the channel length of the first transistor. According to the transistor turn-on power supply formula, reducing the channel length increases the driving current of the transistor, which in turn improves the driving capability of the first transistor. This allows for better matching of the driving capability of the second transistor, reducing the performance difference between the two transistors and improving the reliability of the device.

[0050] like Figure 2 As shown in this embodiment, the first direction (X direction) is the direction of the channel length of the transistor generated by the first active region 103 or the second active region 104, and the second direction (Y direction) is the direction of the channel width of the transistor generated by the first active region 103 or the second active region 104.

[0051] like Figure 3 As shown in the embodiments of this disclosure, a semiconductor structure 100 is proposed, which may include a first well region 101 and a second well region 102. The second well region 102 is located on both sides of the first well region 101. The first well region 101 and the second well region 102 have different ion doping types; the first well region 101 is used to form a PMOS, and the second well region 102 is used to form an NMOS. The first well region 101 may be doped with various dopants such as phosphorus, silicon, germanium, selenium, sulfur, and / or tellurium, and the second well region 102 may be doped with dopants such as boron, beryllium, strontium, barium, zinc, and / or magnesium.

[0052] like Figure 3 As shown, the first well region 101 contains a first active region 103 and a second active region 104. The first active region 103 and the second active region 104 are arranged in a regular order. The first active region 103 and the second active region 104 extend along a first direction (X direction) and are arranged along a second direction (Y direction). In the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, that is, the first active region 103 is closer to the second well region 102 than the second active region 104. The arrangement of the first active region 103 and the second active region 104 differs from... Figure 2 The arrangement of the first active region 103 and the second active region 104 in the image. Figures 2-3 The first active region 103 and the second active region 104 both extend along a first direction, and in a second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104. The first active region 103 and the second active region 104 may have the same structure, for example, in the first direction, the first active region 103 and the second active region 104 have the same length.

[0053] like Figure 3 As shown, a gate 105 is located on a first well region 101, and the gate 105 can contact a first active region 103 and a second active region 104. In a first direction, the gate 105 has a first length L1 on the first active region 103 and a second length L2 on the second active region 104, where the first length L1 is less than the second length L2. The gate 105 extends along a second direction. The gate 105 can be divided into two parts: a first part located on the first active region 103 with a first length L1, and a second part located on the second active region 104 with a second length L2. The first and second parts extend along the second direction and converge between the first active region 103 and the second active region 104 to form the gate 105. In this embodiment, the gate 105 can be polysilicon.

[0054] like Figures 3-4 As shown, Figure 4 for Figure 3This is a cross-sectional view along the AA direction. Both the first active region 103 and the second active region 104 are formed in the substrate. The substrate can be, for example, a bulk material such as silicon (Si, e.g., monocrystalline silicon, polycrystalline silicon, or amorphous silicon), germanium (Ge), silicon-germanium (GeSi), or silicon-carbon (SiC); it can also be a composite material such as silicon-on-insulator (SOI), germanium-on-insulator (GOI), germanium-silicon-on-insulator, or silicon-carbon-on-insulator; or it can be other materials such as gallium arsenide or other group III-V compounds. For example, it can be a composite material such as silicon-on-insulator (SOI), germanium-on-insulator (GOI), germanium-silicon-on-insulator, or silicon-carbon-on-insulator. In this embodiment, the first active region 103 and the second active region 104 are formed before the first well region 101 and the second well region 102. After the first active region 103 and the second active region 104 are formed, the second well region 102 is formed, and then the first well region 101 is formed. After forming the second well region 102, a mask layer is formed on the second well region 102, followed by ion doping to form the first well region 101. However, during the formation of the first well region 101, because the first active region 103 is closer to the side edge of the first well region 101 (i.e., the first active region 103 is closer to the second well region 102), the ion doping process is uneven due to the thickness of the mask layer. This results in more ions being doped into the first active region 103, meaning the ion doping concentration in the first active region 103 is greater than that in the second active region 104. Therefore, if the gate 105 has the same length on both the first and second active regions 103, a significant difference in driving capability will occur between the first transistor (formed with gate 105 and the first active region 103) and the second transistor (formed with gate 105 and the second active region 104). This mismatch in driving capability leads to low device reliability.

[0055] like Figure 3 As shown in the embodiment of this disclosure, the gate 105 has a first length L1 on the first active region 103 and a second length L2 on the second active region 104. The first length L1 is less than the second length L2, that is, the channel length of the first transistor (formed by the gate 105 and the first active region 103) is less than the channel length of the second transistor (formed by the gate 105 and the second active region 104), which reduces the channel length of the first transistor, thereby improving the driving capability of the first transistor and thus better matching the driving capability of the second transistor, thereby improving the reliability of the device.

[0056] like Figures 3-4As shown, in some embodiments, the ion doping concentration in the second active region 104 can be increased, for example, through a multiple doping process, thereby enabling the driving capability of the first transistor to match the driving capability of the second transistor. However, the multiple doping process is relatively complex, while this embodiment improves the driving capability of the first transistor by reducing the channel length of the first transistor, thus enabling the driving capability of the first transistor to match the driving capability of the second transistor. This embodiment has a relatively simple process.

[0057] like Figure 5 As shown, in the semiconductor structure 100, the first active region 103 and the second active region 104 may have the same structure or shape. Figure 5 In this configuration, the first active region 103 and the second active region 104 can have the same length in the first direction. The first active region 103 and the second active region 104 can have the same width in the second direction. For example, the first active region 103 can have a first width W1 in the second direction, and the second active region 104 can have a second width W2 in the second direction. The first width W1 can be equal to the second width W2. Therefore, in the second direction (Y direction), the gate 105 has a first width W1 in the first active region 103 and a second width W2 in the second active region 104, and the first width W1 can be equal to the second width W2. Simultaneously, in the first direction (X direction), the gate 105 has a first length L1 in the first active region 103 and a second length L2 in the second active region 104, and the first length L1 can be less than the second length L2. Since the gate 105 and the first active region 103 can form a first transistor (PMOS), and the gate 105 and the second active region 104 can form a second transistor (PMOS), the channel length of the first transistor is less than the channel length of the second transistor, and the channel width of the first transistor is equal to the channel width of the second transistor. Increasing the channel width of the PMOS transistor improves its driving capability. In this embodiment, the channel width of the first transistor is equal to the channel width of the second transistor, thus allowing the driving capability of the first transistor to match that of the second transistor. Furthermore, by reducing the channel length of the first transistor, the driving capability of the first transistor can be further matched to that of the second transistor, thereby improving the reliability of the device. If the channel width of the second transistor is further increased, its driving capability will be further improved. Although the driving capability of the first transistor is improved by reducing its channel length, the driving capability of the second transistor is still improved by increasing its channel width, resulting in a mismatch between the driving capabilities of the first and second transistors. Therefore, the channel width of the second transistor cannot be greater than the channel width of the first transistor.

[0058] like Figure 5 As shown, the first active region 103, the second active region 104, and the gate 105 are all located in the first well region 101, with second well regions 102 on both sides of the first well region 101. The first well region 101 can be an N-type well region (NWELL), and the second well region 102 can be a P-type well region (PWELL). The first well region 101 and the second well region 102 are doped with different ion types. The first well region 101 can be used to form a PMOS, and the second well region 102 can be used to form an NMOS. In the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, that is, the first active region 103 is closer to the second well region 102. The gate 105 extends from the first active region 103 to the second active region 104, thereby forming the first transistor and the second transistor. In this embodiment, the first direction (X direction) can be the direction of the channel length of the transistor, and the second direction (Y direction) can be the direction of the channel width of the transistor.

[0059] like Figure 3 and Figure 5 As shown, there are two gates 105 on the first active region 103 and the second active region 104. These two gates 105 are arranged in parallel and can have the same structure. Since the first length L1 is less than the second length L2 in the first direction, the gap between the two gates 105 on the first active region 103 is larger, and the gap between the two gates 105 on the second active region 104 is smaller.

[0060] like Figure 6 As shown, in this semiconductor structure 100, the first active region 103 is rectangular, and the second active region 104 is rectangular. In the first direction (X direction), the first active region 103 and the second active region 104 have the same length. In the second direction (Y direction), the first active region 103 has a first width W1, and the second active region 104 has a second width W2, which can be smaller than the first width W1. Simultaneously, in the second direction, the first active region 103 is closer to the side edge of the first well region 101 than the second active region 104, meaning the first active region 103 is closer to the second well region 102 than the second active region 104. During the formation of the first well region 101, the first active region 103 is doped with more ions than the second active region 104, meaning the ion doping concentration in the first active region 103 is higher. A gate 105 is located in the first well region 101, extending along a second direction from the first active region 103 to the second active region 104. Simultaneously, in the first direction, the length of the gate 105 in the first active region 103 is less than the length of the gate 105 in the second active region 104 (see reference). Figure 5A first transistor 107 is formed by a gate 105 and a first active region 103, and a second transistor 108 is formed by a gate 105 and a second active region 104. The first transistor 107 and the second transistor 108 are transistors of the same type, such as PMOS transistors. In a first direction, the length of the gate 105 on the first active region 103 can be the channel length of the first transistor 107, and the length of the gate 105 on the second active region 104 can be the channel length of the second transistor 108. In a second direction, the width of the gate 105 on the first active region 103 (first width W1) can be the channel width of the first transistor 107, and the width of the gate 105 on the second active region 104 (second width W2) can be the channel width of the second transistor 108.

[0061] like Figure 6 As shown, in this embodiment, the ion doping concentration of the first active region 103 is greater than that of the second active region 104. The channel length of the first transistor 107 is less than that of the second transistor 108, thereby improving the driving capability of the first transistor 107 and enabling it to match the driving capability of the second transistor 108. Simultaneously, the channel width of the first transistor 107 is greater than that of the second transistor 108, further improving the driving capability of the first transistor 107 and further enabling it to match the driving capability of the second transistor 108, thereby improving the reliability of the device.

[0062] like Figures 6-7 As shown, in Figure 6 In the middle, both the first active region 103 and the second active region 104 are regular rectangular shapes. Figure 7 In this design, the first active region 103 can be a regular rectangle, while the second active region 104 can be an irregular shape, such as having a groove cut out from the regular first active region 103. This allows the second active region 104 to have a smaller second width W2, making the first width W1 of the first active region 103 larger than the second width W2 of the second active region 104. The gate 105 also contacts the first active region 103 and the second active region 104. The gate 105 has a width of the first width W1 on the first active region 103 and a width of the second width W2 on the second active region 104. In this case, the second width W1 is smaller than the first width W1, which improves the driving capability of the first transistor 107, thereby enabling the driving capability of the first transistor 107 to match the driving capability of the second transistor 108.

[0063] like Figure 8As shown in the embodiments, this disclosure also discloses another structure for the first active region 103 and the second active region 104. The first active region 103 includes an extension 1031, and the second active region 104 includes a recess 1041. The extension 1031 can extend to the recess 1041. However, in a second direction, the width D1 of the extension 1031 can be greater than the width D2 of the recess 1041. Therefore, when the gate 105 is located on the first active region 103 and the second active region 104, the gate 105 can extend from the extension 1031 to the second active region 104, making the width of the gate 105 on the first active region 103 greater than the width of the gate 105 on the second active region 104. This allows the driving capability of the first transistor to match the driving capability of the second transistor, improving the reliability of the device.

[0064] like Figure 9 As shown, this disclosure also proposes a semiconductor structure 100, which includes a first well region 101, a second well region 102, and a mixed well region 106. The first well region 101 contains a first active region 103 and a second active region 104. Gates 105 are located on the first active region 103 and the second active region 104. In a first direction (X direction), the gate 105 has a first length L1 on the first active region 103 and a second length L2 on the second active region 104, wherein the first length L1 may be less than the second length L2. In a second direction (Y direction), the width of the gate 105 on the first active region 103 may be equal to the width of the gate 105 on the second active region 104. The gate 105 and the first active region 103 form a first transistor 107, and the gate 105 and the second active region 104 form a second transistor 108. The channel length of the first transistor 107 is a first length L1, and the channel length of the second transistor 108 is a second length L2. In this case, the channel length of the first transistor 107 is less than the channel length of the second transistor 108. The channel width of the first transistor 107 can be equal to the channel width of the second transistor 108. Alternatively, if the width of the gate 105 on the first active region 103 can be greater than the width of the gate 105 on the second active region 104, then the channel width of the first transistor 107 is greater than the channel width of the second transistor 108.

[0065] like Figures 9-10 As shown, Figure 10 for Figure 9A cross-sectional view along the BB direction. The second well region 102 is located on both sides of the first well region 101. The first well region 101 can be an N-type well region, and the second well region 102 can be a P-type well region. A mixed well region 106 is located between the first well region 101 and the second well region 102. In this embodiment, the second well region 102 can be formed first, and then, while forming the first well region 101, dopant ions can be doped into the second well region 102, thereby forming the mixed well region 106. The mixed well region 106 can include both P-type and N-type ions. The first well region 101 is used, for example, to form a PMOS, and the second well region 102 is used, for example, to form an NMOS. Figure 10 In this process, due to the presence of the mixed well region 106, it is equivalent to the first well region 101 extending into the second well region 102, thereby increasing the distance between the first active region 103 and the side edge of the first well region 101. As a result, when the first well region 101 is ion-doped, more ion doping can be reduced in the first active region 103, making the ion doping concentration in the first active region 103 and the second active region 104 more balanced, thereby reducing the difference in driving capability between the first transistor 107 and the second transistor 108.

[0066] like Figures 9-10 As shown, the presence of the mixed-well region 106 reduces the difference in ion concentration between the first active region 103 and the second active region 104. Simultaneously, the channel length of the first transistor 107 is shorter than that of the second transistor 108, further enhancing the driving capability of the first transistor 107. This allows the driving capability of the first transistor 107 to match that of the second transistor 108, thereby improving the reliability of the device.

[0067] like Figure 11 As shown, this disclosure also proposes a semiconductor structure 100, which may include a first well region 101 and a second well region 102. The second well region 102 is located on both sides of the first well region 101. The first well region 101 can be used to form a PMOS, and the second well region 102 can be used to form an NMOS. The description of the first well region 101 and the second well region 102 can refer to the above description. Of course, the first well region 101 and the second well region 102 may also have a mixed well region 106 (…). Figure 9 (As shown).

[0068] like Figure 11As shown, a first active region 103 and a second active region 104 are located in the first well region 101. In the first direction (X direction), the first active region 103 and the second active region 104 are arranged in parallel. In the second direction (Y direction), the first active region 103 and the second active region 104 are arranged alternately, with the first active region 103 closer to the side edge of the first well region 101 relative to the second active region 104. This side edge is the edge where the first well region 101 and the second well region 102 meet. Because the first active region is closer to the second well region 102, the ion doping concentration in the first active region 103 is higher than the ion doping concentration in the second active region 104.

[0069] like Figure 11 As shown, a first gate 1051 and a second gate 1052 are present in the first well region 101, and the first gate 1051 and the second gate 1052 constitute a gate 105. The first gate 1051 and the second gate 1051 have the same structure. The first gate 1051 and the second gate 1051 are arranged in parallel. In some embodiments, the first gate 1051 and the second gate 1052 can both be defined as gate 105, that is, there can be multiple gates 105 in the first well region 101. The first gate 1051 and the second gate 1052 are both in contact with the first active region 103 and the second active region 104. This embodiment is described using the second gate 1052 as an example. In the first direction (X direction), the length of the second gate 1052 in the first active region 103 is less than the length of the second gate 1052 in the second active region 104, thereby making the channel length of the first transistor less than the channel length of the second transistor, thereby improving the driving capability of the first transistor, reducing the difference in driving capability between the first transistor and the second transistor, and improving the reliability of the device. In the second direction (Y direction), the width of the second gate 1052 on the first active region 103 can be equal to the width of the second gate 1052 on the second active region 104, so that the channel width of the first transistor can be equal to the channel width of the second transistor. If the channel width of the second transistor is larger, the driving capability of the second transistor will be further improved, thereby further increasing the difference in driving capability between the first transistor and the second transistor. However, in the embodiment, the channel width of the first transistor is equal to the channel width of the second transistor, which ensures that the difference in driving capability between the first transistor and the second transistor is not increased. That is, it can be ensured that by reducing the channel length of the first transistor, the difference in driving capability between the first transistor and the second transistor is reduced.

[0070] like Figure 11As shown, the second gate 1052 also includes a first protrusion 109 and a second protrusion 110. The first protrusion 109 is located outside the first active region 103, and the second protrusion 110 is located between the first active region 103 and the second active region 104. The first protrusion 109 and the second protrusion 110 extend along a first direction, and in the first direction, both the first protrusion 109 and the second protrusion 110 protrude beyond the lower edge of the first active region 103. In the first direction, the length of the first protrusion 109 is greater than the length of the second gate 1052 in the first active region 103 (first length L1), while the length of the second protrusion 110 is greater than the length of the second gate 1052 in the second active region 104 (second length L2). The first protrusion 109 on the first gate 1051 extends in the positive direction of the first direction, and the first protrusion 109 on the second gate 1052 extends in the opposite direction of the first direction. The second protrusion 110 on the first gate 1051 extends in the positive direction of the first direction, and the second protrusion 110 on the second gate 1052 extends in the opposite direction of the first direction, thereby leaving sufficient space between the first gate 1051 and the second gate 1052, which is conducive to forming a contact plug in the space.

[0071] like Figure 11 As shown, the first protrusion 109 and the second protrusion 110 are both located outside the first active region 103 and the second active region 104. The first protrusion 109 and the second protrusion 110 do not increase the channel length of the first transistor, thus ensuring that the first transistor has good driving capability. Simultaneously, in the first direction, both the first protrusion 109 and the second protrusion 110 have a large length, and their lengths can be the same. The first protrusion 109 and the second protrusion 110 can also improve the reliability of the second gate 1052, compensate for the degradation of the transistor's turn-off characteristics caused by the hot electron-induced punch-through effect resulting from the hot electron trapping of the trench isolation structure, and thus improve the performance of the semiconductor structure.

[0072] like Figure 12As shown, this disclosure provides a memory chip 10, which may include a word line driving region 11 and a storage region 12. The word line driving region 11 may include the semiconductor structure described above. The memory chip 10 is, for example, a volatile memory semiconductor chip (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) or a non-volatile memory semiconductor chip (such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM)). According to some exemplary embodiments, the memory chip 10 may be flash memory, for example, NAND flash memory. The memory chip 10 can be used in electronic devices, which may include one or more of the following: for example, smartphones, tablet PCs, mobile phones, video phones, e-book readers, desktop PCs, laptop PCs, netbooks, workstations, servers, personal digital assistants (PDAs), portable multimedia players (PMPs), MPEG-1 audio layer 3 (MP3) players, mobile medical devices, cameras, home appliances, medical devices, Internet of Things (IoT) devices, and wearable devices. Wearable devices can be accessory-type, fabric or clothing-type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs). The memory chip 10 can also be used in large servers, such as data centers, AI computers, etc. The memory chip 10 can also be used in personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable computers, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, and / or drones.

[0073] In summary, this disclosure provides a semiconductor structure and a memory chip. The semiconductor structure includes a first active region and a second active region, with a gate located on both regions, thereby enabling the formation of a first transistor and a second transistor, respectively. Furthermore, since the first active region is closer to the side edge of the first well region than the second active region, the first transistor is closer to the side edge of the first well region. Additionally, in a first direction, the length of the gate on the first active region is shorter than the length of the gate on the second active region, meaning the channel length of the first transistor is smaller. This improves the driving capability of the first transistor, allowing it to match the driving capability of the second transistor, thereby reducing the impact on device reliability.

[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a first well region; a first active region in the first well region, extending along a first direction; a second active region in the first well region, extending along the first direction, the first active region being closer to a side edge of the first well region than the second active region in a second direction; a gate on the first well region, contacting the first active region and the second active region; wherein, in the first direction, the gate has a first length on the first active region, the gate has a second length on the second active region, the first length being smaller than the second length; wherein, in the second direction, the gate has a first width on the first active region, the gate has a second width on the second active region, the second width being smaller than the first width.

2. The semiconductor structure of claim 1, wherein, The first active region comprises an extension, the second active region comprises a recess, the extension is embedded in the recess, in the second direction, a width of the extension is larger than a width of the recess.

3. The semiconductor structure according to claim 1 or 2, characterized in that Further comprising a second well region, in the second direction, the second well region is located on both sides of the first well region, wherein an ion doping type of the second well region is different from an ion doping type of the first well region.

4. The semiconductor structure of claim 3, wherein, There is also a mixed well region between the first well region and the second well region, the mixed well region comprising the ion doping type of the first well region and the ion doping type of the second well region.

5. The semiconductor structure of claim 4, wherein, The mixed well region is an overlapping region of the first well region and the second well region.

6. The semiconductor structure of claim 1 or 2, wherein, The gate further comprises a first protruding portion, the first protruding portion is located outside the first active region, wherein, in the first direction, a length of the first protruding portion is larger than the first length.

7. The semiconductor structure of claim 6, wherein, The gate further comprises a second protruding portion, the second protruding portion is located between the first active region and the second active region, wherein, in the first direction, a length of the second protruding portion is larger than the second length.

8. The semiconductor structure of claim 7, wherein, In the first direction, the first protruding portion protrudes from an edge of the first active region, the second protruding portion protrudes from an edge of the first active region.

9. The semiconductor structure of claim 7, wherein, In the first direction, the length of the first protruding portion is equal to the length of the second protruding portion.

10. The semiconductor structure of claim 7, wherein, The gate comprises a first gate and a second gate, the first gate and the second gate are arranged in parallel on the first active region and the second active region.

11. The semiconductor structure of claim 10, wherein, The first protruding portion on the first gate and the first protruding portion on the second gate extend in opposite directions, the second protruding portion on the first gate and the second protruding portion on the second gate extend in opposite directions.

12. The semiconductor structure of claim 1 or 2, wherein, The gate forms a first transistor with the first active region, the gate forms a second transistor with the second active region, the first transistor and the second transistor are the same type of transistor, the first length is a channel length of the first transistor, the second length is a channel length of the second transistor, the first width is a channel width of the first transistor, the second width is a channel width of the second transistor.

13. A memory chip, comprising: A semiconductor structure as claimed in any of claims 1-12. A semiconductor structure as claimed in any of claims 1-12.

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