A preparation method of a molybdenum disulfide-based transistor PUF

Abstract

The present invention discloses a preparation method of a molybdenum disulfide-based transistor PUF, comprising the following steps: pre-treating the surface of a silicon oxide substrate to remove natural organic matters and other impurities on its surface; based on liquid-liquid interface self-assembly, forming a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate with molybdenum disulfide ink; performing patterning treatment on the surface of the molybdenum disulfide thin film to obtain the pattern of source and drain electrodes; depositing a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes, thereby obtaining a molybdenum disulfide transistor PUF array. The present invention is applied to the fields of information security and chip encryption, has good anti-attack performance and high uniqueness, and can effectively improve the security protection performance of electronic devices.

Description

Technical Field

[0001] The present invention relates to the fields of information security and chip encryption technology, and particularly to a preparation method of a transistor PUF based on molybdenum disulfide. Background Art

[0002] Physical Unclonable Function (PUF) technology captures the inherent randomness characteristics generated by material defects, process deviations, and thermal fluctuations at the microscale of semiconductor devices to construct an encryption mechanism with a unique fingerprint. The response characteristics of such devices are strongly related to the physical implementation path. Even in the face of an atomic-level precision reverse engineering attack, an attacker cannot reproduce the same output-input mapping relationship, thus providing a fundamental guarantee for chip-level security. Compared with the traditional cryptography defense method that relies on mathematical problems, PUF technology roots security in the principle of non-clonability in the physical world, realizing a security paradigm of "once manufactured, bound for life".

[0003] In the field of information security, PUF has been successfully applied to key generation for Internet of Things devices, identity authentication in Trusted Execution Environments (TEEs), and hardware anchoring for blockchain nodes. Its dynamic response characteristics enable unique authentication vectors to be generated for each access, effectively resisting side-channel attacks and replay attacks. The latest research shows that PUF chips based on FinFET technology can achieve an integration density of more than 1×10 6 random entropy sources per square millimeter on a 300mm wafer, with a bit error rate lower than 1×10 -6 order of magnitude.

[0004] However, as Moore's Law approaches its physical limit, silicon-based PUFs face multiple technical bottlenecks: the reliability degradation caused by the quantum tunneling effect in process nodes below 7nm, the local heat accumulation problem caused by the three-dimensional FinFET structure, and the exponential increase in manufacturing costs brought about by the improvement of lithography accuracy. Experimental data shows that when the process is scaled down to 5nm, the entropy value of silicon-based SRAM PUFs decreases by about 37% compared to the 28nm process, and the device yield loss increases to 12%. These challenges urgently require breaking through the limitations of material dimensions. Summary of the Invention

[0005] Aiming at the deficiencies in the above-mentioned prior art, the present invention provides a preparation method of a transistor PUF based on molybdenum disulfide, which can not only overcome the limitations of traditional silicon materials, but also significantly enhance the response uniqueness, stability, and attack defense ability of the PUF, thereby providing an efficient and energy-saving hardware security guarantee scheme, and providing new ideas and directions for the development of new hardware security devices and their applications in fields such as the Internet of Things and embedded systems.

[0006] To achieve the above object, the present invention provides a preparation method of a transistor PUF based on molybdenum disulfide, including the following steps:

[0007] Step 1, pre-treat the surface of the silicon oxide substrate to remove natural organic matter and other impurities on its surface;

[0008] Step 2, based on liquid-liquid interface self-assembly, form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate with molybdenum disulfide ink;

[0009] Step 3, perform patterning treatment on the surface of the molybdenum disulfide thin film to obtain the pattern of the source and drain electrodes;

[0010] Step 4, deposit a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes, and obtain a molybdenum disulfide transistor PUF array.

[0011] In one embodiment, in Step 2, based on liquid-liquid interface self-assembly, form the molybdenum disulfide thin film on the silicon oxide substrate at least twice, so as to form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate.

[0012] In one embodiment, Step 2 specifically includes:

[0013] Step 201, after placing the silicon oxide substrate on a customized lifting rack, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the first time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the silicon oxide substrate, and place the silicon oxide substrate on a heating table for heating treatment to ensure that the liquid is completely evaporated, so as to form the first layer of molybdenum disulfide thin film on the sample surface;

[0014] Step 202, after placing the sample obtained in Step 201 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the second time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heating treatment to ensure that the liquid is completely evaporated, so as to form the second layer of molybdenum disulfide thin film on the sample surface;

[0015] Step 203, after placing the sample obtained in Step 202 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the third time, use a pipette to slowly and continuously drip molybdenum disulfide ink in the glass petri dish. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heating treatment to ensure that the liquid is completely evaporated, so as to form the third layer of molybdenum disulfide thin film on the sample surface.

[0016] In one embodiment, in step 201, when molybdenum disulfide ink is dropped onto the glass petri dish for the first time, it is dropped at the middle position of the glass petri dish.

[0017] In step 202, when molybdenum disulfide ink is dropped onto the glass petri dish for the second time, it is dropped at the upper left corner position of the glass petri dish.

[0018] In step 203, when molybdenum disulfide ink is dropped onto the glass petri dish for the third time, it is dropped at the lower right corner position of the glass petri dish.

[0019] In one embodiment, in step 3, electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography or nanoimprinting is used for patterning.

[0020] In one embodiment, in step 4, the process of depositing a titanium thin film and a palladium thin film on the silicon oxide substrate covered with a molybdenum disulfide thin film is as follows:

[0021] First, deposit 10 nm of metallic titanium at a rate of 0.01 nm / s, and then deposit 50 nm of metallic palladium at a rate of 0.05 nm / s.

[0022] Compared with the prior art, the present invention has the following beneficial technical effects:

[0023] 1. The present invention prepares a transistor PUF array based on molybdenum disulfide. By forming a continuous and non-uniform molybdenum disulfide thin film during the array preparation process, the drain current Id of the transistor is distributed between 0.1 mA and 1 mA and is different when the gate voltage is -100 V, showing a large difference, demonstrating excellent performance and high stability, and is expected to play an important role in fields such as chip encryption and information security protection;

[0024] 2. The molybdenum disulfide thin film prepared by the present invention has a significantly improved density compared with the commonly used spin coating, spraying, and drop coating methods, with a porosity of only about 10%, and the non-uniform stacking of nanosheets can improve the uniqueness and unpredictability of the PUF;

[0025] 3. The process of the present invention is simple, requires low experimental equipment, and can prepare array devices in large quantities at room temperature. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0027] Figure 1 Flow chart of the preparation method of a transistor PUF based on molybdenum disulfide in an embodiment of the present invention;

[0028] Figure 2 Design diagram of the source and drain electrode patterns in an embodiment of the present invention;

[0029] Figure 3 Optical schematic diagram of the transistor channel in an embodiment of the present invention;

[0030] Figure 4 Raman characterization diagram of the molybdenum disulfide thin film on a 300nm silicon oxide substrate in an embodiment of the present invention;

[0031] Figure 5 AFM characterization diagram of the molybdenum disulfide thin film on a 300nm silicon oxide substrate in an embodiment of the present invention;

[0032] Figure 6 SEM characterization diagram of the molybdenum disulfide thin film on a 300nm silicon oxide substrate in an embodiment of the present invention;

[0033] Figure 7 Test diagram of the transfer characteristic curve of the transistor array in an embodiment of the present invention.

[0034] The realization, functional characteristics and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions appears to be contradictory or unable to be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0037] This embodiment discloses a preparation method of a transistor PUF based on molybdenum disulfide. Molybdenum disulfide (MoS2), as a two-dimensional material with excellent electrical properties, has become an ideal choice for realizing efficient hardware devices due to its high electron mobility, low power consumption, and good chemical stability. The unique layered structure of MoS2 endows it with superior electron transport characteristics at the nanoscale. Especially at extremely small sizes, it can maintain strong switching performance and anti-interference ability. These characteristics enable molybdenum disulfide to show broad application potential in electronic devices, sensors, and integrated circuits, especially in the field of hardware security. Therefore, the transistor PUF technology based on molybdenum disulfide can not only overcome the limitations of traditional silicon materials but also has good anti-attack performance and high uniqueness. It can effectively improve the security protection performance of electronic devices, significantly enhance the response uniqueness, stability, and anti-attack ability of the PUF, thus providing an efficient and energy-saving hardware security protection solution and offering new ideas and directions for the development of new hardware security devices and their applications in fields such as the Internet of Things and embedded systems.

[0038] Reference Figure 1 , the preparation method of the transistor PUF based on molybdenum disulfide in this embodiment specifically includes the following steps:

[0039] Step 1, pre-treat the surface of the silicon oxide substrate to remove natural organic substances and other impurities on its surface;

[0040] Step 2, based on liquid-liquid interface self-assembly, form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate with molybdenum disulfide ink;

[0041] Step 3, perform patterning on the surface of the molybdenum disulfide thin film to obtain the pattern of the source and drain electrodes;

[0042] Step 4, deposit a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes and obtain a molybdenum disulfide transistor PUF array.

[0043] In the specific implementation process of Step 1, the process of pre-treating the surface of the silicon oxide substrate is specifically as follows: Take an N-type heavily doped silicon wafer with a

[100] crystal orientation and a resistivity less than 0.005 Ω·cm and 300 nm silicon oxide prepared by the CZ method, place it in acetone and ultrasonically treat it for 5 min to 10 min, then take it out with tweezers and soak it in isopropyl alcohol and continue to ultrasonically treat it for 5 min to 10 min to thoroughly remove surface organic substances and other impurities, and finally take it out and dry it with a nitrogen gun.

[0044] In this embodiment, the molybdenum disulfide ink is prepared by an electrochemically assisted liquid-phase exfoliation method, and its specific implementation process is as follows:

[0045] When conducting the electrochemically assisted liquid-phase exfoliation experiment, a CS2350H electrochemical workstation was used. A molybdenum disulfide crystal was clamped as the working electrode with a copper flat alligator clip, a platinum wire as the reference electrode, and a graphite rod as the counter electrode;

[0046] In the experiment, tetraheptylammonium bromide was used as the intercalating ionic liquid solute, and acetonitrile was used as the solvent. Its concentration was controlled at 3 mg / ml to 10 mg / ml, the intercalation voltage was set at -10 V to -4 V, and the intercalation time was maintained at 10 min to 60 min;

[0047] After the intercalation, the fluffy mass was added to a stabilizer with PVP as the solute and ultrasonicated for 5 min to 30 min. The molecular weight of PVP was 8000 to 40000, the solvent was N,N-dimethylformamide (DMF), and the concentration was 0.1 mol / L to 0.5 mol / L;

[0048] Next, a centrifuge was used to centrifuge at 1000 r / min to 3000 r / min for 5 min to 10 min to take the supernatant, and centrifuge at 8000 r / min to 10000 r / min for 10 min to 20 min to take the precipitate (this step was repeated three times), and then centrifuge at 3000 r / min to 5000 r / min for 5 min to 10 min to take the supernatant to obtain the final molybdenum disulfide ink. Isopropyl alcohol (IPA) was used as the solvent throughout the centrifugation process.

[0049] In the specific implementation process of step 2, based on liquid-liquid interface self-assembly, molybdenum disulfide thin films were formed on the silicon oxide substrate in multiple times, thereby forming a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate, making the drain currents Id of each transistor in the transistor array have different distributions, showing significant differences, thereby enhancing the uniqueness and unpredictability of the PUF. The implementation process of step 2 in this embodiment is specifically as follows:

[0050] Step 201, after placing the silicon oxide substrate on a customized lifting frame, the lifting frame was placed in a glass petri dish, and then 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 were added. When a distinct layered interface appeared in the glass petri dish, for the first time, a pipette was used to slowly and continuously drip the molybdenum disulfide ink into the glass petri dish, and the added dose was 1 mL to 2 mL. After a stable thin film was formed (i.e., there was no obvious movement of the material at the interface), the lifting frame was extracted to make the molybdenum disulfide thin film spread flat on the silicon oxide substrate. The silicon oxide substrate was placed on a heating table for heat treatment, heated to 70 °C, and maintained for 3 to 5 minutes to ensure that the liquid completely evaporated, thereby forming the first layer of molybdenum disulfide thin film on the sample surface;

[0051] Step 202: After placing the sample obtained in Step 201 on the lifting rack again, put the lifting rack into a glass Petri dish, and then add 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 . When an obvious layered interface appears in the glass Petri dish, use a pipette to slowly and continuously drop molybdenum disulfide ink into the glass Petri dish for the second time. The added dosage is 1 mL to 2 mL. After a stable film is formed, lift the lifting rack to make the molybdenum disulfide film spread flat on the sample, and place the sample on a heating stage for heating treatment. Heat it to 70 °C and keep it for 3 min to 5 min to ensure that the liquid is completely evaporated, so as to form a second layer of molybdenum disulfide film on the sample surface;

[0052] Step 203: After placing the sample obtained in Step 202 on the lifting rack again, put the lifting rack into a glass Petri dish, and then add 20 mL of deionized water with a density of 995 kg·m -3 and 20 mL of n-hexane with a density of 655 kg·m -3 . When an obvious layered interface appears in the glass Petri dish, use a pipette to slowly and continuously drop molybdenum disulfide ink into the glass Petri dish for the third time. The added dosage is 1 mL to 2 mL. After a stable film is formed, lift the lifting rack to make the molybdenum disulfide film spread flat on the sample, and place the sample on a heating stage for heating treatment. Heat it to 70 °C and keep it for 3 min to 5 min to ensure that the liquid is completely evaporated, so as to form a third layer of molybdenum disulfide film on the sample surface.

[0053] As a preferred embodiment, in Step 201, when dropping molybdenum disulfide ink into the glass Petri dish for the first time, drop it at the middle position of the glass Petri dish; in Step 202, when dropping molybdenum disulfide ink into the glass Petri dish for the second time, drop it at the upper left corner position of the glass Petri dish; in Step 203, when dropping molybdenum disulfide ink into the glass Petri dish for the third time, drop it at the lower right corner position of the glass Petri dish. Drop molybdenum disulfide ink at different positions (the center, upper left corner, and lower right corner of the glass Petri dish) three times, and introduce randomness through spatial non-uniformity, so as to significantly improve the performance of the PUF chip.

[0054] In the specific implementation process of Step 3, electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography or nanoimprinting can be used for patterning. Taking ultraviolet lithography as an example, the specific implementation process of Step 3 is as follows:

[0055] Place the substrate on a spin coater, and use Nr9-3000P negative photoresist for spin coating. The spin coating parameters are set as follows: the pre-rotation speed is 600 r / min for 10 s; then the acceleration is increased to 1000 r / min, and then accelerated to 3000 r / min for 60 s. Finally, the acceleration reaches 5000 r / min;

[0056] Place the substrate spin-coated with photoresist on a heating platform for pre-baking. Set the heating temperature to 110 °C and keep it for 180 s. After heating, the substrate needs to be left standing in the dark for 20 min for re-water absorption operation;

[0057] Use a JB-Ⅷ contact lithography machine for ultraviolet lithography patterning. The source-drain electrodes and channel patterns are specifically as shown in Figure 2 shown. Before operation, preheat the mercury lamp for 20 min. First, install the mask plate into the suction slot of the ultraviolet lithography machine. Then, place the pure silicon wafer processed in the above steps on the sample stage, slowly push it into the lithography machine, set the exposure time to 45 s, and take out the sample after exposure;

[0058] Place the exposed sample on a heating platform for post-baking, set the temperature to 100 °C and the time to 60 s;

[0059] Cool the sample for 10 min to room temperature, and then immerse it in RD6 developer for 10 s for development;

[0060] After development, rinse with deionized water for 1 min and dry with a nitrogen gun.

[0061] In the specific implementation process of step 4, on the silicon oxide substrate covered with a molybdenum disulfide film, first deposit 10 nm of metallic titanium at a rate of 0.01 nm / s, then deposit 50 nm of metallic palladium at a rate of 0.05 nm / s. Subsequently, place the sample deposited with metal into a glass petri dish containing acetone and soak it for 1 min - 3 min. Heat it using a heating platform, set the temperature to 50 °C, gently rinse the heated sample with acetone, then rinse with isopropyl alcohol to remove acetone, and dry with a nitrogen gun to obtain the final transistor PUF array. The optical micrograph of the channel of one transistor is as shown in Figure 3 shown.

[0062] Reference Figure 4 is the Raman characterization of the molybdenum disulfide film on a 300-nm silicon oxide substrate. It can be seen from Figure 4 that the molybdenum disulfide film prepared in this example is molybdenum disulfide with a 2H-phase structure. Reference Figure 5 is the AFM characterization of the molybdenum disulfide film on a 300-nm silicon oxide substrate. It can be seen from Figure 5 that the thickness of the molybdenum disulfide film prepared in this example is 7 nm. Reference Figure 6 is the SEM characterization of the molybdenum disulfide film on a 300-nm silicon oxide substrate. It can be seen from Figure 6 that the molybdenum disulfide film prepared in this example has a high density and an uneven surface stacked distribution.

[0063] Reference Figure 7It is a test diagram of the transfer characteristic curve of a transistor array. As can be seen from Figure 7 it, each transistor in the transistor array has relatively excellent performance, and when the gate voltage is -100V, the drain current Id of the transistors is distributed between 0.1 mA and 1 mA and is different from each other, showing a large difference. Thus, it can be seen that the method for preparing a transistor PUF in this embodiment not only has excellent performance and high stability, but also can play an important role in the fields of chip encryption, information security protection, etc.

[0064] The above are only the preferred embodiments of the present invention, and do not limit the protection scope of the present invention accordingly. Any equivalent structural transformation made by using the content of the specification and drawings of the present invention under the inventive concept of the present invention, or any direct / indirect application in other related technical fields is included in the protection scope of the present invention.

Claims

1. A preparation method of a transistor PUF based on molybdenum disulfide, characterized in that, It includes the following steps: Step 1: Pretreat the surface of the silicon oxide substrate to remove natural organic matters and other impurities on its surface; Step 2: Based on liquid-liquid interface self-assembly, form a continuous and uneven molybdenum disulfide thin film on the silicon oxide substrate, specifically including: Step 201: After placing the silicon oxide substrate on a customized lifting rack, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the first time, slowly and continuously drip molybdenum disulfide ink in the glass petri dish with a pipette. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the silicon oxide substrate, and place the silicon oxide substrate on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the first layer of molybdenum disulfide thin film on the sample surface. When dripping molybdenum disulfide ink in the glass petri dish for the first time, it is dripped at the middle position of the glass petri dish; Step 202: After placing the sample obtained in Step 201 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the second time, slowly and continuously drip molybdenum disulfide ink in the glass petri dish with a pipette. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the second layer of molybdenum disulfide thin film on the sample surface. When dripping molybdenum disulfide ink in the glass petri dish for the second time, it is dripped at the upper left corner position of the glass petri dish; Step 203: After placing the sample obtained in Step 202 on the lifting rack again, put the lifting rack into a glass petri dish, then add deionized water and n-hexane. When an obvious layered interface appears in the glass petri dish, for the third time, slowly and continuously drip molybdenum disulfide ink in the glass petri dish with a pipette. After a stable thin film is formed, extract the lifting rack to make the molybdenum disulfide thin film spread flat on the sample, and place the sample on a heating table for heat treatment to ensure that the liquid is completely evaporated, so as to form the third layer of molybdenum disulfide thin film on the sample surface. When dripping molybdenum disulfide ink in the glass petri dish for the third time, it is dripped at the lower right corner position of the glass petri dish; Step 3: Perform patterning treatment on the molybdenum disulfide thin film surface to obtain the pattern of the source and drain electrodes; Step 4: Deposit a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film to complete the patterning of the source and drain electrodes, and obtain the molybdenum disulfide transistor PUF array.

2. The preparation method of the molybdenum disulfide-based transistor PUF according to claim 1, wherein, In Step 3, electron beam lithography, ultraviolet lithography, extreme ultraviolet lithography or nanoimprinting is used for patterning treatment.

3. The preparation method of the molybdenum disulfide-based transistor PUF according to claim 1, characterized in that, In Step 4, the process of depositing a titanium thin film and a palladium thin film on the silicon oxide substrate covered with the molybdenum disulfide thin film is as follows: First deposit 10 nm of metallic titanium at a rate of 0.01 nm / s, and then deposit 50 nm of metallic palladium at a rate of 0.05 nm / s.

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