Array substrate, manufacturing method thereof and display device
By designing the structure of the buffer layer and flat surface in the array substrate of the oxide thin film transistor, the problem of pixels being unable to light up is solved, and the planarization and doping uniformity of the semiconductor layer are achieved.
Patent Information
- Application Number
- CN202510322530.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2025-06-13
AI Technical Summary
In the display substrate of an oxide thin film transistor (Oxide TFT) with a bottom gate structure, the problem of pixels being unable to light up is mainly due to the slope climbing of the oxide semiconductor layer, which leads to poor doping uniformity.
An array substrate is designed, including a substrate substrate, a first gate layer, a buffer layer, a semiconductor layer, and a source-drain metal layer. By setting a buffer layer between the semiconductor layer and the first gate layer, and forming a flat surface in the buffer layer, a slope climb of the semiconductor layer is avoided.
The planarization of the semiconductor layer is achieved, doping uniformity is improved, and abnormal phenomenon that pixels cannot be lit are solved.
Smart Images
Figure CN120152385A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background Art
[0002] In related technologies, in some display products, for example, in a display substrate using an oxide thin film transistor (Oxide TFT) with a bottom gate structure as a driving transistor, there is a problem that pixels cannot be lit. Summary of the Invention
[0003] To solve at least one of the above technical problems in the related technologies, embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device.
[0004] The technical solutions provided by the embodiments of the present disclosure are as follows:
[0005] In a first aspect, an embodiment of the present disclosure provides an array substrate, including:
[0006] A substrate;
[0007] A first gate layer disposed on the substrate, the first gate layer including a first gate;
[0008] A buffer layer disposed on a side of the first gate layer facing away from the substrate;
[0009] A semiconductor layer disposed on a side of the buffer layer facing away from the substrate;
[0010] A source-drain metal layer disposed on a side of the semiconductor layer facing away from the substrate, the source-drain metal layer including a source electrode and a drain electrode connected to the semiconductor layer; wherein,
[0011] The buffer layer includes a first surface adjacent to the semiconductor layer. At least in a first region, the first surface is a flat surface, so that there is no climbing region on the semiconductor layer. The first region is the region covered by the orthographic projection of the semiconductor layer on the substrate.
[0012] Exemplarily, at least in the first region, the first gate layer is a continuous and non-perforated integral film layer, so that the first surface is a flat surface; wherein, the main material of the first gate layer is made of a first material that does not have conductivity before doping and has conductivity after doping, and the first gate layer includes a doped region containing a doping material and a non-doped region not containing a doping material. The doped region at least includes the pattern of the first gate.
[0013] Exemplarily, the first material includes silicon, and the doping material includes boron and / or phosphorus.
[0014] Exemplarily, at least within the first region, a first structural layer adjacent to the first gate layer on a side away from the semiconductor layer and facing the semiconductor layer has a groove on the side facing the semiconductor layer. The first structural layer includes the substrate and / or any film layer between the first gate layer and the substrate; the first gate is located within the groove, and the first gate is flush with the surface of the first structural layer on the side close to the semiconductor layer, so that the first surface is a flat surface.
[0015] Exemplarily, at least within the first region, the buffer layer conformally covers the first gate and has a ramp region at the pattern edge of the first gate. The buffer layer includes a second region and a third region. The second region coincides with the orthographic projection of the first gate on the substrate. The thickness of the second region is less than the thickness of the third region, and the second region and the third region are flush with the surface on the side close to the semiconductor layer, so that the first surface is a flat surface.
[0016] Exemplarily, the first gate is a metal first gate; alternatively, the main material of the first gate layer is made of a first material that is not conductive before doping and is conductive after doping, and the first gate layer includes a doped region containing a doping material, and the doped region at least includes the pattern of the first gate.
[0017] Exemplarily, the source-drain metal layer further includes a first source-drain pattern other than the source and the drain, and the first source-drain pattern at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.
[0018] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing an array substrate for manufacturing the array substrate as described above. The method includes the following steps:
[0019] Provide a substrate.
[0020] Form a first gate layer on the substrate, and the first gate layer includes a first gate.
[0021] Form a buffer layer on a side of the first gate layer facing away from the substrate. The buffer layer includes a first surface adjacent to the semiconductor layer. At least within the first region, the first surface is a flat surface.
[0022] Form a semiconductor layer on a side of the buffer layer facing away from the substrate. There is no ramp region on the semiconductor layer. The first region is the region covered by the orthographic projection of the semiconductor layer on the substrate.
[0023] A source-drain metal layer is formed on a side of the semiconductor layer facing away from the substrate, and the source-drain metal layer includes a source electrode and a drain electrode connected to the semiconductor layer.
[0024] Exemplarily, forming the first gate layer on the substrate specifically includes:
[0025] Forming a main material layer of the first gate layer, at least within the first region, the main material layer is a continuous and non-perforated integral film layer, and a doping material is doped in the main material layer to form a doped region containing the doping material and an undoped region not containing the doping material, and the doped region at least includes the pattern of the first gate;
[0026] Or,
[0027] Forming the first gate layer on the substrate specifically includes:
[0028] At least within the first region, a groove is formed on a side of the first structure layer adjacent to the first gate layer and facing the semiconductor layer on a side of the first gate layer facing away from the semiconductor layer, the first structure layer includes the substrate and / or any film layer between the first gate layer and the substrate, and the first gate is formed within the groove, wherein the first gate is flush with the surface of the first structure layer on a side close to the semiconductor layer, so that the first surface is a flat surface;
[0029] Or,
[0030] Forming the buffer layer on a side of the first gate layer facing away from the substrate specifically includes:
[0031] The buffer layer is conformally coated on the first gate, and the buffer layer has a ramp region at the edge of the pattern of the first gate, the buffer layer includes a second region and a third region, and the second region coincides with the orthographic projection of the first gate on the substrate;
[0032] Thinning the second region so that the thickness of the second region is less than the thickness of the third region, and the second region and the third region are flush with the surface on a side close to the semiconductor layer, so that the first surface is a flat surface.
[0033] In a third aspect, an embodiment of the present disclosure provides a display device including the array substrate as described above.
[0034] The beneficial effects brought by the embodiments of the present disclosure are as follows:
[0035] In the above solution, a first gate, a semiconductor layer, a source electrode, and a drain electrode are provided on a substrate of an array substrate to form a thin-film transistor. The thin-film transistor adopts a bottom-gate structure. The semiconductor layer is located on a side of the first gate away from the substrate, and a buffer layer is provided between the semiconductor layer and the first gate. The buffer layer includes a first surface adjacent to the semiconductor layer. At least in a first region, the first surface is a flat surface so that there is no climbing region on the semiconductor layer. The first region is a region covered by a positive projection of the semiconductor layer on the substrate. In this way, there is no climbing region on the semiconductor layer, the doping uniformity of the semiconductor layer can be improved, and the abnormal phenomenon that the pixel cannot be lit can be solved. Description of the Drawings
[0036] Figure 1 Schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure;
[0037] Figure 2 Schematic diagram showing the structure of an array substrate in some other embodiments of the present disclosure;
[0038] Figure 3 Schematic diagram showing the structure of an array substrate in some other embodiments of the present disclosure. Detailed Embodiments
[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.
[0040] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure belongs. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
[0041] The features such as "parallel", "perpendicular" and "identical" used in the embodiments of this disclosure include the strictly defined features such as "parallel", "perpendicular" and "identical", as well as the cases with certain tolerances such as "substantially parallel", "substantially perpendicular" and "substantially identical". Considering measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of a measurement system), it means within an acceptable deviation range for a particular value determined by those of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 3% or 5% of the value.
[0042] In addition, in this document, unless otherwise defined, the terms "substantially", "essentially", "about" and "approximately" are used to describe and explain small variations. When used with an event or situation, these terms can cover the exact occurrence of the event or situation, or can also cover the approximate occurrence of the event or situation. For example, when used with a numerical value, these terms can include a variation range of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can mean that two surfaces are arranged along the same flat surface within a micron range, for example, within 40μm, 30μm, 20μm, 10μm or 1μm along the same flat surface.
[0043] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate. "A and B are arranged on the same layer" means that after A and B are formed into a film layer for forming a specific pattern by the same film-forming process, the layer structure is formed by using the same mask through a single patterning process.
[0044] In order to describe in detail the display substrate, its manufacturing method, and the display device provided by the embodiments of the present disclosure, the following description is made on the related technologies:
[0045] In the related technologies, in some display products, for example, in a display substrate using an oxide thin-film transistor (Oxide TFT) with a bottom-gate structure as a driving transistor, there is a problem that pixels cannot be lit.
[0046] The applicant of the present disclosure has found through research that one of the reasons for the above problems is that for an oxide thin-film transistor with a bottom-gate structure, the oxide semiconductor layer is located above the first gate, which will cause the oxide semiconductor layer to have a slope, and then the doping uniformity of the oxide semiconductor layer becomes poor, especially in the slope area where there is a region with less doping.
[0047] There is a source-drain metal layer above the oxide semiconductor layer. The pattern of the source-drain metal layer includes a source electrode, a drain electrode, and other source-drain patterns. The source electrode and the drain electrode can be connected to the oxide semiconductor layer. However, when other source-drain patterns are located above the oxide semiconductor layer and pass through the slope area, the slope area and other source-drain patterns will form a new thin-film transistor. The new thin-film transistor will be in series with the original thin-film transistor. When a negative voltage is input on other source-drain patterns, the series-connected thin-film transistors cannot be turned on, resulting in the corresponding pixels not being lit.
[0048] To solve the above problems, the embodiments of the present disclosure provide an array substrate, its manufacturing method, and a display device.
[0049] As Figures 1 to 3 shown, the embodiments of the present disclosure provide an array substrate, including:
[0050] A substrate substrate 100;
[0051] A first gate layer 200 provided on the substrate substrate 100, and the first gate layer 200 includes a first gate 210;
[0052] A buffer layer 300 provided on the side of the first gate layer 200 facing away from the substrate substrate 100;
[0053] A semiconductor layer 400 provided on a side of the buffer layer 300 facing away from the substrate 100;
[0054] A source-drain metal layer 500 provided on a side of the semiconductor layer 400 facing away from the substrate 100, the source-drain metal layer 500 including a source electrode 510 and a drain electrode 520 connected to the semiconductor layer 400; wherein,
[0055] The buffer layer 300 includes a first surface 301 adjacent to the semiconductor layer 400. At least in a first region A, the first surface 301 is a flat surface, so that there is no ramp region on the semiconductor layer 400. The first region A is an area covered by a positive projection of the semiconductor layer 400 on the substrate 100.
[0056] In the present application, "flat" and "flush" include features such as strictly "flat" and "flush", as well as cases such as "substantially flat" and "substantially flush" with a certain tolerance. Considering measurements and tolerances related to the measurement of a specific quantity (for example, limitations of the measurement system), it means within an acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "substantially" can mean within one or more standard deviations, or within 3% or 5% of the value.
[0057] In the above solution, the first gate 210, the semiconductor layer 400, the source electrode 510, and the drain electrode 520 are provided on the substrate 100 of the array substrate to form a thin-film transistor. The thin-film transistor adopts a bottom-gate structure. The semiconductor layer 400 is located on a side of the first gate 210 facing away from the substrate 100, and the buffer layer 300 is provided between the semiconductor layer 400 and the first gate 210. At least in the first region A, the first surface 301 of the buffer layer 300 adjacent to the semiconductor layer 400 is a flat surface. The first region A is an area covered by a positive projection of the semiconductor layer 400 on the substrate 100. In this way, there is no ramp region on the semiconductor layer 400, avoiding the problem of poor doping uniformity caused by the presence of a ramp on the semiconductor layer 400. In particular, when the thin-film transistor is a driving transistor and there are other source-drain patterns other than the source electrode 510 and the drain electrode 520 above the semiconductor layer 400, it is possible to prevent the other source-drain patterns from forming a new thin-film transistor with the ramp region on the semiconductor layer 400, so that signals such as voltage on the other source-drain patterns cannot affect the current of the thin-film transistor, and the abnormal phenomenon that the pixel cannot be lit can be solved.
[0058] It should be noted that the semiconductor layer 400 may be an oxide semiconductor layer 400, such as IGZO (indium gallium zinc oxide), etc. However, it is not limited thereto.
[0059] In some exemplary embodiments, as Figure 1 shown, at least within the first region A, the first gate layer 200 is a continuous, non-perforated, integral film layer, such that the first surface 301 is a flat surface; wherein, the main material of the first gate layer 200 is made of a first material that is non-conductive before doping and conductive after doping, and the first gate layer 200 includes a doped region 220 containing a doping material and a non-doped region 230 not containing a doping material, and the doped region 220 at least includes the pattern of the first gate 210.
[0060] Adopting the above solution, at least within the first region A covered by the semiconductor layer 400, the first gate layer 200 in the thin-film transistor with a bottom-gate structure is set as a continuous integral film layer, and the main material of the first gate layer 200 is non-conductive before doping and conductive after doping. In this way, doping can be performed at the position corresponding to the pattern of the target first gate 210 in the main material of the first gate layer 200, so that the doped region 220 is formed as the first gate 210, while other non-doped regions 230 are non-conductive. Thus, a non-patterned design of the first gate layer 200 can be achieved at least within the first region A, that is, the surface of the first gate layer 200 is flat within the first region A, and further the purpose of the semiconductor layer 400 having no ramp region can be achieved.
[0061] The first material can be selected as silicon, for example, and the doping material can be selected as boron and / or phosphorus, for example.
[0062] However, the selection of the first material and the doping material is not limited thereto, as long as the first material is non-conductive before doping and conductive after doping, it can be applied here. For example: the first material can also be selected as zinc oxide, and the doping material can be selected as aluminum or magnesium; or, the first material can also be selected as gallium nitride, and the doping material can be selected as carbon or silicon.
[0063] Selecting the first material as silicon has the following advantages compared with other main materials:
[0064] Silicon is one of the most abundant elements on Earth and is relatively easy to mine and refine. At the same time, the processing technology of silicon has been very mature and is widely used in the semiconductor industry. Silicon has a moderate bandgap (about 1.1 eV), enabling it to conduct electricity effectively at room temperature and maintain good electrical properties within different temperature ranges. By doping different elements (such as phosphorus, boron), the conductivity of silicon can be precisely controlled to meet the requirements of different applications. Silicon can still maintain its conductivity and structural stability at high temperatures, making it suitable for applications in high-temperature environments. Silicon has relatively high hardness and compressive strength, making it more reliable in certain applications. Compared with some other conductive materials, the production cost of silicon is relatively low, especially in large-scale production. Silicon-doped materials are widely used in fields such as electronic devices, solar cells, sensors, etc., and have good market acceptance and application prospects.
[0065] In the related art, in addition to forming the pattern of the first gate 210, the first gate layer 200 on the array substrate can also form other conductive patterns such as gate lines.
[0066] In some embodiments of the present disclosure, the first gate layer 200 can form the first gate 210 only within the first region A by doping a doping material into the main material. For example, other conductive patterns of the same layer as the first gate 210, such as gate lines, can still be made of a gate metal layer; or, in some other embodiments of the present disclosure, the first gate layer 200 can not only entirely cover the first region A, but also cover other regions except the first region A, and use the pattern of the doping region 220 to form other conductive patterns of the same layer arranged, such as gate lines.
[0067] In addition, in some exemplary embodiments, as Figure 2 shown, at least within the first region A, on the side of the first structure layer 10 adjacent to the first gate layer 200 and away from the semiconductor layer 400, a groove 20 is provided on the side facing the semiconductor layer 400.
[0068] For example, when the first gate layer 200 is directly formed on the substrate 100, the first structure layer 10 is the substrate 100; when there are other film layers such as a buffer layer 300 between the first gate layer 200 and the substrate 100, the first structure layer 10 can be the substrate 100 and / or any film layer between the first gate layer 200 and the substrate 100.
[0069] Take Figure 2Taking the example shown, when the first structural layer 10 is the substrate 100, a groove 20 is provided on the substrate 100, the first gate 210 is located in the groove 20, and the first gate 210 is flush with the first structural layer 10 on the surface close to the semiconductor layer 400, so that the first surface 301 is a flat surface.
[0070] In the above solution, the first gate 210 can maintain the patterned design in the related art. By providing a groove 20 on the first structural layer 10 to accommodate the first gate 210 and making the first gate 210 substantially flush with the first structural layer 10 on the surface close to the semiconductor layer 400, the step difference caused by the presence of the first gate 210 is eliminated, so that the buffer layer 300 and the semiconductor layer 400 can be prepared flatly, and the formation of a ramp region on the semiconductor layer 400 is avoided. Among them, the groove 20 can be formed on the first structural layer 10 by means of etching or the like.
[0071] It should be noted that when the first gate 210 is located in the groove 20, the first gate 210 can be a metal first gate 210; or, the main material of the first gate layer 200 is made of a first material that is not conductive before doping and is conductive after doping, and the first gate layer 200 includes a doped region 220 containing a doping material, and the doped region 220 at least includes the pattern of the first gate 210.
[0072] In addition, when the first gate 210 is located in the groove 20, the first gate layer 200 can also include other conductive patterns other than the first gate 210, such as gate lines, etc. Grooves 20 corresponding to other conductive patterns can also be provided on the first structural layer 10. The other conductive patterns on the first gate layer 200 can be directly arranged in the corresponding grooves 20, or the other conductive patterns on the first gate layer 200 located outside the first region A can be directly on the surface of the first structural layer 10.
[0073] In addition, in some exemplary embodiments, as Figure 3 shown, at least in the first region A, the buffer layer 300 conformally covers the first gate 210 and has a ramp region at the pattern edge of the first gate 210. The buffer layer 300 includes a second region 302 and a third region 303. The second region 302 coincides with the first gate 210 in the orthographic projection on the substrate 100. The thickness of the second region 302 is less than the thickness of the third region 303, and the second region 302 and the third region 303 are flush with each other on the surface close to the semiconductor layer 400, so that the first surface 301 is a flat surface.
[0074] In the above solution, after the buffer layer 300 is formed on the first gate layer 200, since the buffer layer 300 conformally covers the first gate 210 and a ramp region is formed at the pattern edge of the first gate 210, the portion of the buffer layer 300 corresponding to the first gate 210 can be thinned to form the second region 302, so that the second region 302 and the third region 303 are substantially flush on the surface close to the semiconductor layer 400, realizing the planarization of the first surface 301.
[0075] It should be noted that, in this embodiment, the first gate 210 may be a metal first gate 210; alternatively, the main material of the first gate layer 200 is made of a first material that is not conductive before doping and conductive after doping, and the first gate layer 200 includes a doped region 220 containing a doping material, and the doped region 220 at least includes the pattern of the first gate 210.
[0076] It should also be noted that, in this embodiment, within the first region A, the first gate layer 200 may be a whole surface structure that is continuously arranged and has no hollow structure, and the first gate 210 is formed by the doped region 220, or alternatively, the first gate layer 200 may be a pattern of the first gate 210 formed by patterning a gate metal layer.
[0077] In addition, there may be one or at least two buffer layers 300 between the first gate layer 200 and the semiconductor layer 400. Figure 3 Taking the shown as an example, there are two buffer layers 300 between the first gate layer 200 and the semiconductor layer 400, namely the first buffer layer 310 and the second buffer layer 320, and the planarization of the semiconductor layer 400 can be achieved by thinning any one of the buffer layers 300.
[0078] In addition, in some exemplary embodiments, as Figure 1 shown, the source-drain metal layer 500 further includes a first source-drain pattern 530 in addition to the source electrode 510 and the drain electrode 520, wherein the first source-drain pattern 530 at least partially overlaps with the positive projection of the semiconductor layer 400 on the substrate 100. In the array substrate of the present disclosure, by adopting a non-ramp design for planarizing the semiconductor layer 400, it is possible to avoid forming a new thin film transistor between the first source-drain pattern 530 and the semiconductor layer 400, so that the signal on the first source-drain pattern 530 cannot affect the current of the thin film transistor, and the abnormal phenomenon that the pixel cannot be lit can be solved.
[0079] In addition, please refer to Figure 1As shown, in some embodiments, the thin film transistor on the array substrate may have a double-gate structure. In addition to including a first gate 210 as the bottom gate, it may further include a second gate 610 as the top gate. The second gate 610 may be located on the side of the semiconductor layer 400 away from the substrate 100 and on the side of the source-drain metal layer 500 close to the substrate 100. However, this is not a limitation.
[0080] After the semiconductor layer 400 is flattened without a ramp design, a doping uniformity simulation test is performed on the semiconductor layer of the array substrate. The obtained semiconductor layer doping simulation results show that the doping of the semiconductor layer is uniform.
[0081] In addition, embodiments of the present disclosure provide a method for manufacturing an array substrate for manufacturing the array substrate provided by the embodiments of the present disclosure. The method includes the following steps:
[0082] Step S01: Provide a substrate 100;
[0083] Step S02: Form a first gate layer 200 on the substrate 100. The first gate layer 200 includes a first gate 210;
[0084] Step S03: Form a buffer layer 300 on the side of the first gate layer 200 away from the substrate 100. The buffer layer 300 includes a first surface 301 adjacent to the semiconductor layer 400. At least in the first region A, the first surface 301 is a flat surface;
[0085] Step S04: Form a semiconductor layer 400 on the side of the buffer layer 300 away from the substrate 100. There is no ramp region on the semiconductor layer 400. The first region A is the region covered by the orthographic projection of the semiconductor layer 400 on the substrate 100;
[0086] Step S05: Form a source-drain metal layer 500 on the side of the semiconductor layer 400 away from the substrate 100. The source-drain metal layer 500 includes a source electrode 510 and a drain electrode 520 connected to the semiconductor layer 400.
[0087] In the above solution, the first gate 210, the semiconductor layer 400, the source electrode 510, and the drain electrode 520 are provided on the substrate 100 of the array substrate to form a thin-film transistor. The thin-film transistor adopts a bottom-gate structure. The semiconductor layer 400 is located on a side of the first gate 210 away from the substrate 100, and a buffer layer 300 is provided between the semiconductor layer 400 and the first gate 210. At least in the first region A, a first surface 301 of the buffer layer 300 adjacent to the semiconductor layer 400 is a flat surface. The first region A is an area covered by a positive projection of the semiconductor layer 400 on the substrate 100.
[0088] In this way, there is no climbing area on the semiconductor layer 400, avoiding the problem of poor doping uniformity caused by the climbing of the semiconductor layer 400. In particular, when the thin-film transistor is used as a driving transistor and there are other source-drain patterns above the semiconductor layer 400 in addition to the source electrode 510 and the drain electrode 520, it is possible to prevent the other source-drain patterns from forming a new thin-film transistor with the climbing area on the semiconductor layer 400. Thus, signals such as voltage on the other source-drain patterns cannot affect the current of the thin-film transistor, and the abnormal phenomenon that the pixel cannot be lit can be solved.
[0089] In some exemplary embodiments, the above step S02 specifically includes:
[0090] Step S021: Form a main material layer of the first gate layer 200;
[0091] Step S022: At least in the first region A, the main material layer is a continuous and non-hollowed-out integral film layer, and a doping material is doped into the main material layer to form a doped region 220 containing the doping material and a non-doped region 230 not containing the doping material. The doped region 220 at least includes the pattern of the first gate 210.
[0092] In some other exemplary embodiments, the above step S02 specifically includes:
[0093] Step S021': At least in the first region A, a groove 20 is formed on a side of the first gate layer 200 away from the semiconductor layer 400 and adjacent to the first gate layer 200, on a side of a first structure layer 10 facing the semiconductor layer 400. The first structure layer 10 includes the substrate 100 and / or any film layer between the first gate layer 200 and the substrate 100.
[0094] Step S022': Form the first gate 210 in the groove 20, where the first gate 210 is flush with the first structural layer 10 on the surface closer to the semiconductor layer 400, so that the first surface 301 is a flat surface.
[0095] In some other exemplary embodiments, the above step S03 specifically includes:
[0096] Step S031: Conformally cover the buffer layer 300 on the first gate 210, and the buffer layer 300 has a ramp region at the pattern edge of the first gate 210. The buffer layer 300 includes a second region 302 and a third region 303, and the second region 302 coincides with the first gate 210 in the orthographic projection on the substrate 100.
[0097] Step S032: Thin the second region 302 so that the thickness of the second region 302 is less than the thickness of the third region 303. The second region 302 and the third region 303 are flush with each other on the surface closer to the semiconductor layer 400, so that the first surface 301 is a flat surface.
[0098] Among them, in the above step S032, the partial film layer thickness of the second region 302 can be thinned by etching or other means.
[0099] In addition, the embodiments of the present disclosure provide a display device including the array substrate provided by the embodiments of the present disclosure. The display device includes, but is not limited to, devices with display functions such as smart phones, displays, laptop computers, tablet computers, electronic photo frames, dash cams, and smart wearable devices. Other essential components of the display device (such as a driving chip) should be understood by those of ordinary skill in the art and will not be elaborated here, nor should it be regarded as a limitation to the present disclosure. Since the principle of solving problems of this display device is similar to that of the above array substrate, the embodiments of this display device provided by the embodiments of the present disclosure can refer to the embodiments of the above array substrate provided by the embodiments of the present disclosure and will not be elaborated here.
[0100] The following points need to be explained:
[0101] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general designs.
[0102] (2) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced, that is, these drawings are not drawn to actual scale. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element or there can be intervening elements.
[0103] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0104] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims
1. An array substrate, characterized in that: include: substrate substrate; A first gate layer provided on the base substrate, wherein the first gate layer comprises a first gate; A buffer layer provided on a side of the first gate layer away from the base substrate; A semiconductor layer disposed on a side of the buffer layer away from the substrate; A source-drain metal layer is provided on a side of the semiconductor layer away from the substrate, the source-drain metal layer includes a source electrode and a drain electrode connected to the semiconductor layer; wherein, The buffer layer includes a first surface adjacent to the semiconductor layer. At least in a first region, the first surface is flat so that there is no climbing region on the semiconductor layer. The first region is a region covered by the orthographic projection of the semiconductor layer on the substrate.
2. The array substrate according to claim 1, characterized in that: At least in the first region, the first gate layer is a whole-surface film layer that is continuously arranged without any hollow region, so that the first surface is a flat surface; wherein the main material of the first gate layer is made of a first material that is non-conductive before undoping and conductive after doping, and the first gate layer includes a doped region containing doped material and a non-doped region not containing doped material, and the doped region at least includes a pattern of the first gate.
3. The array substrate according to claim 2, characterized in that: The first material includes silicon, and the doping material includes boron and / or phosphorus.
4. The array substrate according to claim 1, characterized in that: At least in the first region, a first structural layer adjacent to the first gate layer on a side of the first gate layer away from the semiconductor layer is provided with a groove on a side facing the semiconductor layer, and the first structural layer includes the substrate, and / or any film layer between the first gate layer and the substrate; the first gate is located in the groove, and the first gate is flush with the surface of the first structural layer on a side close to the semiconductor layer, so that the first surface is a flat surface.
5. The array substrate according to claim 1, characterized in that: At least in the first region, the buffer layer conformally covers the first gate and has a climbing region at the pattern edge of the first gate, the buffer layer includes a second region and a third region, the second region coincides with the orthographic projection of the first gate on the substrate, the thickness of the second region is less than the thickness of the third region, and the second region is flush with the third region on the side close to the semiconductor layer, so that the first surface is a flat surface.
6. The array substrate according to any one of claims 4 or 5, characterized in that: The first gate is a metal first gate; or, the main material of the first gate layer is made of a first material that is non-conductive before being doped and conductive after being doped, and the first gate layer includes a doping region containing a doping material, and the doping region at least includes a pattern of the first gate.
7. The array substrate according to claim 1, characterized in that: The source-drain metal layer further includes a first source-drain pattern except the source electrode and the drain electrode, wherein the first source-drain pattern at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.
8. A method for manufacturing an array substrate, characterized in that: For manufacturing the array substrate according to any one of claims 1 to 7, the method comprises the following steps: providing a substrate base plate; forming a first gate layer on the base substrate, wherein the first gate layer includes a first gate; forming a buffer layer on a side of the first gate layer away from the substrate, the buffer layer comprising a first surface adjacent to the semiconductor layer, and at least in a first region, the first surface is a flat surface; Forming a semiconductor layer on a side of the buffer layer away from the substrate, wherein there is no climbing area on the semiconductor layer, and the first area is an area covered by an orthographic projection of the semiconductor layer on the substrate; A source-drain metal layer is formed on a side of the semiconductor layer away from the base substrate, and the source-drain metal layer includes a source electrode and a drain electrode connected to the semiconductor layer.
9. The method according to claim 8, characterized in that The step of forming a first gate layer on the base substrate specifically includes: A main material layer for forming a first gate layer, wherein at least in the first region, the main material layer is a whole-surface film layer continuously provided without a hollow region, and a doping material is doped in the main material layer to form a doped region containing the doping material and a non-doped region containing no doping material, wherein the doped region at least includes a pattern of the first gate; or, The step of forming a first gate layer on the base substrate specifically includes: At least in the first region, a first structure layer adjacent to the first gate layer on a side of the first gate layer away from the semiconductor layer forms a groove on a side facing the semiconductor layer, the first structure layer includes the substrate, and / or any film layer between the first gate layer and the substrate, the first gate is formed in the groove, wherein the first gate is flush with a surface of the first structure layer on a side close to the semiconductor layer, so that the first surface is a flat surface; or, The forming of a buffer layer on a side of the first gate layer away from the base substrate specifically includes: The buffer layer is conformally covered on the first gate, and the buffer layer has a climbing area at the pattern edge of the first gate, the buffer layer includes a second area and a third area, and the second area coincides with the orthographic projection of the first gate on the substrate; The second region is thinned so that the thickness of the second region is smaller than that of the third region, and the second region is flush with the third region on a side close to the semiconductor layer, so that the first surface is a flat surface.
10. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 7.