Display device

Abstract

A display device is provided. The display device includes: a substrate including a plurality of sub-pixels; a plurality of light emitting diodes disposed on the substrate in the plurality of sub-pixels and each including a first electrode and a second electrode disposed in a higher position than the first electrode; a first planarization layer disposed on the substrate so as to surround a portion of side surfaces of the plurality of light emitting diodes; a plurality of first connection electrodes disposed on the first planarization layer and connected to the first electrodes; a second planarization layer disposed on the first planarization layer and the plurality of first connection electrodes; and a plurality of second connection electrodes disposed on the second planarization layer and connected to the second electrodes. Therefore, short circuit defects can be minimized or reduced.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example but not limited to, a display device that minimizes or reduces short - circuit defects between electrodes. Background Art

[0002] As display devices for monitors of computers, televisions, or mobile phones, there are organic light - emitting display devices (OLEDs) as self - emissive devices and liquid - crystal display devices (LCDs) that require a separate light source, etc.

[0003] The application range of display devices has been diversified to personal digital assistants, monitors of computers, and televisions, and display devices with a large display area and reduced volume and weight are being studied.

[0004] In addition, recently, display devices including light - emitting diodes (LEDs) that can be made of inorganic materials have been attracting attention as next - generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, their reliability is excellent, making their lifespan longer than that of liquid - crystal display devices or organic light - emitting display devices. In addition, LEDs have a fast lighting speed, excellent luminous efficiency, and strong shock resistance, making their stability excellent and enabling them to display images with high brightness.

[0005] The description provided in this background art section should not be assumed to be prior art merely because it is mentioned in or related to the background art section. The background art section may include information that describes one or more aspects of the subject technology. Summary of the Invention

[0006] One aspect of the present disclosure is to provide a display device capable of self - aligning a first connection electrode and a first electrode of a light - emitting diode.

[0007] One aspect of the present disclosure is to provide a display device capable of self - aligning a second connection electrode and a second electrode of a light - emitting diode.

[0008] Another aspect of the present disclosure is to provide a display device that separates a region where a passivation film under a light - emitting diode is torn from a first connection electrode to minimize or reduce short - circuit defects of the first connection electrode.

[0009] One aspect of the present disclosure is to provide a display device that minimizes or reduces short - circuit defects.

[0010] One aspect of the present disclosure is to provide a display device that suppresses short - circuit defects and is driven at low power to reduce power consumption.

[0011] Another aspect of the present disclosure is to provide a display device that is easy to repair.

[0012] Aspects of the present disclosure are not limited to the above aspects, and those skilled in the art can clearly understand other aspects not mentioned above from the following description.

[0013] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device includes: a substrate including a plurality of sub-pixels; a plurality of light-emitting diodes disposed on the substrate among the plurality of sub-pixels, and each including a first electrode and a second electrode disposed at a higher position than the first electrode; a first planarization layer disposed on the substrate so as to surround a part of the side surfaces of the plurality of light-emitting diodes; a plurality of first connection electrodes disposed on the first planarization layer and connected to the first electrode; a second planarization layer disposed on the first planarization layer and the plurality of first connection electrodes; and a plurality of second connection electrodes disposed on the second planarization layer and connected to the second electrode. Accordingly, short-circuit defects can be minimized or reduced.

[0014] Other details of the exemplary embodiments are included in the detailed description and the drawings.

[0015] According to an exemplary embodiment of the present disclosure, the first connection electrode and the second connection electrode are connected to the light-emitting diode in a self-aligned manner without a separate alignment process by means of an ashing process of the first planarization layer and the second planarization layer to ensure transfer margin.

[0016] According to an exemplary embodiment of the present disclosure, the first planarization layer fills a region where a passivation film under the light-emitting diode is torn, and the first connection electrode is disposed on the first planarization layer to minimize or reduce short-circuit defects of the first connection electrode due to the torn passivation film.

[0017] According to an exemplary embodiment of the present disclosure, the first sub-electrode and the second sub-electrode are separated in a plane to minimize or reduce short-circuit defects caused by misalignment between the first sub-electrode and the second sub-electrode due to process errors.

[0018] According to an exemplary embodiment of the present disclosure, only a part of the first sub-electrode or the second sub-electrode that contacts the defective light-emitting diode is cut with a laser, thereby facilitating repair.

[0019] According to an exemplary embodiment of the present disclosure, a display device is provided that suppresses short-circuit defects and is driven at low power in terms of reducing power consumption.

[0020] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification.

[0021] It is to be understood that both the foregoing description and the following description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the claimed inventive concept. Brief Description of the Drawings

[0022] The drawings may be included to provide a further understanding of the present disclosure, and may be incorporated into and form a part of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain various principles of the present disclosure.

[0023] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the drawings, in which:

[0024] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 3 and Figure 4 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 5 is a schematic enlarged plan view of a display device according to another exemplary embodiment of the present disclosure;

[0029] Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0030] Figures 7A to 7F is a process diagram for explaining a manufacturing method of a display device according to another exemplary embodiment of the present disclosure;

[0031] Figure 8 is a diagram for explaining the effects of a first connection electrode and a second connection electrode of a display device according to another exemplary embodiment of the present disclosure;

[0032] Figure 9 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure;

[0033] Figure 10 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure;

[0034] Figure 11 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure;

[0035] Figure 12is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure;

[0036] Figures 13A to 13C is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure; and

[0037] Figure 14 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0038] Throughout the drawings and the detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, and their illustrations, may be exaggerated. Detailed Embodiments

[0039] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of well-known functions or configurations related to the present document is determined to unnecessarily obscure the gist of the inventive concept, its detailed description will be omitted or briefly provided. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein and may be changed as is known in the art, except for steps and / or operations that must occur in a specific order. Like reference numerals designate like elements throughout. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification and may thus be different from the names used in actual products.

[0040] By referring to the following exemplary embodiments described in detail in conjunction with the Figure One drawings, the advantages and features of the present disclosure, and the methods of achieving the advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0041] The shapes, dimensions, areas, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Like reference numerals generally refer to like elements throughout the present specification. In addition, in the following description of the present disclosure, a detailed explanation of known related technologies may be omitted or briefly provided to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," "having," "including," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Any reference to the singular may include the plural unless otherwise expressly stated.

[0042] Even if not explicitly stated, components are construed to include ordinary error ranges.

[0043] When describing positional relationships, for example, when using terms such as "on", "above", "below", "over", "under", "beneath", "lower", "adjacent to", "close to", or "next to", "beside", "alongside" to describe the positional relationship between two components, one or more other components may be disposed between the two components, unless more restrictive terms such as "immediately", "directly", or "closely" are used. For example, when a structure is described as being "on", "above", "under", "over", "beneath", "below", "adjacent to", "close to", or "next to" another structure, "beside" another structure, "alongside" another structure, this description should be construed to include cases where the structures are in contact with each other and cases where a third structure is disposed or interposed therebetween. In addition, terms such as "left", "right", "top", "bottom", "downward", "upward", "upper", "lower" etc. refer to any reference system.

[0044] When an element or layer is disposed "on" another element or layer, another layer or another element may be directly interposed on or between yet another element.

[0045] Although terms such as "first", "second", "A", "B", "(a)", "(b)" etc. are used to describe various components, these components are not bound by these terms. These terms are only used to distinguish one component from another. Thus, in the technical concept of the present disclosure, the first component mentioned below may be the second component. In addition, when an element or layer is described as "connected", "coupled", or "adhered" to another element or layer, the element or layer may not only be directly connected or adhered to the other element or layer, but may also be indirectly connected or adhered to the other element or layer and one or more intermediate elements or layers are "disposed" between the element or layer, unless otherwise specified.

[0046] Like reference numerals throughout the specification generally refer to like elements.

[0047] The dimensions and thicknesses of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0048] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" encompasses the combination of all three listed elements, the combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0049] The features of the various embodiments of the present disclosure may adhere to or combine with each other in part or in whole, and may be coupled and operated in various technical manners, and the embodiments may be implemented independently of or in association with each other.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, the term "component" or "unit" may be applied, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as would be understood by one of ordinary skill in the art.

[0051] The transistor used in the display device according to the exemplary embodiment of the present disclosure may be implemented as either an n-channel transistor (NMOS) or a p-channel transistor (PMOS). The transistor may be implemented as an oxide semiconductor transistor having an oxide semiconductor as an active layer, or a low-temperature polycrystalline silicon (LTPS) transistor having LTPS as an active layer. The transistor may at least include a gate electrode, a source electrode, and a drain electrode. The transistor may be implemented as a thin-film transistor (TFT) on a display panel. Carriers in the transistor flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the carriers are electrons, the source voltage may be lower than the drain voltage so that electrons can flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), the current may flow from the drain electrode to the source electrode, and the source electrode may be the output terminal. In the case of a p-channel transistor (PMOS), since the carriers are holes, the source voltage may be higher than the drain voltage so that holes can flow from the source electrode to the drain electrode. Since holes flow from the source electrode to the drain electrode in a p-channel transistor (PMOS), the current may flow from the source electrode to the drain electrode, and the drain electrode may be the output terminal. Therefore, it should be noted that since the source and drain electrodes may vary depending on the applied voltage, the source and drain electrodes of the transistor are not fixed. In the present disclosure, the description is made by assuming that the transistor is an n-channel transistor (NMOS), but the present disclosure is not limited thereto, and a p-channel transistor may be used, and thus the circuit configuration may also change.

[0052] The strobe signal of the transistor used as a switching element can swing between a gate-on voltage and a gate-off voltage. The gate-on voltage can be set to a voltage higher than the threshold voltage Vth of the transistor, while the gate-off voltage can be set to a voltage lower than the threshold voltage Vth of the transistor. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor (NMOS), the gate-on voltage can be the gate high voltage (VGH), and the gate-off voltage can be the gate low voltage (VGL). In the case of a p-channel transistor (PMOS), the gate-on voltage can be the gate low voltage (VGL), and the gate-off voltage can be the gate high voltage (VGH).

[0053] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. In Figure 1 order to facilitate the description, among the various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated.

[0055] Referring to Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that provide various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0056] The gate driver GD provides a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals provided from the timing controller TC. Even in Figure 1 one gate driver GD is illustrated as being spaced apart from one side of the display panel PN, the number and placement of the gate drivers GD are not limited thereto. For example, the gate driver can be arranged on one or both sides of the display panel PN in the gate-in-panel (GIP) manner, or arranged within the display area of the display panel PN in the gate-in-area (GIA) manner, and the present disclosure is not limited thereto.

[0057] The data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage according to a plurality of data control signals provided from the timing controller TC. The data driver DD can provide the converted data voltage to a plurality of data lines DL.

[0058] The timing controller TC aligns the image data input from the outside to provide the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using the synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. The timing controller TC provides the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0059] The display panel PN is a structure that displays an image to the user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and the plurality of sub-pixels SP are respectively connected to the scan lines SL and the data lines DL. In addition, although not shown in the figure, each of the plurality of sub-pixels SP may be connected to a high-potential power supply line, a low-potential power supply line, a reference line, etc.

[0060] In the display panel PN, a display area AA and a non-display area NA surrounding the display area AA may be defined.

[0061] The display area AA is an area where the display image in the display device 100 is displayed. In the display area AA, a plurality of sub-pixels SP that constitute a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units that constitute the display area AA, and n sub-pixels SP may form one pixel PX. In each of the plurality of sub-pixels SP, a light-emitting diode and a thin-film transistor for driving the light-emitting diode may be provided. Depending on the type of the display panel PN, the plurality of light-emitting diodes may be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel, the light-emitting diode may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED), and the micro LED may have a size less than 100 micrometers, but is not limited thereto.

[0062] In the display area AA, a plurality of signal lines for sending various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines may include a plurality of data lines DL for providing a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL for providing a gate voltage to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the display area AA to connect to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in which the scan lines extend in the display area AA to connect to the plurality of sub-pixels SP. In addition, in the display area AA, a low-potential power supply line and a high-potential power supply line may also be provided, but are not limited thereto.

[0063] The non-display area NA is an area where an image is not displayed, such that the non-display area NA can be defined as an area extending from the display area AA or an area adjacent to the display area AA. In the non-display area NA, link lines, pad electrodes, or driving ICs (such as a gate driver IC or a data driver IC) that send signals to the sub-pixels SP of the display area AA can be provided. The non-display area NA can be located on the rear surface of the display panel PN (e.g., on the surface where the sub-pixels SP are not provided) or can be omitted, and is not limited to that shown in the figure.

[0064] In addition, drivers such as a gate driver GD, a data driver DD, and a timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-display area NA in a gate-in-panel (GIP) manner or can be mounted between a plurality of sub-pixels SP in the display area AA in a gate-in-area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards, and can be electrically connected to the display panel PN by bonding the flexible films and printed circuit boards to pad electrodes formed in the non-display area NA of the display panel PN. If the gate driver GD is mounted in the GIP manner and the data driver DD and the timing controller TC send signals to the display panel PN through the pad electrodes of the non-display area NA, it is necessary to ensure the area in the non-display area NA where the gate driver GD and the pad electrodes are provided. In this case, the bezel may increase.

[0065] On the contrary, when the gate driver GD is mounted in the GIA manner in the display area AA and the side line SRL connects the signal lines on the front surface of the display panel PN to the pad electrodes formed on the rear surface of the display panel PN for bonding the flexible film and the printed circuit board on the rear surface of the display panel PN, the non-display area NA can be minimized or reduced on the front surface of the display panel PN. For example, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel with substantially no bezel can be achieved, which will be described in more detail with reference to Figure 2A and Figure 2B more specifically.

[0066] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure, and Figure 2B is a perspective view of a tiled display device according to an exemplary embodiment of the present disclosure.

[0067] In a non-display area NA of a display panel PN, a plurality of pad electrodes are provided for sending various signals to a plurality of sub-pixels SP. For example, in the non-display area NA on the front surface of the display panel PN, a first pad electrode PAD1 for sending signals to the plurality of sub-pixels SP is provided. In the non-display area NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board is provided.

[0068] For example, the display panel PN can be formed by joining two or more substrates in a vertical direction. At this time, the first pad electrode PAD1 and the second pad electrode PAD2 can be provided on different substrates. For example, the first pad electrode PAD1 can be provided on the front surface of the upper substrate. The second pad electrode PAD2 can be provided on the rear surface of the lower substrate. For example, the display panel PN can be formed by joining an upper substrate having the first pad electrode PAD1 provided on the front surface and a lower substrate having the second pad electrode PAD2 provided on the rear surface, but is not limited thereto.

[0069] In this case, although not shown in the figure, various signal lines (e.g., a scan line SL or a data line DL) connected to the plurality of sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0070] A side line SRL is provided along a side surface of the display panel PN. The side line SRL can electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals from the driving component on the rear surface of the display panel PN can be sent to the plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Accordingly, a signal transmission path is formed from the front surface to the side surface and the rear surface of the display panel PN to minimize or reduce the area of the non-display area NA of the display panel PN.

[0071] Refer to Figure 2B , a tiled display device TD having a large screen size can be realized by connecting or combining a plurality of display devices 100. At this time, as Figure 2A shown, when the tiled display device TD is realized using the display device 100 having a minimized or reduced bezel, a seam area between the display devices 100 where no image is displayed is minimized or reduced, so that the display quality can be improved.

[0072] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Accordingly, a constant interval of pixels PX between display devices 100 is implemented, thereby minimizing or reducing a seam area.

[0073] However, Figure 2A and Figure 2B are exemplary, such that the display device 100 according to an exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0074] Figure 3 and Figure 4 are cross-sectional views of a display device according to an exemplary embodiment of the present disclosure. For example, Figure 3 and Figure 4 are cross-sectional views of a sub-pixel SP.

[0075] Referring to Figure 3 and Figure 4 , in each of a plurality of sub-pixels SP of a display panel PN of a display device 100 according to an exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, an outer coating layer 115, an adhesive layer 116, a first planarization layer 117a, a second planarization layer 117b, a bank 118, a third planarization layer 119, a driving transistor DT, a light emitting diode LED, a plurality of reflective electrodes RE, a light shielding layer LS, an auxiliary electrode LE, a plurality of first connection electrodes CE1, and a plurality of second connection electrodes CE2 may be provided.

[0076] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic, or may be formed of a flexible material. For example, the substrate 110 may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any one of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cycloolefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are merely examples and are not necessarily limited thereto.

[0077] The light-shielding layer LS can be disposed in each of a plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident from the lower portion of the substrate 110 onto the active layer ACT of the driving transistor DT to be described below. The light incident on the active layer ACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize or reduce leakage current.

[0078] The buffer layer 111 can be disposed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the infiltration of moisture or impurities through the substrate 110. The buffer layer 111 can be constructed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 can be omitted depending on the type of the substrate 110 or the type of the transistor, but is not limited thereto.

[0079] The driving transistor DT can be disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0080] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. The oxide semiconductor can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and their oxides. Specifically, the oxide semiconductor can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO), but is not limited thereto.

[0081] The gate insulating layer 112 can be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE, and can be constructed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0082] The gate electrode GE can be disposed on the gate insulating layer 112. The gate electrode GE can be constructed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0083] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be disposed on the gate electrode GE. In the first interlayer insulating layer 113 and the second interlayer insulating layer 114, contact holes are formed, and the source electrode SE and the drain electrode DE are connected to the active layer ACT through the contact holes. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting the components below the first interlayer insulating layer 113 and the second interlayer insulating layer 114, and may be constructed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0084] The source electrode SE and the drain electrode DE electrically connected to the active layer ACT may be disposed on the second interlayer insulating layer 114. The source electrode SE and the drain electrode DE may be constructed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0085] In addition, in the present disclosure, it is described that the first interlayer insulating layer 113 and the second interlayer insulating layer 114 (e.g., a plurality of insulating layers) are disposed between the gate electrode GE and the source electrode SE and the drain electrode DE. However, only one insulating layer may be disposed between the gate electrode GE and the source electrode SE and the drain electrode DE, but is not limited thereto.

[0086] As shown in the figure, when a plurality of insulating layers such as the first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed between the gate electrode GE, the source electrode SE, and the drain electrode DE, an electrode may be further formed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The additionally formed electrode may form a capacitor with other structures disposed below the first interlayer insulating layer 113 or above the second interlayer insulating layer 114.

[0087] The auxiliary electrode LE may be disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to any one of the source electrode SE and the drain electrode DE on the second interlayer insulating layer 114. For example, the light-shielding layer LS is electrically connected to any one of the source electrode SE or the drain electrode DE through the auxiliary electrode LE, so that it does not operate as a floating gate. Therefore, fluctuations in the threshold voltage of the driving transistor DT caused by the floating light-shielding layer LS can be minimized or reduced. Although the light-shielding layer LS is illustrated as being connected to the source electrode SE in the figure, the light-shielding layer LS may also be connected to the drain electrode DE, but is not limited thereto.

[0088] The power supply line VDD may be disposed on the second interlayer insulating layer 114. The power supply line VDD is electrically connected to the light-emitting diode LED together with the driving transistor DT to allow the light-emitting diode LED to emit light. The power supply line VDD may be constructed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto. It should be noted that although the power supply line is shown as a high-potential power supply line VDD in some embodiments of the present disclosure, the present disclosure is not limited thereto, and the power supply line electrically connected to the light-emitting diode LED may also be a low-potential power supply line VSS.

[0089] The outer coating 115 is disposed on the driving transistor DT and the power supply line VDD. The outer coating 115 may flatten the upper portion of the substrate 110 on which the driving transistor DT is disposed. The outer coating 115 may be constructed of a single layer or a double layer, and for example, may be formed of a photoresist or an acrylic organic material, but is not limited thereto.

[0090] A plurality of reflection electrodes RE spaced apart from each other may be disposed on the outer coating 115. The plurality of reflection electrodes RE may electrically connect the light-emitting diode LED to the power supply line VDD and the driving transistor DT, and may serve as a reflector for reflecting the light emitted from the light-emitting diode LED upward. The plurality of reflection electrodes RE are formed of a conductive material having excellent reflection performance to reflect the light emitted from the light-emitting diode LED upward.

[0091] The plurality of reflection electrodes RE may include a first reflection electrode RE1 and a second reflection electrode RE2. The first reflection electrode RE1 may electrically connect the driving transistor DT and the light-emitting diode LED. The first reflection electrode RE1 may be connected to the source electrode SE or the drain electrode DE of the driving transistor DT through a contact hole formed in the outer coating 115. The first reflection electrode RE1 may be electrically connected to the first electrode 124 of the light-emitting diode LED through a first connection electrode CE1.

[0092] The second reflection electrode RE2 may electrically connect the power supply line VDD and the light-emitting diode LED. The second reflection electrode RE2 may be connected to the power supply line VDD through a contact hole formed in the outer coating 115, and may be electrically connected to the second electrode 125 of the light-emitting diode LED through a second connection electrode CE2 to be described below.

[0093] On the plurality of reflection electrodes RE, an adhesive layer 116 is formed on the front surface of the substrate 110 to fix the light-emitting diode LED disposed on the adhesive layer 116. The adhesive layer 116 may be formed of a photocurable adhesive material cured by light. For example, the adhesive layer 116 may be formed of an acrylic material including a photoresist, but is not limited thereto.

[0094] On the adhesive layer 116, a plurality of light-emitting diodes LED can be disposed in each of the plurality of sub-pixels SP. The plurality of light-emitting diodes LED are elements that emit light through an electric current, and can include light-emitting diodes LED that emit red, green, and blue light, and various colors of light including white light can be achieved through their combination. For example, the plurality of light-emitting diodes LED can be light-emitting diodes (LEDs) or micro LEDs, but are not limited thereto. In the present disclosure, the light-emitting diode LED can also be referred to as a light-emitting element or a light-emitting device, but is not limited thereto.

[0095] The light-emitting diode LED can include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126.

[0096] The first semiconductor layer 121 can be disposed on the adhesive layer 116, and the second semiconductor layer 123 can be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 can be layers formed by doping an n-type impurity and a p-type impurity into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers doped with an n-type impurity and a p-type impurity in materials such as gallium nitride (GaN), aluminum indium phosphide (InAlP), or gallium arsenide (GaAs), respectively. The p-type impurity can be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurity can be silicon (Si), germanium, and tin (Sn), but is not limited thereto.

[0097] A part of the first semiconductor layer 121 can be disposed to protrude outward from the second semiconductor layer 123. The top surface of the first semiconductor layer 121 can be formed by a part that overlaps the bottom surface of the second semiconductor layer 123 and a part disposed outside the bottom surface of the second semiconductor layer 123. The light-emitting diode LED can be a lateral light-emitting diode LED. However, the sizes and shapes of the first semiconductor layer 121 and the second semiconductor layer 123 can be modified in various forms, but are not limited thereto. In the present disclosure, the top surface of an element can also be referred to as the upper surface of such an element, and the bottom surface of an element can also be referred to as the lower surface of such an element, and vice versa.

[0098] For example, referring to Figure 3, the second semiconductor layer 123 is disposed in the middle of the upper surface (e.g., the top surface) of the first semiconductor layer 121 such that the entire second semiconductor layer 123 can overlap with the first semiconductor layer 121. The second semiconductor layer 123 is disposed inside the first semiconductor layer 121 and the edge of the second semiconductor layer 123 can be disposed inside the edge of the first semiconductor layer 121. The first semiconductor layer 121 can protrude from the entire edge of the second semiconductor layer 123 to the outside of the second semiconductor layer 123. The first semiconductor layer 121 can protrude outward from the second semiconductor layer 123 in all directions.

[0099] Referring to Figure 4 , the first semiconductor layer 121 can protrude outward from the second semiconductor layer 123 in some directions. The first semiconductor layer 121 can protrude from a part of the edge of the second semiconductor layer 123 to the outside of the second semiconductor layer 123. A part of the first semiconductor layer 121 can protrude outward from the second semiconductor layer 123 in a specific direction.

[0100] The light-emitting layer 122 can be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light.

[0101] The light-emitting layer 122 can be formed of a single layer or a multi-quantum well (MQW) structure, and for example, can be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0102] The first electrode 124 can be disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with an n-type impurity, and the first electrode 124 can be a cathode. The first electrode 124 can be disposed on the top surface of the first semiconductor layer 121 that is exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 is disposed along the periphery of the top surface of the first semiconductor layer 121 and can have an annular shape in a plan view. The first electrode 124 can be constructed of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0103] The second electrode 125 may be disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. At this time, the second semiconductor layer 123 is disposed on the first semiconductor layer 121 such that the second electrode 125 disposed on the top surface of the second semiconductor layer 123 may be disposed higher than the first electrode 124 disposed on the top surface of the first semiconductor layer 121. The second electrode 125 is an electrode that electrically connects the power supply line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be constructed of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof), but is not limited thereto.

[0104] Next, a passivation film 126 may be disposed. The passivation film 126 surrounds the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. In the passivation film 126, contact holes exposing the first electrode 124 and the second electrode 125 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 124 and the second electrode 125 to be formed later, respectively.

[0105] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the light-emitting diodes LED disposed in different sub-pixels SP are respectively constructed in different shapes to distinguish the plurality of light-emitting diodes LED. Therefore, when self-assembling the light-emitting diodes LED, the plurality of light-emitting diodes LED are formed in different shapes to self-assemble at positions corresponding to each of the plurality of sub-pixels SP.

[0106] In addition, the present disclosure is not limited thereto, and the light-emitting diodes LED may have the same size or shape. For example, the light-emitting diodes LED are transferred to a separate transfer substrate instead of the self-assembly method to be disposed at positions corresponding to the plurality of sub-pixels SP.

[0107] The first planarization layer 117a may be disposed on the adhesive layer 116. The first planarization layer 117a is disposed to surround a part of the side surfaces of the plurality of light-emitting diodes LED to fix and protect the plurality of light-emitting diodes LED.

[0108] For example, the first planarization layer 117a may be arranged to surround the passivation film 126 disposed on the lower edge of the light-emitting diode LED. Accordingly, short-circuit defects of the first connection electrode CE1 due to tearing of the passivation film 126 can be suppressed. For example, during the process of separating the wafer and the light-emitting diode LED, a part of the passivation film 126 may be torn at the lower edge of the light-emitting diode LED. Accordingly, a part of the first semiconductor layer 121 at the lower edge of the light-emitting diode LED may be exposed through the torn passivation film 126. Accordingly, steps may be caused at the lower edge of the light-emitting diode LED through the torn passivation film 126. At this time, when the first connection electrode CE1 is arranged to surround the side surface of the passivation film 126, the first connection electrode CE1 may be short-circuited due to the steps caused by the torn passivation film 126.

[0109] Accordingly, before placing the first connection electrode CE1, the first planarization layer 117a is arranged to surround the lower edge of the light-emitting diode LED, such that the lower edge of the light-emitting diode LED may be spaced apart from the first connection electrode CE1. Accordingly, even if an undercut (UC) structure caused by the torn passivation film 126 is formed at the lower edge of the light-emitting diode LED, the first planarization layer 117a also contacts at least a part of the side surface of the light-emitting diode LED to be filled in the undercut (UC) structure. Accordingly, short-circuit defects of the first connection electrode CE1 due to the undercut (UC) structure can be minimized or reduced.

[0110] The first planarization layer 117a may be constructed of a single layer or a double layer, and for example, may be formed of a photoresist or an acrylic organic material, but is not limited thereto.

[0111] In addition, the first planarization layer 117a may be lower than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a may be adjusted by performing an ashing process. For example, after applying a material layer of the first planarization layer 117a to cover the light-emitting diode LED, an ashing process is performed to reduce the total thickness of the material layer of the first planarization layer 117a, such that the height of the first planarization layer 117a is formed to be lower than the height of the first electrode 124, but the present disclosure is not limited thereto. For example, the first planarization layer 117a may have a height lower than or equal to the height of the first electrode 124, as long as the first electrode 124 is exposed through the first planarization layer 117a. Accordingly, the first planarization layer 117a may expose the first electrode 124. Accordingly, the first connection electrode CE1 disposed on the first planarization layer 117a can be easily connected to the first electrode 124 without a separate contact hole.

[0112] The first connection electrode CE1 can be disposed on the first planarization layer 117a. The first connection electrode CE1 is an electrode disposed in each of the plurality of sub-pixels SP to electrically connect the light-emitting diode LED and the driving transistor DT. The first connection electrode CE1 can be connected to the first reflective electrode RE1 through a contact hole formed in the first planarization layer 117a and the bonding layer 116. Therefore, the first connection electrode CE1 can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflective electrode RE1. For example, the first connection electrode CE1 can connect the first electrode 124 of the light-emitting diode LED to the source electrode SE of the driving transistor DT, but is not limited thereto.

[0113] In addition, the first connection electrode CE1 can be formed by placing a material layer of the first connection electrode CE1 to cover the light-emitting diode LED, and then locally removing such a material layer provided on a part of the side surface and the top surface of the second semiconductor layer 123 and the material layer of the first connection electrode CE1 provided on the second electrode 125. For example, after applying a photoresist on the light-emitting diode LED, the photoresist applied on the top surface of the second electrode 125 and a part of the top surface and the side surface of the second semiconductor layer 123 is removed to expose the second electrode 125. Therefore, only the part of the material layer of the first connection electrode CE1 provided on the top surface of the second electrode 125 and a part of the side surface and the top surface of the second semiconductor layer 123 can be exposed. In addition, the exposed material layer of the first connection electrode CE1 is removed by an ashing process to form the first connection electrode CE1, but is not limited thereto.

[0114] The second planarization layer 117b can be disposed on the first planarization layer 117a and the plurality of first connection electrodes CE1. The second planarization layer 117b, together with the first planarization layer 117a, planarizes the upper part of the substrate 110 in which the light-emitting diode LED is disposed, and can fix the light-emitting diode LED to the substrate 110 together with the bonding layer 116.

[0115] In addition, the second planarization layer 117b is disposed to cover the first connection electrode CE1 to separate the first connection electrode CE1 from the second connection electrode CE2. Therefore, short-circuit defects between the first connection electrode CE1 and the second connection electrode CE2 can be suppressed.

[0116] For example, only the second planarization layer 117b can be disposed between the first connection electrode CE1 and the second connection electrode CE2. The second planarization layer 117b can be constructed of a single layer, and can be formed of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0117] The second connection electrode CE2 may be disposed on the second planarization layer 117b. The second connection electrode CE2 is an electrode for electrically connecting the light-emitting diode LED and the power supply line VDD. The second connection electrode CE2 may be connected to the second reflective electrode RE2 through contact holes formed in the second planarization layer 117b, the first planarization layer 117a, and the adhesive layer 116. Accordingly, the second connection electrode CE2 may be electrically connected to the power supply line VDD through the second reflective electrode RE2. For example, the second connection electrode CE2 may connect the second electrode 125 of the light-emitting diode LED to the power supply line VDD, but is not limited thereto.

[0118] The bank 118 may be disposed on the second planarization layer 117b and the second connection electrode CE2. The bank 118 is disposed so as not to overlap with the light-emitting diode LED to define a light-emitting region. For example, the bank 118 covers the edges of the second connection electrode CE2 connected to each light-emitting diode LED to define a light-emitting region. For example, the bank 118 may divide a plurality of sub-pixels SP. The bank 118 may be formed of an insulating material to insulate the second connection electrodes CE2 of adjacent sub-pixels SP from each other. In addition, the bank 118 may include a black component having a high light absorption rate, or may be configured as a black bank to suppress color mixing between adjacent sub-pixels SP. For example, the bank 118 may be formed of a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin, but is not limited thereto.

[0119] The third planarization layer 119 may be disposed on the second planarization layer 117b and the bank 118. The third planarization layer 119 is disposed to cover the top surface of the light-emitting diode LED to planarize the upper portion of the substrate 110 on which the light-emitting diode LED is disposed, and to fix and protect the light-emitting diode LED. The third planarization layer 119 may be configured by a single layer or a double layer, and may be formed of, for example, a photoresist or an acrylic organic material, but is not limited thereto.

[0120] For example, when manufacturing a display device, light-emitting diodes are grown on a wafer and then separated from the wafer to be transferred onto an adhesive layer. At this time, during the process of separating the wafer and the light-emitting diodes, a part of the lower edge of the light-emitting diode may be torn. For example, when the light-emitting diodes are separated from the wafer, a part of the lower edge of the passivation film of the light-emitting diode may be torn, such that a part of the semiconductor layer may be exposed. Accordingly, a step may be generated near the torn area of the passivation film. At this time, when the first connection electrode is directly formed to surround the side surface of the passivation film, due to the step near the torn area of the passivation film, a short-circuit defect between the first connection electrode and the exposed semiconductor layer may occur.

[0121] In addition, during the process of placing or transferring a plurality of light-emitting diodes onto a substrate, some of the light-emitting diodes may be misaligned or mispositioned. At this time, when subsequent processes are performed in a state where some of the light-emitting diodes are misaligned or mispositioned, a short-circuit defect between electrodes may occur.

[0122] For example, when the light-emitting diodes are misaligned such that the same electrode is connected to the first electrode and the second electrode of the light-emitting diode, or the electrodes connected to the first electrode and the second electrode of the light-emitting diode are not separately arranged to overlap, resulting in a short-circuit defect, the light-emitting diodes may not emit light normally.

[0123] In the display device 100 according to an exemplary embodiment of the present disclosure, the first connection electrode CE1 connected to the first electrode 124 of the light-emitting diode LED may be disposed on the first planarization layer 117a. For example, the first planarization layer 117a may be disposed before placing the first connection electrode CE1. The first planarization layer 117a may be disposed to surround a part of the side surface of the light-emitting diode LED, for example, the lower edge portion. Therefore, even during the processing process, when the passivation film 126 in the lower edge portion of the light-emitting diode LED is torn to cause a step in the nearby area, the first planarization layer 117a may fill the torn area of the passivation film 126. For example, the first planarization layer 117a is disposed to surround the lower edge portion of the light-emitting diode LED to separate the first connection electrode CE1 from the torn area of the passivation film 126. Therefore, the first planarization layer 117a contacts the torn area of the passivation film 126 to minimize or reduce a short-circuit defect caused by a step between the torn area of the passivation film 126 and the surrounding area.

[0124] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrode 124 of the light-emitting diode LED are self-aligned for connection. For example, the material layer of the first planarization layer 117a may be disposed to surround the light-emitting diode LED. Next, the material layer of the first planarization layer 117a is subjected to an ashing process to expose the first electrode 124. Next, the material layer of the first connection electrode CE1 may be disposed on the first planarization layer 117a. At this time, a photoresist is applied to the material layer of the first connection electrode CE1, and the photoresist may be removed by an ashing process until the second electrode 125 of the light-emitting diode LED is exposed. Next, the material layer of the first connection electrode CE1 exposed by the ashing process is removed so that only the material layer of the first connection electrode CE1 disposed on the first electrode 124 and the first planarization layer 117a remains to form the first connection electrode CE1. Therefore, the first connection electrode CE1 and the first electrode 124 can be self-aligned by the ashing process of the first planarization layer 117a and the photoresist without precisely aligning the positions of the first electrode 124 and the first connection electrode CE1. Therefore, short-circuit defects due to process errors can be minimized or reduced.

[0125] In addition, in the display device 100 according to an exemplary embodiment of the present disclosure, the second connection electrode CE2 of the light-emitting diode LED and the second semiconductor layer 123 are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layer 123 and the second electrode 125 of the light-emitting diode LED to expose only the second semiconductor layer 123 and the second electrode 125 of the light-emitting diode LED. In this case, even if the second connection electrode CE2 is formed by forming and patterning the material layer of the second connection electrode CE2 on the front surface of the substrate 110 including the second planarization layer 117b, the second connection electrode CE2 only contacts the top surface of the second electrode 125 exposed from the second planarization layer 117b. In addition, the second connection electrode CE2 may be spaced apart from the first connection electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121 disposed below the second planarization layer 117b. Therefore, the second connection electrode CE2 only contacts the top surface of the second electrode 125. Therefore, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layer 121 and the first connection electrode CE1 to ensure a process margin. Therefore, the second connection electrode CE2 and the first electrode 124 can be self-aligned by the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrode 125 and the second connection electrode CE2. Therefore, short-circuit defects between the first connection electrode CE1 and the second connection electrode CE2 due to process errors can be minimized or reduced.

[0126] Figure 5is a schematic enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 6 is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. In Figure 5 only the light-emitting element LED, the first connection electrode CE1, and the second connection electrode CE2 among various structures of the display device are illustrated. Due to the actual structure, the first connection electrode CE1 and the second connection electrode CE2 are disposed on the light-emitting diode LED, but for convenience of description, the light-emitting diode LED is illustrated by a solid line. In addition, for convenience of description, the light-emitting layers 222, 232, and 242 are not illustrated among the structures of the light-emitting diode LED. In Figure 6 a cross-sectional view of the first sub-pixel SP1 is illustrated. In addition to the light-emitting diode LED, the first connection electrode CE1, and the second connection electrode CE2, Figure 5 and Figure 6 the other structures of the display device 200 are substantially the same as the other structures of the display device 100 in Figures 1 to 4 so redundant description will be omitted. In addition, in Figure 5 and Figure 6 as Figure 3 illustrated, an example is illustrated in which the light-emitting diode LED includes two first electrodes 224, 234, and 244, and among other examples, an example is specified in which the light-emitting diode LEDs disposed in different sub-pixels SP are configured with different sizes and shapes.

[0127] First, referring to Figure 5 , the display panel PN includes a plurality of pixels PX formed of a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode LED and a pixel circuit to emit light independently. One pixel PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, one pixel PX may include one first sub-pixel SP1, one second sub-pixel SP2, and one third sub-pixel SP3. At this time, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but they are not limited thereto.

[0128] Multiple light-emitting diodes ED can be disposed in multiple sub-pixels SP. Specifically, the multiple light-emitting diodes LED include a first light-emitting diode 220, a second light-emitting diode 230, and a third light-emitting diode 240. The first light-emitting diode 220 can be disposed in the first sub-pixel SP1, the second light-emitting diode 230 can be disposed in the second sub-pixel SP2, and the third light-emitting diode 240 can be disposed in the third sub-pixel SP3. For example, the first light-emitting diode 220 can be a red light-emitting diode, the second light-emitting diode 130 can be a green light-emitting diode, and the third light-emitting diode 240 can be a blue light-emitting diode.

[0129] In addition, the first light-emitting diode 220, the second light-emitting diode 230, and the third light-emitting diode 240 can be formed in different shapes. For example, the planar shape of the first light-emitting diode 220 can be a circular shape, and the planar shapes of the second light-emitting diode 230 and the third light-emitting diode 240 can be oval shapes. At this time, the second light-emitting diode 230 and the third light-emitting diode 240 can have different sizes. In addition, the major axis directions of the second light-emitting diode 230 and the third light-emitting diode 240 can be the same, but the present disclosure is not limited thereto.

[0130] The first light-emitting diode 220 can include a first semiconductor layer 221, a light-emitting layer 222, a second semiconductor layer 223, a first electrode 224, a second electrode 225, and a passivation film 226. At this time, the planar shape of each of the first semiconductor layer 221, the light-emitting layer 222, the second semiconductor layer 223, the first electrode 224, and the second electrode 225 can be a circular shape. Among them, the first electrode 224 is disposed along the perimeter of the first semiconductor layer 221 to form a closed-loop circular electrode. The second electrode 225 can be formed in a shape corresponding to the top surface of the second semiconductor layer 223.

[0131] The second light-emitting diode 230 may include a first semiconductor layer 231, a light-emitting layer 232, a second semiconductor layer 233, a first electrode 234, a second electrode 235, and a passivation film 236. At this time, the planar shapes of the first semiconductor layer 231, the second semiconductor layer 233, and the second electrode 235 of the second light-emitting diode 230 may be elliptical shapes. At this time, the major axis direction of the first semiconductor layer 231 may be configured to be different from the major axis direction of the second semiconductor layer 233. For example, when the first semiconductor layer 231 has an elliptical shape with a major axis in the horizontal direction, the second semiconductor layer 233 may have an elliptical shape with a major axis in the vertical direction. On the top surface of the first semiconductor layer 231, the first electrode 234 may be disposed in each of the two end portions in the major axis direction of the first semiconductor layer 231. Accordingly, the plurality of first electrodes 234 disposed on the two end portions of the first semiconductor layer 231 may be formed in a semi-circular shape. Finally, the second electrode 235 may be formed in an elliptical shape identical to the top surface of the second semiconductor layer 233.

[0132] The third light-emitting diode 240 may include a first semiconductor layer 241, a light-emitting layer 242, a second semiconductor layer 243, a first electrode 244, a second electrode 245, and a passivation film 246. At this time, the planar shapes of the first semiconductor layer 241, the second semiconductor layer 243, and the second electrode 245 of the third light-emitting diode 240 may be elliptical shapes. Different from the second light-emitting diode 230, in the third light-emitting diode 240, the major axis direction of the first semiconductor layer 241 and the major axis direction of the second semiconductor layer 243 may be configured to be the same. On the top surface of the first semiconductor layer 241, the first electrode 244 is disposed in each of the two end portions in the major axis direction of the first semiconductor layer 241, and may be formed in a semi-circular shape. The second electrode 245 may be formed in an elliptical shape identical to the top surface of the second semiconductor layer 243. For example, in the display device 200 according to another exemplary embodiment of the present disclosure, the first light-emitting diode 220, the second light-emitting diode 230, and the third light-emitting diode 240 are configured to have different shapes, respectively, to distinguish the plurality of light-emitting diodes LEDs. For example, when self-assembling the light-emitting diodes LEDs, the plurality of light-emitting diodes LEDs are formed to have different shapes to self-assemble at positions corresponding to each of the plurality of sub-pixels SP. However, the shapes of the plurality of light-emitting diodes LEDs are exemplary, and thus it is not limited thereto.

[0133] Referring to Figure 5 and Figure 6, a plurality of first connection electrodes CE1 and a plurality of second connection electrodes CE2 may be provided on a plurality of light emitting diodes LED. The first connection electrode CE1 may include a plurality of first sub - electrodes CE1a arranged to be spaced apart from each other and a first base electrode CE1b connected to the plurality of first sub - electrodes CE1a. Similarly, the second connection electrode CE2 may include a plurality of second sub - electrodes CE2a arranged to be spaced apart from each other and a second base electrode CE2b connected to the plurality of second sub - electrodes CE2a.

[0134] Specifically, the plurality of first sub - electrodes CE1a may be connected to the first electrodes 224, 234, and 244 of the plurality of light emitting diodes LED, and the plurality of second sub - electrodes CE2a may be connected to the second electrodes 225, 235, and 245 of the plurality of light emitting diodes LED. At this time, the plurality of first sub - electrodes CE1a and the plurality of second sub - electrodes CE2a may be alternately arranged in a plane to minimize or reduce short - circuit defects. Therefore, the plurality of first sub - electrodes CE1a and the plurality of second sub - electrodes CE2a may be arranged in parallel in a plane. For example, the plurality of first sub - electrodes CE1a and the plurality of second sub - electrodes CE2a may be arranged parallel to the long - axis direction of the second light emitting diode 230 and the third light emitting diode 240, but is not limited thereto.

[0135] At this time, referring to Figure 6 , the width t1 of the plurality of first sub - electrodes CE1a may be equal to or less than the interval t4 between the plurality of second sub - electrodes CE2a such that the plurality of second sub - electrodes CE2a and the plurality of first sub - electrodes CE1a do not overlap. Similarly, the width t3 of the plurality of second sub - electrodes CE2a may be equal to or less than the interval t2 between the plurality of first sub - electrodes CE1a. In addition, considering the size and shape of the light emitting diode LED or the interval between the first electrodes 224, 234, and 244 and the second electrodes 225, 235, and 245, the width t1 of the plurality of first sub - electrodes CE1a or the interval t4 between the plurality of second sub - electrodes CE2a may be designed in various forms.

[0136] The first connection electrode CE1 and the second connection electrode CE2 may be formed of the same conductive material, and for example, may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0137] Hereinafter, with reference to Figures 7A to 7F a manufacturing method of a display device according to another exemplary embodiment of the present disclosure will be described in detail.

[0138] Figures 7A to 7F is a process diagram for explaining a manufacturing method of a display device according to another exemplary embodiment of the present disclosure.

[0139] First, referring to Figure 7A, a process of etching a part of the bonding layer 116 and the first planarization layer 117a to form a contact hole can be performed. The contact hole formed in this process is a contact hole that exposes the first reflective electrode RE1.

[0140] Next, referring to Figure 7B , the first layer ML1 can be disposed on the first planarization layer 117a and the light-emitting diode LED. The first layer ML1 is patterned through subsequent processes to become a plurality of first sub-electrodes CE1a.

[0141] Next, referring to Figure 7C , a process of patterning the first layer ML1 to form an initial first sub-electrode CE1a′ can be performed.

[0142] Specifically, a process of locally applying a photoresist on the first layer ML1, a process of selectively exposing and developing the photoresist, and a process of wet-etching the first layer ML1 are performed to form the initial first sub-electrode CE1a′. Therefore, the initial first sub-electrode CE1a′ can be disposed on the first planarization layer 117a, the first electrodes 224, 234, and 244, and the second electrodes 225, 235, and 245 to be spaced apart from each other.

[0143] Next, referring to Figure 7D , a process of removing the initial first sub-electrode CE1a′ disposed on the second electrodes 225, 235, and 245 to form the first sub-electrode CE1a can be performed.

[0144] Specifically, after applying a photoresist on the entire surface to cover the top surface of the light-emitting diode LED, only the photoresist applied on the second electrodes 225, 235, and 245 undergoes an ashing process to be removed. For example, the photoresist is ashed to expose only the initial first sub-electrode CE1a′ disposed on the second electrodes 225, 235, and 245. Thereafter, the initial first sub-electrode CE1a′ disposed on the second electrodes 225, 235, and 245 can be removed through a wet-etching process.

[0145] Therefore, the portion covered by the photoresist, for example, the initial first sub-electrode CE1a′ disposed only on the first planarization layer 117a and the first electrode 124 can become the first sub-electrode CE1a. For example, the first sub-electrode CE1a of the first connection electrode CE1 is self-aligned with the first electrode 124 through the ashing process of the first planarization layer 117a and the photoresist to minimize or reduce short-circuit defects due to process errors.

[0146] Next, referring to Figure 7E , the second planarization layer 117b and the second layer ML2 can be sequentially disposed on the light-emitting diode LED and the first planarization layer 117a.

[0147] Specifically, the second planarization layer 117b may be set to expose the top surface of the light-emitting diode LED. For example, after applying a material layer of the second planarization layer 117b to cover the top surface of the light-emitting diode LED, the material layer of the second planarization layer 117b applied on the second electrodes 225, 235, and 245 may be locally ashed and removed. Next, a dry etching process for forming a contact hole exposing the second reflective electrode RE2 may be performed. Next, a second layer ML2 may be provided on the second planarization layer 117b and the contact hole. The second layer ML2 is patterned through subsequent processes to become a plurality of second sub-electrodes CE2a. Finally, referring to Figure 7F , through the patterning process of the second layer ML2, a plurality of second sub-electrodes CE2a may be formed.

[0148] Specifically, patterning may be performed through a process of exposing a photoresist provided on the second layer ML2 and a process of wet etching the second layer ML2.

[0149] In addition, the second layer ML2 is provided and patterned on the front surface of the substrate 110 including the second planarization layer 117b to form a plurality of second sub-electrodes CE2a of the second connection electrode CE2. However, even in this case, the plurality of second sub-electrodes CE2a may only contact the top surface of the second electrode 125 exposed from the second planarization layer 117b, and may be spaced apart from the first connection electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121 provided below the second planarization layer 117b. Therefore, the plurality of second sub-electrodes CE2a may only contact the top surface of the second electrode 125. Therefore, during the formation of the plurality of second sub-electrodes CE2a, there is no need to consider the positions of the first semiconductor layer 121 and the plurality of first sub-electrodes CE1a to ensure a process margin. For example, the light-emitting diode LED and the plurality of second sub-electrodes CE2a are self-aligned through an ashing process to minimize or reduce short-circuit defects due to process errors.

[0150] Next, a bank 118 and a third planarization layer 119 are provided on the plurality of second sub-electrodes CE2a and the second planarization layer 117b to complete the manufacturing process of the display device 200.

[0151] Figure 8 is a diagram for explaining the effects of the first connection electrode and the second connection electrode of a display device according to another exemplary embodiment of the present disclosure. In Figure 8 , for ease of description, only a part of the first planarization layer 117a, the second planarization layer 117b, and the light-emitting diode LED is enlarged for illustration. Figure 8FIG. is a diagram for explaining the principle of suppressing a short - circuit defect between a first connection electrode CE1 and a second connection electrode CE2, and assumes a case where a first sub - electrode CE1a of the first connection electrode CE1 is disposed on side surfaces of second semiconductor layers 223, 233, and 243.

[0152] Referring together to Figure 7E and Figure 8 In region A, the first sub - electrode CE1a on the side surfaces of the second semiconductor layers 223, 233, and 243 may not be removed. Thus, during a processing step, the first sub - electrode CE1a and the second layer ML2 may come into contact with each other. At this time, the second layer ML2 is patterned to be alternately disposed with a plurality of first sub - electrodes CE1a to suppress a short - circuit defect. For example, the second layer ML2 disposed in region A is removed by wet etching so that the first sub - electrode CE1a is insulated from the second layer ML2. At this time, the first sub - electrode CE1a has been crystallized by a heat treatment process of the second planarization layer 117b, such that even when the patterning process of the second layer ML2 is performed, the first sub - electrode CE1a can remain unetched. For example, even if a process error occurs, a plurality of second sub - electrodes CE2a are patterned to be spaced apart from a plurality of first sub - electrodes CE1a to suppress a short - circuit defect.

[0153] In a display device 200 according to another exemplary embodiment of the present disclosure, a first connection electrode CE1 connected to first electrodes 224, 234, and 244 of light - emitting diodes LED may be disposed on a first planarization layer 117a. For example, the first planarization layer 117a may be disposed before placing the first connection electrode CE1. Thus, even during a processing step, when a passivation film 226, 236, and 246 at a lower edge portion of the light - emitting diode LED is torn, resulting in a step with a nearby region, the first planarization layer 117a may fill in a torn region of the passivation film 226, 236, and 246. For example, the first planarization layer 117a is disposed to surround the lower edge portion of the light - emitting diode LED to separate the first connection electrode CE1 from the torn region of the passivation film 226, 236, and 246. Thus, the first planarization layer 117a contacts the torn region of the passivation film 226, 236, and 246 to minimize or reduce a short - circuit defect caused by a step between the torn region of the passivation film 226, 236, and 246 and a peripheral region.

[0154] In addition, in the display device 200 according to another exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrodes 224, 234, and 244 of the light-emitting diodes LED are self-aligned for connection. For example, the material layer of the first planarization layer 117a may be provided to surround the light-emitting diodes LED. Next, the material layer of the first planarization layer 117a is subjected to an ashing process to expose the first electrodes 224, 234, and 244. Next, the material layer of the first connection electrode CE1 may be provided on the first planarization layer 117a. At this time, a photoresist may be applied on the material layer of the first connection electrode CE1, and the photoresist may be ashed until the second electrodes 225, 235, and 245 of the light-emitting diodes LED are exposed. Next, the material layer of the first connection electrode CE1 exposed by the ashing process is removed so that only the material layer of the first connection electrode CE1 provided on the first electrode 124 and the first planarization layer 117a remains to form the first connection electrode CE1. Therefore, the first connection electrode CE1 and the first electrodes 224, 234, and 244 can be self-aligned through the ashing process of the first planarization layer 117a and the photoresist without precisely aligning the positions of the first electrodes 224, 234, and 244 and the first connection electrode CE1. Therefore, short-circuit defects due to process errors can be minimized or reduced.

[0155] In addition, in the display device 200 according to another exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED to expose only the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED. Accordingly, the second connection electrode CE2 contacts only the top surfaces of the second electrodes 225, 235, and 245 exposed from the second planarization layer 117b, and can be spaced apart from the first connection electrode CE1, the light-emitting layers 222, 232, and 242, and the first semiconductor layers 221, 231, and 241 provided under the second planarization layer 117b. Accordingly, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245. Accordingly, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layers 221, 231, and 241 and the first connection electrode CE1 to ensure a process margin. Accordingly, the second connection electrode CE2 and the second electrodes 225, 235, and 245 can be self-aligned through the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrodes 225, 235, and 245 and the second connection electrode CE2. Accordingly, short-circuit defects due to process errors can be minimized or reduced. Specifically, in the display device 200 according to another exemplary embodiment of the present disclosure, the first electrodes 224, 234, and 244 of the light-emitting diodes LED are connected to a plurality of first sub-electrodes CE1a of the first connection electrode CE1 provided on the first planarization layer 117a. In addition, the second electrodes 225, 235, and 245 are connected to a plurality of second sub-electrodes CE2a of the second connection electrode CE2 provided on the second planarization layer 117b. At this time, after the plurality of first sub-electrodes CE1a are patterned, the plurality of second sub-electrodes CE2a are patterned to be alternately arranged with the plurality of first sub-electrodes in a plane. For example, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be arranged not only to be separated in the Z-axis direction but also to not overlap in the XY plane. Accordingly, even if the light-emitting diodes LED are misaligned or mispositioned, short-circuit defects caused by the overlap of the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be minimized or reduced.

[0156] In addition, in the display device 200 according to another exemplary embodiment of the present disclosure, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 and a plurality of second sub-electrodes CE2a of the second connection electrode CE2 are arranged to be spaced apart from each other. Therefore, when a defect occurs in the light-emitting diode LED, some of the first sub-electrodes CE1a or some of the second sub-electrodes CE2a that are in contact with only the defective light-emitting diode are cut with a laser to make them dim. For example, the light-emitting diode LED can be easily repaired. It should be noted that although Figures 3 to 8 the specific arrangement and layer structure of the display device are shown, it is provided only by way of example, and the present disclosure is not limited thereto. For example, the layer structure of the display device can be changed in various ways, and if necessary, one or more of the interlayer insulating layer or the planarization layer can be omitted.

[0157] Figure 9 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. In Figure 9 , only the light-emitting element LED, the first connection electrode CE1, and the second connection electrode CE2 among various configurations of the display device 300 are illustrated. Due to the actual structure, the first connection electrode CE1 and the second connection electrode CE2 are disposed on the light-emitting diode LED, but for ease of description, the light-emitting diode LED is illustrated with a solid line. In addition, for ease of description, the light-emitting layers 222, 232, and 242 are not illustrated among the configurations of the light-emitting diode LED. Except for the placement structure of the first connection electrode CE1 and the second connection electrode CE2, Figure 9 the other components of the display device 300 are substantially the same as those in the display device 200 of Figures 5 to 8 , and thus redundant descriptions will be omitted.

[0158] Referring to Figure 9 , a plurality of first connection electrodes CE1 and a plurality of second connection electrodes CE2 can be disposed on a plurality of light-emitting diodes LED. The first connection electrode CE1 can include a plurality of first sub-electrodes CE1a arranged to be spaced apart from each other and a first base electrode CE1b connected to the plurality of first sub-electrodes CE1a. Similarly, the second connection electrode CE2 can include a plurality of second sub-electrodes CE2a arranged to be spaced apart from each other and a second base electrode CE2b connected to the plurality of second sub-electrodes CE2a.

[0159] Specifically, multiple first sub - electrodes CE1a can be connected to the first electrodes 224, 234, and 244 of multiple light - emitting diodes LED, and multiple second sub - electrodes CE2a can be connected to the second electrodes 225, 235, and 245 of multiple light - emitting diodes LED. At this time, the multiple first sub - electrodes CE1a and the multiple second sub - electrodes CE2a can be alternately arranged on a plane to minimize or reduce short - circuit defects. Therefore, the multiple first sub - electrodes CE1a and the multiple second sub - electrodes CE2a can be arranged in parallel on the plane. For example, the multiple first sub - electrodes CE1a and the multiple second sub - electrodes CE2a can be arranged perpendicular to the long - axis direction of the second light - emitting diode 230 and the third light - emitting diode 240, but not limited thereto.

[0160] In a display device 300 according to another exemplary embodiment of the present disclosure, a first connection electrode CE1 connected to the first electrodes 224, 234, and 244 of the light - emitting diode LED can be disposed on a first planarization layer 117a. For example, the first planarization layer 117a can be disposed before placing the first connection electrode CE1. Therefore, even during a processing process, when the passivation films 226, 236, and 246 in the lower - edge portion of the light - emitting diode LED are torn to result in a step with a nearby area, the first planarization layer 117a can fill the torn areas of the passivation films 226, 236, and 246. For example, the first planarization layer 117a is disposed to surround the lower - edge portion of the light - emitting diode LED to separate the first connection electrode CE1 from the torn areas of the passivation films 226, 236, and 246. Therefore, the first planarization layer 117a contacts the torn areas of the passivation films 226, 236, and 246 to minimize or reduce short - circuit defects caused by the step between the torn areas of the passivation films 226, 236, and 246 and the surrounding areas.

[0161] In addition, in the display device 300 according to another exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrodes 224, 234, and 244 of the light-emitting diodes LED are self-aligned for connection. For example, the material layer of the first planarization layer 117a may be provided to surround the light-emitting diodes LED. Next, the material layer of the first planarization layer 117a is subjected to an ashing process to expose the first electrodes 224, 234, and 244. Next, the material layer of the first connection electrode CE1 may be provided on the first planarization layer 117a. At this time, a photoresist is applied to the material layer of the first connection electrode CE1, and the photoresist may be ashed until the second electrodes 225, 235, and 245 of the light-emitting diodes LED are exposed. Next, the material layer of the first connection electrode CE1 exposed through the ashing process is removed so that only the material layer of the first connection electrode CE1 provided on the first electrodes 224, 234, and 244 and the first planarization layer 117a are left to form the first connection electrode CE1. Accordingly, the first connection electrode CE1 and the first electrodes 224, 234, and 244 may be self-aligned through the ashing process of the first planarization layer 117a and the photoresist without precisely aligning the positions of the first electrodes 224, 234, and 244 and the first connection electrode CE1. Therefore, short-circuit defects due to process errors may be minimized or reduced.

[0162] In addition, in the display device 300 according to another exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED to expose only the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED. Therefore, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245 exposed from the second planarization layer 117b, and can be spaced apart from the first connection electrode CE1, the light-emitting layers 222, 232, and 242, and the first semiconductor layers 221, 231, and 241 provided below the second planarization layer 117b. Therefore, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245. Therefore, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layers 221, 231, and 241 and the first connection electrode CE1 to ensure a process margin. Therefore, the second connection electrode CE2 and the second electrodes 225, 235, and 245 can be self-aligned by the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrodes 225, 235, and 245 with the second connection electrode CE2. Therefore, short-circuit defects due to process errors can be minimized or reduced. Specifically, in the display device 300 according to another exemplary embodiment of the present disclosure, the first electrodes 224, 234, and 244 of the light-emitting diodes LED are connected to a plurality of first sub-electrodes CE1a of the first connection electrode CE1 provided on the first planarization layer 117a. In addition, the second electrodes 225, 235, and 245 are connected to a plurality of second sub-electrodes CE2a of the second connection electrode CE2 provided on the second planarization layer 117b. At this time, after the plurality of first sub-electrodes CE1a are patterned, the plurality of second sub-electrodes CE2a are patterned to be alternately arranged with the plurality of first sub-electrodes in a plane. For example, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be arranged not only to be separated in the Z-axis direction but also to not overlap in the XY plane. Therefore, even if the light-emitting diodes LED are misaligned or mispositioned, short-circuit defects caused by the overlap of the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be minimized or reduced.

[0163] In addition, in the display device 300 according to still another exemplary embodiment of the present disclosure, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 and a plurality of second sub-electrodes CE2a of the second connection electrode CE2 are arranged to be spaced apart from each other. Therefore, when a defect occurs in the light-emitting diode LED, some of the first sub-electrodes CE1a or some of the second sub-electrodes CE2a that are in contact with only the defective light-emitting diode are cut with a laser to be darkened. For example, the light-emitting diode LED can be easily repaired.

[0164] Figure 10 is an enlarged plan view of a display device according to still another exemplary embodiment of the present disclosure. In Figure 10 only the light-emitting element LED, the first connection electrode CE1, and the second connection electrode CE2 among the various configurations of the display device 400 are illustrated. In addition, in Figure 10 in order to illustrate the effects of the first connection electrode CE1 and the second connection electrode CE2, only the portion of the first sub-pixel SP1 in which the first light-emitting diode 220 is provided is enlarged. Except for the structures of the first connection electrode CE1 and the second connection electrode CE2, Figure 10 the other components of the display device 400 are substantially the same as those in Figures 5 to 8 the display device 200, so redundant descriptions will be omitted.

[0165] Referring to Figure 10 , a plurality of first connection electrodes CE1 and a plurality of second connection electrodes CE2 may be provided on a plurality of light-emitting diodes LED. The first connection electrode CE1 may include a plurality of first sub-electrodes CE1a arranged to be spaced apart from each other and a first base electrode CE1b connected to the plurality of first sub-electrodes CE1a. Similarly, the second connection electrode CE2 may include a plurality of second sub-electrodes CE2a arranged to be spaced apart from each other and a second base electrode CE2b connected to the plurality of second sub-electrodes CE2a.

[0166] Specifically, the plurality of first sub-electrodes CE1a may be connected to the first electrodes 224, 234, and 244 of the plurality of light-emitting diodes LED, and the plurality of second sub-electrodes CE2a may be connected to the second electrodes 225, 235, and 245 of the plurality of light-emitting diodes LED. At this time, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a may be alternately arranged in a plane to minimize or reduce short-circuit defects. Therefore, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a may be arranged in parallel in a plane.

[0167] For example, like the first light-emitting diode 220 disposed in the first sub-pixel SP1, the planar shape of the light-emitting diode may be a circular shape. In this case, the plurality of first sub-electrodes CE1a of the first connection electrode CE1 disposed on the first light-emitting diode 220 may have a circular shape with an open side in a plane, but is not limited thereto. For example, the plurality of first sub-electrodes CE1a may have a shape corresponding to the shape of the first electrode 224 of the first light-emitting diode 220 so as to be easily electrically connected to the first electrode 224 of the first light-emitting diode 220.

[0168] In addition, the plurality of first base electrodes CE1b of the first connection electrode CE1 are disposed in a region where the plurality of second sub-electrodes CE2a of the second connection electrode CE2 are open to connect to the plurality of first sub-electrodes CE1a. Therefore, unlike the plurality of first sub-electrodes CE1a, the first base electrodes CE1b may have a linear shape.

[0169] One of the plurality of second sub-electrodes CE2a of the second connection electrode CE2 has a circular shape, and the remaining second sub-electrodes may have a circular shape with an open side, but is not limited thereto. For example, one of the plurality of second sub-electrodes CE2a may have a shape corresponding to the shape of the second electrode 225 of the first light-emitting diode 220 so as to be easily electrically connected to the second electrode 225 of the first light-emitting diode 220. In addition, the plurality of second sub-electrodes CE2a having a circular shape with an open side may be open on the opposite side of an open side of the plurality of first sub-electrodes CE1a of the first connection electrode CE1. For example, the plurality of second sub-electrodes CE2a having a circular shape with an open side may be disposed to face the plurality of first sub-electrodes CE1a in a plane.

[0170] In addition, the plurality of second base electrodes CE2b of the second connection electrode CE2 are disposed in a region where the plurality of first sub-electrodes CE1a are open to connect to the plurality of second sub-electrodes CE2a. Therefore, unlike the plurality of second sub-electrodes CE2a, the second base electrodes CE2b may have a linear shape.

[0171] Thus, in a display device 400 according to another exemplary embodiment of the present disclosure, a first connection electrode CE1 connected to the first electrodes 224, 234, and 244 of the light-emitting diodes LED can be disposed on the first planarization layer 117a. For example, the first planarization layer 117a can be disposed before placing the first connection electrode CE1. Thus, even during the processing, when the passivation films 226, 236, and 246 in the lower edge portions of the light-emitting diodes LED are torn to result in a step with the nearby regions, the first planarization layer 117a can fill the torn regions of the passivation films 226, 236, and 246. For example, the first planarization layer 117a is disposed to surround the lower edge portions of the light-emitting diodes LED to separate the first connection electrode CE1 from the torn regions of the passivation films 226, 236, and 246. Thus, the first planarization layer 117a contacts the torn regions of the passivation films 226, 236, and 246 to minimize or reduce short-circuit defects caused by the step between the torn regions of the passivation films 226, 236, and 246 and the surrounding regions.

[0172] Furthermore, in a display device 400 according to another exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrodes 224, 234, and 244 of the light-emitting diodes LED are self-aligned for connection. For example, a material layer of the first planarization layer 117a can be disposed to surround the light-emitting diodes LED. Next, the material layer of the first planarization layer 117a undergoes an ashing process to expose the first electrodes 224, 234, and 244. Next, a material layer of the first connection electrode CE1 can be disposed on the first planarization layer 117a. At this time, a photoresist is applied to the material layer of the first connection electrode CE1, and the photoresist can be ashed until the second electrodes 225, 235, and 245 of the light-emitting diodes LED are exposed. Next, the material layer of the first connection electrode CE1 exposed through the ashing process is removed, such that only the material layer of the first connection electrode CE1 disposed on the first electrodes 224, 234, and 244 and the first planarization layer 117a remains to form the first connection electrode CE1. Thus, the first connection electrode CE1 and the first electrodes 224, 234, and 244 can be self-aligned through the ashing processes of the first planarization layer 117a and the photoresist without precisely aligning the positions of the first electrodes 224, 234, and 244 and the first connection electrode CE1. Thus, short-circuit defects due to process errors can be minimized or reduced.

[0173] In addition, in a display device 400 according to another exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED to expose only the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED. Accordingly, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245 exposed from the second planarization layer 117b, and can be spaced apart from the first connection electrode CE1, the light-emitting layers 222, 232, and 242, and the first semiconductor layers 221, 231, and 241 provided below the second planarization layer 117b. Accordingly, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245. Accordingly, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layers 221, 231, and 241 and the first connection electrode CE1 to ensure a process margin. Accordingly, the second connection electrode CE2 and the second electrodes 225, 235, and 245 can be self-aligned through the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrodes 225, 235, and 245 and the second connection electrode CE2. Accordingly, short-circuit defects due to process errors can be minimized or reduced.

[0174] Specifically, in a display device 400 according to another exemplary embodiment of the present disclosure, the first electrodes 224, 234, and 244 of the light-emitting diodes LED are connected to a plurality of first sub-electrodes CE1a of the first connection electrode CE1 provided on the first planarization layer 117a. In addition, the second electrodes 225, 235, and 245 are connected to a plurality of second sub-electrodes CE2a of the second connection electrode CE2 provided on the second planarization layer 117b. At this time, after the plurality of first sub-electrodes CE1a are patterned, the plurality of second sub-electrodes CE2a are patterned to be alternately arranged with the plurality of first sub-electrodes in a plane. For example, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be provided not only to be separated in the Z-axis direction but also to not overlap in the XY plane. Accordingly, even if the light-emitting diodes LED are misaligned or mispositioned, short-circuit defects caused by the overlap of the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be minimized or reduced.

[0175] In addition, in a display device 400 according to another exemplary embodiment of the present disclosure, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 and a plurality of second sub-electrodes CE2a of the second connection electrode CE2 are arranged to be spaced apart from each other. Therefore, when a defect occurs in a light-emitting diode LED, some of the first sub-electrodes CE1a or some of the second sub-electrodes CE2a that are only in contact with the defective light-emitting diode are cut with a laser to make them dim. For example, the light-emitting diode LED can be easily repaired.

[0176] Specifically, in a display device 400 according to another exemplary embodiment of the present disclosure, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 and a plurality of second sub-electrodes CE2a of the second connection electrode CE2 may have a shape corresponding to a first light-emitting diode 220 having a circular planar shape. For example, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 connected to the first electrode 224 of the first light-emitting diode 220 may have a circular shape with one open side. In addition, one of a plurality of second sub-electrodes CE2a of the second connection electrode CE2 connected to the second electrode 225 of the first light-emitting diode 220 has a circular shape. Therefore, the first light-emitting diode 220 can be easily electrically connected to the first connection electrode CE1 and the second connection electrode CE2.

[0177] Figure 11 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. In Figure 11 only the light-emitting element LED, the first connection electrode CE1, and the second connection electrode CE2 among the various structures of the display device 500 are illustrated. Due to the actual structure, the first connection electrode CE1 and the second connection electrode CE2 are provided on the light-emitting diode LED, but for ease of description, the light-emitting diode LED is illustrated with a solid line. In addition, for ease of description, among the structures of the light-emitting diode LED, the light-emitting layers 222, 232, and 242 are not illustrated. Except for the placement structure of the first connection electrode CE1 and the second connection electrode CE2, Figure 11 the other components of the display device 500 of Figures 5 to 8 are substantially the same as those in the display device 200 of

[0178] Referring to Figure 11 , a plurality of first connection electrodes CE1 and a plurality of second connection electrodes CE2 may be provided on a plurality of light-emitting diodes LED. The first connection electrode CE1 may include a plurality of first sub-electrodes CE1a arranged to be spaced apart from each other and a first base electrode CE1b connected to the plurality of first sub-electrodes CE1a. Similarly, the second connection electrode CE2 may include a plurality of second sub-electrodes CE2a arranged to be spaced apart from each other and a second base electrode CE2b connected to the plurality of second sub-electrodes CE2a.

[0179] Specifically, multiple first sub-electrodes CE1a can be connected to the first electrodes 224, 234, and 244 of multiple light-emitting diodes LED, and multiple second sub-electrodes CE2a can be connected to the second electrodes 225, 235, and 245 of multiple light-emitting diodes LED. At this time, multiple first sub-electrodes CE1a and multiple second sub-electrodes CE2a can be alternately arranged on a plane to minimize or reduce short-circuit defects. Therefore, multiple first sub-electrodes CE1a and multiple second sub-electrodes CE2a can be arranged in parallel on a plane.

[0180] For example, multiple first sub-electrodes CE1a of the first connection electrode CE1 can include a first portion CE1a1 extending in a first direction on a plane and a second portion CE1a2 extending in a second direction. At this time, the first portion CE1a1 and the second portion CE1a2 can be arranged perpendicular to each other. For example, when the first direction is the x-axis direction, the second direction can be the y-axis direction. Conversely, when the first direction is the y-axis direction, the second direction can be the x-axis direction.

[0181] Similarly, multiple second sub-electrodes CE2a of the second connection electrode CE2 can include a first portion CE2a1 extending in a first direction on a plane and a second portion CE2a2 extending in a second direction. At this time, the first portion CE2a1 and the second portion CE2a2 can be arranged perpendicular to each other. Similarly, when the first direction is the x-axis direction, the second direction can be the y-axis direction. Conversely, when the first direction is the y-axis direction, the second direction can be the x-axis direction.

[0182] At this time, in order to suppress short-circuit defects caused when multiple first sub-electrodes CE1a and multiple second sub-electrodes CE2a arranged in the first direction overlap, the first portions CE1a1 of multiple first sub-electrodes CE1a and the first portions CE2a1 of multiple second sub-electrodes CE2a can be alternately arranged on a plane. Similarly, the second portions CE1a2 of multiple first sub-electrodes CE1a and the second portions CE2a2 of multiple second sub-electrodes CE2a arranged in the second direction can be alternately arranged on a plane so as not to overlap each other.

[0183] Accordingly, in the display device 500 according to another exemplary embodiment of the present disclosure, a first connection electrode CE1 connected to the first electrodes 224, 234, and 244 of the light-emitting diodes LED may be disposed on the first planarization layer 117a. For example, the first planarization layer 117a may be disposed before the first connection electrode CE1 is placed. Accordingly, even during the processing process, when the passivation films 226, 236, and 246 in the lower edge portions of the light-emitting diodes LED are torn to result in a step with the nearby regions, the first planarization layer 117a may fill the torn regions of the passivation films 226, 236, and 246. For example, the first planarization layer 117a is disposed to surround the lower edge portions of the light-emitting diodes LED to separate the first connection electrode CE1 from the torn regions of the passivation films 226, 236, and 246. Accordingly, the first planarization layer 117a contacts the torn regions of the passivation films 226, 236, and 246 to minimize or reduce short-circuit defects caused by the step between the torn regions of the passivation films 226, 236, and 246 and the peripheral regions.

[0184] In addition, in the display device 500 according to another exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrodes 224, 234, and 244 of the light-emitting diodes LED are self-aligned for connection. For example, a material layer of the first planarization layer 117a may be disposed to surround the light-emitting diodes LED. Next, the material layer of the first planarization layer 117a undergoes an ashing process to expose the first electrodes 224, 234, and 244. Next, a material layer of the first connection electrode CE1 may be disposed on the first planarization layer 117a. At this time, a photoresist is applied to the material layer of the first connection electrode CE1, and the photoresist may be ashed until the second electrodes 225, 235, and 245 of the light-emitting diodes LED are exposed. Next, the material layer of the first connection electrode CE1 exposed through the ashing process is removed such that only the material layer of the first connection electrode CE1 disposed on the first electrodes 224, 234, and 244 and the first planarization layer 117a remains to form the first connection electrode CE1. Accordingly, the first connection electrode CE1 and the first electrodes 224, 234, and 244 may be self-aligned through the ashing process of the first planarization layer 117a and the photoresist without precisely aligning the positions of the first electrodes 224, 234, and 244 and the first connection electrode CE1. Accordingly, short-circuit defects due to process errors may be minimized or reduced.

[0185] In addition, in the display device 500 according to another exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED to expose only the second semiconductor layers 223, 233, and 243 and the second electrodes 225, 235, and 245 of the light-emitting diodes LED. Accordingly, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245 exposed from the second planarization layer 117b, and can be spaced apart from the first connection electrode CE1, the light-emitting layers 222, 232, and 242, and the first semiconductor layers 221, 231, and 241 provided under the second planarization layer 117b. Accordingly, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 225, 235, and 245. Accordingly, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layers 221, 231, and 241 and the first connection electrode CE1 to ensure a process margin. Accordingly, the second connection electrode CE2 and the second electrodes 225, 235, and 245 can be self-aligned by the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrodes 225, 235, and 245 and the second connection electrode CE2. Accordingly, short-circuit defects due to process errors can be minimized or reduced.

[0186] Specifically, in the display device 500 according to another exemplary embodiment of the present disclosure, the first electrodes 224, 234, and 244 of the light-emitting diodes LED are connected to a plurality of first sub-electrodes CE1a of the first connection electrode CE1 provided on the first planarization layer 117a. In addition, the second electrodes 225, 235, and 245 are connected to a plurality of second sub-electrodes CE2a of the second connection electrode CE2 provided on the second planarization layer 117b. At this time, after the plurality of first sub-electrodes CE1a are patterned, the plurality of second sub-electrodes CE2a are patterned to be alternately provided with the plurality of first sub-electrodes CE1a in a plane. For example, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be provided not only to be separated in the Z-axis direction but also to not overlap in the XY plane. Accordingly, even if the light-emitting diodes LED are misaligned or mispositioned, short-circuit defects caused by the overlap of the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be minimized or reduced.

[0187] In addition, in a display device 500 according to another exemplary embodiment of the present disclosure, a plurality of first sub - electrodes CE1a of the first connection electrode CE1 and a plurality of second sub - electrodes CE2a of the second connection electrode CE2 are arranged to be spaced apart from each other. Accordingly, when a defect occurs in a light - emitting diode LED, some of the first sub - electrodes CE1a or some of the second sub - electrodes CE2a that are in contact with only the defective light - emitting diode are cut with a laser to be darkened. For example, the light - emitting diode LED can be easily repaired.

[0188] Figure 12 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figures 13A to 13C is a cross - sectional view of a display device according to another exemplary embodiment of the present disclosure. Specifically, Figure 13A is a diagram illustrating that a light - emitting diode LED is disposed at a correct position R without misalignment or transfer error. Figure 13B and Figure 13C is a diagram showing that the light - emitting diode LED is misaligned or mis - transferred such that the light - emitting diode is not disposed at the correct position R. Figure 14 is a cross - sectional view of a display device according to another exemplary embodiment of the present disclosure.

[0189] In Figure 12 and Figure 14 only the light - emitting element LED, the first connection electrode CE1, and the second connection electrode CE2 among various configurations of the display device 600 are illustrated. Due to the actual structure, the first connection electrode CE1 and the second connection electrode CE2 are disposed on the light - emitting diode LED, but for ease of description, the light - emitting diode LED is illustrated with a solid line. In addition, for ease of description, among the configurations of the light - emitting diode LED, the light - emitting layers 322, 332, and 342 are not illustrated. In addition, except for the shapes of the first light - emitting diode 320, the second light - emitting diode 330, and the third light - emitting diode 340, Figure 12 the display device 600 of Figure 14 and Figures 5 to 8 the display device 200 of Figure 9 the display device 300 of Figures 12 to 14 are substantially the same. Therefore, redundant descriptions will be omitted. In addition, in the display device 600 of Figure 4 as shown, an example is illustrated in which the light - emitting diode LED includes one first electrode 324, 334, or 344, and it is specified that the light - emitting diode LEDs configured in different sub - pixels SP have the same size and shape.

[0190] Referring to Figure 12 and Figure 14, multiple light-emitting diodes (LEDs) can be disposed in multiple sub-pixels (SPs). Specifically, the multiple light-emitting diodes (LEDs) include a first light-emitting diode 320, a second light-emitting diode 330, and a third light-emitting diode 340. The first light-emitting diode 320 can be disposed in the first sub-pixel SP1, the second light-emitting diode 330 can be disposed in the second sub-pixel SP2, and the third light-emitting diode 340 can be disposed in the third sub-pixel SP3. For example, the first light-emitting diode 320 can be a red light-emitting diode, the second light-emitting diode 330 can be a green light-emitting diode, and the third light-emitting diode 340 can be a blue light-emitting diode.

[0191] In addition, all of the first light-emitting diode 320, the second light-emitting diode 330, and the third light-emitting diode 340 can have a rectangular planar shape. In addition, the major axis directions of the first light-emitting diode 320, the second light-emitting diode 330, and the third light-emitting diode 340 can be the same, but the present disclosure is not limited thereto.

[0192] Referring together Figures 12 to 14 , the first light-emitting diode 320 includes a first semiconductor layer 321, a light-emitting layer 322, a second semiconductor layer 323, a first electrode 324, a second electrode 325, and a passivation film 326. At this time, the planar shape of each of the first semiconductor layer 321, the light-emitting layer 322, the second semiconductor layer 323, and the first electrode 324 can be a rectangular shape, but the planar shape of the second electrode 325 can be an oval shape. Among them, the major axis directions of the first semiconductor layer 321, the light-emitting layer 322, and the second semiconductor layer 323 can be the same as the major axis direction of the first light-emitting diode 320. In contrast, the major axis directions of the first electrode 324 and the second electrode 325 can be different from the major axis direction of the first light-emitting diode 320.

[0193] The second light-emitting diode 330 includes a first semiconductor layer 331, a light-emitting layer 332, a second semiconductor layer 333, a first electrode 334, a second electrode 335, and a passivation film 336. At this time, the planar shapes of the first semiconductor layer 331, the second semiconductor layer 333, and the second electrode 335 of the second light-emitting diode 330 can be rectangular shapes.

[0194] Among them, the major axis directions of the first semiconductor layer 331, the light-emitting layer 332, and the second semiconductor layer 333 can be the same as the major axis direction of the first light-emitting diode 320. In contrast, the major axis directions of the first electrode 334 and the second electrode 335 can be different from the major axis direction of the first light-emitting diode 320.

[0195] The third light-emitting diode 340 includes a first semiconductor layer 341, a light-emitting layer 342, a second semiconductor layer 343, a first electrode 344, a second electrode 345, and a passivation film 346. At this time, the planar shapes of the first semiconductor layer 341, the second semiconductor layer 343, and the second electrode 345 of the third light-emitting diode 340 may be rectangular shapes.

[0196] Among them, the major axis directions of the first semiconductor layer 341, the light-emitting layer 342, and the second semiconductor layer 343 may be the same as the major axis direction of the first light-emitting diode 320. In contrast, the major axis directions of the first electrode 344 and the second electrode 345 may be different from the major axis direction of the first light-emitting diode 320.

[0197] For example, in the display device 600 according to another exemplary embodiment of the present disclosure, the first light-emitting diode 320, the second light-emitting diode 330, and the third light-emitting diode 340 may have the same shape. Therefore, instead of the self-assembly method, a separate substrate is used to transfer multiple light-emitting diodes LED to set multiple light-emitting diodes LED at positions corresponding to each of the multiple sub-pixels SP. However, the shapes of the multiple light-emitting diodes LED are exemplary and thus not limited thereto.

[0198] Multiple first connection electrodes CE1 and multiple second connection electrodes CE2 may be provided on the multiple light-emitting diodes LED. The first connection electrode CE1 may include multiple first sub-electrodes CE1a arranged to be spaced apart from each other and a first base electrode CE1b connected to the multiple first sub-electrodes CE1a. Similarly, the second connection electrode CE2 may include multiple second sub-electrodes CE2a arranged to be spaced apart from each other and a second base electrode CE2b connected to the multiple second sub-electrodes CE2a.

[0199] Specifically, the multiple first sub-electrodes CE1a may be connected to the first electrodes 324, 334, and 344 of the multiple light-emitting diodes LED, and the multiple second sub-electrodes CE2a may be connected to the second electrodes 325, 335, and 345 of the multiple light-emitting diodes LED. At this time, the multiple first sub-electrodes CE1a and the multiple second sub-electrodes CE2a may be alternately arranged in a plane to minimize or reduce short-circuit defects. Therefore, the multiple first sub-electrodes CE1a and the multiple second sub-electrodes CE2a may be arranged in parallel in a plane. For example, the multiple first sub-electrodes CE1a and the multiple second sub-electrodes CE2a may be arranged parallel to the major axis direction of the first light-emitting diode 320, the second light-emitting diode 330, and the third light-emitting diode 340, but not limited thereto.

[0200] Refer to Figure 13A, the width t1 of the plurality of first sub - electrodes CE1a can be equal to or less than the interval t4 between the plurality of second sub - electrodes CE2a, such that the plurality of second sub - electrodes CE2a and the plurality of first sub - electrodes CE1a do not overlap. In addition, the width t1 of the plurality of first sub - electrodes CE1a or the interval t4 between the plurality of second sub - electrodes CE2a can be designed in various forms considering the size and shape of the light - emitting diode LED or the interval between the first electrodes 324, 334, and 344 and the second electrodes 325, 335, and 345.

[0201] The first connection electrode CE1 and the second connection electrode CE2 can be formed of the same conductive material, for example, formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but not limited thereto.

[0202] Referring to Figure 13B and Figure 13C , the light - emitting diode LED is misaligned or transferred incorrectly, and is set to deviate to the left or right from the correct position R instead of being set in the correct position R. In this case, the first sub - electrodes CE1a of the first connection electrode CE1 can also be alternately arranged in a plane with the second sub - electrodes CE2a of the second connection electrode CE2. For example, even if the light - emitting diode LED is transferred incorrectly or misaligned, after the plurality of first sub - electrodes CE1a of the first connection electrode CE1 are patterned, the plurality of second sub - electrodes CE2a of the second connection electrode CE2 are patterned so as not to overlap with the plurality of first sub - electrodes CE1a. Therefore, short - circuit defects can be minimized or reduced.

[0203] Therefore, the width t1 of the plurality of first sub - electrodes CE1a can be equal to or less than the interval t4 between the plurality of second sub - electrodes CE2a, such that the plurality of second sub - electrodes CE2a and the plurality of first sub - electrodes CE1a do not overlap. Similarly, the width t3 of the plurality of second sub - electrodes CE2a can be equal to or less than the interval t2 between the plurality of first sub - electrodes CE1a. In addition, the width t1 of the plurality of first sub - electrodes CE1a or the interval t4 between the plurality of second sub - electrodes CE2a can be designed in various forms considering the size and shape of the light - emitting diode LED or the interval between the first electrodes 324, 334, and 344 and the second electrodes 325, 335, and 345.

[0204] In display devices 600 and 700 according to another exemplary embodiment of the present disclosure, a first connection electrode CE1 connected to first electrodes 324, 334, and 344 of light-emitting diodes LED may be disposed on a first planarization layer 117a. For example, the first planarization layer 117a may be disposed before placing the first connection electrode CE1. Thus, even during a processing process, when passivation films 326, 336, and 346 in a lower edge portion of the light-emitting diode LED are torn to result in a step with a nearby region, the first planarization layer 117a may be filled in a torn region of the passivation films 326, 336, and 346. For example, the first planarization layer 117a is disposed to surround the lower edge portion of the light-emitting diode LED to separate the first connection electrode CE1 from the torn region of the passivation films 326, 336, and 346. Thus, the first connection electrode CE1 contacts the torn region of the passivation films 326, 336, and 346 to minimize or reduce a short-circuit defect caused by a step between the torn region of the passivation films 326, 336, and 346 and a peripheral region.

[0205] Furthermore, in display devices 600 and 700 according to another exemplary embodiment of the present disclosure, the first connection electrode CE1 and the first electrodes 324, 334, and 344 of the light-emitting diode LED are self-aligned for connection. For example, a material layer of the first planarization layer 117a may be disposed to surround the light-emitting diode LED. Next, the material layer of the first planarization layer 117a undergoes an ashing process to expose the first electrodes 324, 334, and 344. Next, a material layer of the first connection electrode CE1 may be disposed on the first planarization layer 117a. At this time, a photoresist is applied on the material layer of the first connection electrode CE1, and the photoresist may be ashed until the second electrodes 325, 335, and 345 of the light-emitting diode LED are exposed. Next, the material layer of the first connection electrode CE1 exposed through the ashing process is removed, such that only the material layer of the first connection electrode CE1 disposed on the first electrodes 324, 334, and 344 and the first planarization layer 117a remains to form the first connection electrode CE1. Thus, the first connection electrode CE1 and the first electrodes 324, 334, and 344 may be self-aligned through the ashing process of the first planarization layer 117a and the photoresist, without precisely aligning the positions of the first electrodes 324, 334, and 344 and the first connection electrode CE1. Thus, a short-circuit defect due to a process error may be minimized or reduced.

[0206] In addition, in display devices 600 and 700 according to another exemplary embodiment of the present disclosure, the second connection electrode CE2 and the second electrodes 325, 335, and 345 of the light-emitting diodes LED are self-aligned for connection. For example, an ashing process is performed on the second planarization layer 117b covering the second semiconductor layers 323, 333, and 343 and the second electrodes 325, 335, and 345 of the light-emitting diodes LED to expose only the second semiconductor layers 323, 333, and 343 and the second electrodes 325, 335, and 345 of the light-emitting diodes LED. Therefore, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 325, 335, and 345 exposed from the second planarization layer 117b, and can be spaced apart from the first connection electrode CE1, the light-emitting layers 322, 332, and 342, and the first semiconductor layers 321, 331, and 341 provided below the second planarization layer 117b. Therefore, the second connection electrode CE2 can contact only the top surfaces of the second electrodes 325, 335, and 345. Therefore, during the formation of the second connection electrode CE2, there is no need to consider the positions of the first semiconductor layers 321, 331, and 341 and the first connection electrode CE1 to ensure a process margin. Therefore, the second connection electrode CE2 and the second electrodes 325, 335, and 345 can be self-aligned by the ashing process of the second planarization layer 117b without precisely aligning the positions of the second electrodes 325, 335, and 345 and the second connection electrode CE2. Therefore, short-circuit defects due to process errors can be minimized or reduced.

[0207] Specifically, in display devices 600 and 700 according to another exemplary embodiment of the present disclosure, the light-emitting diodes LED can have the same size or shape. For example, the light-emitting diodes LED are transferred to a separate transfer substrate instead of a self-assembly method to be disposed at positions corresponding to a plurality of sub-pixels SP. In addition, the first electrodes 324, 334, and 344 of the light-emitting diodes LED are connected to a plurality of first sub-electrodes CE1a of the first connection electrode CE1 provided on the first planarization layer 117a. In addition, the second electrodes 325, 335, and 345 are connected to a plurality of second sub-electrodes CE2a of the second connection electrode CE2 provided on the second planarization layer 117b. At this time, after the plurality of first sub-electrodes CE1a are patterned, the plurality of second sub-electrodes CE2a are patterned to be alternately disposed with the plurality of first sub-electrodes in a plane. For example, the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be disposed not only to be separated in the Z-axis direction but also to not overlap in the XY plane. Therefore, even if the light-emitting diodes LED are misaligned or disposed incorrectly, short-circuit defects caused by the overlap of the plurality of first sub-electrodes CE1a and the plurality of second sub-electrodes CE2a can be minimized or reduced.

[0208] In addition, in display devices 600 and 700 according to another exemplary embodiment of the present disclosure, a plurality of first sub-electrodes CE1a of the first connection electrode CE1 and a plurality of second sub-electrodes CE2a of the second connection electrode CE2 are arranged to be spaced apart from each other. Therefore, when a defect occurs in a light-emitting diode LED, some of the first sub-electrodes CE1a or some of the second sub-electrodes CE2a that are in contact with only the defective light-emitting diode are cut with a laser to make them dim. For example, the light-emitting diode LED can be easily repaired.

[0209] The exemplary embodiment of the present disclosure can also be described as follows:

[0210] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of sub-pixels; a plurality of light-emitting diodes disposed on the substrate among the plurality of sub-pixels, and each including a first electrode and a second electrode disposed at a higher position than the first electrode; a first planarization layer disposed on the substrate to surround a part of the side surfaces of the plurality of light-emitting diodes; a plurality of first connection electrodes disposed on the first planarization layer and respectively connected to the first electrodes of the plurality of light-emitting diodes; a second planarization layer disposed on the first planarization layer and the plurality of first connection electrodes; and a plurality of second connection electrodes disposed on the second planarization layer and respectively connected to the second electrodes of the plurality of light-emitting diodes.

[0211] The height of the upper surface of the first planarization layer may be lower than the height of the upper surface of the first electrode.

[0212] A part of the side surfaces of the plurality of light-emitting diodes may be in contact with the first planarization layer.

[0213] The second planarization layer may be disposed between the plurality of first connection electrodes and the plurality of second connection electrodes and may be disposed to completely cover the plurality of first connection electrodes.

[0214] The display device may further include: a bank disposed on the second planarization layer so as not to overlap with the plurality of light-emitting diodes; and a third planarization layer disposed on the second planarization layer and the bank.

[0215] The plurality of first connection electrodes may include a plurality of first sub-electrodes spaced apart from each other. The plurality of second connection electrodes may include a plurality of second sub-electrodes spaced apart from each other. The plurality of first sub-electrodes and the plurality of second sub-electrodes may be alternately arranged in a plane.

[0216] The plurality of first connection electrodes may further include a first base electrode connected to the plurality of first sub-electrodes. The plurality of second connection electrodes may further include a second base electrode connected to the plurality of second sub-electrodes.

[0217] The width of each of the plurality of first sub - electrodes may be equal to or less than the interval between the plurality of second sub - electrodes. The width of each of the plurality of second sub - electrodes may be equal to or less than the interval between the plurality of first sub - electrodes.

[0218] The plurality of first sub - electrodes and the plurality of second sub - electrodes may be arranged parallel to each other on a plane.

[0219] The plurality of light - emitting diodes may include a first light - emitting diode having a circular planar shape, a second light - emitting diode having an elliptical planar shape, and a third light - emitting diode having an elliptical planar shape, wherein the size of the elliptical planar shape of the third light - emitting diode is different from the size of the elliptical planar shape of the second light - emitting diode. The major - axis directions of the second light - emitting diode and the third light - emitting diode may be the same. The plurality of first sub - electrodes and the plurality of second sub - electrodes may be arranged parallel to the major - axis directions of the second light - emitting diode and the third light - emitting diode.

[0220] The plurality of light - emitting diodes may include a first light - emitting diode having a circular planar shape, a second light - emitting diode having an elliptical planar shape, and a third light - emitting diode having an elliptical planar shape, wherein the size of the elliptical planar shape of the third light - emitting diode is different from the size of the elliptical planar shape of the second light - emitting diode. The major - axis directions of the second light - emitting diode and the third light - emitting diode may be the same. The plurality of first sub - electrodes and the plurality of second sub - electrodes may be arranged perpendicular to the major - axis directions of the second light - emitting diode and the third light - emitting diode.

[0221] The plurality of light - emitting diodes may include a first light - emitting diode having a circular planar shape. The plurality of first sub - electrodes connected to the first light - emitting diode may have a circular shape with an open side on a plane. One of the plurality of second sub - electrodes connected to the first light - emitting diode may have a circular shape, and the other second sub - electrodes may have a circular shape with an open side on the other side opposite to the open side of the plurality of first sub - electrodes.

[0222] The plurality of first connection electrodes may further include a first base electrode, which is connected to the plurality of first sub - electrodes and is arranged in the open area of the plurality of second sub - electrodes. The plurality of second connection electrodes may further include a second base electrode, which is connected to the plurality of second sub - electrodes and is arranged in the open area of the plurality of first sub - electrodes.

[0223] The plurality of first sub - electrodes may include a first part extending in a first direction on a plane and a second part extending in a second direction different from the first direction. The plurality of second sub - electrodes may include a first part extending in the first direction and a second part extending in the second direction.

[0224] The first portions of the plurality of first sub - electrodes and the first portions of the plurality of second sub - electrodes may be alternately arranged in a plane. The second portions of the plurality of first sub - electrodes and the second portions of the plurality of second sub - electrodes may be alternately arranged in a plane.

[0225] The plurality of first sub - electrodes and the plurality of second sub - electrodes may not overlap each other in a plane.

[0226] The display device may further include: a plurality of driving transistors disposed on the substrate; and a power supply line disposed on the substrate. The plurality of first connection electrodes may electrically connect the plurality of driving transistors and the first electrode, and the plurality of second connection electrodes may electrically connect the power supply line and the second electrode.

[0227] The height of the upper surface of the second planarization layer may be lower than the height of the upper surface of the second electrode.

[0228] Each of the plurality of light - emitting diodes may further include a first semiconductor layer and a passivation film. The first semiconductor layer is disposed under and in contact with the first electrode, and the passivation film is disposed to surround the first semiconductor layer. The first planarization layer may be disposed to completely cover the lower end of the passivation film.

[0229] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of sub - pixels, each of the plurality of sub - pixels including a light - emitting diode, wherein the light - emitting diode includes a first electrode and a second electrode disposed at a higher position than the first electrode; a first connection electrode connected to the first electrode; a second connection electrode connected to the second electrode; and a planarization layer disposed between the first connection electrode and the second connection electrode. The first connection electrode may include a plurality of first sub - electrodes spaced apart from each other. The second connection electrode may include a plurality of second sub - electrodes spaced apart from each other. The plurality of first sub - electrodes and the plurality of second sub - electrodes may be alternately arranged in a plane.

[0230] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above - mentioned exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0231] Cross - reference to related applications

[0232] This application claims the benefit and priority of Korean Patent Application No. 10-2023-0177675, filed on December 8, 2023, and Korean Patent Application No. 10-2024-0093097, filed on July 15, 2024, the entire disclosures of which are incorporated herein by reference for all purposes.

Claims

1. A display device, comprising: a substrate, the substrate comprising a plurality of sub-pixels; a plurality of light emitting diodes, the plurality of light emitting diodes being disposed on the substrate in the plurality of sub-pixels and each comprising a first electrode and a second electrode disposed at a higher position than the first electrode; a first planarization layer, the first planarization layer being disposed on the substrate so as to surround a portion of a side surface of the plurality of light emitting diodes; a plurality of first connection electrodes, the plurality of first connection electrodes being disposed on the first planarization layer and respectively connected to the first electrodes of the plurality of light emitting diodes; a second planarization layer, the second planarization layer being disposed on the first planarization layer and the plurality of first connection electrodes; as well as A plurality of second connection electrodes are disposed on the second planarization layer and are respectively connected to the second electrodes of the plurality of light emitting diodes.

2. The display device according to claim 1, wherein: A height of an upper surface of the first planarization layer is lower than a height of an upper surface of the first electrode.

3. The display device according to claim 1, wherein: The portion of the side surfaces of the plurality of light emitting diodes is in contact with the first planarization layer.

4. The display device according to claim 1, wherein: The second planarization layer is disposed between the plurality of first connection electrodes and the plurality of second connection electrodes and is disposed to completely cover the plurality of first connection electrodes.

5. The display device according to claim 1, further comprising: a bank, the bank being disposed on the second planarization layer so as not to overlap with the plurality of light emitting diodes; as well as A third planarization layer is disposed on the second planarization layer and the bank.

6. The display device according to claim 1, wherein: The plurality of first connection electrodes include a plurality of first sub-electrodes spaced apart from each other, The plurality of second connection electrodes include a plurality of second sub-electrodes spaced apart from each other, and The plurality of first sub-electrodes and the plurality of second sub-electrodes are alternately arranged on a plane.

7. The display device according to claim 6, wherein: The plurality of first connection electrodes further include a first base electrode connected to the plurality of first sub-electrodes, and The plurality of second connection electrodes further include a second base electrode connected to the plurality of second sub-electrodes.

8. The display device according to claim 6, wherein: The width of each of the plurality of first sub-electrodes is equal to or smaller than the interval between the plurality of second sub-electrodes, and A width of each of the plurality of second sub-electrodes is equal to or smaller than an interval between the plurality of first sub-electrodes.

9. The display device according to claim 6, wherein: The plurality of first sub-electrodes and the plurality of second sub-electrodes are arranged in parallel on the plane.

10. The display device according to claim 6, wherein: The plurality of light emitting diodes include a first light emitting diode having a circular plan shape, a second light emitting diode having an elliptical plan shape, and a third light emitting diode having an elliptical plan shape, the size of the elliptical plan shape of the third light emitting diode being different from the size of the elliptical plan shape of the second light emitting diode, The long axis direction of the second light emitting diode is the same as the long axis direction of the third light emitting diode, and The plurality of first sub-electrodes and the plurality of second sub-electrodes are disposed parallel to the long axis directions of the second light emitting diode and the third light emitting diode.

11. The display device according to claim 6, wherein: The plurality of light emitting diodes include a first light emitting diode having a circular plan shape, a second light emitting diode having an elliptical plan shape, and a third light emitting diode having an elliptical plan shape, the size of the elliptical plan shape of the third light emitting diode being different from the size of the elliptical plan shape of the second light emitting diode, The long axis direction of the second light emitting diode is the same as the long axis direction of the third light emitting diode, and The plurality of first sub-electrodes and the plurality of second sub-electrodes are disposed perpendicular to the long axis direction of the second light emitting diode and the third light emitting diode.

12. The display device according to claim 6, wherein: The plurality of light emitting diodes include a first light emitting diode having a circular planar shape, The plurality of first sub-electrodes connected to the first light emitting diode have a circular shape with one open side on the plane, and One of the plurality of second sub-electrodes connected to the first light-emitting diode has a circular shape, and the other second sub-electrodes have a circular shape, with an opening on the other side of the circular shape of the other second sub-electrodes opposite to the one open side of the plurality of first sub-electrodes.

13. The display device according to claim 12, wherein: The plurality of first connection electrodes further include a first base electrode connected to the plurality of first sub-electrodes and disposed in an opening region of the plurality of second sub-electrodes, and The plurality of second connection electrodes further include a second base electrode connected to the plurality of second sub-electrodes and disposed in an opening region of the plurality of first sub-electrodes.

14. The display device according to claim 6, wherein: The plurality of first sub-electrodes include a first portion extending along a first direction on the plane and a second portion extending along a second direction different from the first direction, and The plurality of second sub-electrodes include a first portion extending along the first direction and a second portion extending along the second direction.

15. The display device according to claim 14, wherein: The first portions of the plurality of first sub-electrodes and the first portions of the plurality of second sub-electrodes are alternately arranged on the plane, and The second portions of the plurality of first sub-electrodes and the second portions of the plurality of second sub-electrodes are alternately disposed on the plane.

16. The display device according to claim 6, wherein: The plurality of first sub-electrodes and the plurality of second sub-electrodes do not overlap each other on the plane.

17. The display device according to claim 1, further comprising: a plurality of driving transistors, wherein the plurality of driving transistors are disposed on the substrate; as well as a power line, the power line being arranged on the substrate, The plurality of first connection electrodes electrically connect the plurality of driving transistors and the first electrode, and the plurality of second connection electrodes electrically connect the power line and the second electrode.

18. The display device according to claim 1, wherein: A height of an upper surface of the second planarization layer is lower than a height of an upper surface of the second electrode.

19. The display device according to claim 1, wherein: Each of the plurality of light emitting diodes further includes a first semiconductor layer and a passivation film, the first semiconductor layer being disposed below and in contact with the first electrode, the passivation film being disposed to surround the first semiconductor layer, and Wherein, the first planarization layer is configured to completely cover the lower end of the passivation film.

20. A display device, comprising: A substrate comprising a plurality of sub-pixels, each of the plurality of sub-pixels comprising a light emitting diode, wherein: The light emitting diode includes a first electrode and a second electrode disposed at a higher position than the first electrode; a first connecting electrode connected to the first electrode; a second connection electrode connected to the second electrode; and a planarization layer, the planarization layer being arranged between the first connection electrode and the second connection electrode, The first connecting electrode includes a plurality of first sub-electrodes spaced apart from each other. The second connection electrode includes a plurality of second sub-electrodes spaced apart from each other, and The plurality of first sub-electrodes and the plurality of second sub-electrodes are alternately arranged on a plane.

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