Display device and manufacturing method thereof

Abstract

A display device according to an embodiment of the present disclosure may include: a substrate divided into a display area and a non-display area; the gate driving circuit is arranged on the substrate and is arranged in the non-display area; a plurality of gate clock lines disposed on the substrate and outside the gate drive circuit; a passivation layer disposed on the gate drive circuit and the plurality of gate clock lines; the common electrode is arranged on the passivation layer and is not overlapped with the plurality of grid clock lines; and a shielding layer in the non-display area, disposed on the passivation layer, and overlapping the plurality of gate clock lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0180719, filed on December 13, 2023, and Korean Patent Application No. 10 - 2024 - 0125273, filed on September 13, 2024, which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein. Technical field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background art

[0004] With the development of the information society, the demand for display devices for displaying various forms of images has been increasing. In recent years, various display devices such as liquid crystal displays and organic light - emitting display devices have been used.

[0005] To display an image, a display device may include a display panel including a plurality of data lines and a plurality of gate lines, a data driving circuit for outputting data signals through the plurality of data lines, and a gate driving circuit for outputting gate signals through the plurality of gate lines.

[0006] In the conventional display field, in - panel gate (GIP) technology in which a gate driving circuit is embedded in a display panel is being developed to reduce the number of components and reduce the bezel size.

[0007] In the case where a gate driving circuit is embedded in a display panel and a narrow bezel structure is formed, unexpected abnormal operations or display abnormalities of the gate driving circuit may occur. Summary of the invention

[0008] Embodiments of the present disclosure may provide a display device having a reliability structure and a method of manufacturing the same, the reliability structure being capable of preventing or at least partially reducing abnormal operations of a gate driving circuit that may occur in a display panel having a built - in gate driving circuit.

[0009] Embodiments of the present disclosure may provide a display device having a reliability structure and a method of manufacturing the same, the reliability structure being capable of preventing or at least partially reducing display abnormalities that may occur in a display panel having a built - in gate driving circuit.

[0010] Embodiments of the present disclosure may provide a display device having a reliability structure and a method of manufacturing the same, the reliability structure being capable of preventing or at least partially reducing output deviation of gate signals in a gate driving circuit.

[0011] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can prevent or at least partially reduce a load deviation between gate clock lines input to a gate driving circuit.

[0012] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can prevent or at least partially reduce a burnout defect in at least one gate clock line that may occur in a display panel having a built-in gate driving circuit.

[0013] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can implement a narrow bezel structure of a display panel having a built-in gate driving circuit without causing driving defects, image defects, or safety problems.

[0014] Embodiments of the present disclosure may provide a display device having a reliability structure in a display area and a manufacturing method thereof.

[0015] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can eliminate a parasitic capacitance between a signal line and a common electrode provided in a display area.

[0016] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can implement high-speed display driving or high-speed sensing.

[0017] Embodiments of the present disclosure may provide a display device having a reliability structure and a manufacturing method thereof. The reliability structure can reduce a signal line width, thereby increasing an aperture ratio of the display panel.

[0018] A display device according to an embodiment of the present disclosure may include: a substrate divided into a display area and a non-display area; a gate driving circuit disposed on the substrate and in the non-display area; a plurality of gate clock lines disposed on the substrate and outside the gate driving circuit; a passivation layer disposed on the gate driving circuit and the plurality of gate clock lines; a common electrode disposed on the passivation layer and not overlapping with the plurality of gate clock lines; and a shielding layer located in the non-display area, disposed on the passivation layer, and overlapping with the plurality of gate clock lines.

[0019] In the display device according to an embodiment of the present disclosure, the shielding layer may include a non-metal having a property of blocking or capturing moisture and oxygen. For example, the shielding layer may include a fluorine-based material.

[0020] In the display device according to an embodiment of the present disclosure, the shielding layer may be spaced apart from the common electrode and may not overlap with the common electrode in a vertical direction.

[0021] In a display device according to an embodiment of the present disclosure, a plurality of gate clock lines may not overlap with a common electrode.

[0022] In a display device according to an embodiment of the present disclosure, a shielding layer may include a metal having a property of blocking or capturing moisture and oxygen. For example, the shielding layer may include at least one of barium, magnesium, cerium, lanthanum, and titanium.

[0023] A display device according to an embodiment of the present disclosure may further include at least one signal line disposed on a substrate, a pixel electrode disposed on a passivation layer, a bank having a bank hole overlapping a part of the pixel electrode and disposed on the pixel electrode, an intermediate layer disposed in the bank hole and between the pixel electrode and the common electrode, at least one shielding pattern disposed on the bank, and a first encapsulation layer disposed on the at least one shielding pattern and the common electrode.

[0024] According to a display device according to an embodiment of the present disclosure, the shielding pattern may include the same material as the shielding layer.

[0025] According to a display device according to an embodiment of the present disclosure, the common electrode may not be disposed on the at least one shielding pattern, and the at least one shielding pattern may overlap with the at least one signal line in a vertical direction.

[0026] A display device according to an embodiment of the present disclosure may include: a substrate in which a display area and a non-display area are defined; at least one signal line disposed on the substrate and in the non-display area; an outer coating disposed on the at least one signal line; a pixel electrode disposed on the outer coating; a bank having a bank hole overlapping at least a part of the pixel electrode; a common electrode disposed on the bank and extending inside the bank hole; and a shielding pattern disposed on the bank.

[0027] According to an embodiment of the present disclosure, the common electrode may be disconnected by the shielding pattern, and the shielding pattern may overlap with the at least one signal line. The at least one signal line may not overlap with the common electrode.

[0028] A method of manufacturing a display device according to an embodiment of the present disclosure may include: a first step in which a gate driving circuit and a plurality of gate clock lines are formed in a non-display area around a display area on a substrate, the plurality of gate clock lines are formed outside the gate driving circuit, a passivation layer is formed on the gate driving circuit and the plurality of gate clock lines, and an outer coating and a bank are formed on the passivation layer; a second step in which a shielding layer is formed in the display area and the non-display area; a third step in which a photoresist is formed on the shielding layer; a fourth step in which the photoresist is developed and the photoresist remains in a first area in the non-display area; a fifth step in which the shielding layer is developed and the shielding layer remains in a second area overlapping the first area; and a sixth step in which a common electrode is deposited.

[0029] The shielding layer remaining in the second area in the fifth step may overlap with the plurality of gate clock lines.

[0030] In the first step, in the display area, at least one signal line may be formed on the substrate, a passivation layer may be formed on the plurality of signal lines, an outer coating may be formed on the passivation layer, a pixel electrode may be formed on the outer coating in the display area, and a bank having a bank hole overlapping at least a part of the pixel electrode may be formed.

[0031] In the fourth step, the photoresist may be left or retained in a plurality of third areas overlapping the plurality of signal lines in the display area.

[0032] In the fifth step, the shielding layer may be left or retained in a plurality of fourth areas overlapping the plurality of third areas. The shielding layer retained in the plurality of fourth areas overlaps with the plurality of signal lines.

[0033] The second area may overlap with the first area and may be smaller than the first area. Each of the plurality of fourth areas may be smaller than each of the plurality of third areas.

[0034] In the sixth step, the common electrode may be formed in a disconnected state around the photoresist remaining in the first area and the plurality of third areas.

[0035] A method of manufacturing a display device according to an embodiment of the present disclosure may further include a seventh step after the sixth step, in which the remaining photoresist in the first area and the plurality of third areas is removed, and the common electrode provided on the remaining photoresist in the first area and the plurality of third areas is removed.

[0036] After the seventh step, the common electrode in the portion overlapping with the plurality of gate clock lines may be removed, and the common electrode in the portion overlapping with the plurality of signal lines may also be removed. The common electrode remains only in the portion not overlapping with the plurality of gate clock lines and the portion not overlapping with the plurality of signal lines.

[0037] The method of manufacturing a display device according to an embodiment of the present disclosure may further include an eighth step after the seventh step, in which a first encapsulation layer is formed.

[0038] In the non-display area, the first encapsulation layer may be disposed on the shielding layer and the common electrode, and may be interposed between the shielding layer and the common electrode. Accordingly, the shielding layer and the common electrode may be separated from each other by the first encapsulation layer.

[0039] In the display area, the first encapsulation layer may be interposed between the disconnection spaces of the common electrodes, such that the common electrodes may be separated from each other by the first encapsulation layer.

[0040] The shielding layer may include a material having moisture and oxygen barrier or trapping properties.

[0041] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of preventing abnormal operation of a gate driving circuit that may occur in a display panel having a built-in gate driving circuit.

[0042] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of preventing display abnormalities that may occur in a display panel having a built-in gate driving circuit.

[0043] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of preventing output deviation of gate signals in a gate driving circuit.

[0044] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of preventing load deviation between gate clock lines input to a gate driving circuit.

[0045] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of preventing burnout defects in at least one gate clock line that may occur in a display panel having a built-in gate driving circuit.

[0046] According to an embodiment of the present disclosure, there is provided a display device having a reliability structure and a manufacturing method thereof, the reliability structure being capable of implementing a narrow bezel structure of a display panel having a built-in gate driving circuit without causing driving defects, image defects, or safety problems.

[0047] According to an embodiment of the present disclosure, the weight of the display device may be reduced by implementing a narrow bezel structure.

[0048] According to an embodiment of the present disclosure, a display device having a reliability structure in a display area and a manufacturing method thereof can be provided.

[0049] According to an embodiment of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided, and the reliability structure can eliminate the parasitic capacitance between a signal line and a common electrode provided in a display area.

[0050] According to an embodiment of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided, and the reliability structure can achieve high-speed display driving or high-speed sensing.

[0051] According to an embodiment of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided, and the reliability structure can reduce the signal line width to improve the aperture ratio of the display panel. Description of the Drawings

[0052] Figure 1 It is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0053] Figure 2 It is a display panel according to an embodiment of the present disclosure.

[0054] Figure 3 It is an equivalent circuit of a sub-pixel of a display panel according to an embodiment of the present disclosure.

[0055] Figure 4 It is an example of a system implementation manner of a display device according to an embodiment of the present disclosure.

[0056] Figure 5 It is a plan view of a display panel according to an embodiment of the present disclosure.

[0057] Figure 6 It is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0058] Figure 7 It is a plan view of a display panel having a reliability structure according to an embodiment of the present disclosure.

[0059] Figure 8 It is a cross-sectional view of a display panel having a reliability structure according to an embodiment of the present disclosure.

[0060] Figure 9A and Figure 9B It is a shielding layer material in a display panel according to an embodiment of the present disclosure.

[0061] Figure 10 It is a cross-sectional view of a display area and a non-display area of a display panel when the display panel has a reliability structure according to an embodiment of the present disclosure.

[0062] Figures 11 to 19 The manufacturing process of a display device according to an embodiment of the present disclosure. Detailed implementation manners

[0063] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. When assigning reference numerals to components of each figure, the same reference numerals may be assigned to the same components even if they are shown in different figures. Details of known technologies or functions may be skipped when it is determined that they will obscure the subject matter of the present disclosure. As used herein, when a component "comprises", "has" another component or "consists of" another component, other components may be added to the component unless the component "only" comprises, has or "consists of" another component. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0064] Designations such as "first", "second", "A", "B", "(a)" and "(b)" may be used to describe components of the present disclosure. These symbols are provided merely to distinguish the respective components, and the nature, order or quantity of the components is not limited by the symbols.

[0065] When describing the positional relationship between components, when two or more components are described as "connected", "coupled" or "linked", the two or more components may be directly "connected", "coupled" or "linked", or another component may intervene. Here, the other component may be included in one or more of the two or more components that are "connected", "coupled" or "linked" to each other.

[0066] When using terms such as "after", "next" and "before" to describe the time flow relationship related to components, operation methods and manufacturing methods, it may include a non - continuous relationship unless the term "immediately" or "directly" is used.

[0067] When specifying a component with a value or its corresponding information (e.g., level), the value or corresponding information may be interpreted as including tolerances that may arise due to various factors (e.g., process factors, internal or external influences, or noise).

[0068] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0069] Figure 1 FIG. is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0070] Refer to Figure 1 , the display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110.

[0071] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and may further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130.

[0072] The display panel 110 may include a substrate SUB and signal lines disposed on the substrate SUB, such as a plurality of data lines DL and a plurality of gate lines GL. The display panel 110 may include a plurality of sub-pixels SP connected to the plurality of data lines DL and the plurality of gate lines GL.

[0073] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. In the display panel 110, a plurality of sub-pixels SP for displaying an image may be disposed in the display area DA. In the non-display area NDA, the driving circuits 120, 130, and 140 may be electrically connected, or the driving circuits 120, 130, and 140 may be mounted, and a pad portion may be provided, to which an integrated circuit or a printed circuit may be connected.

[0074] The data driving circuit 120 is a circuit for driving a plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0075] The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0076] The controller 140 may supply a data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120, and may supply a gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130.

[0077] The controller 140 may start scanning according to the timing implemented per frame, may convert input image data input from the outside to a data signal format suitable for use in the data driving circuit 120, and may supply the converted image data Data to the data driving circuit 120, and control data driving at an appropriate time according to the scanning.

[0078] In addition to receiving input image data from the outside (e.g., the host system 150), the controller 140 may receive various timing signals, including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal (LK).

[0079] To control the data driving circuit 120 and the gate driving circuit 130, the controller 140 may receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK, and generate various control signals DCS and GCS, and output them to the data driving circuit 120 and the gate driving circuit 130.

[0080] For example, the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE to control the gate driving circuit 130.

[0081] In addition, to control the data driving circuit 120, the controller 140 may output various data control signals DCS including a source start pulse SS, a source sampling clock SSC, and a source output enable signal SOE.

[0082] The controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0083] The data driving circuit 120 may receive image data Data from the controller 140 and supply data voltages to a plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0084] The data driving circuit 120 may include one or more source driver integrated circuits SDIC.

[0085] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter (DAC), and an output buffer. In some cases, each source driver integrated circuit SDIC may further include an analog-to-digital converter ADC.

[0086] For example, each source driver integrated circuit SDIC may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0087] The gate driving circuit 130 may output a gate signal of a conductive level voltage or a gate signal of a non-conductive level voltage according to the control of the controller 140. The gate driving circuit 130 may sequentially drive a plurality of gate lines GL by sequentially supplying a gate signal of a conductive level voltage to the plurality of gate lines GL.

[0088] The gate driving circuit 130 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to the bonding pads of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 using a chip on film (COF) method. Alternatively, the gate driving circuit 130 may be a gate on panel (GIP) type and may be formed in the non-display area NDA of the display panel 110. The gate driving circuit 130 may be disposed on the substrate SUB or connected to the substrate SUB. That is, if the gate driving circuit 130 is of the GIP type, it may be disposed in the non-display area NDA of the substrate SUB. In the case of a chip on glass (COG) type, a chip on film (COF) type, etc., the gate driving circuit 130 may be connected to the substrate SUB.

[0089] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA.

[0090] For example, the gate driving circuit 130 may be disposed in the display area DA. In this case, the gate driving circuit 130 may be disposed over the entire display area DA or only in a part of the display area DA. The gate driving circuit 130 may be disposed so as not to overlap with the sub-pixels SP, or may be disposed so as to partially or entirely overlap with the sub-pixels SP.

[0091] As another example, the data driving circuit 120 may be disposed in the display area DA. In this case, the data driving circuit 120 may be disposed over the entire display area DA or only in a part of the display area DA. The data driving circuit 120 may be disposed so as not to overlap with the sub-pixels SP, or may be disposed so as to partially or entirely overlap with the sub-pixels SP.

[0092] When the gate driving circuit 130 selects a specific gate line GL, the data driving circuit 120 may convert the image data Data received from the controller 140 into an analog data voltage and supply it to a plurality of data lines DL.

[0093] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method or the panel design method, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more sides out of the four sides of the display panel 110.

[0094] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the driving method or the panel design method, the gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to two or more sides among the four sides of the display panel 110.

[0095] The controller 140 may be a timing controller used in typical display technologies, or may be a control device including a timing controller that can further perform other control functions, or may be a control device different from the timing controller, or may be a control device other than the timing controller, or may be a circuit within the control device. The controller 140 may be implemented with various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0096] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit.

[0097] The controller 140 may transmit and receive signals with the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signal (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI).

[0098] The controller 140 may include a storage medium, such as one or more registers.

[0099] The display device 100 according to an embodiment of the present disclosure may be a display device in which the display panel 110 cannot emit light by itself. For example, the display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device including a backlight unit.

[0100] Alternatively, the display device 100 according to an embodiment of the present disclosure may be a self-emitting display device in which the display panel 110 can emit light by itself. For example, the display device 100 according to an embodiment of the present disclosure may be one of display devices including an organic light emitting diode (OLED) display device, a quantum dot display, and a micro light emitting diode (Micro LED) display device.

[0101] If the display device 100 according to an embodiment of the present disclosure is an organic light emitting diode display device, each sub-pixel SP may include an organic light emitting diode that emits light itself as a light emitting device. If the display device 100 according to an embodiment of the present disclosure is a quantum dot display device, each sub-pixel SP may include a light emitting element made of quantum dots, which are semiconductor crystals that emit light themselves. If the display device 100 according to an embodiment of the present disclosure is a micro light emitting diode display device, each sub-pixel SP may include a micro light emitting diode that emits light itself and is made of an inorganic material as a light emitting device.

[0102] Figure 2 A display panel 110 according to an embodiment of the present disclosure is shown.

[0103] Referring Figure 2 , the display panel 110 may include a substrate SUB disposed in a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate SUB. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0104] Referring Figure 2 , when the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP disposed on the substrate SUB may include a light emitting device ED and a sub-pixel circuit SPC for driving the light emitting device ED.

[0105] Referring Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light emitting device ED. In the present disclosure, the sub-pixel circuit SPC may drive the light emitting device ED by supplying a driving current to the light emitting device ED at a predetermined timing. The light emitting device ED may be driven by the driving current and emit light.

[0106] The plurality of pixel driving transistors may include a driving transistor DRT for driving the light emitting device ED and a scanning transistor SCT that is turned on or off according to a scanning signal SC.

[0107] The driving transistor DRT may supply a driving current to the light emitting device ED.

[0108] The scanning transistor SCT may be configured to control the electrical state of a corresponding node (e.g., the second node, N2) in the sub-pixel circuit SPC or control the state or operation of the driving transistor DRT.

[0109] The at least one capacitor may include a storage capacitor Cst to maintain a constant voltage during a frame.

[0110] To drive the sub-pixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the sub-pixel SP. In addition, a common driving voltage including a first driving voltage VDD and a second driving voltage VSS may also be applied to the sub-pixel SP to drive the sub-pixel SP.

[0111] The light-emitting device ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0112] In the case where the light-emitting device ED is an organic light-emitting device, the intermediate layer EL may include an emission layer EML and a common intermediate layer EL_COM. The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 may be disposed between the pixel electrode PE and the emission layer EML and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 may be disposed between the emission layer EML and may include at least one layer (e.g., an organic layer).

[0113] For example, the emission layer EML may be disposed in each of the plurality of sub-pixels SP, or in another example, may be commonly disposed in the plurality of sub-pixels SP. The common intermediate layer EL_COM may be commonly disposed in the plurality of sub-pixels SP.

[0114] The emission layer EML may be disposed in each emission region, and the common intermediate layer EL_COM may be commonly disposed in a plurality of emission regions and non-emission regions.

[0115] The pixel electrode PE may be an electrode disposed in each sub-pixel SP, and the common electrode CE may be an electrode commonly disposed in the plurality of sub-pixels SP.

[0116] For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode. Again, for example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. Hereinafter, an example in which the pixel electrode PE is an anode and the common electrode CE is a cathode will be described.

[0117] For example, the first common intermediate layer COM1 of the common intermediate layer EL_COM may include a hole injection layer HIL and a hole transport layer HTL, and the second common intermediate layer COM2 of the common intermediate layer EL_COM may include an electron transport layer ETL and an electron injection layer EIL.

[0118] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, the hole transport layer can transport the holes to the emission layer EML, the electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport the electrons to the emission layer EML.

[0119] For example, the common electrode CE can be electrically connected to the second driving voltage line VSSL. The second driving voltage VSS, which is a type of common driving voltage, can be applied to the common electrode CE through the second driving voltage line VSSL. The pixel electrode PE can be directly or indirectly (via another transistor) electrically connected to the first node N1 of the driving transistor DRT of each sub-pixel SP. In the present disclosure, the "second common driving voltage VSS" can also be referred to as the "base voltage VSS", and the "second common driving voltage line VSSL" can be referred to as the "base voltage line VSSL".

[0120] Each light-emitting device ED can be composed of the overlapping portion of the pixel electrode PE, the emission layer EML in the intermediate layer EL, and the common electrode (CE). A predetermined emission region can be formed by each light-emitting device ED. For example, the emission region of each light-emitting device ED can include the overlapping region of the pixel electrode PE, the emission layer EML in the intermediate layer (EL), and the common electrode CE.

[0121] For example, the light-emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting device. For example, in the case where the light-emitting device ED is an organic light-emitting diode OLED, the intermediate layer EL in the light-emitting device ED can include an organic film containing an organic material.

[0122] The driving transistor DRT can be a driving transistor for supplying a driving current to the light-emitting device ED. The driving transistor DRT can be connected between the first common driving voltage line VDDL and the light-emitting device ED.

[0123] The driving transistor DRT can include a first node N1, a second node N2, and a third node N3. The first node N1 can be electrically connected to the light-emitting device ED, the second node N2 can be applied with a data signal VDATA, and the third node N3 can be applied with the first common driving voltage VDD from the first common driving voltage line VDDL.

[0124] In the driving transistor DT, the second node N2 can be a gate node, the first node N1 can be a source node or a drain node, and the third node N3 can be a drain node or a source node. Hereinafter, for convenience of explanation, the case where the second node N2 is the gate node, the first node N1 is the source node, and the third node N3 is the drain node in the driving transistor DRT will be described.

[0125] Figure 2 The scanning transistor SCT included in the sub-pixel circuit SPC shown can be a switching transistor for transmitting a data signal VDATA, which is an image signal, to a second node N2 that is a gate node of a driving transistor DRT.

[0126] The scanning transistor SCT can be controlled to turn on and off by a scanning signal SC, which is a gate signal applied through a scanning line SCL that is a type of gate line GL, and can control the electrical connection between the second node N2 of the driving transistor DRT and a data line DL. A drain electrode or a source electrode of the scanning transistor SCT can be electrically connected to the data line DL, and a source electrode or a drain electrode of the scanning transistor SCT can be electrically connected to the second node N2 of the driving transistor DRT. A gate electrode of the scanning transistor SCT can be electrically connected to the scanning line SCL.

[0127] A storage capacitor Cst can be electrically connected between a first node N1 and a second node N2 of the driving transistor DRT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DRT or corresponding to the first node N1 of the driving transistor DRT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DRT or corresponding to the second node N2 of the driving transistor DRT.

[0128] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DRT, rather than a parasitic capacitor (e.g., Cgs, Cgd) that may exist between the first node N1 and the second node N2 of the driving transistor DRT and act as an internal capacitor.

[0129] Each of the driving transistor DRT and the scanning transistor SCT can be an n-type transistor or a p-type transistor.

[0130] The display panel 110 can have a top emission structure or a bottom emission structure.

[0131] In the case where the display panel 110 has a top emission structure, at least a part of the sub-pixel circuit SPC can overlap with at least a part of the light-emitting device ED in the vertical direction. Thus, the area of the emission region and the aperture ratio can be increased.

[0132] If the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light-emitting device ED in the vertical direction.

[0133] As Figure 2As shown, the sub-pixel circuit SPC may have a 2T-1C structure, including two transistors DRT and SCT and a capacitor Cst. In some cases, the sub-pixel circuit SPC may further include one or more transistors or one or more capacitors.

[0134] According to the structure of the sub-pixel circuit SPC, the type and number of gate signals and / or gate lines supplied to the sub-pixel SP may vary. In addition, according to the structure of the sub-pixel circuit SPC, the type and number of common driving voltages supplied to the sub-pixel SP may vary.

[0135] Since the circuit elements within each sub-pixel SP (especially the light-emitting device ED implemented with an organic light-emitting diode (OLED) containing an organic material) are vulnerable to external moisture or oxygen, an encapsulation layer 200 may be provided on the display panel 110 to prevent oxygen from penetrating into the circuit elements (especially the light-emitting device ED). The encapsulation layer 200 may be configured in various shapes to prevent the light-emitting device ED from coming into contact with moisture or oxygen.

[0136] The display device 100 according to an embodiment of the present disclosure may have an extremely narrow bezel structure, where the non-display area NDA of the display panel 110 is very small.

[0137] Figure 3 is an equivalent circuit of a sub-pixel of the display panel 110 according to an embodiment of the present disclosure.

[0138] Reference Figure 3 , each sub-pixel among the plurality of sub-pixels SP provided on the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include a sensing transistor SENT compared to the sub-pixel SP shown in Figure 2 .

[0139] Reference Figure 3 , the sensing transistor SENT may be controlled by a sensing signal SE as a type of gate signal and may be connected between the first node N1 of the driving transistor DRT and the reference voltage line RVL. That is, the sensing transistor SENT may be turned on or off according to the sensing signal SE supplied from the sensing signal line SENL as another type of gate line GL, thereby controlling the connection between the reference voltage line RVL and the first node N1 of the driving transistor DRT.

[0140] The sensing transistor SENT may be turned on by the sensing signal SE having a conductive level voltage and may transmit the reference voltage VREF supplied from the reference voltage line RVL to the first node N1 of the driving transistor DRT.

[0141] In addition, the sensing transistor SENT can be turned on by a sensing signal SE having a conductive level voltage, and can transfer the voltage of the first node N1 of the driving transistor DRT to the reference voltage line RVL.

[0142] Here, if the sensing transistor SENT is an n-type transistor, the conductive level voltage of the sensing signal SE can be a high level voltage. If the sensing transistor SENT is a p-type transistor, the conductive level voltage of the sensing signal SE can be a low level voltage.

[0143] The function of the sensing transistor SENT to transfer the voltage of the first node N1 of the driving transistor DRT to the reference voltage line RVL can be used when driving to sense the characteristic value of the sub-pixel SP. In this case, the voltage transferred to the reference voltage line RVL can be a voltage for calculating the characteristic value of the sub-pixel SP, or a voltage reflecting the characteristic value of the sub-pixel SP.

[0144] In the present disclosure, the characteristic value of the sub-pixel SP can be the characteristic value of the driving transistor DRT or the light-emitting device ED. For example, the characteristic values of the driving transistor DRT can include the threshold voltage and mobility of the driving transistor DRT. The characteristic values of the light-emitting device ED can include the threshold voltage of the light-emitting device ED.

[0145] The sensing transistor SENT can be an n-type transistor or a p-type transistor. In the present disclosure, for ease of explanation, the n-type sensing transistor SENT is taken as an example for description.

[0146] The scan signal line SCL and the sense signal line SENL can be different gate lines GL. In this case, the scan signal SC and the sense signal SE can be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT within one sub-pixel SP can be independent. That is, the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT within one sub-pixel SP can be the same or different.

[0147] Alternatively, the scan signal line SCL and the sense signal line SENL can be the same gate line GL. That is, the gate nodes of the scan transistor SCT and the sensing transistor SENT within one sub-pixel SP can be connected to the same gate line GL. In this case, the scan signal SC and the sense signal SE can be the same gate signal, and the on-off timing of the scan transistor SCT and the on-off timing of the sensing transistor SENT within one sub-pixel (SP) can be the same.

[0148] Figure 4 An example of a system implementation of the display device 100 according to an embodiment of the present disclosure is shown.

[0149] Reference Figure 4 As shown, the display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image.

[0150] Reference Figure 4 As shown, in the case where the data driving circuit 120 includes one or more source driver integrated circuits SDICs and is implemented by a chip on film (COF) method, each source driver integrated circuit SDIC may be mounted on a circuit film SF connected to the non-display area NDA of the panel 110.

[0151] Reference Figure 4 As shown, the gate driving circuit 130 may be implemented as an in-panel gate (GIP) type. In this case, the gate driving circuit 130 may be formed in the non-display area NDA of the display panel 110. Different from Figure 4 this, the gate driving circuit 130 may be implemented as a chip on film (COF) type.

[0152] To implement the circuit connection between one or more source driver integrated circuits SDICs and other devices, the display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for mounting control components and various electrical devices.

[0153] The film SF on which the source driver integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board SPCB. That is, one side of the film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board SPCB.

[0154] The controller 140 and the power management integrated circuit (PMIC) 310 may be mounted on the control printed circuit board CPCB. The controller 140 may execute the overall control function related to driving the display panel 110 and control the operations of the data driving circuit 120 and the gate driving circuit 130. The power management integrated circuit 310 may supply various voltages or currents to the data driving circuit 120 and the gate driving circuit 130, or control the various voltages or currents to be supplied.

[0155] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be electrically connected through at least one connection cable CBL, where the connection cable CBL may be, for example, a flexible printed circuit FPC, a flexible flat cable FFC, etc.

[0156] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated and implemented as one printed circuit board.

[0157] The display device 100 according to an embodiment of the present disclosure may further include a level shifter 300 for adjusting a voltage level. For example, the level shifter 300 may be disposed on a control printed circuit board CPCB or a source printed circuit board SPCB.

[0158] In the display device 100 according to an embodiment of the present disclosure, the level shifter 300 may supply a signal required for gate driving to the gate driving circuit 130. For example, the level shifter 300 may supply a plurality of clock signals (i.e., gate clock signals) to the gate driving circuit 130. Accordingly, the gate driving circuit 130 may generate a plurality of gate signals based on the plurality of gate clock signals input from the level shifter 300 and output the plurality of gate signals to a plurality of gate lines GL. Here, the plurality of gate lines GL may transmit the plurality of gate signals to sub-pixels SP disposed in a display area DA of a substrate SUB.

[0159] Reference Figure 4 , a non-display area NDA of the display panel 110 may include a gate border area GBZ, and the gate driving circuit 130 and its related lines are disposed in the gate border area GBZ.

[0160] Reference Figure 4 , in the gate border area GBZ, in addition to the GIP type gate driving circuit 130, various lines required for the operation of the gate driving circuit 130 may need to be provided. Here, the various lines required for the operation of the gate driving circuit 130 may include a plurality of gate clock lines, at least one high-level gate voltage line, and at least one low-level gate voltage line.

[0161] The structure of the gate border area GBZ of the display panel 110 according to an embodiment of the present disclosure will be described below. Hereinafter, for convenience of explanation, the GIP type gate driving circuit 130 may be referred to as an in-panel gate circuit GIPC.

[0162] Figure 5 is a plan view of a display panel 110 according to an embodiment of the present disclosure.

[0163] Reference Figure 5 , the display panel 110 according to an embodiment of the present disclosure may include a common electrode CE for a light emitting device ED constituting each sub-pixel SP.

[0164] Reference Figure 5 , in the display panel 110, the substrate SUB may include a display area DA capable of displaying an image and a non-display area NDA not displaying an image. A plurality of sub-pixels SP may be disposed in the display area DA. The non-display area NDA may be an area outside the display area DA.

[0165] Reference Figure 5, in the display panel 110, the common electrode CE can be disposed on the substrate SUB, can be disposed over the entire display area DA, and can extend to a part of the non-display area NDA.

[0166] Reference Figure 5 , the non-display area NDA may include a gate border area GBZ, and the gate border area GBZ includes an area where the gate driving circuit 130 and its related lines are disposed. The common electrode CE can extend to a part of the gate border area GBZ. That is, the common electrode CE can overlap with a part of the gate border area GBZ.

[0167] The common electrode CE is a type of display driving electrode for constructing the light-emitting device ED, and can be an electrode to which a base voltage VSS is applied. For example, the base voltage VSS applied to the common electrode CE can be a ground voltage.

[0168] The gate driving circuit 130 of the GIP type can be disposed in the gate border area GBZ.

[0169] The gate driving circuit 130 can be disposed only on the first side (e.g., the left side) of the display area DA, or can be disposed on both the first side (e.g., the left side) and the second side (e.g., the right side) of the display area DA at the same time. Therefore, the position of the gate border area GBZ can vary. That is, the gate border area GBZ can exist only on the first side (e.g., the left side) of the display area DA, and can exist on both the first side (e.g., the left side) and the second side (e.g., the right side) of the display area DA at the same time.

[0170] In addition, a plurality of gate clock lines GCLKL can be disposed in the gate border area GBZ to supply a gate clock signal required for the operation of the gate driving circuit 130 to the gate driving circuit 130.

[0171] The number of the gate clock lines GCLKL can vary according to the gate driving method. For example, the number of the gate clock lines GCLKL can be 2, 4, 6, or 8.

[0172] A plurality of gate clock lines GCLKL can be disposed only on the first side (e.g., the left side) of the display area DA, or can be disposed on both the first side (e.g., the left side) and the second side (e.g., the right side) of the display area DA at the same time.

[0173] In addition, a high-level gate voltage line can be disposed in the gate border area GBZ to supply a high-level gate voltage required for the operation of the gate driving circuit 130 to the gate driving circuit 130.

[0174] In addition, a low-level gate voltage line may be disposed in the gate border region GBZ to supply a low-level gate voltage required for the operation of the gate driving circuit 130 to the gate driving circuit 130.

[0175] Meanwhile, if the display panel 110 has a narrow border structure, it is necessary to reduce the gate border region GBZ. As a result, the common electrode CE may overlap at least one of the plurality of gate clock lines GCLKL. In this case, a capacitor may be formed between at least one of the plurality of gate clock lines GCLKL and the common electrode CE.

[0176] The capacitor formed between the common electrode CE and the gate clock line GCLKL may correspond to an unwanted parasitic capacitor and may cause an unwanted effect on both the common electrode CE and the gate clock line GCLKL.

[0177] Figure 6 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure. Figure 6 is Figure 5 a cross-sectional view of a region 500 including a part of the display area DA and the gate border region GBZ.

[0178] Reference Figure 6 As shown in, in order to make the display panel 110 according to an embodiment of the present disclosure have a narrow layer structure, it is necessary to reduce the gate border region GBZ. Therefore, the common electrode CE may overlap at least one of the plurality of gate clock lines GCLKL. In this case, a capacitor may be formed between at least one of the plurality of gate clock lines GCLKL and the common electrode CE.

[0179] Reference Figure 6 As shown in, the display panel 110 according to an embodiment of the present disclosure may include an in-panel gate circuit GIPC, at least one first gate voltage line GVDDL disposed outside the in-panel gate circuit GIPC, at least one second gate voltage line GVSSL disposed inside the in-panel gate circuit GIPC, and a plurality of gate clock lines GCLKL disposed outside at least one first gate voltage line GVDDL.

[0180] The in-panel gate circuit GIPC, at least one first gate voltage line GVDDL, at least one second gate voltage line GVSSL, and the plurality of gate clock lines GCLKL may be disposed on the substrate SUB and may be disposed in the gate border region GBZ in the non-display area NDA.

[0181] Reference Figure 6 As shown in, the display panel 110 according to an embodiment of the present disclosure may further be provided with a ground line GND further outside the plurality of gate clock lines GCLKL.

[0182] Reference Figure 6 According to an embodiment of the present disclosure, the display panel 110 may include a pixel region PA located within the display region DA. The pixel region PA may include various transistors (e.g., driving transistors DRT, scanning transistors SCT, etc.) and capacitors (e.g., storage capacitors Cst, etc.) included in the sub-pixels SP. In addition, the pixel region PA may further include pixel electrodes PE included in the light-emitting device ED.

[0183] Reference Figure 6 According to an embodiment of the present disclosure, the display panel 110 may further include a passivation layer 610 disposed on the in-panel gate circuit GIPC and a plurality of gate clock lines GCLKL within the panel, an outer coating 620 disposed on the passivation layer 610, and a bank 630 disposed on the outer coating 620.

[0184] Reference Figure 6 According to an embodiment of the present disclosure, the display panel 110 may further include an intermediate layer EL disposed on the pixel electrode PE and the bank 630 within the pixel region PA, and a common electrode CE disposed on the intermediate layer EL.

[0185] Reference Figure 6 According to an embodiment of the present disclosure, the display panel 110 may further include a cover layer 640 disposed on the common electrode CE.

[0186] Reference Figure 6 According to an embodiment of the present disclosure, the display panel 110 may further include a packaging layer 200 located on the cover layer 640. The packaging layer 200 may include an adhesive layer 650 located on the cover layer 640 and a metal packaging layer 660 located on the adhesive layer 650.

[0187] Reference Figure 6 The common electrode CE may be disposed within the display region DA and may extend to the gate border region GBZ within the non-display region NDA.

[0188] Reference Figure 6 In order for the display panel 110 according to an embodiment of the present disclosure to have a narrow border structure, it is necessary to reduce the gate border region GBZ.

[0189] Therefore, within the gate border region GBZ in the non-display region NDA, the common electrode CE may overlap with at least one second gate voltage line GVSSL and the in-panel gate circuit GIPC.

[0190] In addition, within the gate border region GBZ in the non-display region NDA, the common electrode CE may overlap with at least a portion of a plurality of gate clock lines GCLKL.

[0191] As described above, since the display panel 110 according to an embodiment of the present disclosure has a narrow bezel structure, the common electrode CE can overlap at least one of the plurality of gate clock lines GCLKL. In this case, a capacitor can be formed between at least one of the plurality of gate clock lines GCLKL and the common electrode CE.

[0192] The capacitor formed between the common electrode CE and the gate clock line GCLKL can correspond to an unwanted parasitic capacitor and may cause an undesirable effect on both the common electrode CE and the gate clock line GCLKL.

[0193] For example, the capacitor induced by the common electrode CE in at least one of the plurality of gate clock lines GCLKL can act as an unnecessary load or cause distortion of the gate clock signal. In addition, an output deviation may occur between the gate signals output by the gate driving circuit 130, which may cause an abnormal gate driving operation, thereby possibly deteriorating the image quality.

[0194] Even if a capacitor is formed between the plurality of gate clock lines GCLKL and the common electrode CE in the display panel 110, it is more desirable that no capacitor deviation occurs.

[0195] However, even if the panel is designed such that the plurality of gate clock lines GCLKL do not overlap with the common electrode CE, due to process errors that inevitably occur during panel manufacturing, there is a high possibility that some of the plurality of gate clock lines GCLKL overlap with the common electrode CE.

[0196] The load deviation (which can also be referred to as "capacitive load deviation") in the gate clock line GCLKL caused by the common electrode CE may cause abnormal gate driving, thereby possibly causing image abnormalities. For example, a phenomenon of abnormal horizontal lines appearing on the screen (which can be referred to as line darkening phenomenon) may occur.

[0197] In addition, in the case where the common electrode CE overlaps at least one of the plurality of gate clock lines GCLKL in order to implement a narrow bezel structure, a burn-out defect may occur due to static electricity. For example, when the common electrode CE overlaps at least one of the plurality of gate clock lines GCLKL, a burn-out defect may occur due to static electricity in at least one of the gate clock lines GCLKL that overlaps with the common electrode CE.

[0198] Therefore, the display panel 110 according to an embodiment of the present disclosure can include a reliability structure that can fundamentally prevent the overlap of the common electrode CE and the plurality of gate clock lines GCLKL. Hereinafter, the reliability structure for the display panel 110 according to an embodiment of the present disclosure will be described.

[0199] Figure 7It is a plan view of a display panel 110 having a reliability structure according to an embodiment of the present disclosure.

[0200] Reference Figure 7 , according to an embodiment of the present disclosure, the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA that does not display an image. A plurality of sub-pixels SP may be provided in the display area DA. The non-display area NDA may be an area outside the display area DA.

[0201] Reference Figure 7 , the non-display area NDA may include a gate border area GBZ located outside the display area DA in the row direction (or column direction).

[0202] Reference Figure 7 , according to an embodiment of the present disclosure, the display panel 110 may include a common electrode CE for forming a light-emitting device ED of each sub-pixel SP. The common electrode CE may be provided on the substrate SUB, may be provided to pass through the entire display area DA, and may extend to a part of the non-display area NDA. For example, the common electrode CE may extend to a part of the gate border area GBZ within the non-display area NDA.

[0203] Reference Figure 7 , according to an embodiment of the present disclosure, the display panel 110 may include a plurality of gate clock lines GCLKL provided in the non-display area NDA. The plurality of gate clock lines GCLKL may pass through the gate border area GBZ in the non-display area NDA.

[0204] Reference Figure 7 , according to an embodiment of the present disclosure, the display panel 110 may have a reliability structure that fundamentally prevents the common electrode CE from overlapping with the plurality of gate clock lines GCLKL.

[0205] Figure 8 It is a cross-sectional view of a display panel 110 having a reliability structure according to an embodiment of the present disclosure. Figure 8 Is Figure 7 A cross-sectional view of an area 700 including a part of the display area DA and the gate border area GBZ in . In the following description, the description of the same content as above will be omitted.

[0206] Reference Figure 8, the display panel 110 according to an embodiment of the present disclosure may include: an in-panel gate circuit GIPC, which is a GIP type gate driving circuit 130; at least one first gate voltage line GVDDL, which is disposed outside the in-panel gate circuit GIPC; at least one second gate voltage line GVSSL, which is disposed inside the in-panel gate circuit GIPC; and a plurality of gate clock lines GCLKL, which are disposed outside at least one first gate voltage line GVDDL.

[0207] Reference Figure 8 , the in-panel gate circuit GIPC, at least one first gate voltage line GVDDL, at least one second gate voltage line GVSSL, and a plurality of gate clock lines GCLKL may be disposed on the substrate SUB and may be disposed in the gate border region GBZ within the non-display area NDA.

[0208] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include a ground wire GND disposed further outside the plurality of gate clock lines GCLKL.

[0209] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include a pixel region PA within the display area DA. The pixel region PA may include various transistors (e.g., driving transistors DRT, scanning transistors SCT, etc.) and capacitors (e.g., storage capacitors Cst, etc.) included in the sub-pixels SP. In addition, the pixel region PA may further include pixel electrodes PE included in the light-emitting device ED.

[0210] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include a passivation layer 610 disposed on the in-panel gate circuit GIPC and the plurality of gate clock lines GCLKL, an outer coating layer 620 disposed on the passivation layer 610, and a bank 630 disposed on the outer coating layer 620.

[0211] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include an intermediate layer EL disposed on the pixel electrode PE and the bank 630 in the pixel region PA, and a common electrode CE disposed on the intermediate layer EL.

[0212] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include a cover layer 640 disposed on the common electrode CE.

[0213] Reference Figure 8 , the display panel 110 according to an embodiment of the present disclosure may further include a packaging layer 200 disposed on the cover layer 640.

[0214] The encapsulation layer 200 may include a first encapsulation layer 810, a second encapsulation layer 820, and a third encapsulation layer 830.

[0215] The second encapsulation layer 820 may be arranged to cover the first encapsulation layer 810.

[0216] The third encapsulation layer 830 may be disposed on the second encapsulation layer 820.

[0217] For example, the first encapsulation layer 810 may be an inorganic film. The second encapsulation layer 820 may include an adhesive layer and may further include a moisture absorbent. The third encapsulation layer 830 may be a metal thin film.

[0218] Reference Figure 8 , the common electrode CE may be disposed in the display area DA and may extend to the gate border area GBZ in the non-display area NDA.

[0219] That is, reference Figure 8 , the display panel 110 of the display device 100 according to an embodiment of the present disclosure may include: a substrate SUB that defines a display area DA and a non-display area NDA; an in-panel gate circuit GIPC that is a GIP type gate driving circuit 130 disposed on the substrate SUB and in the non-display area NDA; a plurality of gate clock lines GCLKL that are disposed on the substrate SUB and outside the in-panel gate circuit GIPC; a passivation layer 610 that is disposed on the in-panel gate circuit GIPC and the plurality of gate clock lines GCLKL; and a common electrode CE that is disposed on the passivation layer 610 and does not overlap with the plurality of gate clock lines GCLKL.

[0220] Reference Figure 8 , the display panel 110 of the display device 100 according to an embodiment of the present disclosure may include a shielding layer 800 as a reliability structure that can fundamentally prevent the common electrode CE from overlapping with the plurality of gate clock lines GCLKL.

[0221] Reference Figure 8 , in the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may be disposed in the non-display area NDA, may be disposed on the passivation layer 610, and may overlap with the plurality of gate clock lines GCLKL.

[0222] Reference Figure 8, the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include: at least one first gate voltage line GVDDL, which is disposed between the in-panel gate circuit GIPC and multiple gate clock lines GCLKL and transmits a first gate voltage to the in-panel gate circuit GIPC; and at least one second gate voltage line GVSSL, which is disposed between the in-panel gate circuit GIPC and the display area DA and transmits a second gate voltage different from the first gate voltage to the in-panel gate circuit GIPC.

[0223] For example, the first gate voltage may be a high-level gate voltage, and the second gate voltage may be a low-level gate voltage. Alternatively, the first gate voltage may be a low-level gate voltage, and the second gate voltage may be a high-level gate voltage.

[0224] Reference Figure 8 , the common electrode CE may overlap at least one second gate voltage line GVSSL. The common electrode CE does not overlap at least one first gate voltage line GVDDL.

[0225] Reference Figure 8 , the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include a ground wire GND disposed further outside the multiple gate clock lines GCLKL.

[0226] Reference Figure 8 , the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include a first encapsulation layer 810 disposed on the shielding layer 800 and the common electrode CE and between the shielding layer 800 and the common electrode CE.

[0227] Reference Figure 8 , the shielding layer 800 and the common electrode CE may be separated from each other by the first encapsulation layer 810. The first encapsulation layer 810 may cover the upper surface and side surfaces of the shielding layer 800.

[0228] Reference Figure 8 , the cover layer 640 may be disposed between a part of the common electrode CE and a part of the first encapsulation layer 810.

[0229] Reference Figure 8 , the display panel 110 of the display device 100 according to an embodiment of the present disclosure may further include an outer coating 620 disposed on the passivation layer 610, and a bank 630 disposed on the outer coating 620.

[0230] Reference Figure 8 , the common electrode CE may be disposed on the outer coating 620 and may extend and be disposed outside the outer coating 620. The common electrode CE may be disposed on the bank 630 and may extend to be disposed outside the bank 630.

[0231] Reference Figure 8 According to an embodiment of the present disclosure, the display panel 110 of the display device 100 may further include an intermediate layer EL as part of the layers PE, EL, and CE for constructing the light-emitting device ED in the display area DA. Here, the intermediate layer EL may include at least one organic layer extending from the display area DA to a part of the non-display area NDA.

[0232] Reference Figure 8 The intermediate layer EL may overlap with at least one second gate voltage line GVSSL. Additionally, the intermediate layer EL may overlap with at least a part of the in-panel gate circuit GIPC.

[0233] Reference Figure 8 In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may be disposed in the non-display area NDA, may be disposed on the passivation layer 610, and may overlap with a plurality of gate clock lines GCLKL.

[0234] Reference Figure 8 In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may be spaced apart from the common electrode CE and may not overlap with the common electrode CE in the vertical direction.

[0235] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a non-metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer 800 may include a fluorine-based material.

[0236] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer 800 may include at least one of barium, magnesium, cerium, lanthanum, and titanium.

[0237] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a non-metal having a moisture and oxygen barrier or trapping property and a metal having a moisture and oxygen barrier or trapping property.

[0238] As described above, in the reliability structure of the display panel 110 according to an embodiment of the present disclosure, the common electrode CE does not overlap with the plurality of gate clock lines GCLKL. Therefore, an unwanted parasitic capacitor can be prevented from being formed between the common electrode CE and the gate clock lines GCLKL.

[0239] The reliability structure of the display panel 110 according to an embodiment of the present disclosure can prevent an unnecessary load from being generated on the plurality of gate clock lines GCLKL by the common electrode CE, prevent distortion of the gate clock signal, and prevent an output deviation between the gate signals output by the gate driving circuit 130. Accordingly, a normal gate driving operation can be achieved.

[0240] The reliability structure of the display panel 110 according to an embodiment of the present disclosure can prevent an unnecessary parasitic capacitor from being formed between the plurality of gate clock lines GCLKL and the common electrode CE in the display panel 110. Accordingly, a parasitic capacitor deviation can naturally be prevented.

[0241] The reliability structure of the display panel 110 according to an embodiment of the present disclosure can prevent image quality degradation since there is no gate signal output deviation. For example, an abnormal horizontal line display phenomenon (i.e., line dark phenomenon) caused by the overlap of at least one of the plurality of gate clock lines GCLKL with the common electrode CE can be prevented.

[0242] The reliability structure of the display panel 110 according to an embodiment of the present disclosure can prevent a burn-out defect caused by static electricity generated when the common electrode CE overlaps with at least one of the plurality of gate clock lines GCLKL.

[0243] Figure 9A and Figure 9B shows the material of the shielding layer 800 in the display panel 110 according to an embodiment of the present disclosure.

[0244] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a non-metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer 800 may include a fluorine-based material.

[0245] For example, if the shielding layer 800 includes a fluorine-based material, due to its effect of blocking moisture and trapping oxygen, the reliability can be effectively improved by preventing moisture or oxygen from penetrating into the gate border region GBZ.

[0246] For example, with reference to Figure 9A and Figure 9B , the fluorine-based material may be a single molecule on a carbon-carbon backbone or a complex containing a large amount of fluorine (F). The fluorine-based solvent may be as shown in FIG. 9, and the shielding layer 800 containing the fluorine-based material may be as Figure 9B shown.

[0247] The material inspection of the shielding layer 800 can be performed by TOF-SIMS analysis.

[0248] The shielding layer 800 containing a fluorine-based material may have an orthogonality property due to the large amount of fluorine contained therein, and may be separated from and repel moisture (H 2 O).

[0249] The shielding layer 800 containing a fluorine-based material may be oxidized by oxygen to form a covalent bond with the fluorine-based material, thereby providing an oxygen capture effect.

[0250] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a metal having a blocking or capturing property for moisture and oxygen. For example, the shielding layer 800 may include at least one of barium, magnesium, cerium, lanthanum, and titanium.

[0251] In the display panel 110 according to an embodiment of the present disclosure, the shielding layer 800 may include a non-metal having a blocking or capturing property for moisture and oxygen and a metal having a blocking or capturing property for moisture and oxygen.

[0252] The reliability structure according to an embodiment of the present disclosure may be disposed in the non-display area NDA of the display panel 110. Accordingly, it is possible to fundamentally prevent or at least partially reduce the overlap of at least one gate clock line GCLKL disposed in the non-display area NDA of the display panel 110 with the common electrode CE.

[0253] The reliability structure according to an embodiment of the present disclosure may also be disposed in the display area DA of the display panel 110. Therefore, the case where the reliability structure according to an embodiment of the present disclosure is disposed in both the display area DA and the non-display area NDA of the display panel 110 will be described as an example below.

[0254] Figure 10 FIG. is a cross-sectional view of the display area DA and the non-display area NDA of the display panel 110 when the display panel 110 has a reliability structure according to an embodiment of the present disclosure.

[0255] Reference Figure 10 , the reliability structure according to an embodiment of the present disclosure may be disposed in the display area DA and the non-display area NDA of the display panel 110.

[0256] The vertical structure of the display panel 110 in which the reliability structure according to an embodiment of the present disclosure is disposed in the non-display area NDA may be the same as Figure 8 that shown. Therefore, the vertical structure of the display panel 110 in which the reliability structure according to an embodiment of the present disclosure is disposed in the display area DA will be described below, and the description of the vertical structure of the display panel 110 in which the reliability structure according to an embodiment of the present disclosure is disposed in the non-display area NDA will be omitted.

[0257] When the reliability structure according to an embodiment of the present disclosure is disposed in the display area DA of the display panel 110, it is possible to fundamentally prevent or at least partially reduce the overlap of at least one signal line DL, RVL, and VDDL disposed in the display area DA with the common electrode CE. Accordingly, it is possible to prevent or at least partially reduce an abnormal display driving operation and a screen abnormality that may occur when at least one signal line DL, RVL, and VDDL overlaps with the common electrode CE.

[0258] Reference Figure 10 , the reliability structure of the display panel 110 according to an embodiment of the present disclosure may be disposed in the non-display area NDA and the display area DA.

[0259] Reference Figure 10 , a gate driving related circuit may be disposed in the non-display area NDA of the display panel 110 according to an embodiment of the present disclosure. The gate driving related circuit may be disposed on the substrate SUB and may be disposed within a gate border area GBZ in the non-display area NDA.

[0260] The gate driving related circuit may include an in-panel gate circuit GIPC disposed on the substrate SUB, at least one first gate voltage line GVDDL disposed outside the in-panel gate circuit GIPC, at least one second gate voltage line GVSSL disposed inside the in-panel gate circuit GIPC, and a plurality of gate clock lines GCLKL disposed outside at least one first gate voltage line GVDDL.

[0261] Reference Figure 10 , in the non-display area NDA of the display panel 110 according to an embodiment of the present disclosure, a ground line GND may be disposed outside the plurality of gate clock lines GCLKL.

[0262] Reference Figure 10 , in the non-display area NDA of the display panel 110 according to an embodiment of the present disclosure, a passivation layer 610 may be disposed on the gate driving related circuit and the ground line GND.

[0263] An outer coating 620 and a bank 630 may be disposed on the passivation layer 610 by extending from a part of the display area DA to the non-display area NDA.

[0264] An intermediate layer EL may be disposed on the bank 630 by extending from a part of the display area DA to the non-display area NDA. Among them, the intermediate layer EL may be an organic layer.

[0265] The common electrode CE may be disposed on the intermediate layer EL by extending from a part of the display area DA to the non-display area NDA.

[0266] The common electrode CE may extend further outward than the intermediate layer EL.

[0267] The common electrode CE may extend along the sides of the bank portion 630 and the outer coating 620.

[0268] The first encapsulation layer 810 may be arranged to extend from the display area DA to a part of the non-display area NDA and cover the common electrode CE extending into the non-display area NDA.

[0269] In the non-display area NDA, the first encapsulation layer 810 may be arranged to extend further outward than the common electrode CE.

[0270] In the non-display area NDA, the first encapsulation layer 810 may be arranged to cover the shielding layer 800 that is set more outward than the common electrode CE.

[0271] Reference Figure 10 , according to the reliability structure of an embodiment of the present disclosure, the common electrode CE may extend to the non-display area NDA, but may not extend to the upper part of at least one gate clock line GCLKL, and the shielding layer 800 arranged more outward of the common electrode CE may be arranged to overlap at least one gate clock line GCLKL.

[0272] The width W1 of the shielding layer 800 may be greater than the width of the area where at least one gate clock line GCLKL overlapping with the shielding layer 800 is arranged.

[0273] According to the reliability structure of an embodiment of the present disclosure, it is possible to fundamentally prevent at least one gate clock line GCLKL arranged in the non-display area NDA of the display panel 110 from overlapping with the common electrode CE. This can prevent abnormal gate driving operations and display abnormalities that may occur when at least one gate clock line GCLKL overlaps with the common electrode CE.

[0274] Reference Figure 10 , the display area DA of the display panel 110 according to an embodiment of the present disclosure may include at least one signal line DL, RVL, and VDDL arranged on the substrate SUB, a pixel electrode PE arranged on the passivation layer 610, a bank portion 630 arranged on the pixel electrode PE and having a bank hole BH overlapping a part of the pixel electrode PE, an intermediate layer EL arranged in the bank hole BH and between the pixel electrode PE and the common electrode CE, and a common electrode CE arranged on the intermediate layer EL.

[0275] In the bank hole BH, the pixel electrode PE, the intermediate layer EL, and the common electrode CE may overlap to form a light-emitting device ED.

[0276] Reference Figure 10, in the display area DA of the display panel 110 according to an embodiment of the present disclosure, the intermediate layer EL and the common electrode CE can both be disposed on the upper part of the bank 630 and the bank hole (BH).

[0277] Reference Figure 10 , the display area DA of the display panel 110 according to an embodiment of the present disclosure may further include at least one shielding pattern 1000 disposed on the bank 630.

[0278] Since at least one shielding pattern 1000 is disposed on the bank 630, at least one shielding pattern 1000 may not overlap with the light-emitting device ED and may not overlap with the emission region formed by the light-emitting device ED.

[0279] Reference Figure 10 , in the display panel 110 according to an embodiment of the present disclosure, the first encapsulation layer 810 may be disposed on the shielding pattern 1000 and the common electrode CE in the display area DA, and on the shielding layer 800 and the common electrode CE in the non-display area NDA.

[0280] Reference Figure 10 , in the display panel 110 according to an embodiment of the present disclosure, the second encapsulation layer 820 may be disposed to cover the first encapsulation layer 810, and the third encapsulation layer 830 may be disposed on the second encapsulation layer 820.

[0281] In the display area DA of the display panel 110 according to an embodiment of the present disclosure, at least one shielding pattern 1000 may vertically overlap at least one signal line DL, RVL, and VDDL, and at least one signal line DL, RVL, and VDDL may vertically overlap the bank 630.

[0282] The width W2 of each shielding pattern 1000 may be greater than or equal to the width of the region where at least one signal line overlapping with each shielding pattern 1000 is disposed.

[0283] According to the reliability structure configured in the display area DA of the display panel 110 according to an embodiment of the present disclosure, at least one signal line DL, RVL, and VDDL, the bank 630, and at least one shielding pattern 1000 disposed in the display area DA may overlap in the vertical direction.

[0284] According to the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, in the display area DA, the common electrode CE may not be disposed on at least one shielding pattern 1000. That is, according to the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, in the display area DA, the common electrode CE may not overlap with at least one shielding pattern 1000, and the common electrode CE may not overlap with at least one signal line DL, RVL, and VDDL.

[0285] According to the display panel 110 according to an embodiment of the present disclosure, the shielding pattern 1000 disposed in the display area DA may include the same material as the shielding layer 800 disposed in the non-display area NDA.

[0286] According to the display panel 110 according to an embodiment of the present disclosure, at least one signal line DL, RVL, and VDDL overlapping with the shielding pattern 1000 disposed in the display area DA may include at least one of a data line DL, a reference voltage line RVL, and a first common driving voltage line VDDL.

[0287] According to the display panel 110 according to an embodiment of the present disclosure, if at least one signal line is the data line DL, the signal applied to at least one signal line may have a voltage that varies per frame.

[0288] According to the display panel 110 according to an embodiment of the present disclosure, if at least one signal line is the reference voltage line RVL or the first common driving voltage line VDDL, the signal applied to at least one signal line may have a constant voltage per frame.

[0289] Reference Figure 10 , the display area DA of the display panel 110 according to an embodiment of the present disclosure may further include a color filter CF overlapping with the pixel electrode PE. The color filter CF may be disposed between the passivation layer 610 and the outer coating layer 620.

[0290] According to the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, in the display area DA, in the area where the shielding pattern 1000 overlaps with the signal lines DL, RVL, or VDDL, the common electrode CE may be disconnected by the shielding pattern 1000.

[0291] According to the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, in the display area DA, the common electrode CE may not overlap with at least one shielding pattern 1000, and the common electrode CE may not overlap with at least one signal line DL, RVL, or VDDL. Accordingly, abnormal display driving operations and screen abnormalities that may occur due to the overlap of at least one signal line DL, RVL, or VDDL with the common electrode CE can be prevented.

[0292] According to the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, unwanted parasitic capacitance between the signal lines DL, RVL, or VDDL and the common electrode CE in the display area DA can be eliminated. Accordingly, the resistance-capacitance (RC) delay in the signal lines DL, RVL, and VDDL can be significantly reduced.

[0293] By reducing the RC delay by means of the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, high-speed driving of the display can be achieved. In addition, by reducing the RC delay by means of the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, the sensing time used to sense characteristic values (e.g., threshold voltage, mobility) of the sensing driving transistors can be reduced.

[0294] In addition, by reducing the RC delay by means of the reliability structure disposed in the display area DA of the display panel 110 according to an embodiment of the present disclosure, the width of the signal lines can be reduced. In this way, the aperture ratio of the display panel 110 can be increased by reducing the width of the signal lines made of metal.

[0295] Hereinafter, reference will be made to Figures 11 to 19 a method of manufacturing the display device 100 according to an embodiment of the present disclosure will be described.

[0296] Figures 11 to 19 A manufacturing process of the display device 100 according to an embodiment of the present disclosure is shown.

[0297] Reference Figures 11 to 16 , a method of manufacturing the display device 100 according to an embodiment of the present disclosure may include a transistor forming step (S10), a shielding layer forming step (S20), a photoresist forming step (S30), a photoresist developing step (S40), a shielding layer developing step (S50), and an intermediate layer / common electrode / cover layer forming step (S60).

[0298] Reference Figure 11, in the transistor formation step (S10), an in-panel gate circuit GIPC and a plurality of gate clock lines GCLKL can be formed on a substrate SUB in a non-display area NDA. Specifically, a plurality of gate clock lines GCLKL can be formed outside the in-panel gate circuit GIPC, a passivation layer 610 can be formed on the in-panel gate circuit GIPC and the plurality of gate clock lines GCLKL, and an insulating layer 620 and 630 can be formed on the passivation layer 610. Here, the insulating layer can include an outer coating 620 and a dam 630.

[0299] Reference Figure 11 , in the transistor formation step (S10), in a display area DA, a plurality of signal lines DL, RVL, and VDDL can be formed on a substrate SUB, a passivation layer 610 can be formed on the plurality of signal lines DL, RVL, and VDDL, an outer coating 620 can be formed on the passivation layer 610, a pixel electrode PE can be formed on the outer coating 620, and a dam 630 having a dam hole BH overlapping at least a part of the pixel electrode PE can be formed.

[0300] Reference Figure 12 , in the shielding layer formation step (S20), a shielding layer 800 can be formed on the entire surface. That is, in the shielding layer formation step (S20), the shielding layer 800 can be formed in both the display area DA and the non-display area NDA. For example, the shielding layer 800 can include a material having a moisture and oxygen barrier or trapping property.

[0301] The shielding layer 800 can include a non-metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer 800 can include a fluorine-based material.

[0302] The shielding layer 800 can include a metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer 800 can include at least one of barium, magnesium, cerium, lanthanum, and titanium.

[0303] The shielding layer 800 can include a non-metal having a moisture and oxygen barrier or trapping property and a metal having a moisture and oxygen barrier or trapping property.

[0304] Reference Figure 13 , in the photoresist formation step (S30), a photoresist 1300 can be formed on the shielding layer 800. The photoresist 1300 can be formed in both the display area DA and the non-display area NDA.

[0305] Reference Figure 14 , in the photoresist development step (S40), the photoresist 1300 can be developed, but the photoresist 1300 can only remain or be retained in a first area A1 in the non-display area NDA.

[0306] In the photoresist developing step (S40), the photoresist 1300 may remain or be retained on each of a plurality of third regions A3 that overlap with a plurality of signal lines DL, RVL, and VDDL within the display area DA.

[0307] Reference Figure 15 , in the mask layer developing step (S50), the mask layer 800 may be developed, but the mask layer 800 may remain or be retained in the second region A2 that overlaps with the first region A1.

[0308] In the mask layer developing step (S50), the mask layer 800 may remain or be retained in each of a plurality of fourth regions A4 that overlap with a plurality of third regions A3. The mask layer 800 retained in the plurality of fourth regions A4 may overlap with a plurality of signal lines DL, RVL, and VDDL.

[0309] Reference Figure 15 , the second region A2 where the mask layer 800 remains may have a size smaller than the size of the first region A1 where the photoresist remains. Accordingly, each of the plurality of fourth regions A4 where the mask layer 800 is retained may be smaller than each of the plurality of third regions A3 where the photoresist 1300 is retained. Thus, an undercut structure in which the side surface of the mask layer 800 is recessed inward compared to the side surface of the photoresist 1300 may be formed.

[0310] Reference Figure 15 , the second region A2 where the mask layer 800 remains may overlap with the region where a plurality of gate clock lines GCLKL are formed. The mask layer 800 retained in the second region A2 may overlap with a plurality of gate clock lines GCLKL.

[0311] Reference Figure 15 , in the intermediate layer / common electrode / cover layer forming step (S60), an intermediate layer EL included in the light-emitting device ED may be deposited on the photoresist 1300. Due to the undercut structure in which the mask layer 800 below the photoresist 1300 is recessed, the intermediate layer EL may be disconnected in the region where the undercut structure is formed. That is, around the photoresist 1300 remaining in the first region A1 and the plurality of third regions A3, the intermediate layer EL may be formed in a disconnected state.

[0312] Reference Figure 16, in the intermediate layer / common electrode / cover layer forming step (S60), the common electrode CE can be deposited. At this time, due to the undercut structure of the recessed shielding layer 800 below the photoresist 1300, the common electrode CE can be disconnected in the area where the undercut structure is formed. That is, the common electrode CE can be formed in a disconnected state around the remaining photoresist 1300 in the first area A1 and the plurality of third areas A3. The common electrode CE provided on the shielding layer 800 and the photoresist 1300 and the common electrode CE around it can be separated from each other.

[0313] That is, in the intermediate layer / common electrode / cover layer forming step (S60), the common electrode CE can be deposited in a disconnected state between the photoresist 1300 remaining only in the first area A1 and the insulating layers 620 and 630.

[0314] Reference Figure 16 , in the intermediate layer / common electrode / cover layer forming step (S60), the cover layer 640 can be deposited. At this time, due to the undercut structure of the shielding layer 800 being cut or recessed below the photoresist 1300, the cover layer 640 can be disconnected in the area where the undercut structure is formed. That is, the cover layer 640 provided on the shielding layer 800 and the cover layer 640 provided in the display area DA can be separated from each other.

[0315] Reference Figures 17 to 19 , the manufacturing method of the display device 100 according to an embodiment of the present disclosure may further include an upper shielding layer removing step (S70) and a packaging layer forming step (S80, S90).

[0316] Reference Figure 17 , in the upper shielding layer removing step (S70), the remaining photoresist 1300 in the first area A1 and the plurality of third areas A3 can be removed, and the common electrode CE provided on the remaining photoresist 1300 in the first area A1 and the plurality of third areas A3 can be removed. At this time, a certain thickness of the upper layer of the shielding layer 800 can also be removed. The shielding layer 800 formed in the display area DA can also be referred to as the shielding pattern 1000.

[0317] After the upper shielding layer removing step (S70), the overlapping part of the common electrode CE and the plurality of gate clock lines GCLKL can be removed, and the overlapping part of the common electrode CE and the plurality of signal lines DL, RVL, and VDDL can be removed.

[0318] Reference Figure 18 , in the packaging layer forming step (S80), the first packaging layer 810 can be formed. For example, the first packaging layer 810 can include an inorganic layer, and in some cases, can include an organic layer.

[0319] Reference Figure 18, the first encapsulation layer 810 may be disposed on the shielding layer 800 and the common electrode CE.

[0320] In the non-display area NDA, the first encapsulation layer 810 may be interposed between the shielding layer 800 and the common electrode CE. Accordingly, the first encapsulation layer 810 may separate the shielding layer 800 and the common electrode CE from each other.

[0321] In the display area (DA), the first encapsulation layer 810 may be interposed between the disconnection spaces of the common electrode CE. Accordingly, the common electrode CE may be separated from each other through the first encapsulation layer 810.

[0322] Reference Figure 19 , in the second and third encapsulation layer forming steps (S90), a second encapsulation layer 820 may be formed to cover the first encapsulation layer 810, and a third encapsulation layer 830 may be formed on the second encapsulation layer 820.

[0323] For example, the first encapsulation layer 810 may be an inorganic film. The second encapsulation layer 820 may include an adhesive layer and may further include a moisture absorbent. The third encapsulation layer 830 may be a metal thin film.

[0324] The embodiments of the present disclosure described above are briefly described as follows.

[0325] A display device according to an embodiment of the present disclosure may include: a substrate divided into a display area and a non-display area; a gate driving circuit disposed on the substrate and in the non-display area; a plurality of gate clock lines disposed on the substrate and outside the gate driving circuit; a passivation layer disposed on the gate driving circuit and the plurality of gate clock lines; a common electrode disposed on the passivation layer and not overlapping with the plurality of gate clock lines; and a shielding layer located in the non-display area, disposed on the passivation layer, and overlapping with the plurality of gate clock lines. The common electrode is disposed on the passivation layer, inside the shielding layer, and spaced apart from the shielding layer in the lateral direction.

[0326] A display device according to an embodiment of the present disclosure may further include: a first encapsulation layer disposed on the shielding layer and the common electrode and interposed between the shielding layer and the common electrode.

[0327] The shielding layer and the common electrode may be separated from each other by the first encapsulation layer.

[0328] The first encapsulation layer may cover the upper surface and the side surface of the shielding layer.

[0329] A display device according to an embodiment of the present disclosure may further include: a covering layer disposed between a part of the common electrode and a part of the first encapsulation layer.

[0330] The display device according to an embodiment of the present disclosure may further include: an outer coating disposed on the passivation layer.

[0331] The common electrode may be disposed on the outer coating and may extend to be disposed on the outer surface of the outer coating.

[0332] The display device according to an embodiment of the present disclosure may further include an intermediate common layer, which is part of the layer for constructing the light-emitting device in the display area and includes at least one organic film extending from the display area to a part of the non-display area.

[0333] The intermediate common layer may overlap at least a part of the gate driving circuit.

[0334] The display device according to an embodiment of the present disclosure may further include: at least one first gate voltage line disposed between the gate driving circuit and a plurality of gate clock lines and configured to transmit a first gate voltage to the gate driving circuit; and at least one second gate voltage line disposed between the gate driving circuit and the display area and configured to transmit a second gate voltage different from the first gate voltage to the gate driving circuit.

[0335] The common electrode may not overlap with at least one first gate voltage line, but may overlap with at least one second gate voltage line.

[0336] The display device according to an embodiment of the present disclosure may further include a ground line disposed outside the plurality of gate clock lines.

[0337] In the display device according to an embodiment of the present disclosure, the shielding layer may include a non-metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer may include a fluorine-based material.

[0338] In the display device according to an embodiment of the present disclosure, the shielding layer may be spaced apart from the common electrode and may not overlap with the common electrode in the vertical direction.

[0339] In the display device according to an embodiment of the present disclosure, the shielding layer may include a metal having a moisture and oxygen barrier or trapping property. For example, the shielding layer may include at least one of barium, magnesium, cerium, lanthanum, and titanium.

[0340] The display device according to an embodiment of the present disclosure may further include: at least one signal line disposed on the substrate; a pixel electrode disposed on the passivation layer; a bank disposed on the pixel electrode and having a bank hole overlapping a part of the pixel electrode; an intermediate layer disposed in the bank hole and between the pixel electrode and the common electrode; at least one shielding pattern disposed on the bank; and a first encapsulation layer disposed on the at least one shielding pattern and the common electrode.

[0341] The common electrode may not be provided on at least one shielding pattern, and at least one shielding pattern may overlap at least one signal line in the vertical direction.

[0342] The shielding pattern may include the same material as the shielding layer. For example, the shielding pattern and the shielding layer may be formed by depositing together during the process. Therefore, the shielding pattern may also be referred to as the shielding layer.

[0343] The common electrode may be disconnected by the shielding pattern in the region where at least one shielding pattern overlaps at least one signal line. That is, in the region where at least one shielding pattern overlaps at least one signal line, there may be no common electrode.

[0344] A display device according to an embodiment of the present disclosure may include: a substrate having a display area and a non-display area; at least one signal line provided on the substrate and disposed in the display area; an outer coating provided on the at least one signal line; a pixel electrode provided on the outer coating; a bank having a bank hole overlapping at least a part of the pixel electrode; a common electrode provided on the bank and extending inside the bank hole; and a shielding pattern provided on the bank.

[0345] According to an embodiment of the present disclosure, the common electrode may be disconnected by the shielding pattern, and the shielding pattern may overlap at least one signal line. At least one signal line may not overlap with the common electrode.

[0346] A method of manufacturing a display device according to an embodiment of the present disclosure may include: a first step in which a gate driving circuit and a plurality of gate clock lines are formed in a non-display area around the display area on the substrate, a plurality of gate clock lines are formed outside the gate driving circuit, a passivation layer is formed on the gate driving circuit and the plurality of gate clock lines, and an outer coating and a bank are formed on the passivation layer; a second step in which a shielding layer is formed in the display area and the non-display area; a third step in which a photoresist is formed on the shielding layer; a fourth step in which the photoresist is developed and the photoresist remains in a first area in the non-display area; a fifth step in which the shielding layer is developed and the shielding layer remains in a second area overlapping the first area; and a sixth step in which a common electrode is deposited.

[0347] The shielding layer remaining in the second area in the fifth step may overlap the plurality of gate clock lines.

[0348] In the first step, in the display area, at least one signal line may be formed on the substrate, a passivation layer may be formed on the plurality of signal lines, an outer coating may be formed on the passivation layer, a pixel electrode may be formed on the outer coating in the display area, and a bank having a bank hole overlapping at least a part of the pixel electrode may be formed.

[0349] In the fourth step, photoresist may be left or retained in a plurality of third regions that overlap with a plurality of signal lines in the display region.

[0350] In the fifth step, a shielding layer may be left or retained in a plurality of fourth regions that overlap with the plurality of third regions. The shielding layer retained in the plurality of fourth regions overlaps with the plurality of signal lines.

[0351] The second region may overlap with the first region and may be smaller than the first region. Each of the plurality of fourth regions may be smaller than each of the plurality of third regions.

[0352] In the sixth step, a common electrode may be formed in a disconnected state around the photoresist retained in the first region and the plurality of third regions.

[0353] The method of manufacturing a display device according to an embodiment of the present disclosure may further include a seventh step after the sixth step, in which the remaining photoresist in the first region and the plurality of third regions is removed, and the common electrode provided on the remaining photoresist in the first region and the plurality of third regions is removed.

[0354] After the seventh step, the common electrode in the portion overlapping with the plurality of gate clock lines may be removed, and the portion where the common electrode overlaps with the plurality of signal lines may be removed. Thus, the common electrode may be retained only in the portion that does not overlap with the plurality of gate clock lines and the portion that does not overlap with the plurality of signal lines.

[0355] The method of manufacturing a display device according to an embodiment of the present disclosure may further include an eighth step after the seventh step, in which a first encapsulation layer is formed.

[0356] The first encapsulation layer may be provided on the shielding layer and the common electrode and may include an inorganic layer.

[0357] In the non-display region, the first encapsulation layer may be interposed between the shielding layer and the common electrode such that the first encapsulation layer separates the shielding layer and the common electrode from each other.

[0358] In the display region, the first encapsulation layer may be interposed between the disconnected spaces of the common electrodes such that the first encapsulation layer separates the common electrodes from each other.

[0359] For example, the shielding layer may include a material having a barrier or trapping property against moisture and oxygen. For example, the shielding layer may include a metal having a barrier or trapping property against moisture and oxygen; for another example, the shielding layer may include a non-metal having a barrier or trapping property against moisture and oxygen.

[0360] According to the embodiments of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided. The reliability structure can prevent abnormal operations of the gate driving circuit that may occur in a display panel having a built-in gate driving circuit.

[0361] According to the embodiments of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided. The reliability structure can prevent display abnormalities that may occur in a display panel having a built-in gate driving circuit.

[0362] According to the embodiments of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided. The reliability structure can prevent output deviation of gate signals in the gate driving circuit.

[0363] According to the embodiments of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided. The reliability structure can prevent load deviation between gate clock lines input to the gate driving circuit.

[0364] According to the embodiments of the present disclosure, a display device having a reliability structure and a manufacturing method thereof can be provided. The reliability structure can prevent burnout defects in at least one gate clock line that may occur in a display panel having a built-in gate driving circuit.

[0365] According to the embodiments of the present disclosure, the weight of the display device can be reduced by implementing a narrow bezel structure.

[0366] The above description and the drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. Various modifications, additions, and substitutions to the embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

Claims

1. A display device, comprising: A substrate, the substrate being divided into a display area and a non-display area; a gate driving circuit, the gate driving circuit being disposed on the substrate and in the non-display area; A plurality of gate clock lines, wherein the plurality of gate clock lines are arranged on the substrate and arranged outside the gate driving circuit; A passivation layer, the passivation layer being disposed on the gate drive circuit and the plurality of gate clock lines; a shielding layer, the shielding layer being located in the non-display area, being disposed on the passivation layer, and overlapping the plurality of gate clock lines; as well as A common electrode is disposed on the passivation layer, disposed inside the shielding layer and spaced apart from the shielding layer in a lateral direction.

2. The display device according to claim 1 , further comprising a first encapsulation layer, the first encapsulation layer being disposed on the shielding layer and the common electrode and being interposed between the shielding layer and the common electrode, in, The shielding layer and the common electrode are separated from each other by the first encapsulation layer.

3. The display device according to claim 2, wherein: The first encapsulation layer covers both the upper surface and the side surfaces of the shielding layer.

4. The display device according to claim 2, further comprising: A covering layer is disposed between a portion of the common electrode and a portion of the first encapsulation layer.

5. The display device according to claim 1, further comprising: an outer coating layer, the outer coating layer being disposed on the passivation layer, Wherein, the common electrode is disposed on the outer coating layer and extends to be disposed on an outer side surface of the outer coating layer.

6. The display device according to claim 1, further comprising: an intermediate common layer which is part of a layer for constructing the light emitting device in the display area and includes at least one organic film extending from the display area to a part of the non-display area, Wherein, the middle common layer overlaps with at least a portion of the gate driving circuit.

7. The display device according to claim 1, further comprising: at least one first gate voltage line, the at least one first gate voltage line being disposed between the gate driving circuit and the plurality of gate clock lines and configured to transmit a first gate voltage to the gate driving circuit; as well as At least one second gate voltage line is disposed between the gate driving circuit and the display area and is configured to transmit a second gate voltage different from the first gate voltage to the gate driving circuit.

8. The display device according to claim 7, wherein: The common electrode does not overlap with the at least one first gate voltage line but overlaps with the at least one second gate voltage line. 9 . The display device according to claim 1 , further comprising a ground line disposed at a further outer side of the plurality of gate clock lines.

10. The display device according to claim 1, wherein: The shielding layer is spaced apart from the common electrode and does not overlap with the common electrode in a vertical direction.

11. The display device according to claim 1, further comprising: at least one signal line, wherein the at least one signal line is disposed on the substrate; A pixel electrode, wherein the pixel electrode is disposed on the passivation layer; a bank, the bank being disposed on the pixel electrode and having a bank hole overlapping a portion of the pixel electrode; an intermediate layer, the intermediate layer being disposed in the bank hole and between the pixel electrode and the common electrode; at least one shielding pattern, the at least one shielding pattern being disposed on the bank; as well as a first encapsulation layer, the first encapsulation layer being disposed on the at least one shielding pattern and the common electrode, wherein the common electrode is not disposed on the at least one shielding pattern, The at least one shielding pattern overlaps with the at least one signal line in a vertical direction.

12. The display device according to claim 11, wherein: The shielding pattern includes the same material as the shielding layer.

13. The display device according to claim 11, wherein: In a region where at least one shielding pattern and at least one signal line overlap, the common electrode is disconnected by the shielding pattern.

14. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; at least one signal line, the at least one signal line being disposed on the substrate and in the display area; an outer coating, the outer coating being disposed on the at least one signal line; A pixel electrode, wherein the pixel electrode is disposed on the outer coating layer; a bank having a bank hole overlapping at least a portion of the pixel electrode; a common electrode, the common electrode being disposed on the bank and extending inside the bank hole; as well as a shielding pattern, the shielding pattern being disposed on the bank, The common electrode is disconnected by the shielding pattern, and the shielding pattern overlaps with at least one signal line.

15. A method for manufacturing a display device, comprising: forming a gate driving circuit and a plurality of gate clock lines in a non-display area surrounding a display area on a substrate, forming the plurality of gate clock lines outside the gate driving circuit, forming a passivation layer on the gate driving circuit and the plurality of gate clock lines, and forming an outer coating layer and a bank on the passivation layer; forming a shielding layer in the display area and the non-display area; forming a photoresist on the shielding layer; developing the photoresist and leaving the photoresist in a first area in the non-display area; developing the shielding layer and retaining the shielding layer in a second region overlapping the first region; as well as Deposition of common electrode, Wherein, the shielding layer remaining in the second region when the shielding layer is developed overlaps with the plurality of gate clock lines.

16. The method according to claim 15, wherein: In the display area, a plurality of signal lines are formed on the substrate, a passivation layer is formed on the plurality of signal lines, an overcoat layer is formed on the passivation layer, a pixel electrode is formed on the overcoat layer, and a bank having a bank hole overlapping at least a portion of the pixel electrode is formed, wherein retaining the photoresist comprises retaining the photoresist in each of a plurality of third regions overlapping the plurality of signal lines in the display area, wherein retaining the shielding layer comprises retaining the shielding layer in each of a plurality of fourth regions overlapping the plurality of third regions, The shielding layer remaining in the plurality of fourth regions overlaps with the plurality of signal lines.

17. The method according to claim 16, wherein: The second area is smaller than the first area, Each of the plurality of fourth regions is smaller than each of the plurality of third regions.

18. The method according to claim 16, wherein: Depositing a common electrode includes forming the common electrode in an open state around the photoresist remaining in the first region and the plurality of third regions.

19. The method according to claim 16, further comprising: After depositing the common electrode, removing the remaining photoresist in the first region and the plurality of third regions, and removing the common electrode disposed on the remaining photoresist in the first region and the plurality of third regions; After the common electrode is removed, the common electrode in a portion overlapping with the plurality of gate clock lines is removed, and the common electrode in a portion overlapping with the plurality of signal lines is removed.

20. The method according to claim 19, wherein: The method further includes forming a first encapsulation layer after removing the common electrode, Wherein, the first encapsulation layer is disposed on the shielding layer and the common electrode and comprises an inorganic film, Wherein, in the non-display area, the first encapsulation layer is interposed between the shielding layer and the common electrode, so that the shielding layer and the common electrode are separated from each other by the first encapsulation layer. Wherein, in the display area, the first encapsulation layer is interposed between the disconnected spaces of the common electrodes, and the common electrodes are separated from each other by the first encapsulation layer.

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