Semiconductor device including selector and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device including a selector and a method of manufacturing the semiconductor device. A method for manufacturing a semiconductor device includes: forming a first electrode layer; forming a plurality of dielectric layers over the first electrode layer, wherein one or more metal-containing patterns or one or more metal-containing thin films are disposed between at least two adjacent dielectric layers of the plurality of dielectric layers; and forming a selector layer by performing a first implantation process to implant dopants into at least two adjacent dielectric layers including the one or more metal-containing patterns or the one or more metal-containing thin films or in contact therewith.

Description

[0001] Cross - reference to related applications

[0002] This patent document claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0179471, filed on December 12, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] The technology disclosed in this patent document relates to a semiconductor device including a selector and a method of manufacturing a semiconductor device. Background art

[0004] With the recent trend in the electrical and electronics industries towards miniaturization, low power consumption, high performance, and diversification, the importance of semiconductor devices capable of storing data in various electronic devices such as computers and portable communication devices has been increasing. Such semiconductor devices include semiconductor devices that can store data by using the characteristic of switching between different resistance states according to an applied voltage or current, for example, resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electronic fuse (E - fuse). Summary of the invention

[0005] The disclosed technology may be implemented in some embodiments to provide a semiconductor device and a method of manufacturing the same that can ensure the characteristics of a selector.

[0006] In an embodiment of the disclosed technology, a method of manufacturing a semiconductor device includes: forming a first electrode layer; forming a plurality of dielectric layers over the first electrode layer, wherein one or more metal - containing patterns or one or more metal - containing thin films are disposed between at least two adjacent dielectric layers of the plurality of dielectric layers; and forming a selector layer by performing a first implantation process to implant dopants into at least two adjacent dielectric layers including one or more metal - containing patterns or one or more metal - containing thin films or in contact therewith. In some implementations, the plurality of dielectric layers having one or more metal - containing patterns or one or more metal - containing thin films may be formed by stacking the plurality of dielectric layers and one or more metal - containing patterns or one or more metal - containing thin films in a certain order.

[0007] In another embodiment of the disclosed technology, a semiconductor device includes: a first electrode layer; and a selector layer configured to exhibit threshold switching behavior and disposed over the first electrode layer. In some implementations, the selector layer includes: a dielectric layer; a dopant configured to form trap sites that provide channels for conductive carriers in the dielectric layer; and metal ions distributed in the dielectric layer. Brief description of the drawings

[0008] Figure 1 is a perspective view of a semiconductor device showing an embodiment based on the disclosed technology.

[0009] Figure 2A and Figure 2B is a cross-sectional view of a method for forming a selector unit showing an embodiment based on the disclosed technology.

[0010] Figure 3A and Figure 3B is a cross-sectional view of a method for forming a selector unit and the selector unit thus formed showing another embodiment based on the disclosed technology.

[0011] Figure 3C is a cross-sectional view of a selector unit showing another embodiment based on the disclosed technology.

[0012] Figure 4A and Figure 4B is a cross-sectional view of a method for forming a selector unit and the selector unit thus formed showing another embodiment based on the disclosed technology.

[0013] Figure 4C is a cross-sectional view of a selector unit showing another embodiment based on the disclosed technology.

[0014] Figure 5A and Figure 5B is a cross-sectional view of a method for forming a selector unit and the selector unit thus formed showing another embodiment based on the disclosed technology.

[0015] Figures 6A to 6C is a cross-sectional view of a method for forming a selector unit and the selector unit thus formed showing another embodiment based on the disclosed technology.

[0016] Figure 7A and Figure 7B is a cross-sectional view of a method for forming a selector unit and the selector unit thus formed showing another embodiment based on the disclosed technology. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the disclosed technology will be described in more detail with reference to the accompanying drawings.

[0018] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it means not only that the first layer is directly formed on the second layer or the substrate, but also that a third layer is present between the first layer and the second layer or the substrate.

[0019] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0020] Figure 1 is a perspective view showing a semiconductor device according to an embodiment of the disclosed technology.

[0021] Referring Figure 1 , the semiconductor device of this embodiment of the disclosed technology may include a substrate 100, a plurality of first wires 110, a plurality of second wires 120, and a plurality of memory cells MC. In some embodiments of the disclosed technology discussed below, a first direction D1 may be substantially perpendicular to the surface of the substrate 100, while a second direction D2 and a third direction D3 may be substantially parallel to the surface of the substrate 100. The second direction D2 and the third direction D3 may cross each other. For example, the second direction D2 and the third direction D3 may be perpendicular to each other.

[0022] The substrate 100 may include a semiconductor material, such as a silicon wafer. In some embodiments, a lower structure (not shown), such as an integrated circuit, for driving (e.g., controlling, selecting, activating, etc.) the first wires 110 and / or the second wires 120 may be formed in and / or on the substrate 100.

[0023] The plurality of first wires 110 may be disposed on the substrate 100. The first wires 110 may extend along the second direction D2 and may be spaced apart from each other in the third direction D3. The first wires 110 may include various conductive materials, for example, metals (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), etc.), metal nitrides (such as titanium nitride (TiN) and tantalum nitride (TaN), etc.), or a combination thereof, and the first wires 110 may have a single-layer structure or a multi-layer structure.

[0024] The plurality of second wires 120 may be disposed to be spaced apart from the first wires 110 above the first wires 110. The second wires 120 may extend along the third direction D3 and may be spaced apart from each other in the second direction D2. The second wires 120 may include various conductive materials, for example, metals (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), and tantalum (Ta), etc.), metal nitrides (such as titanium nitride (TiN) and tantalum nitride (TaN), etc.), or a combination thereof, and the second wires 120 may have a single-layer structure or a multi-layer structure.

[0025] Multiple memory cells MC may be arranged to overlap with a cross - over region between a first wire 110 and a second wire 120. Each memory cell MC may include a memory component MU configured to store data, and a selector unit SU that controls access to the memory component MU. For example, each memory cell MC may include a stacked structure that includes a lower electrode layer 130, a selector layer 140, an intermediate electrode layer 150, a variable - resistance layer 160, and an upper electrode layer 170. Here, the selector unit SU may include the lower electrode layer 130, the selector layer 140, and the intermediate electrode layer 150, while the memory component MU may include the intermediate electrode layer 150, the variable - resistance layer 160, and the upper electrode layer 170. The intermediate electrode layer 150 may be shared by the selector unit SU and the memory component MU.

[0026] The lower electrode layer 130 and the upper electrode layer 170 may be disposed at a first end and a second end of the memory cell MC, respectively, for example, at a bottom end and a top end of the memory cell MC, respectively, and may transfer a voltage or current for the operation of the memory cell MC. The intermediate electrode layer 150 may electrically connect the selector layer 140 to the variable - resistance layer 160 and physically separate them from each other. The lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include various conductive materials, for example, metals (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), and titanium (Ti), etc.), metal nitrides (such as titanium nitride (TiN) and tantalum nitride (TaN), etc.), or combinations thereof. In some implementations, the lower electrode layer 130, the intermediate electrode layer 150, or the upper electrode layer 170 may include a carbon electrode.

[0027] The selector layer 140 may control access to the variable - resistance layer 160 within each memory cell MC and prevent possible current leakage between memory cells MC sharing the first wire 110 or the second wire 120. To this end, the selector layer 140 in each memory cell MC may exhibit threshold - switching characteristics between different electrical conductivity states, including: (1) a non - conductive state that blocks current flow through the selector layer 140 or allows a very small amount of current to flow when the voltage levels supplied to the top and bottom of the selector layer 140 are lower than a predetermined threshold voltage; and (2) a conductive state that allows electrical conduction such that current begins to flow through the selector layer 140 and rapidly increases when the voltage levels supplied to the top and bottom of the selector layer 140 are equal to or higher than the threshold voltage. Thus, by controlling the voltage supplied to the selector layer 140, the selector layer 140 may be turned on to be in a conductive state at a supply voltage level that is at or higher than the threshold voltage, and turned off to be in a non - conductive state at a supply voltage level lower than the threshold voltage.

[0028] In various embodiments, selector layer 140 may include a two-terminal threshold switch (OTS) material (such as diodes and chalcogenide-based materials), a mixed ionic electronic conductor (MIEC) material (such as metal chalcogenide-based materials), a metal insulator transition (MIT) material (such as NbO 2 , and VO 2 , etc.), or a tunneling dielectric material having a relatively wide bandgap (such as SiO 2 , and Al 2 O 3 , etc.).

[0029] In some embodiments, selector layer 140 may include a dielectric material containing dopants implanted by an ion implantation process. In one example, the dielectric material may include a silicon-containing dielectric material (such as silicon oxide, silicon nitride, and silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. The dopants may be used to trap the conductive carriers migrating in the dielectric material, or to create trap sites that provide a channel for the trapped conductive carriers to migrate again. To form trap sites, various elements that can create an energy potential in the dielectric material to accommodate conductive carriers may be used as dopants. For example, when the dielectric material includes a silicon-containing dielectric material, the dopants may include metals having a valence different from that of silicon, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. In addition, when the dielectric material includes a dielectric metal oxide or a dielectric metal nitride, the dopants may include silicon or a metal having a valence different from that of the metal in the metal oxide or metal nitride. For example, selector layer 140 may include silicon dioxide (SiO 2 ), into which arsenic (As) is implanted by an ion implantation method. When a voltage equal to or higher than the threshold voltage is applied to selector layer 140, the conductive carriers can migrate through the trap sites, and selector layer 140 is in an "on" state to allow current to flow through selector layer 140. When the voltage applied to selector layer 140 is reduced to a level lower than the threshold voltage, selector layer 140 transitions to an "off" state to not allow the conductive carriers to move and thus no current flows.

[0030] The variable resistance layer 160 may be part of a memory cell MC for storing data. To this end, the variable resistance layer 160 may exhibit variable resistance characteristics of switching between different resistance states according to an applied voltage. The variable resistance layer 160 may have a single-layer structure or a multi-layer structure including a plurality of materials used in a resistive random access memory (RRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), and a magnetic random access memory (MRAM), etc., such as transition metal oxides, metal oxides (such as perovskite-based materials), phase change materials (such as chalcogenide-based materials), ferroelectric materials, and ferromagnetic materials, etc. When the variable resistance layer 160 has a high resistance state, the data bit stored in the memory cell MC may correspond to "0", and when the variable resistance layer 160 has a low resistance state, the data bit stored in the memory cell MC may correspond to "1".

[0031] The memory cell MC may have a columnar shape overlapping with the cross-region of the first wire 110 and the second wire 120. Although Figure 1 the memory cell MC is shown to have a cylindrical shape, the disclosed technology is not limited thereto, and the memory cell MC may have a shape different from the cylindrical shape, such as a square column or an oval column. In some implementations, the layers 130 to 170 forming the memory cell MC are shown to have sidewalls aligned with each other by patterning using one mask, but the disclosed technology is not limited thereto. In some implementations, when the variable resistance layer 160 has a multi-layer structure such as a magnetic tunnel junction structure, it may be difficult to etch the layers 130 to 170 constituting the memory cell MC collectively. In this case, the selector layer 140 and the variable resistance layer 160 may be patterned separately by adopting different etching masks, and in this case, the selector layer 140 and the variable resistance layer 160 may include non-aligned sidewalls. The lower electrode layer 130 and the intermediate electrode layer 150 may be patterned together with the selector layer 140, and the upper electrode layer 170 may be patterned together with the variable resistance layer 160.

[0032] In some implementations, the layer structure of the memory cell MC is not limited to the shown layer structure, but the stacking order of the layers may be changed, or one or more layers may be omitted, or one or more layers may be added. For example, one or more of the lower electrode layer 130, the intermediate electrode layer 150, and the upper electrode layer 170 may be omitted. In some implementations, the positions of the selector layer 140 and the variable resistance layer 160 may be exchanged. In other words, the selector layer 140 may be disposed above the intermediate electrode layer 150, and the variable resistance layer 160 may be disposed below the intermediate electrode layer 150. In some implementations, one or more layers (not shown) may be added to the memory cell MC to improve the process or characteristics of the memory cell MC.

[0033] As described below, the disclosed technology may be implemented in some embodiments to provide a selector unit and a method for forming a selector unit to improve the characteristics of the selector unit in a semiconductor device. In some implementations, the selector layer of the selector unit is formed by implanting dopants into a dielectric material, as described below.

[0034] Figure 2A and Figure 2B is a cross-sectional view showing a method for forming a selector unit according to an embodiment of the disclosed technology.

[0035] Referring to Figure 2A , a first electrode layer 210 may be provided or formed. The first electrode layer 210 may substantially correspond to Figure 1 the lower electrode layer 130, as described above.

[0036] Subsequently, a dielectric layer 220 may be formed over the first electrode layer 210. The dielectric layer 220 may serve as a matrix for forming a selector and may be formed by a deposition process. For example, the dielectric layer 220 may include a silicon-containing dielectric material (such as silicon oxide, silicon nitride, and silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. In some implementations, the dielectric layer 220 may include silicon dioxide.

[0037] Subsequently, dopants may be implanted into the dielectric layer 220. The ion implantation may be performed in a direction from a vertical direction toward the dielectric layer 220, i.e., from top to bottom (see the arrow in Figure 2A ). The dopants may create trap sites that provide channels for conductive charge carriers (such as electrons or holes) migrating in the dielectric layer 220. The dopants may include elements having a valence different from that of the elements of the dielectric layer 220, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. When the dielectric layer 220 includes silicon dioxide, the dopants may include arsenic.

[0038] The dielectric layer containing the dopants implanted by the ion implantation process may form a selector layer 230, which is shown in Figure 2B .

[0039] Referring to Figure 2B , a selector layer 230 may be formed over the first electrode layer 210. The selector layer 230 may substantially correspond to Figure 1 the selector layer 140.

[0040] Subsequently, a second electrode layer 240 can be formed over the selector layer 230. The second electrode layer 240 can substantially correspond to Figure 1 the intermediate electrode layer 150.

[0041] Subsequently, although not shown, the first electrode layer 210, the selector layer 230, and the second electrode layer 240 can be patterned to form selector units.

[0042] In some implementations, during the ion implantation process of the dopant, elements of the first electrode layer 210, particularly metal ions, can be incorporated into the dielectric layer 220 and / or the selector layer 230 by using a dispersion mechanism. Thus, some elements of the first electrode layer 210 are distributed in the dielectric layer 220 and / or the selector layer 230. In Figure 2B M x+ represents metal ions in the selector layer 230. For example, when the first electrode layer 210 includes titanium nitride, titanium ions of the first electrode layer 210 can be incorporated into the dielectric layer 220 and / or the selector layer 230. The incorporation of titanium nitride and titanium ions of the first electrode layer 210 into the dielectric layer 220 and / or the selector layer 230 can occur through the following mechanism. When the dielectric layer 220 includes a material with a very large binding energy (such as silicon dioxide), elements with relatively large mass and size (such as arsenic (As)) can be implanted to break the bonds (such as chemical bonds) in the dielectric layer 220, and in this case, arsenic ions can collide with the surface of the first electrode layer 210. These metal ions are metal components, and when the metal ions are uniformly distributed in the selector layer 230 at an appropriate concentration, the switching characteristics can be improved. For example, the switching characteristics can be improved by reducing the formation voltage / threshold voltage of the selector layer 230.

[0043] However, when the metal ions are incorporated by the dispersion mechanism, it may be difficult to control the concentration and distribution of the metal ions. When the metal ions are incorporated by the dispersion mechanism, the metal ions are mainly concentrated in the part of the selector layer 230 adjacent to the interface with the first electrode layer 210, that is, the lower part of the selector layer 230 (see the P1 part in Figure 2B ). To increase the concentration of the metal ions and make them uniformly distributed in the selector layer 230, it is necessary to increase the ion implantation energy when the dopant is implanted. However, as the ion implantation energy increases, a part of the dielectric layer 220 may be lost, and it is difficult to ensure the selector layer 230 with the required thickness. In addition, the interface between the selector layer 230 and the first electrode layer 210 may become uneven, and the switching characteristics of the selector layer 230 may deteriorate. In addition, as the ion implantation energy increases, a part of the first electrode layer 210 may be lost during the ion implantation process.

[0044] The disclosed technology can be implemented in some embodiments to solve the above problems by enabling metal ions to be uniformly incorporated into the selector layer at an appropriate concentration without increasing the ion implantation energy when forming the selector unit.

[0045] Figure 3A and Figure 3B is a cross-sectional view showing a method for forming a selector unit and the selector unit thus formed according to another embodiment of the disclosed technology.

[0046] Referring to Figure 3A , a first electrode layer 310 can be provided.

[0047] Subsequently, a first dielectric layer 320-1 can be formed over the first electrode layer 310. The first dielectric layer 320-1 can be used to form at least a part of the selector and can be formed by a deposition process. For example, the first dielectric layer 320-1 can include a silicon-containing dielectric material (such as silicon oxide, silicon nitride, and silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. For example, the first dielectric layer 320-1 can include silicon dioxide.

[0048] Subsequently, a metal-containing pattern 330 can be formed over the first dielectric layer 320-1. The metal-containing pattern 330 can serve as a metal ion source. In some implementations, the metal-containing pattern 330 can correspond to a fine pattern as small as a few nanometers (nm) in size, such that it is prone to dispersion during subsequent dopant ion implantation processes. The metal-containing pattern 330 can have various island shapes, such as dot-shaped or strip-shaped. The maximum length of the metal-containing pattern 330 can be a few nanometers (nm). For example, the range of the maximum length of the metal-containing pattern 330 can be from 1 to 10 nanometers. For example, when the metal-containing pattern 330 has a spherical or spherical-like dot shape, it can have a diameter of a few nanometers. Additionally, for example, when the metal-containing pattern 330 has a predetermined thickness and has a strip shape (where the length of one axis in the plane is greater than the other axis), the thickness and / or the maximum length in the plane can reach a few nanometers. In some embodiments of the disclosed technology, the term "pattern" can be used to refer to a material layer formed by a patterning process using one or more masks.

[0049] The metal-containing pattern 330 may include a metal (such as tantalum (Ta), titanium (Ti), iridium (Ir), magnesium (Mg), tungsten (W), and platinum (Pt), etc.), a metal oxide containing one or more of these metals, a metal nitride containing one or more of these metals, or an alloy containing two or more of these metals. In addition, the metal-containing pattern 330 may be formed by a seeding process of atomic layer deposition (ALD) using a metal precursor, or may be formed by a nucleation and growth process of physical vapor deposition (PVD) under conditions that do not result in thin film deposition (such as low pressure, low RF power, and / or short time).

[0050] Subsequently, a second dielectric layer 320-2 may be formed over the first dielectric layer 320-1 on which the metal-containing pattern 330 is formed. The second dielectric layer 320-2 may be used to form at least a part of the selector, and it may be formed by a deposition process. For example, the second dielectric layer 320-2 may include a silicon-containing dielectric material (such as silicon oxide, silicon nitride, and silicon oxynitride, etc.), a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. The second dielectric layer 320-2 may include the same material as the first dielectric layer 320-1, such as silicon dioxide. In addition, the thickness of the second dielectric layer 320-2 may be substantially the same as the thickness of the first dielectric layer 320-1. However, the disclosed technology is not limited thereto, and in some embodiments, at least one of the material and thickness of the second dielectric layer 320-2 may be different from those of the first dielectric layer 320-1.

[0051] Subsequently, the metal-containing pattern 330 may be formed again over the second dielectric layer 320-2. The process conditions for forming the metal-containing pattern 330 over the first dielectric layer 320-1 and the process conditions for forming the metal-containing pattern 330 over the second dielectric layer 320-2 may be substantially the same. Even if the process conditions are the same, the number, shape, and position of the metal-containing pattern 330 may vary in many ways.

[0052] Although two dielectric layers 320-1 and 320-2 are formed based on some embodiments and a metal-containing pattern 330 is formed on each of the dielectric layers 320-1 and 320-2 after each process of forming the dielectric layers 320-1 and 320-2, the disclosed technology is not limited thereto. In another embodiment of the disclosed technology, a plurality of dielectric layers may be formed on the first electrode layer 310, and a metal-containing pattern 330 may be formed on each dielectric layer after the process of forming each dielectric layer. In addition, considering the concentration or distribution of metal ions, if necessary, the metal-containing pattern 330 on one or more specific dielectric layers may be omitted. In other words, when the first to Nth dielectric layers (where N is a natural number equal to or greater than 2) are formed on the first electrode layer 310, a metal-containing pattern 330 may be formed on each of the first to Nth dielectric layers. In some implementations, the metal-containing pattern 330 may not be formed on the tth dielectric layer among the first to Nth dielectric layers (where t is any number equal to or greater than 2 and equal to or less than N), but may be formed on each of the remaining dielectric layers. In any case, the metal-containing pattern 330 may be formed to be disposed between at least two adjacent dielectric layers in the dielectric layer. For example, the metal-containing pattern 330 may be formed on the first dielectric layer 320-1 and disposed between at least the first dielectric layer 320-1 and the second dielectric layer 320-2, and the metal-containing pattern 330 on the second dielectric layer 320-2 may be omitted.

[0053] Subsequently, dopants may be implanted into the first dielectric layer 320-1 and the second dielectric layer 320-2 on which the metal-containing pattern 330 is formed. The ion implantation process may be performed in a direction from the vertical direction toward the first dielectric layer 320-1 and the second dielectric layer 320-2, for example, in the direction from top to bottom (see Figure 3A the arrow in). The dopants may create trap sites that provide channels for conductive carriers (such as electrons or holes) migrating in the first dielectric layer 320-1 and the second dielectric layer 320-2. The dopants may be elements having a valence different from the valence of the elements in the first dielectric layer 320-1 and the second dielectric layer 320-2, such as aluminum (Al), lanthanum (La), niobium (Nb), vanadium (V), tantalum (Ta), tungsten (W), chromium (Cr), molybdenum (Mo), gallium (Ga), boron (B), indium (In), phosphorus (P), arsenic (As), antimony (Sb), germanium (Ge), carbon (C), or a combination thereof. When the first dielectric layer 320-1 and the second dielectric layer 320-2 include silicon dioxide, the dopants may include arsenic.

[0054] The first dielectric layer 320-1 and the second dielectric layer 320-2 containing the dopants implanted by the ion implantation process may form a selector layer 350, which is shown in Figure 3B illustrated.

[0055] Reference Figure 3B A selector layer 350 may be formed over the first electrode layer 310.

[0056] Subsequently, a second electrode layer 360 may be formed over the selector layer 350.

[0057] In some implementations, during the ion implantation process of the dopant, the dopant ions may collide with the metal-containing pattern 330, thereby dispersing and incorporating the metal ions of the metal-containing pattern 330 into the first dielectric layer 320-1 and the second dielectric layer 320-2. Thus, in addition to the implanted dopant, the selector layer 350 may further include metal ions incorporated by the dispersion method. The metal ions in the selector layer 350 may be represented by M X+ When the metal-containing pattern 330 is pre-formed in or on the first dielectric layer 320-1 and the second dielectric layer 320-2 in this way, the concentration or distribution of the metal ions in the selector layer 350 can be easily controlled. The following mechanism can make the metal ions uniformly incorporated into the selector layer. By controlling the position or number of the metal-containing patterns 330, the concentration or distribution of the metal ions can be controlled. For example, when the number of depositions of the dielectric layer increases and thus the number of formations of the metal-containing patterns also increases, the distribution of the metal ions can become uniform as the concentration of the metal ions increases.

[0058] In this way, the metal ions can be uniformly distributed in the selector layer 350 at an appropriate concentration, thereby improving the switching characteristics. For example, the switching characteristics can be improved by reducing the formation voltage / threshold voltage of the selector layer 350. Additionally, since the dispersion of the metal ions in the first electrode layer 310 is unnecessary, there is no need to increase the ion implantation energy when implanting the dopant. In other words, a relatively low ion implantation energy can be used, thereby ensuring the thickness of the selector layer 350, the thickness of the first electrode layer 310, and a uniform and clear interface between the selector layer 350 and the first electrode layer 310. Since the metal ions in the selector layer 350 do not originate from the first electrode layer 310, they may be the same as or different from the metal ions in the first electrode layer 310.

[0059] In some embodiments of the disclosed technology, during the ion implantation process of the dopant, the metal-containing pattern 330 may be completely removed and may exist in the selector layer 350 in the form of metal ions. However, the disclosed technology is not limited thereto, but a trace of the metal-containing pattern 330 may remain in the selector layer 350. This will be described with reference to Figure 3C this.

[0060] Figure 3C To show a cross-sectional view of a selector unit according to another embodiment of the disclosed technology.

[0061] Reference Figure 3C Referring to Figure 3C , traces 335 of the metal-containing pattern 330 may be present in the selector layer 350. The traces 335 of the metal-containing pattern 330 may be fine particles having a size smaller than the size of the metal-containing pattern 330, and the traces 335 of the metal-containing pattern 330 may also be referred to as metal-containing particles.

[0062] The traces 335 may exhibit a relatively high concentration in the region where the metal-containing pattern 330 was once disposed. In some implementations, the concentration of the traces 335 may reach a maximum value at the interface between the first dielectric layer 320-1 and the second dielectric layer 320-2 (e.g., corresponding to the dashed line in Figure 3C ), or at the interface between the selector layer 350 and the second electrode layer 360. For example, the concentration of the traces 335 may correspond to different positions, such as a specific point between the interface (such as, corresponding to the dashed line in Figure 3C ), and the interface between the selector layer 350 and the second electrode layer 360, or a specific point between the interface (such as, corresponding to the dashed line in Figure 3C ), and the interface between the first electrode layer 310 and the selector layer 350. The concentration distribution curve of the traces 335 is shown by way of example on the right side of the selector layer 350.

[0063] Figure 4A and Figure 4B are cross-sectional views of a method for forming a selector unit and a selector unit formed using the method, which illustrate another embodiment based on the disclosed technology. The following explanation will focus on the differences from the embodiments of Figure 3A and Figure 3B above.

[0064] Reference Figure 4A Figure 4A , a first electrode layer 410 may be provided.

[0065] Subsequently, a buffer layer 440 may be formed over the first electrode layer 410. The buffer layer 440 may serve to prevent or reduce the loss of the first electrode layer 410 that occurs when dopant ions reach the first electrode layer 410 during the ion implantation process of the dopant, as described below. In addition, the buffer layer 440 may be interposed between the first electrode layer 410 and the first dielectric layer 420-1, as described below, to improve the adhesion characteristics therebetween. The buffer layer 440 may be selectively formed. In other words, the buffer layer 440 may be omitted. The buffer layer 440 may include various materials containing non-conductive elements, such as SiB, SiCN, SiO 2, SiN, SiBN, or a combination thereof. The buffer layer 440 may include non-conductive elements so that even if the elements of the buffer layer 440 are present in the selector layer formed in subsequent processes, they do not participate in the operation of the selector layer. For example, the buffer layer 440 may include silicon nitride (SiN).

[0066] Subsequently, a metal-containing pattern 430 may be formed on the buffer layer 440. In some implementations, forming the metal-containing pattern 430 on the buffer layer 440 may also be optional.

[0067] Subsequently, a first dielectric layer 420-1, a metal-containing pattern 430, a second dielectric layer 420-2, and a metal-containing pattern 430 may be sequentially formed on the buffer layer 440 on which the metal-containing pattern 430 is formed.

[0068] Subsequently, dopants may be implanted into the buffer layer 440 on which the metal-containing pattern 430 is formed, as well as the first dielectric layer 420-1 and the second dielectric layer 420-2.

[0069] The first dielectric layer 420-1 and the second dielectric layer 420-2 containing dopants implanted through an ion implantation process may form a selector layer 450, which is shown in Figure 4B in.

[0070] Reference Figure 4B , the selector layer 450 may be formed on the first electrode layer 410.

[0071] Subsequently, a second electrode layer 460 may be formed on the selector layer 450.

[0072] During the ion implantation process of the dopants, the dopant ions may collide with the metal-containing pattern 430, and the metal ions of the metal-containing pattern 430 are controllably dispersed and uniformly incorporated into the first dielectric layer 420-1 and the second dielectric layer 420-2. Therefore, in addition to including the implanted dopants, the selector layer 450 may also include the dispersed and incorporated metal ions.

[0073] In addition, during the ion implantation process of the dopants, the buffer layer 440 may be mixed with the first dielectric layer 420-1 and the second dielectric layer 420-2, so that the elements of the buffer layer 440 may be included in the selector layer 450. In other words, the selector layer 450 may include all the elements of the first dielectric layer 420-1 and the second dielectric layer 420-2 as well as the elements of the buffer layer 440. For example, when the first dielectric layer 420-1 and the second dielectric layer 420-2 include silicon dioxide and the buffer layer 440 includes silicon nitride, the selector layer 450 may include silicon, oxygen, and nitrogen.

[0074] In an embodiment of the disclosed technology, during the ion implantation process of the dopant, the metal-containing pattern 430 may break and completely disappear, and only metal ions may exist in the selector layer 450. However, the disclosed technology is not limited thereto, and traces of the metal-containing pattern 430 may remain in the selector layer 450. This will be described below in conjunction with Figure 4C This will be described.

[0075] Figure 4C FIG. is a cross-sectional view of a selector unit according to another embodiment of the disclosed technology.

[0076] Referring to Figure 4C , traces 435 of the metal-containing pattern 430 may exist in the selector layer 450.

[0077] The traces 435 may exhibit a relatively high concentration in the region where the metal-containing pattern 430 was once disposed. For example, the concentration of the traces 435 may be at a maximum at the interface between the first dielectric layer 420-1 and the second dielectric layer 420-2 (e.g., corresponding to the upper dashed line in Figure 4C ), the interface between the buffer layer 440 and the first dielectric layer 420-1 (e.g., corresponding to the lower dashed line in Figure 4C ), or the interface between the selector layer 450 and the second electrode layer 460. The concentration distribution curve of the traces 435 is shown by way of example on the right side of the selector layer 450.

[0078] Figure 5A And Figure 5B FIGS. are cross-sectional views of a method for forming a selector unit according to another embodiment of the disclosed technology and the selector unit thus formed. The differences from the embodiments of Figure 3A And Figure 3B above will be explained below.

[0079] Referring to Figure 5A , a first electrode layer 510 may be formed.

[0080] Subsequently, a first dielectric layer 520-1 may be formed over the first electrode layer 510.

[0081] Subsequently, a first metal-containing thin film 530-1 can be formed on the first dielectric layer 520-1. The first metal-containing thin film 530-1 can correspond to a metal ion source, similar to the above-described metal-containing pattern. The thickness of the first metal-containing thin film 530-1 can be greater than 0 nm and equal to or less than 1 nm. In one example, the thickness of the first metal-containing thin film 530-1 can be greater than 0 nm but equal to or less than about 0.5 nm. The first metal-containing thin film 530-1 within these ranges can be easily dispersed and physically fragmented during subsequent dopant ion implantation processes. The first metal-containing thin film 530-1 can include a metal (such as tantalum (Ta), titanium (Ti), iridium (Ir), magnesium (Mg), tungsten (W), and platinum (Pt), etc.), a metal oxide containing one or more of these metals, a metal nitride containing one or more of these metals, or an alloy containing two or more of these metals, and the first metal-containing thin film 530-1 can be formed by various deposition methods, such as PVD or ALD.

[0082] Subsequently, a second dielectric layer 520-2 can be formed on the first metal-containing thin film 530-1.

[0083] Subsequently, a second metal-containing thin film 530-2 can be formed on the second dielectric layer 520-2. The second metal-containing thin film 530-2 can be formed of the same material and thickness as the first metal-containing thin film 530-1. However, the disclosed technology is not limited thereto, and at least one of the material and thickness of the second metal-containing thin film 530-2 can be different from that of the first metal-containing thin film 530-1.

[0084] As described above, in some embodiments, two dielectric layers 520-1 and 520-2 are formed, and after the process of forming dielectric layers 520-1 and 520-2, two metal-containing thin films 530-1 and 530-2 are formed on dielectric layers 520-1 and 520-2 respectively, but the disclosed technology is not limited thereto. In another embodiment of the disclosed technology, multiple dielectric layers may be formed on the first electrode layer 510, and metal-containing thin films may be formed on each dielectric layer after the process of forming each dielectric layer. In some implementations, considering the concentration or distribution of metal ions, the metal-containing thin film on a predetermined dielectric layer may be omitted if necessary. In other words, when the first to Nth dielectric layers (where N is a natural number equal to or greater than 2) are formed on the first electrode layer 510, metal-containing thin films may be formed on each of the first to Nth dielectric layers. However, the metal-containing thin film may not be formed on the tth dielectric layer (where t is any number equal to or greater than 2 and equal to or less than N) among the first to Nth dielectric layers, but may be formed only on each of the remaining dielectric layers. In any case, the metal-containing thin film may be formed to be disposed between at least two adjacent dielectric layers among the dielectric layers. For example, the first metal-containing thin film 530-1 may be retained and the second metal-containing thin film 530-2 may be omitted.

[0085] Subsequently, dopants may be implanted into the stacked structure of the first dielectric layer 520-1, the first metal-containing thin film 530-1, the second dielectric layer 520-2, and the second metal-containing thin film 530-2.

[0086] The first dielectric layer 520-1, the first metal-containing thin film 530-1, the second dielectric layer 520-2, and the second metal-containing thin film 530-2 containing the dopants implanted through the ion implantation process may form a selector layer 550, which is shown in Figure 5B .

[0087] Referring to Figure 5B , the selector layer 550 may be formed on the first electrode layer 510.

[0088] Subsequently, a second electrode layer 560 may be formed on the selector layer 550.

[0089] During the ion implantation process of the dopants, the dopant ions may collide with the first metal-containing thin film 530-1 and the second metal-containing thin film 530-2, and thus the metal ions of the first metal-containing thin film 530-1 and the second metal-containing thin film 530-2 are controllably dispersed and uniformly incorporated into the first dielectric layer 520-1 and the second dielectric layer 520-2. Therefore, in addition to the implanted dopants, the selector layer 550 may also include metal ions incorporated by the dispersion method.

[0090] In some embodiments of the disclosed technology, during the ion implantation process of the dopant, the first metal-containing thin film 530-1 and the second metal-containing thin film 530-2 may be completely removed and may exist in the selector layer 550 in the form of metal ions. However, the disclosed technology is not limited thereto, and traces of the first metal-containing thin film 530-1 and the second metal-containing thin film 530-2 may remain in the selector layer 550. Since the selector layer 550 with traces may be the same as or similar to that described in Figure 3C the detailed description thereof will be omitted.

[0091] Figure 6A and Figure 6B are cross-sectional views showing a method for forming a selector unit and the selector unit formed thereby according to another embodiment of the disclosed technology. The differences from the above Figure 5A and Figure 5B embodiments will be explained in detail below.

[0092] Referring to Figure 6A , a first electrode layer 610 may be provided.

[0093] Subsequently, a first dielectric layer 620-1 may be formed over the first electrode layer 610.

[0094] Subsequently, a first metal-containing thin film 630-1 may be formed over the first dielectric layer 620-1.

[0095] Subsequently, a main dopant may be implanted into the stacked structure of the first dielectric layer 620-1 and the first metal-containing thin film 630-1. When the main dopant is implanted, the dopant ions may collide with the first metal-containing thin film 630-1, and the metal ions of the first metal-containing thin film 630-1 may be controllably dispersed and uniformly incorporated into the first dielectric layer 620-1. As a result, an initial selector layer 640 as shown in Figure 6B may be formed.

[0096] Referring to Figure 6B , a second dielectric layer 620-2 may be formed over the initial selector layer 640, and a second metal-containing thin film 630-2 may be formed over the second dielectric layer 620-2.

[0097] Subsequently, a secondary dopant may be implanted into the stacked structure of the second dielectric layer 620-2 and the second metal-containing thin film 630-2. When the secondary dopant is implanted, the dopant ions may collide with the second metal-containing thin film 630-2, and the metal ions of the second metal-containing thin film 630-2 may be controllably dispersed and uniformly incorporated into the second dielectric layer 620-2. Depending on the ion implantation energy, when the secondary dopant is implanted, the dopant ions may also be incorporated into the initial selector layer 640. As a result, an as shown in Figure 6CSelector layer 650 shown.

[0098] Subsequently, a second electrode layer 660 can be formed over the selector layer 650.

[0099] Based on Figure 6A and Figure 6B Some embodiments can be different from embodiments based on Figure 5A and Figure 5B in that a dopant ion implantation process is additionally performed in the middle of the process of stacking dielectric layers and metal-containing thin films. For example, in the embodiments of Figure 5A and Figure 5B , after alternately stacking a plurality of dielectric layers and a plurality of metal-containing thin films, dopants can be implanted into the stacked structure. On the other hand, in some embodiments of the disclosed technology based on Figure 6A and Figure 6B , after forming one or more of the plurality of dielectric layers and forming a metal-containing thin film over each of the one or more dielectric layers, dopant ion implantation can be additionally performed. Compared with the embodiments based on Figure 5A and Figure 5B , in some embodiments of the disclosed technology based on Figure 6A and Figure 6B , even with a smaller ion implantation energy, dopants can be implanted and metal ions can be dispersed. Therefore, the thickness of the selector layer 650, the thickness of the first electrode layer 610, and a uniform and clear interface between the selector layer 650 and the first electrode layer 610 can be ensured.

[0100] Figure 7A and Figure 7B are cross-sectional views showing a method for forming a selector unit and the selector unit thus formed according to another embodiment of the disclosed technology. The following explanation will focus on the differences from the embodiments of Figure 5A and Figure 5B above.

[0101] Referring to Figure 7A , a first electrode layer 710 can be provided.

[0102] Subsequently, a buffer layer 740 can be formed over the first electrode layer 710. The buffer layer 740 can be formed selectively. In other words, the buffer layer 740 can be omitted. The buffer layer 740 can include a variety of materials containing non-conductive elements, such as SiB, SiCN, SiO 2 , SiN, SiBN, or a combination thereof.

[0103] Subsequently, a first metal-containing thin film 730-1 can be formed over the buffer layer 740. Forming the first metal-containing thin film 730-1 over the buffer layer 740 can also be optional.

[0104] Subsequently, a first dielectric layer 720-1, a second metal-containing thin film 730-2, a second dielectric layer 720-2, and a third metal-containing thin film 730-3 can be sequentially formed over the buffer layer 740.

[0105] Subsequently, dopants can be implanted into the stack structure of the buffer layer 740, the first metal-containing thin film 730-1, the first dielectric layer 720-1, the second metal-containing thin film 730-2, the second dielectric layer 720-2, and the third metal-containing thin film 730-3.

[0106] The buffer layer 740, the first metal-containing thin film 730-1, the first dielectric layer 720-1, the second metal-containing thin film 730-2, the second dielectric layer 720-2, and the third metal-containing thin film 730-3 containing dopants implanted through an ion implantation process can form a selector layer 750, which is shown in Figure 7B .

[0107] Reference Figure 7B , the selector layer 750 can be formed over the first electrode layer 710.

[0108] Subsequently, a second electrode layer 760 can be formed over the selector layer 750.

[0109] During the ion implantation process of the dopants, the dopant ions can collide with the first to third metal-containing thin films 730-1, 730-2, and 730-3, thereby dispersing and incorporating the metal ions of the first to third metal-containing thin films 730-1, 730-2, and 730-3 into the first and second dielectric layers 720-1 and 720-2. Therefore, in addition to the implanted dopants, the selector layer 750 can also include metal ions incorporated through the dispersion process.

[0110] In addition, during the ion implantation process of the dopants, the buffer layer 740 can be mixed with the first dielectric layer 720-1 and the second dielectric layer 720-2, such that the elements of the buffer layer 740 are also included in the selector layer 750.

[0111] In some embodiments of the disclosed technology, during the ion implantation process of the dopants, the first to third metal-containing thin films 730-1, 730-2, and 730-3 may fragment and completely disappear, while existing in the selector layer 750 in the form of metal ions. However, the disclosed technology is not limited thereto, and traces of the first to third metal-containing thin films 730-1, 730-2, and 730-3 can remain in the selector layer 750. Since the selector layer 750 with traces can be the same or similar to that described in Figure 4C , a detailed description thereof will be omitted.

[0112] In some embodiments of the disclosed technology, the characteristics of the selector can be ensured.

[0113] Only a few embodiments and examples are described. Enhancements and variations can be made to the disclosed embodiments as well as other embodiments based on what is described and illustrated in this patent document.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first electrode layer; forming a plurality of dielectric layers on the first electrode layer, wherein one or more metal-containing patterns or one or more metal-containing films are disposed between at least two adjacent dielectric layers among the plurality of dielectric layers; as well as A selector layer is formed by performing a first implantation process to implant dopants into the at least two adjacent dielectric layers including or contacting the one or more metal-containing patterns or the one or more metal-containing films, wherein the selector layer exhibits a threshold switching characteristic of switching between different electrical conductivity states in response to a voltage applied across the selector layer.

2. The method according to claim 1, wherein: The dopant forms trap sites that provide pathways for migration of conductive carriers in the plurality of dielectric layers.

3. The method according to claim 1, wherein: When the dopant is implanted, metal ions of the one or more metal-containing patterns or the one or more metal-containing films are dispersed and incorporated into the plurality of dielectric layers with a predetermined uniformity.

4. The method according to claim 1, wherein: The one or more metal-containing patterns have at least one of a dot shape and a stripe shape.

5. The method according to claim 1, wherein: The maximum length of the metal-containing pattern ranges from 1 to 10 nanometers.

6. The method according to claim 1, wherein: The thickness of the metal-containing film is greater than 0 nm and equal to or less than 1 nm.

7. The method according to claim 1, wherein: The plurality of dielectric layers include silicon dioxide; and The dopant includes arsenic.

8. The method according to claim 1, wherein: The one or more metal-containing patterns or the one or more metal-containing thin films include a metal different from the dopant and the first electrode layer.

9. The method according to claim 1, further comprising: After forming the first electrode layer and before forming the plurality of dielectric layers, A buffer layer including a non-conductive element is formed on the first electrode layer.

10. The method according to claim 9, wherein: The buffer layer includes silicon nitride.

11. The method according to claim 9, wherein: The buffer layer is mixed with the plurality of dielectric layers when the dopant is implanted.

12. The method according to claim 9, wherein: The one or more metal-containing patterns or the one or more metal-containing thin films are further formed on the buffer layer.

13. The method according to claim 1, wherein: The one or more metal-containing patterns or the one or more metal-containing thin films are further formed on an uppermost dielectric layer among the plurality of dielectric layers.

14. The method according to claim 1, further comprising: After forming one or more dielectric layers among the plurality of dielectric layers and forming the one or more metal-containing films over each of the one or more dielectric layers among the plurality of dielectric layers, a second implantation process is performed to implant dopants into the plurality of dielectric layers.

15. The method according to claim 1, wherein: As the dopant is implanted, the size of the metal-containing pattern decreases.

16. The method according to claim 1, wherein: When the dopant is implanted, the metal-containing film is broken.

17. A semiconductor device comprising: a first electrode layer; as well as a selector layer disposed on the first electrode layer and exhibiting a threshold switching characteristic of switching between different electrical conductivity states in response to a voltage applied across the selector layer relative to a threshold voltage, and Wherein, the selector layer includes: Dielectric layer; a dopant that forms trap sites that provide pathways for conductive carriers in the dielectric layer; and Metal ions are incorporated into the dielectric layer.

18. The semiconductor device according to claim 17, wherein: The selector layer further includes: metal-containing particles in the dielectric layer; and The metal contained in the metal-containing particles corresponds to the metal of the metal ions.

19. The semiconductor device according to claim 18, wherein: The dielectric layer comprises a plurality of dielectric layers; and The concentration of the metal-containing particles is greatest at an interface between at least two adjacent dielectric layers of the plurality of dielectric layers.

20. The semiconductor device according to claim 17, wherein The metal of the metal ion is different from the metal of the dopant and the metal of the first electrode layer.

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