Cache unit and circuit structure and cache management method thereof

Abstract

The embodiment of the invention discloses a cache unit, a circuit structure thereof and a cache management method. According to the embodiment of the invention, a cache management command comprising at least one address structure body with address information of a corresponding physical page is received, and each cache tag in a cache unit is traversed, so that whether the address structure body consistent with the address information of the corresponding cache tag exists in each address structure body or not is determined; and determining the cache tag consistent with the address information of any address structural body as a target cache tag, and performing target data management operation on the cache data corresponding to the target cache tag. Therefore, according to the embodiment, whether the cache tag in the cache unit is hit or not can be traversed and searched by issuing the cache management command, the search frequency is relatively low, meanwhile, the number of commands issued by the manager module can be reduced, the system load and power consumption are reduced, and the system performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and more particularly, to a cache unit, its circuit structure, and a cache management method. Background Art

[0002] In a computer system, a cache (Cache) maintains a small amount of data that is frequently accessed. This data is a mirror image of the data in the main memory. When the computer accesses this part of the data, the access behavior stops at the Cache instead of the main memory, thereby reducing the access latency of this part of the data. Therefore, the amount of data cached in the Cache is much smaller than the size of the system main memory.

[0003] Data management in a computer system is usually granular at the physical page (Physical Page). Data within the same page has the same base address, and data is located within the page through an offset within the page. In a specific application scenario, the data accessed through the Cache may be located in multiple physical pages. However, due to the characteristics of the Cache, only a small amount of frequently accessed data is cached inside the Cache, and the computer cannot know in advance which data is cached in the Cache and which is not. When the system needs to perform cache resource management, the manager (operating system, Driver software, etc.) usually only knows the maximum range of the data space accessed through the Cache, but cannot anticipate in advance which data has been cached in the Cache. It is very difficult to search for and operate on the data that has been cached within this maximum range. The unoptimized operation process is very inefficient and will introduce a large performance and power consumption overhead. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a cache unit, its circuit structure, and a cache management method, so as to traverse and search whether the cache tags in the cache unit are hit by issuing a cache management command, such that the number of searches is relatively low. At the same time, the number of commands issued by the manager module can be reduced, the system load and power consumption are reduced, and the system performance is improved.

[0005] In a first aspect, an embodiment of the present invention provides a cache management method, the method comprising:

[0006] Receiving a cache management command, where the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information of the corresponding physical page;

[0007] Traversing each cache tag in the cache unit to determine whether there is an address structure in each of the address structures that is consistent with the address information of the corresponding cache tag;

[0008] Determining the cache tag that is consistent with the address information of any of the address structures as the target cache tag;

[0009] Perform a target data management operation on the cache data corresponding to the target cache tag.

[0010] In a second aspect, an embodiment of the present invention provides a circuit structure of a cache unit. The circuit structure of the cache unit includes:

[0011] A tag storage module configured to store cache tags, where the cache tags are unique identifiers of the cache data stored in the cache unit;

[0012] A search engine configured to receive a cache management command and read the corresponding cache tag from the tag storage module. The cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information of the corresponding physical page;

[0013] A first matching module configured to receive the currently read cache tag sent by the search engine and each of the address structures carried by the cache management command, and perform an address consistency comparison between the currently read cache tag and each of the address structures. In response to the currently read cache tag being consistent with the address information in any of the address structures, determine the cache tag as the target cache tag;

[0014] A data execution module configured to perform a target management operation on the cache data corresponding to the target cache tag received from the matching module.

[0015] In a third aspect, an embodiment of the present invention provides a cache management system. The cache management system includes:

[0016] The circuit structure of the cache unit as described above;

[0017] A manager module configured to receive and parse a data access request, generate a cache management command or a cache access command, and send the cache management command or the cache access command to the circuit structure of the cache unit for processing.

[0018] In a fourth aspect, an embodiment of the present invention provides a cache unit. The cache unit includes:

[0019] A cache space configured to store cache data;

[0020] The circuit structure of the cache unit as described above.

[0021] In a fifth aspect, an embodiment of the present invention provides an electronic device. The electronic device includes:

[0022] The cache unit as described above;

[0023] The management module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the cache unit for processing;

[0024] The main memory is used to store data.

[0025] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program or data is stored, and when the computer program is executed by a processor, the method described above is implemented.

[0026] An embodiment of the present invention discloses a cache unit, its circuit structure, and a cache management method. In the embodiment of the present invention, by receiving a cache management command including an address structure with at least one address information having a corresponding physical page, and traversing each cache tag in the cache unit to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag, the cache tag whose address information is consistent with any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. Thus, in this embodiment, it is possible to traverse and search whether the cache tags in the cache unit are hit by issuing a cache management command, the number of searches is relatively low, and at the same time, the number of commands issued by the management module can be reduced, reducing the system load and power consumption, and improving the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0028] Figure 1 is a data schematic diagram of the cache unit and the main memory according to an embodiment of the present invention;

[0029] Figure 2 is a flowchart of a cache management method of a comparative example;

[0030] Figure 3 is a schematic diagram of the circuit structure of a cache unit of a comparative example;

[0031] Figure 4 is a flowchart of a cache management method according to an embodiment of the present invention;

[0032] Figure 5 is a flowchart of a matching method according to an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a matching process according to an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of another matching process according to an embodiment of the present invention;

[0035] Figure 8 It is a schematic diagram of another matching process according to an embodiment of the present invention;

[0036] Figure 9 It is a flowchart of another cache management method according to an embodiment of the present invention;

[0037] Figure 10 It is a schematic diagram of the circuit structure of a cache unit according to an embodiment of the present invention;

[0038] Figure 11 It is a schematic diagram of a cache unit according to an embodiment of the present invention;

[0039] Figure 12 It is a schematic diagram of a cache management system according to an embodiment of the present invention;

[0040] Figure 13 It is a schematic diagram of a cache data management device according to an embodiment of the present invention;

[0041] Figure 14 It is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed implementation manners

[0042] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0043] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0044] Unless the context clearly requires otherwise, the words such as "including" and "comprising" in the entire application document should be interpreted as the meaning of including rather than exclusive or exhaustive; that is, the meaning of "including but not limited to".

[0045] In the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0046] In the solutions described in this specification and the embodiments, if personal information processing is involved, it will be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. If a user refuses to process personal information other than the necessary information required for the basic functions, it will not affect the user's use of the basic functions.

[0047] Figure 1 It is a data schematic diagram of the cache unit and the main memory in an embodiment of the present invention. It should be understood that the cache unit and the main memory in this embodiment are only exemplary and do not represent the cache and the main memory in an actual computer system. As Figure 1 shown, in an actual application scenario, the cache unit 11 can access two physical pages PageA and PageB in the main memory 12. Among them, the size of the physical page PageA is 8 data blocks, and the size of the physical page PageB is 4 data blocks. These data blocks all have a unique logical tag (logical Tag), where the logical tag is the address of the corresponding data block. Further, the address of the data block is composed of the base address of the corresponding physical page and the offset address within the page. For example, the logical tag (PageA, 5) identifies the 5th data block within the physical page PageA. It can be seen that there are 8 data blocks (PageA, 0)-(PageA, 7) within PageA, and 4 data blocks (PageB, 0)-(PageA, 3) within PageB.

[0048] The total capacity of the cache unit 11 is 4 physical cache tags (Cache Tag), which are composed of two cache sets Set1 and Set2. Among them, each cache set includes two cache ways (Cache Way). In a computer system, a cache tag Tag within a Cache Set becomes a Way. As Figure 1 shown, the cache unit 11 caches (PageA, 0), (PageB, 3), (PageA, 5) and an empty cache tag (Empty Tag). Further, (PageA, 0) and (PageB, 3) are in the same cache set Set1, and (PageA, 5) and the empty cache tag (Empty Tag) are in the same cache set Set2. For other data blocks such as {PageB, 0} that are not in the cache unit 11, they may have been cached in the cache unit 11 before, but due to reasons such as low access frequency of non-hot data, they have been replaced by the currently cached data blocks. Therefore, among the 12 logical tags corresponding to the 12 data blocks in the two physical pages PageA and PageB, only 3 are mapped to the physical cache tags in the cache unit 11.

[0049] It can be seen that the amount of data cached in the cache unit 11 is much smaller than that in the main memory. If multiple physical pages Page in the main memory are accessed in an actual application scenario, since the management module cannot anticipate in advance which logical tags have been cached in the cache unit 11, it can only sequentially issue commands corresponding to all logical tags in the multiple physical pages Page accessed to the cache unit 11 for searching. If the logical tag in the command hits the physical cache tag in the cache unit 11, the corresponding data operation is performed; if it does not hit, no operation is performed. Obviously, in this case, the number of commands to be issued is relatively large (the number of all logical tags in the multiple physical pages Page accessed), the number of searches is relatively large, and the performance and power consumption overhead of the system are relatively large.

[0050] Figure 2 is a flowchart of a cache management method of a comparative example. As Figure 2 shown, in this comparative example, after the search and matching process corresponding to the data management operation in the cache unit starts, search commands corresponding to individual logical tags are sequentially issued to the cache unit for search and matching. The specific process includes the following steps:

[0051] Step S110, obtain the current physical page being traversed. Taking the main memory 12 in Figure 1 as an example, after the search and matching process starts, PageA can be traversed first.

[0052] Step S120, obtain the current logical tag being traversed in the current physical page. Taking the currently traversed physical page as PageA as an example, based on the offset addresses of each data block in PageA in ascending order, traversal can be performed sequentially. Then the current logical tag obtained at the beginning of the traversal in PageA is (PageA, 0).

[0053] Step S130, issue a search command corresponding to the current logical tag to the cache unit for matching. Taking the current logical tag as (PageA, 0) as an example, each address bit of the current logical tag (PageA, 0) is sequentially matched with each address bit of each cache tag in each cache group in the cache unit one by one.

[0054] Step S140, determine whether the match hits. If there exists a cache tag in the cache unit whose address bit values are all the same as those of the current logical tag, it is determined that the current match hits; if there is no cache tag in the cache unit whose address bit values are all the same as those of the current logical tag, it is determined that the current match does not hit. If the current match hits, execute Step S150; if the current match does not hit, execute Step S160.

[0055] Step S150: In response to a current match hit, perform corresponding data management operations, that is, perform corresponding data management operations on the cache data corresponding to the cache tag hit in the cache, such as deleting the cache data, reading the cache data, etc. After performing the data management operations corresponding to the currently hit cache tag, continue to execute Step S160.

[0056] Step S160: Determine whether the current physical page has been traversed completely. That is, after the current match is not hit or the current match is hit and the corresponding data management operations are performed, determine whether the current physical page has been traversed completely. If the current physical page has not been traversed completely, continue to execute Step S120, that is, continue to traverse and obtain the next current logical tag from the current physical page. For example, if the current logical tag is (PageA, 0), after performing the search and match operation, if it is determined that the corresponding current physical page PageA has not been traversed completely, continue to traverse and obtain the next current logical tag (PageA, 1) from PageA to repeat the execution of Steps S130 - S160 until PageA is traversed completely, that is, the search and match operation for the logical tag (PageA, 7) is completed. Further, if the current physical page has been traversed completely, continue to execute Step S170.

[0057] Step S170: Determine whether all physical pages have been traversed. After the logical tags in the current physical page have all completed the corresponding search and match operations, determine whether there are still untraversed physical pages among all the physical pages to be accessed. If there are still untraversed physical pages, continue to execute Steps S110 - S160 to sequentially traverse the search and match operations of each logical tag in this physical page until all the physical pages in the main memory have been traversed. If there are no untraversed physical pages, execute Step S180.

[0058] Step S180: After traversing all the physical pages to be accessed, determine that the current search and match process is completed. Further, the corresponding operation results can be fed back, such as feeding back that the corresponding cache data has been deleted, or feeding back the read cache data, etc.

[0059] Figure 3 is a schematic diagram of the circuit structure of a cache unit of a comparative example. As Figure 3As shown, the Manager module 10 sequentially issues search commands carrying logical tags to the cache unit 30 through the Cache Interface 20, so that the cache unit 30 performs corresponding search matching and corresponding data management operations. Specifically, the circuit structure of the cache unit 30 includes a Tag Unit 31, an Exact Match Unit 32, and an Execution Unit 33. Among them, the Tag Unit 31 is used to store physical cache tags, and the Exact Match Unit 32 is used to perform precise matching of cache tags. Specifically, each cache tag read from the Tag Unit 31 is sequentially compared precisely with each address bit (bit) of the logical tag carried by the received search command. If there is a cache tag whose all address bits are the same as the logical tag, it is determined to be a hit; otherwise, it is determined to be a miss. Further, the Exact Match Unit 32 sends the hit result to the Execution Unit 33 to perform the management operation of the response cache data. That is, the above steps S110 - S170 are executed through the manager module and the cache unit in this comparative example, which will not be described in detail here.

[0060] Take Figure 1 the cache unit 11 and the main memory 12 in [reference], as well as accessing PageA and PageB in the main memory 12 as an example. Since the manager module does not know which data blocks in the 2 physical pages PageA and PageB have been cached in the cache unit 11, it can only completely edit all the logical tags in PageA and PageB, form these logical tags into search commands and issue them sequentially to the cache unit 11 for precise matching. Only when the cached tags cached in the cache unit 11 are exactly the same as the logical tags, corresponding management operations are performed. It can be seen that a total of 12 search commands will be generated to the cache unit 11 in this access, and only 3 commands can generate effective management operations. 9 commands become invalid commands because they cannot be hit, and these invalid commands will waste the bandwidth and power consumption of the cache unit 11. In addition, all commands need to be initiated by the manager module, and the manager module needs to control the traversal process. In the traditional scheme, it will occupy the processing time of 12 commands of the manager module, and the manager module usually has a main processor such as a CPU. Occupying the time of the main processor such as the CPU will further reduce the system performance.

[0061] Therefore, the embodiment of the present invention provides a cache unit, its circuit structure, and a cache management method, so as to traverse and search whether the cache tags in the cache unit are hit by issuing cache management commands, so that the number of searches is relatively low, and at the same time, the number of commands issued by the manager module can be reduced, the system load and power consumption are reduced, and the system performance is improved.

[0062] Figure 4It is a flowchart of a cache management method according to an embodiment of the present invention. As Figure 4 shown, the cache management method according to the embodiment of the present invention includes the following steps:

[0063] Step S210, receiving a cache management command. Among them, the cache management command includes at least one address structure corresponding to the data to be managed. Among them, the address structure includes the address information of the corresponding physical page.

[0064] In an optional implementation manner, the manager module parses the corresponding data access request, and determines whether it meets the conditions for adopting the cache management method according to the type of the data access request. If it meets the conditions, it generates and sends a cache management command corresponding to the data access request to the cache unit. Further, in this embodiment, the data access request can be parsed to determine whether the cache data that needs to be cache-managed in the accessed physical page is managed in units of physical pages, so as to determine whether the cache management process meets the conditions for adopting the cache management method according to the embodiment of the present invention. Optionally, the manager module parses the most recent data access request and determines that the data access frequency of some physical pages cached in the cache unit is relatively low, and can generate a cache management command to clear the cache data corresponding to these physical pages in the cache unit. It should be understood that this embodiment does not limit the specific type of data access request that meets the conditions for adopting the cache management method according to the embodiment of the present invention, and it can be configured according to the corresponding actual situation.

[0065] Further, in an optional implementation manner, at least one address structure in the cache management command is determined by screening from the address structures of the physical pages accessed from the cache unit. Further, at least one address structure in the cache management command may include the address structures of the physical pages that need to perform corresponding management operations among all the physical pages accessed through the cache unit. Optionally, the corresponding management operation for the cache data in the cache unit may be to clear the corresponding cache data of the corresponding physical page in the cache unit. For example, if 4 physical pages in the main memory are accessed through the cache unit, and these 4 physical pages have corresponding 4 address structures, assuming that currently 2 of these physical pages need to be managed, find and clear the cache data that may be cached in the cache unit for these 2 physical pages, then it is necessary to send the address structures corresponding to these 2 physical pages to the cache unit through the cache management command for search and matching processing. This embodiment only mainly takes the cache clearing operation as an example for illustration here. It should be understood that this embodiment is not limited thereto, and it can be configured and determined according to the actual application situation.

[0066] Thus, in this embodiment, multiple physical pages that need to perform management operations and are accessed through the cache unit can be merged into the same cache management command and sent to the cache unit, reducing the number of commands sent by the manager module, lowering the system load and power consumption, and improving the system performance.

[0067] Further, the address information of the address structure in this embodiment is determined according to the data address required in the data access request. Among them, the data address includes the base address (Page Base Address) of the physical page where it is located and the offset address (Page Offset) within the physical page.

[0068] In an optional implementation manner, the address information in the address structure of this embodiment includes the physical page base address and the in-page offset address. Optionally, each piece of data accessed in the data access request has a corresponding address structure. In such an implementation manner, both application scenarios that require precise matching and application scenarios that require fuzzy matching can be realized. It should be understood that the precise matching in this embodiment means precisely matching the data operations in the corresponding data. However, since many application scenarios in computer systems are used to perform data operations on the entire physical page simultaneously, fuzzy matching can be performed based on the physical page as a unit, that is, as long as the part of the cache tag in the cache unit corresponding to the physical page base address is the same as the part of the address information carried in the cache management command corresponding to the physical page base address, it is determined to be a hit. The fuzzy matching method can further reduce the number of address structures in the cache management command, further reduce the number of search and matching times, reduce the corresponding computational amount, and thus reduce the system power consumption.

[0069] Further optionally, for each physical page accessed by the data access request, a data address is selected from at least one piece of data located in the same physical page as the accessed data as the address information in the corresponding address structure. That is, in this embodiment, each physical page accessed in the data access request can have a corresponding address structure, so as to further reduce the computational amount of subsequent search and matching and reduce the system power consumption. It should be understood that only when performing management operations on all cached data in the corresponding physical page in the cache unit simultaneously can each physical page have a corresponding address structure to ensure the accuracy of data management operations. For example, the data management operation is to clear all cached data in the cache unit that is located in a certain physical page in the main memory, etc.

[0070] In another alternative implementation, the address information of the address structure in this embodiment includes the corresponding physical page address and the corresponding physical page size. Among them, the corresponding physical page size is used to represent the amount of data that the corresponding physical page can store or the number of data blocks. Further, the physical page address in the address structure of this embodiment can be represented by a certain data address in the physical page, that is, the format of the address structure can be {Page Address, Page Size}. Further optionally, this embodiment can determine the address bits of the physical page base address in the corresponding data address based on the corresponding physical page size to obtain the physical page base address. In this case, the physical page address in the address information of the address structure of this embodiment is the physical page base address, that is, the format of the address structure can be {Page Base Address, Page Size}.

[0071] Further, when different physical pages have different physical page sizes (Page size), that is, different numbers of data blocks in the physical page, the amount of data that can be stored in the physical page is different. For a physical page that can store more data, a larger offset address range is required to represent all the data in the physical page. Therefore, for the data addresses in physical pages with different Page sizes, the number of address bits occupied by the offset address is different. And for a physical page with a larger Page size, the offset address in the corresponding data address occupies a longer address bit. When the total number of bits of the data address is the same, the offset address in the data address corresponding to a physical page with a larger Page size occupies a longer address bit, and the physical page base address occupies a shorter address bit. It should be understood that the specific address bit lengths of the physical page base address and the offset address in the data addresses corresponding to different physical pages with different Page sizes can be determined according to the specific configuration of the computer system, and this embodiment does not limit this.

[0072] Further, this embodiment can also first calculate the offset address in the data address, determine the low bits occupied by the offset address in the data address based on the size of the offset address, and then determine the address bit length of the physical page base address in the high bits. Further optionally, Page Offsrt = Log(Page Size). Where Page Size is the amount of data that the corresponding physical page can store. It should be understood that this embodiment does not limit the method for determining the address bits of the physical page base address in the data address.

[0073] Further, this embodiment can determine the address bit lengths of the physical page base address and the offset address corresponding to each Page size based on the pre-determined total data address length, and according to the physical page size corresponding to the accessed data, determine the address bit lengths of the physical page base address and the offset address of the corresponding physical page. Then, based on the physical page base address length, intercept the corresponding address bits from the data address of the accessed data to obtain the base address of the physical page where the accessed data is located. Furthermore, an address structure {Page Base Address, Page Size} can be generated based on the base address of the physical page. Optionally, the high bits of the data address in this embodiment are used to store the base address of the physical page where it is located, and the low bits are used to store the offset address within the page. This embodiment can intercept the corresponding address bits from the high bits of the corresponding data address based on the physical page base address length to obtain the corresponding physical page base address.

[0074] Further, assume that the cache management command is used to indicate corresponding data management operations on the data in the physical pages PageA and PageB cached in the cache unit. The address structure in the cache management command can include {PageAAddress, PageA Size}, {PageB Address, PageB Size}, or the address structure in the cache management command can include {PageA Base Address, PageA Size}, {PageB Base Address, PageB Size}.

[0075] Step S220, traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag.

[0076] In an alternative implementation, this embodiment can sequentially traverse each cache tag in the cache unit and perform an address consistency comparison between the currently traversed cache tag and each address structure in the cache management command to determine whether the currently obtained cache tag hits in each address structure in the management command, that is, whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag. Further, this embodiment sequentially traverses the cache groups in the cache unit and sequentially traverses the cache tags in the cache groups until all the cache tags in the cache unit are traversed. As described above, the number of cache tags in the cache unit is greatly reduced compared to the logical tags in the accessed physical page, so the number of traversal searches is also correspondingly reduced compared to the above comparative example method, further reducing the system power and performance overhead.

[0077] Figure 5It is a flowchart of a matching method according to an embodiment of the present invention. The matching method in this embodiment describes the process of fuzzy matching the address of a certain cache tag with an address structure. It should be understood that if a parallel matching method is adopted, the fuzzy matching process of the cache tag with multiple address structures, or the fuzzy matching process of multiple cache tags with multiple address structures respectively, can be executed in parallel according to the following matching method. As Figure 5 shown, the consistency comparison step of the currently traversed cache tag and the corresponding address structure in this embodiment includes:

[0078] Step 221, determine the address comparison bits of the address structure and the currently traversed cache tag based on the physical page size in the address structure.

[0079] Step 222, in response to the values of the address comparison bits of the address structure and the currently traversed cache tag being the same, determine that the address information in the currently traversed cache tag is the same as that in the address structure, that is, determine that the currently traversed cache tag hits.

[0080] In an optional implementation manner, the physical page address in the address information of the address structure includes a physical page base address and a corresponding page offset address within the page. The address information in the address structure also includes the corresponding physical page size. Further, this embodiment can determine the base address length of the physical page corresponding to the address structure based on the physical page size in the address structure, and intercept the corresponding address comparison bits from the address information of the address structure and the currently traversed cache tag according to the base address length. It should be understood that the base address lengths of the physical pages corresponding to various physical page sizes are determined in advance, and they can be determined based on the data storage configuration of the memory.

[0081] Figure 6 It is a schematic diagram of a matching process according to an embodiment of the present invention. This embodiment takes the physical page base address being located at the high position of the data address and the page offset address being located at the low position of the data address as an example for illustration. As Figure 6 shown, the physical page address in the address information of address structure A1 includes a physical page base address Page Base Address = A and a corresponding page offset address Page Offset = b. Further, this embodiment determines the base address length of the physical page of the data address in address structure A1 according to the physical page size (PageSize) in address structure A1, and intercepts the high positions of the physical page address 61 in address structure A1 and the high position of cache tag 62 based on the base address length of the physical page to obtain the address comparison bits corresponding to address structure A1 and the address comparison bits corresponding to cache tag 62 (that is, the physical page base address). Further, this embodiment compares the address comparison bits of address structure A1 and cache tag 62.

[0082] This embodiment uses a fuzzy matching method to handle cache data management operations in units of physical pages. For example, Figure 6 As shown, the address comparison bits corresponding to the address structure A1 and the cache tag 62 are both A. Even if the page offset address Page Offset corresponding to the address structure A1 is b and the page offset address PageOffset corresponding to the cache tag 62 is c, and the two are different, it can be determined that the cache tag 62 hits, and the corresponding cache data is executed for the corresponding data caching operation.

[0083] In another alternative implementation, the physical page address in the address information of the address structure only includes the physical page base address. The address information in the address structure also includes the corresponding physical page size. Further, this embodiment can determine the base address length of the physical page corresponding to the address structure based on the physical page size in the address structure, and intercept the corresponding address comparison bits from the address information of the address structure and the currently traversed cache tag according to the base address length. It should be understood that the base address lengths of physical pages corresponding to various physical page sizes are determined in advance, and they can be determined based on the data storage configuration of the memory.

[0084] Figure 7 It is a schematic diagram of another matching process of an embodiment of the present invention. This embodiment takes the physical page base address being located at the high position of the data address and the page offset address being located at the low position of the data address as an example for illustration. For example, Figure 7 As shown, the physical page address in the address information of the address structure A2 includes the physical page base address Page Base Address = A. Further, this embodiment determines the physical page base address length of the data address in the physical page according to the physical page size (Page Size) in the address structure A2, and intercepts the high position of the cache tag 72 based on the physical page base address length to obtain the address comparison bits corresponding to the cache tag 72. Further, this embodiment compares the address consistency between the physical page base address 71 (that is, the address comparison bit) obtained from the address structure A2 and the address comparison bits corresponding to the cache tag 72.

[0085] This embodiment uses a fuzzy matching method to handle cache data management operations in units of physical pages. For example, Figure 7 As shown, the physical page base address 71 in the address structure A2 and the address comparison bits corresponding to the cache tag 72 are both A. In the case of using fuzzy matching, there is no need to match the offset address, so it can be determined that the cache tag 72 hits, and the corresponding cache data is executed for the corresponding data caching operation.

[0086] In a further optional implementation, for the cache tag obtained by the current traversal, this embodiment can perform the address consistency comparison operation between the cache tag and each address structure in parallel, so as to improve the matching efficiency of the cache tag, and further improve the overall execution efficiency of the cache management command.

[0087] Figure 8 It is a schematic diagram of another matching process of an embodiment of the present invention. As Figure 8 shown, assuming that the cache management command includes address structures A1 - A3, the address consistency comparison between the cache tag tag1 obtained by the current traversal and the high-order bits corresponding to the address information of the address structures A1 - A3 can be performed in parallel. As Figure 8 shown, if the comparison result shows that the cache tag tag1 is consistent with the corresponding high-order bits of the address structure A1, it is determined that the cache tag tag1 hits, and the corresponding cache data is executed for the corresponding data caching operation.

[0088] Further, taking the cache tag tag1 as a 64b size with a value of 0x0001020304050607, and the address structures A1 - A3 are respectively {Page Address = 0x0001020304050000, Page Size = 4KB}, {Page Address = 0x00010203040abcde, Page Size = 1GB}, {Page Address = 0x0001020304060123, PageSize = 64KB} as an example.

[0089] For the first address structure A1, the Page Size is 4KB. According to this Page Size, the high-order bits of the cache tag tag1 and the Page Address of the address structure A1 are intercepted, and the results are both 0x0001020304050. Therefore, it can be determined that the cache tag tag1 hits the first address structure A1.

[0090] For the second address structure A2, the Page Size is 1GB. According to this Page Size, the high-order bits of the cache tag tag1 and the Page Address of the address structure A2 are intercepted, and the results are both 0x00010203040. Therefore, it can be determined that the cache tag tag1 hits the second address structure A2.

[0091] For the third address structure A3, the Page Size is 64KB. The result of truncating the high bits of cache tag tag1 according to this Page Size is 0x0x000102030405, but the result of truncating the high bits of the Page Address of address structure A3 is 0x000102030406. Since the truncation results are different, it can be determined that cache tag tag1 misses the third address structure A3.

[0092] It can be seen from this that in this embodiment, there is no need to judge the address bits where the physical page base address of the cache tag is located. Only the address information in the address structure is used to determine the high - address comparison bits for comparison. Even if there may be a possibility that a cache tag hits multiple address structures as in the above example, since this embodiment only needs to determine whether the cache tag hits to perform the corresponding cache data management operation, and does not need to clearly know which physical page base address of the address structure it is exactly the same as. Therefore, in this embodiment, through fuzzy matching, while ensuring the accuracy of the cache tag hit result, the computational complexity in the search - matching process is further reduced, the search - matching efficiency is improved, and the system power consumption is reduced.

[0093] In other alternative implementation manners, this embodiment can also first determine the address bits where the physical page base address corresponding to the cache tag is located, and compare it with the address base addresses of each address structure respectively, so as to more accurately determine which address structure the cache tag hits. This embodiment does not limit the specific fuzzy matching method.

[0094] In another alternative implementation manner, this embodiment can also perform the traversal search - matching operation of each cache tag in the cache unit in parallel to further improve the search - matching efficiency.

[0095] Step S230: Determine the cache tag whose address information is consistent with that of any address structure as the target cache tag. In this embodiment, if there is any address structure whose address information is consistent with the cache tag, it is determined that the cache tag hits, and this cache tag is determined as the target cache tag. Further, if there is no address structure whose address information is consistent with the cache tag, it is determined that the cache tag misses, and no corresponding data management operation is performed on the cache data corresponding to this cache tag.

[0096] Step S240: Perform a target data management operation on the cache data corresponding to the target cache tag. Among them, the target data management operation can be configured according to specific system requirements, such as the corresponding cache data clearing operation, etc. This embodiment does not limit the specific operation.

[0097] In an embodiment of the present invention, a cache management command including at least one address structure with address information corresponding to a physical page is received, and each cache tag in the cache unit is traversed to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag. The cache tag consistent with the address information of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. Thus, compared with Figure 2 the comparative example shown, the management module in this embodiment does not need to generate and send corresponding search commands to the cache unit for each data block in the accessed physical page, greatly reducing the number of command transmissions, thereby avoiding excessive occupation of the performance and power consumption overhead of the management module. Further, in this embodiment, the cache tags in the cache unit are used as the search objects, greatly reducing the number of searches, further reducing the system load and power consumption, and improving the system performance. At the same time, for data management operations in units of physical pages, this embodiment can also use a fuzzy matching method for parallel matching, further reducing the computational amount of search matching, improving the matching efficiency, reducing the system power consumption, and improving the system performance.

[0098] Figure 9 FIG. Figure 9 is a flowchart of another cache management method according to an embodiment of the present invention. In this embodiment, the description is made by taking the traversal of each cache group in the cache unit in sequence and the traversal of the cache tags within each cache group in sequence as an example. It should be understood that the cache groups in the cache unit and the cache tags within the cache groups can also be traversed in a parallel traversal manner, and the specific traversal method can be set according to specific requirements and system performance. As Figure 9 shown, the cache management method according to an embodiment of the present invention includes the following steps:

[0099] Step S310, receiving a cache management command. Among them, the cache management command includes at least one address structure corresponding to the data to be managed. Among them, the address structure includes address information corresponding to a physical page.

[0100] Step S320, obtaining the current cache group to be traversed. In this embodiment, the cache tags in the cache unit are stored in the form of cache groups. Taking the cache unit 11 in Figure 1 as an example, after the search matching process starts, the cache group Set1 can be traversed first.

[0101] Step S330, obtaining the current cache tag to be traversed in the current cache group. Taking the currently traversed cache group Set1 as an example, the tags can be based on the storage order of the cache tags in the cache group Set1. For example, the current cache tag obtained at the beginning of the traversal in the cache group Set1 is (PageA, 0).

[0102] Step S340: Parallelly execute the address comparison between the current cache tag and each address structure in the cache management command. Taking the current cache tag as (PageA, 0) as an example, parallelly execute the address consistency between the current cache tag (PageA, 0) and the address information in each address structure. Optionally, in the parallel matching of this embodiment, based on the corresponding data management operation (such as the data management operation in units of physical pages), a fuzzy matching method can be selected. The specific comparison process can refer to Figures 4 - 8 the embodiment shown, and details will not be elaborated here. In other alternative implementation manners, if the current data management command is not a data management operation in units of physical pages, an exact matching process is required, that is, each address bit of the address information of the current cache tag (PageA, 0) is matched one by one with the address bits of the address information in the address structure to locate the specific data position, so as to perform the corresponding data management operation.

[0103] Step S350: Determine whether the match hits. If there is one or more address structures in the cache management command that match the address information of the current cache tag, it is determined that the current cache tag hits, and step S360 is executed. If there is no address structure in the cache management command that matches the address information of the current cache tag, it is determined that the current cache tag does not hit, and step S370 is executed.

[0104] Step S360: In response to the current match hitting, execute the corresponding data management operation, that is, perform the corresponding data management operation on the cache data corresponding to the cache tag that hits in the cache, such as deleting the cache data, reading the cache data, etc. After executing the data management operation corresponding to the currently hit cache tag, continue to execute step S370.

[0105] Step S370: Determine whether the current cache group has been traversed. That is, after the current match does not hit or the current match hits and the corresponding data management operation is executed, determine whether the current cache group has been traversed. If the current cache group has not been traversed, continue to execute step S330, that is, continue to traverse and obtain the next current cache tag from the current cache group. For example, if the current cache tag is (PageA, 0), after executing the search and match operation, determine that the corresponding current cache group Set1 has not been traversed, then continue to traverse and obtain the next current cache tag (PageB, 3) from the current cache group Set1 to repeat the execution of steps S340 - S370 until the cache group Set1 is traversed, that is, the search and match operation for the cache tag (PageB, 3) is completed. Further, if the current cache group has been traversed, continue to execute step S380.

[0106] Step S380: Determine whether all cache groups have been traversed. After the cache tags in the current cache group have all completed the corresponding search and matching, check whether there are still untraversed cache groups in the cache unit. If there are still untraversed cache groups, continue to execute Step S320 - Step S370 to sequentially traverse the search and matching operations of each cache tag in this cache group until all cache groups in the cache unit have been traversed. If there are no untraversed cache groups, execute Step S390.

[0107] Step S390: After traversing all cache groups in the cache unit, determine that the current search and matching process is completed. Further, the corresponding operation results can be fed back, such as feeding back that the corresponding cache data has been deleted, or feeding back the read cache data, etc.

[0108] Take Figure 1 cache unit 11 and main memory 12 in [reference], as well as accessing PageA and PageB in main memory 12 as an example. Since the management module does not know which data blocks in the two physical pages PageA and PageB have been cached in cache unit 11, it can only completely edit all the logical tags in PageA and PageB, form these logical tags into search commands and send them to cache unit 11 in sequence for precise matching. Only when the cached tags already cached in cache unit 11 are exactly the same as the logical tags, will the corresponding management operations be performed. It can be seen that a total of 12 search commands will be generated to cache unit 11 for this access, among which only 3 commands can generate effective management operations, and 9 commands become invalid commands due to failure to hit. These invalid commands will waste the bandwidth and power consumption of cache unit 11.

[0109] In this embodiment, the physical pages that need cache management in the accessed physical pages can be sent to the cache unit through a cache management command. Compared with the prior art, the management module will not generate invalid commands that fail to hit, and will not cause waste of the bandwidth and power consumption of the cache unit. Further, the management module of this embodiment only needs to send data management commands and does not need to control the traversal process, reducing the time occupied by the cache management process in the management module and further improving the system performance.

[0110] In an embodiment of the present invention, a cache management command including at least one address structure with address information corresponding to a physical page is received, and each cache tag in the cache unit is traversed to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag. The cache tag whose address information is consistent with that of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. Thus, in this embodiment, it is possible to traverse and search whether the cache tags in the cache unit are hit by issuing a cache management command, the number of search times is relatively low, and at the same time, the number of commands issued by the manager module can be reduced, reducing the system load and power consumption and improving the system performance.

[0111] Figure 10 is a schematic diagram of the circuit structure of the cache unit according to an embodiment of the present invention. As Figure 10 shown, the circuit structure 100 of the cache unit according to an embodiment of the present invention includes a tag storage module 101, a search engine 102, a first matching module 103, and a data execution module 104.

[0112] The manager module (Manager) 10 parses and processes a data access request to generate a cache management command cmd1, and issues the cache management command cmd1 to the circuit structure 100 of the cache unit through a cache interface (Cache Interface) 20. The cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information corresponding to a physical page. Among them, the address information in the address structure can refer to the description of the above embodiment and will not be elaborated here.

[0113] The tag storage module 101 is configured to store cache tags. Among them, the cache tag is the unique identifier of the cache data stored in the cache unit.

[0114] The search engine 102 is configured to receive the cache management command cmd1 and read the corresponding cache tag from the tag storage module 101. Further optionally, the search engine 102 can be based on Figure 9 the traversal method shown, that is, the method of sequentially traversing each cache group in the cache unit and sequentially traversing the cache tags in each cache group to read the corresponding cache tags from the tag storage module 101. In other alternative implementation manners, the search engine 102 can also traverse the cache groups and the cache tags in the cache groups in parallel. The manner in which the search engine 102 of this embodiment obtains cache tags from the tag storage module 101 can be set according to the actual application situation (such as performance, power consumption requirements, hardware configuration, etc.), and this embodiment does not limit this.

[0115] The first matching module 103 is configured to receive each address structure carried by the currently read cache tag and the cache management command cmd1 sent by the search engine 102, and compare the address consistency between the currently read cache tag and each address structure. In response to the address information in the currently read cache tag being consistent with the address information in any of the address structures, the cache tag is determined as the target cache tag. Further, the first matching module 103 is further configured to perform the address consistency comparison operation between the currently read cache tag and each address structure in parallel. Further optionally, the address information in the address structure includes the corresponding physical page address and the corresponding physical page size. The first matching module 103 is further configured to determine the address comparison bits between the address structure and the currently read cache tag based on the physical page size in the address structure. In response to the values of the address comparison bits between the address structure and the currently read cache tag being consistent, it is determined that the currently traversed cache tag is consistent with the address information in the address structure. Among them, the address comparison bit represents the data bit storing the base address of the corresponding physical page, and the length of the base address of the corresponding physical page is determined based on the physical page size in the corresponding address structure.

[0116] The specific matching process of the first matching module 103 in this embodiment for performing parallel fuzzy matching between the currently read cache tag and each address structure is similar to that in the above embodiment, and will not be elaborated here. Among them, if the address information in the currently read cache tag is consistent with the address information in any address structure, it is determined that the cache tag hits, that is, the cache data corresponding to the cache tag needs to perform corresponding data management operations, and it is sent to the data execution module 104 as the target cache tag. The data execution module 104 is configured to execute the target management operation of the cache data corresponding to the target cache tag received from the matching module.

[0117] In the embodiment of the present invention, by receiving a cache management command including at least one address structure with address information corresponding to a physical page, and traversing each cache tag in the cache unit to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag, the cache tag whose address information is consistent with the address information of any address structure is determined as the target cache tag, and the target data management operation is performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need to be cache-managed in the accessed physical pages can be sent to the cache unit through a cache management command, as opposed to Figure 2In the comparative example shown, the manager module does not generate invalid commands that cannot be hit, and does not cause waste of the bandwidth and power consumption of the cache unit. Further, the manager module of this embodiment only needs to issue data management commands and does not need to control the traversal process, reducing the time occupied by the cache management process in the manager module and further improving the system performance. Further, this embodiment uses the cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing the system load and power consumption, and improving the system performance. At the same time, for data management operations in units of physical pages, this embodiment can also use a fuzzy matching method for parallel matching, further reducing the computational amount of search matching, improving the matching efficiency, reducing the system power consumption, and improving the system performance.

[0118] In an alternative implementation, the tag storage module 101 is further configured to receive a cache access command cmd2, and the cache access command cmd2 includes the data address of the data to be accessed. Wherein, the data address of the data to be accessed includes the physical page base address and the corresponding offset address. It should be understood that if the manager module 10 analyzes the corresponding data access request and determines that it cannot use the search and matching mode of the search engine 102 and the first matching module 103 to perform the corresponding cache data management operation, for example, the cache data management operation that needs to be accurate to the corresponding data block, etc., the manager module 10 sequentially generates the corresponding cache access command cmd2 based on the accessed data block and issues it to the tag storage module 101.

[0119] Further, the circuit structure 100 of the cache unit further includes a second matching module 105. The second matching module 105 is configured to receive the data address of the data to be accessed from the tag storage module 101, and perform an address consistency comparison on the cache tag read from the tag storage module 101 and the data address of the data to be accessed. In response to the read cache tag being consistent with the data address of the data to be accessed, it is determined that the cache access command cmd2 hits the cache, and the hit result is sent to the data execution module 104. The data execution module 104 is further configured to perform the corresponding data access operation based on this hit result. It should be understood that the search and matching process of the cache access command cmd2 is basically the same as the process of the above comparative example, and this embodiment will not be elaborated here.

[0120] Thus, the circuit structure 100 of the cache unit of this embodiment provides a search and matching hardware for processing data management commands in different situations. While ensuring the accuracy of command execution of the cache unit, by adding a search engine and the first matching module 103 to execute Figures 4 - 9 the various implementation manners shown, the number of commands issued by the manager module is reduced, the system load and power consumption are reduced, and the system performance is improved.

[0121] In other alternative implementation manners, in the circuit structure design of the cache unit in this embodiment, the first matching module 103 and the second matching module 105 can also be integrated together, and the search engine 102, the first matching module 103 and the second matching module 105 can also be integrated together. That is, this embodiment does not limit the specific design of the hardware circuit of the circuit structure of the cache unit, as long as it can implement the above functions.

[0122] Figure 11 is a schematic diagram of the cache unit according to an embodiment of the present invention. As Figure 11 shown, the cache unit 11 according to an embodiment of the present invention includes a cache space 111 and a circuit structure 112 of the cache unit. Among them, the cache space 111 is configured to store cache data. The circuit structure 112 of the cache unit is used to receive a cache management command including an address structure having at least one address information corresponding to a physical page, and traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag, and determine the cache tag that is consistent with the address information of any address structure as the target cache tag, and perform a target data management operation on the cache data corresponding to the target cache tag. Thus, in this embodiment, it is possible to traverse and search whether the cache tags in the cache unit are hit by issuing a cache management command, and the number of searches is relatively low. At the same time, the number of commands issued by the manager module can be reduced, the system load and power consumption are reduced, and the system performance is improved. It should be understood that the specific structure and data processing process of the circuit structure 112 of the cache unit can refer to the above embodiment and will not be elaborated here.

[0123] Figure 12 is a schematic diagram of the cache management system according to an embodiment of the present invention. As Figure 12 shown, the cache management system 12 in this embodiment includes a manager module 121 and a circuit structure 122 of the cache unit. Among them, the manager module 121 is configured to receive and parse a data access request, generate the above cache management command cmd1 or cache access command cmd2, and issue the cache management command cmd1 or cache access command cmd2 to the circuit structure 122 of the cache unit for processing.

[0124] The circuit structure 122 of the cache unit is configured to receive a cache management command including at least one address structure having address information corresponding to a physical page, and traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag. The cache tag whose address information is consistent with that of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. Further, the circuit structure 122 of the cache unit is further configured to receive a cache access command including the address information of the physical page to be accessed, and perform an address consistency comparison between the read cache tag and the address information of the physical page to be accessed. In response to the read cache tag being consistent with the address information of the physical page to be accessed, it is determined that the cache access command hits the cache, and a corresponding data management operation is performed on the cached data that hits.

[0125] It should be understood that the parsing process of the cache management command cmd1 or the cache access command cmd2 generated by the manager module 121, as well as the specific structure and data processing process of the circuit structure 122 of the cache unit, can refer to the above embodiments and will not be elaborated here.

[0126] The cache management system according to the embodiment of the present invention receives a cache management command including at least one address structure having address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag. The cache tag whose address information is consistent with that of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need to be cache-managed in the accessed physical pages can be sent to the cache unit through a cache management command. Compared with Figure 2 the comparative example shown, the manager module will not generate invalid commands that cannot be hit, and will not cause waste of the bandwidth and power consumption of the cache unit. Further, the manager module in this embodiment only needs to issue a data management command and does not need to control the traversal process, reducing the time occupied by the cache management process in the manager module and further improving the system performance. Further, this embodiment uses the cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing the system load and power consumption, and improving the system performance. At the same time, for data management operations in units of physical pages, this embodiment can also use a fuzzy matching method for parallel matching, further reducing the computational amount of search matching, improving the matching efficiency, reducing the system power consumption, and improving the system performance.

[0127] At the same time, the cache management system of this embodiment provides a search matching hardware for processing data management commands in different situations. While ensuring the accuracy of command execution in the cache unit, by adding a search engine and a first matching module 103 to executeFigures 4 - 9 The various implementation manners shown reduce the number of commands issued by the management module, reduce the system load and power consumption, and improve the system performance.

[0128] Figure 13 It is a schematic diagram of the cache data management device according to an embodiment of the present invention. As Figure 13 shown, the cache data management device 13 according to an embodiment of the present invention includes a command receiving unit 131, a traversing unit 132, a determining unit 133, and an executing unit 134.

[0129] The command receiving unit 131 is configured to receive a cache management command, where the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information of a corresponding physical page. The traversing unit 132 is configured to traverse each cache tag in the cache unit to determine whether there is an address structure in each of the address structures that is consistent with the address information of the corresponding cache tag. The determining unit 133 is configured to determine the cache tag that is consistent with the address information of any of the address structures as the target cache tag. The executing unit 134 is configured to perform a target data management operation on the cache data corresponding to the target cache tag.

[0130] In the embodiment of the present invention, by receiving a cache management command including at least one address structure having address information of a corresponding physical page, and traversing each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag, the cache tag that is consistent with the address information of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. Thus, in this embodiment, it is possible to traverse and search whether the cache tags in the cache unit are hit by issuing a cache management command, the number of searches is relatively low, and at the same time, the number of commands issued by the management module can be reduced, the system load and power consumption are reduced, and the system performance is improved.

[0131] Figure 14 It is a schematic diagram of an electronic device according to an embodiment of the present invention. As Figure 14As shown in the figure, the electronic device 14 of this embodiment includes a cache unit 141, a manager module 142, and a main memory 143. Among them, the cache unit 41 is used to receive a cache management command including an address structure with address information of at least one corresponding physical page, and traverse each cache tag in the cache unit to determine whether there is an address structure in each address structure whose address information is consistent with the address information of the corresponding cache tag, determine the cache tag whose address information is consistent with any address structure as the target cache tag, and perform target data management operations on the cache data corresponding to the target cache tag. The manager module 142 is configured to receive and parse a data access request, generate a cache management command or a cache access command, and send the cache management command or the cache access command to the cache unit for processing. The main memory 143 is used to store data. Further, the main memory 143 includes multiple physical pages, and each physical page includes multiple data blocks. For details, reference can be made to Figure 1 the schematic diagram shown.

[0132] It should be understood that the parsing process of the manager module 142 for generating the cache management command or the cache access command, as well as the specific structure and data processing process of the cache unit 141, can refer to the above embodiments and will not be elaborated here.

[0133] Further, the manager module 142 of this embodiment is implemented through an operating system and a corresponding processor (such as a CPU or other processors). The main memory 143, as a non-volatile computer-readable storage medium, can be used to store the accessed data, as well as non-volatile software programs, non-volatile computer-executable programs, and modules. It should be understood that the non-volatile software programs, non-volatile computer-executable programs, and modules can also be implemented using other non-volatile memories, and this embodiment does not limit this.

[0134] The main memory 143 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store an option list, etc. In addition, the main memory 143 can include a high-speed random access memory, and can also include non-volatile memories, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the main memory 143 may optionally include a memory remotely set relative to the manager module 142 and the cache unit 141, and these remote memories can be connected to external devices through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0135] The above product can execute the method provided in the embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided in the embodiment of the present application.

[0136] The cache management system according to the embodiment of the present invention receives a cache management command including at least one address structure with address information corresponding to a physical page, and traverses each cache tag in the cache unit to determine whether there is an address structure in each address structure that is consistent with the address information of the corresponding cache tag. The cache tag that is consistent with the address information of any address structure is determined as the target cache tag, and a target data management operation is performed on the cache data corresponding to the target cache tag. In this embodiment, the physical pages that need to be cache-managed in the accessed physical pages can be sent to the cache unit through a cache management command. Compared with Figure 2 the comparative example shown, the manager module will not generate invalid commands that cannot be hit, and will not cause waste of the bandwidth and power consumption of the cache unit. Further, the manager module of this embodiment only needs to send a data management command and does not need to control the traversal process, reducing the time occupied by the cache management process in the manager module and further improving the system performance. Further, this embodiment uses the cache tags in the cache unit as the search object, greatly reducing the number of searches, further reducing the system load and power consumption, and improving the system performance. At the same time, for the data management operation in units of physical pages, this embodiment can also use a fuzzy matching method for parallel matching, further reducing the computational amount of search matching, improving the matching efficiency, reducing the system power consumption, and improving the system performance.

[0137] At the same time, the cache management system of this embodiment provides a search matching hardware for processing data management commands in different situations. While ensuring the accuracy of command execution in the cache unit, by adding a search engine and a first matching module 103 to execute Figures 4 - 9 the various implementation methods shown, the number of commands sent by the manager module is reduced, the system load and power consumption are reduced, and the system performance is improved.

[0138] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, and the computer-readable program is used for a computer to execute the above-mentioned partial or all method embodiments.

[0139] That is, those skilled in the art can understand that all or part of the steps of implementing the above-mentioned embodiment methods can be completed by instructing relevant hardware through a program. This program is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0140] The foregoing are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and variations can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A cache management method, characterized in that: The method comprises: receiving a cache management command, wherein the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information of a corresponding physical page; Traversing each cache tag in the cache unit to determine whether there is an address structure consistent with the address information of the corresponding cache tag in each address structure; Determine a cache tag that is consistent with the address information of any of the address structures as a target cache tag; Perform target data management operations on cache data corresponding to the target cache tag.

2. The method according to claim 1, characterized in that The traversing each cache tag in the cache unit to determine whether there is an address structure consistent with the address information of the corresponding cache tag in each address structure comprises: Determine the cache tag currently traversed; The address consistency comparison between the currently traversed cache tag and each of the address structures is performed in parallel to determine whether there is an address structure in each of the address structures that is consistent with the address information of the currently traversed cache tag.

3. The method according to claim 1, characterized in that The address information in the address structure includes a corresponding physical page address and a corresponding physical page size.

4. The method according to claim 3, characterized in that The consistency comparison steps between the currently traversed cache tag and the corresponding address structure include: Determine an address comparison bit between the address structure and the currently traversed cache tag based on a physical page size in the address structure; In response to the address structure and the address comparison bit values ​​of the currently traversed cache tag being consistent, it is determined that the currently traversed cache tag is consistent with the address information in the address structure.

5. The method according to claim 4, characterized in that The determining, based on the physical page size in the address structure, the address comparison bit between the address structure and the currently traversed cache tag comprises: Determine the base address length of the physical page corresponding to the address structure based on the physical page size in the address structure; The corresponding address comparison bits are captured from the address structure and the address information of the currently traversed cache tag according to the base address length.

6. A circuit structure of a cache unit, characterized in that: The circuit structure of the cache unit includes: a tag storage module, configured to store a cache tag, wherein the cache tag is a unique identifier of the cache data stored in the cache unit; A search engine configured to receive a cache management command and read a corresponding cache tag from the tag storage module, wherein the cache management command includes at least one address structure corresponding to the data to be managed, and the address structure includes address information of a corresponding physical page; a first matching module configured to receive the currently read cache tag sent by the search engine and each of the address structures carried by the cache management command, and perform an address consistency comparison between the currently read cache tag and each of the address structures, and in response to the currently read cache tag being consistent with the address information in any of the address structures, determine the cache tag as a target cache tag; The data execution module is configured to execute the target management operation of the cache data corresponding to the target cache tag received from the matching module.

7. The circuit structure of the cache unit according to claim 6, characterized in that: The first matching module is further configured to perform an address consistency comparison operation between the currently read cache tag and each of the address structures in parallel.

8. The circuit structure of the cache unit according to claim 6, characterized in that: The address information in the address structure includes a corresponding physical page address and a corresponding physical page size; The first matching module is further configured to determine the address comparison bits of the address structure and the currently read cache tag based on the physical page size in the address structure, and in response to the consistency of the values ​​of the address comparison bits of the address structure and the currently read cache tag, determine that the currently traversed cache tag is consistent with the address information in the address structure, the address comparison bits represent data bits storing the base address of the corresponding physical page, and the base address length of the corresponding physical page is determined based on the corresponding physical page size in the address structure.

9. The circuit structure of the cache unit according to claim 6, characterized in that: The tag storage module is further configured to receive a cache access command, wherein the cache access command includes a data address of data to be accessed, and the circuit structure of the cache unit further includes: a second matching module configured to receive the data address of the to-be-accessed data from the tag storage module, and perform an address consistency comparison between the cache tag read from the tag storage module and the data address of the to-be-accessed data, and in response to the read cache tag being consistent with the data address of the to-be-accessed data, determine that the cache access command hits the cache, and send the hit result to the data execution module; The data execution module is further configured to execute a corresponding data access operation based on the hit result.

10. A cache management system, characterized in that: The cache management system comprises: The circuit structure of the cache unit according to any one of claims 6 to 9; The manager module is configured to receive and parse data access requests, generate cache management commands or cache access commands, and send the cache management commands or cache access commands to the circuit structure of the cache unit for processing.

11. A cache unit, characterized in that: The cache unit comprises: A cache space, configured to store cache data; The circuit structure of a cache unit as described in any one of claims 6 to 9.

12. An electronic device, characterized in that: The electronic device comprises: The cache unit according to claim 11; A manager module is configured to receive and parse a data access request, generate a cache management command or a cache access command, and send the cache management command or the cache access command to the cache unit for processing; Main memory, used to store data.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or data, and when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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