Address information updating method, storage device and controller thereof

Abstract

The embodiment of the invention discloses an address information updating method, a storage device and a controller thereof, and the method comprises the steps: reading an incremental log into a corresponding cache queue, reading at least one target incremental log from the corresponding cache queue, the mapping relation of the same operation address in the address mapping table is updated based on at least one target incremental log, the incremental log has the corresponding operation address, and the storage group where the operation address of the incremental log is located has the corresponding cache queue. Therefore, according to the embodiment of the invention, the operation addresses corresponding to different storage groups are respectively provided with the corresponding cache queues, and the incremental logs are cached into the corresponding cache queues based on the storage groups where the operation addresses of the incremental logs are located, so that the burst flow of accessing the same storage group is effectively relieved, the reconstruction efficiency of the address mapping table is improved, and the user experience is improved. And the system performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of storage devices, and more particularly, to an address information updating method, a storage device and its controller. Background Art

[0002] In a storage device, such as a solid state drive (SSD), an address mapping table (logical address to physical address, L2P) records the mapping from the logical address space to the physical address space. Further, when new data is written to the storage space of the storage device or the data in the storage space is erased, the mapping relationship between the logical address and the physical address changes. Usually, an incremental log can be used to record the corresponding address mapping relationship changes, and then the address mapping table can be updated and rebuilt according to the incremental log. How to optimize the rebuilding process of the address mapping table is crucial for improving the device performance. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an address information updating method, a storage device and its controller, so that the operation addresses corresponding to different storage groups respectively have corresponding cache queues, and each incremental log is cached into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, effectively alleviating the burst traffic of accessing the same storage group, improving the rebuilding efficiency of the address mapping table, and further improving the system performance.

[0004] In a first aspect, an embodiment of the present invention provides an address information updating method, the method comprising:

[0005] Reading an incremental log into a corresponding cache queue; the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue;

[0006] Reading at least one target incremental log from the cache queue;

[0007] Updating the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

[0008] In a second aspect, an embodiment of the present invention provides a storage device controller, the storage device controller comprising:

[0009] A rebuilding module, the rebuilding unit includes a cache queue unit and a control unit, the cache queue unit includes at least one cache queue, each of the cache queues respectively has a corresponding storage group, and each cache queue is used to cache the incremental log whose operation address is located in the corresponding storage group;

[0010] A storage unit configured to store an address mapping table for recording the mapping relationship between a logical address and a physical address;

[0011] Wherein, the control unit is configured to read the incremental log into a corresponding cache queue, and read at least one target incremental log from the cache queue to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

[0012] In a third aspect, an embodiment of the present invention provides a storage device, which includes:

[0013] A storage space including at least one storage group, and the storage group includes at least one storage area;

[0014] The storage device controller as described above.

[0015] In a fourth aspect, an embodiment of the present invention provides an electronic device, which includes:

[0016] The storage device as described above;

[0017] A host configured to send a data processing request to the storage device and receive a data processing result from the storage device.

[0018] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, in which a computer program or data is stored, and when the computer program is executed by a processor, the method as described above is implemented.

[0019] In a sixth aspect, an embodiment of the present invention provides an address information update device, which includes:

[0020] A first reading unit configured to read the incremental log into a corresponding cache queue; the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue;

[0021] A second reading unit configured to read at least one target incremental log from the cache queue;

[0022] An update unit configured to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

[0023] In the embodiment of the present invention, the incremental log is read into the corresponding cache queue, at least one target incremental log is read from the corresponding cache queue, and the mapping relationship of the same operation address in the address mapping table is updated based on the at least one target incremental log. Wherein, the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to have corresponding cache queues respectively, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, the burst traffic of accessing the same storage group is effectively alleviated, the reconstruction efficiency of the address mapping table is improved, and thus the system performance is improved. Description of the Drawings

[0024] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0025] Figure 1 is a schematic diagram of the incremental log in the embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of the address mapping table in the embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of the L2P update process of a comparative example;

[0028] Figure 4 is a flowchart of a method for updating address information in the embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of the process of reading the incremental log into the cache queue in the embodiment of the present invention;

[0030] Figure 6 is a flowchart of the L2P entry update process in the embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of the storage device controller in the embodiment of the present invention;

[0032] Figure 8 is a flowchart of another method for updating address information in the embodiment of the present invention;

[0033] Figure 9 is a schematic diagram of a way to read the cache queue in the embodiment of the present invention;

[0034] Figure 10 is a schematic diagram of another way to read the cache queue in the embodiment of the present invention;

[0035] Figure 11 is a schematic diagram of a cache unit update process in the embodiment of the present invention;

[0036] Figure 12 is a schematic diagram of another cache unit update process according to an embodiment of the present invention;

[0037] Figure 13 is a schematic diagram of yet another cache unit update process according to an embodiment of the present invention;

[0038] Figure 14 is a schematic diagram of yet another cache unit update process according to an embodiment of the present invention;

[0039] Figure 15 is a schematic diagram of an address mapping update device according to an embodiment of the present invention;

[0040] Figure 16 is a schematic diagram of a storage device according to an embodiment of the present invention;

[0041] Figure 17 is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed implementation manners

[0042] The following description is based on embodiments of the present application, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, elements, and circuits are not described in detail.

[0043] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0044] Unless the context clearly requires otherwise, the words such as "including" and "comprising" in the entire application document should be interpreted as the meaning of including rather than exclusive or exhaustive; that is, the meaning of "including but not limited to".

[0045] In the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0046] For the solutions described in this specification and embodiments, if they involve personal information processing, they will be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. If the user refuses to process personal information other than the necessary information required for the basic functions, it will not affect the user's use of the basic functions.

[0047] The embodiments of the present invention will be mainly described in detail by taking a solid-state drive as an example of a storage device. It should be understood that the embodiments of the present invention do not limit the type of the storage device, that is, any storage device that adopts an address mapping table for recording the relationship between logical addresses and physical addresses and is updated and rebuilt based on an incremental log can adopt the embodiments of the present invention, and the specific implementation processes of various storage devices will not be described in detail one by one herein.

[0048] A solid-state drive is a hard disk that uses non-volatile memory to store data and is usually implemented using flash memory technology. A solid-state drive consists of a controller and a storage space. Among them, the storage space uses flash memory, such as NAND flash memory. The controller is responsible for data read, write, and erase operations, as well as functions such as error correction, garbage collection, and wear leveling to ensure the lifespan of the solid-state drive.

[0049] Figure 1 It is a schematic diagram of the incremental log of the embodiments of the present invention. Figure 2 It is a schematic diagram of the address mapping table of the embodiments of the present invention. After receiving a write command from the host, the solid-state drive writes the corresponding data into the storage space, which will change the mapping relationship of the corresponding address. Usually, an incremental log is used to store the address mapping relationship corresponding to these write commands. As Figure 1 shown, the incremental log stores the mapping relationship of LBA-FPA corresponding to the data processing command. Among them, the data processing command can be any command that changes the data address mapping relationship, such as a write command, an erase command, etc. Among them, LBA (Logical Block Address) is the host logical address, and FPA (Flash Physical Address) is the flash physical address of the storage space of the storage device. The address mapping table (L2P table) is used to record the mapping relationship between the data logical address and the physical address of the data stored in the storage space. As Figure 2 shown, the L2P table is an array with LBA as the subscript, and the array content is FPA. Further, the storage device usually flushes a snapshot of the L2P table (that is, the periodic log) to the corresponding storage through the incremental log every certain time or when a certain condition is met to save the L2P table. The L2P table snapshot contains the complete L2P table state at a certain point in time. By periodically creating such snapshots, the data recovery time and complexity when the main L2P table is lost or damaged can be reduced.

[0050] During the operation of the SSD, the L2P table cycle log and incremental log are periodically refreshed and cached in the NAND Flash. When the power is turned on again, the SSD controller can rebuild and restore the system L2P mapping by reading the L2P table cycle log and incremental log. Furthermore, during reconstruction, the SSD controller first reads the L2P table cycle log and incremental log from the corresponding storage unit in the NAND Flash. Among them, the L2P table cycle log and incremental log can be stored in the same storage unit or in different storage units. Furthermore, the incremental log can be read in batches or all at once according to the corresponding reconstruction plan, and the incremental log read in batches can be cached in the corresponding memory. The SSD controller implements the reconstruction and update of the L2P table based on the read L2P table cycle log and incremental log.

[0051] Furthermore, the storage unit in the SSD controller for storing the L2P table and / or the incremental log may use DRAM (Dynamic Random Access Memory). Further optionally, the storage unit for storing the L2P table may use DDR (Double Data Rate SDRAM). The SSD controller may also use SRAM (Static Random Access Memory) to cache the incremental log. It should be understood that this embodiment does not limit the storage type used by the above-mentioned storage unit or memory, which can be configured based on the actual situation of the storage device, and this embodiment will not give examples one by one.

[0052] Take DDR, the storage unit used to store the L2P table in SSD, as an example. In DDR, the memory chip is divided into multiple independent storage areas (banks), and each bank can perform read and write operations independently. With the increase of memory frequency and the improvement of data transmission rate, the operation of a single bank may become a factor limiting the overall performance, so the concept of storage group (Bank Group) is introduced in DDR design. That is, DDR optimizes the corresponding performance by dividing the storage area (bank) in the memory into multiple BankGroups and allowing concurrent operations between different BankGroups. For example, DDR4, DDR5, etc. can support multiple storage groups.

[0053] The L2P table is interleaved and stored in the Bank Group in the DDR based on a certain granularity. For sequential writes, a single Bank Group may be accessed continuously for a period of time, which reduces the DDR bandwidth utilization. For example, for DDR4 or DDR5, the performance of continuously accessing the same Bank Group is lower than that of interleaved access to different Bank Groups. In the case of random writes, in a large-capacity SSD, such as 16TB, there may be 4G L2P Entries. For DDR4, each Bank Group will cache 1G L2P Entries. The random traffic of tasks may randomly occupy different Bank Groups macroscopically, but there may be serious access to the same Bank Group microscopically, that is, there may be a situation of sudden access to a single Bank Group in a short period, reducing the overall reconstruction efficiency.

[0054] Figure 3 is a schematic diagram of the L2P update process of a comparative example. As Figure 3 shown, in this comparative example, the SSD controller includes an incremental log storage unit 31, a reconstruction unit 32, and an L2P table storage unit 33. Among them, when the SSD controller powers on and reconstructs, it reads the L2P table from the NANA storage space into the L2P table storage unit 33 and reads the incremental log into the incremental log storage unit 31. Among them, the reconstruction unit 32 includes a cache queue FIFO, a reconstruction operation module 322, and an L2P Cache.

[0055] Further, the L2P update process of this comparative example includes the following steps:

[0056] Step S31, read the incremental log from the incremental log storage unit 31 into the cache queue FIFO for caching.

[0057] Step S32, sequentially read the incremental log from the cache queue FIFO into the reconstruction operation module 322.

[0058] Step S33, the reconstruction operation module 322 parses the LBA and FPA mapping relationships in the read incremental log to generate updated L2P entries.

[0059] Step S34, the reconstruction operation module 322 sends the updated L2P entries to the L2P Cache.

[0060] Step S35, the L2P Cache performs hit detection and update operations.

[0061] Step S36, the L2P Cache reads the corresponding L2P entries to be updated from the L2P table storage unit 33 and writes the updated L2P entries into the L2P table in the L2P table storage unit 33.

[0062] Specifically, if the updated L2P entry hits the L2P Cache (i.e., an L2P entry with the same operation address is detected in the L2P Cache), the L2P entry in the L2P Cache is replaced with the updated L2P entry. Further, if the updated L2P entry misses the L2P Cache, at least one L2P entry is read from the L2P table storage unit 33 into the L2P Cache based on the operation address of the updated L2P entry, and the entry in the L2P Cache with the same operation address as the updated L2P entry is replaced with the updated L2P entry. Further, when the L2P Cache meets a predetermined condition (for example, the data volume in the L2P Cache reaches a predetermined value or a corresponding cache conflict occurs), each L2P entry in the L2P Cache is written into the L2P table in the L2P table storage unit 33 to complete the reconstruction and update of the L2P table.

[0063] For the above comparative example, in the sequential write scenario, since the incremental logs are continuous, multiple incremental logs with consecutive addresses can be updated simultaneously based on the L2P Cache, reducing the amount of data accessed from the DDR. Moreover, this comparative example also filters unnecessary DDR accesses through the L2P Cache during repeated accesses to a certain range of LBAs. However, in the random write scenario, the incremental logs are random, but they may also show local small-range access to a certain DRAM Bank Group. When accessing the same Bank Group, as the DDR interface frequency increases, the efficiency after conflict will decrease more. For example, when the DDR5 particles are at 6400MT / s, the access efficiency to the same Bank Group will decrease by 50%. Therefore, during the reconstruction in the random write scenario of the above comparative example, due to local access conflicts, it may cause a burst access to a Bank Group for a certain period of time, resulting in a decrease in the overall reconstruction performance. At the same time, in the actual application scenario, local sequential writes and local random writes coexist in a mixed manner, and the above comparative example cannot sense this, resulting in a low reconstruction performance. Based on this, the embodiments of the present invention provide an address information update method, a storage device, and its controller, so that the operation addresses corresponding to different storage groups respectively have corresponding cache queues, and each incremental log is cached into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, effectively alleviating the burst traffic of accessing the same storage group, improving the reconstruction efficiency of the address mapping table, and further improving the system performance. Thus, in this embodiment, by isolating the incremental logs corresponding to different storage groups through different cache queues, both in the random write scenario and the sequential write scenario, it is possible to avoid and alleviate the burst traffic of accessing the same storage group and improve the system performance.

[0064] Figure 4 is a flowchart of an address information update method according to an embodiment of the present invention. AsFigure 4 As shown in the figure, the address information update method according to an embodiment of the present invention includes the following steps:

[0065] Step S41: Read the incremental log into the corresponding cache queue. The incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue.

[0066] In the embodiment of the present invention, the SSD controller stores the incremental log and the L2P table obtained from the storage space into the corresponding storage unit. Among them, the storage unit for storing the incremental log can be SRAM or DRAM, or other types of storage memories. The storage unit for storing the L2P table can be DRAM, or other types of storage memories. This embodiment does not limit this.

[0067] Further, in step S41, the SSD controller controls to read the incremental log from the storage unit storing the incremental log and cache it into the corresponding cache queue.

[0068] In this embodiment, taking the L2P table stored in DRAM as the storage unit as an example, assume that the DRAM has N (N is greater than or equal to 1) storage groups (i.e., N Bank Groups). For example, a DDR5 chip has 8 storage groups, and a DDR4 chip has 4 storage groups. Then, N cache queues are configured in the SSD controller to cache the incremental logs whose operation addresses are located in the corresponding storage groups respectively. That is, the incremental logs generated by the data operations corresponding to each storage group are cached into the cache queue corresponding to the storage group when performing the reconstruction update operation.

[0069] Figure 5 It is a schematic diagram of the process of reading the incremental log of the embodiment of the present invention into the cache queue. As Figure 5 shown, taking the storage unit for storing the L2P table as DDR4 as an example, it includes 4 storage groups, Bank Group1 - Bank Group4. Among them, Bank Group1 has a corresponding cache queue FIFO1, Bank Group2 has a corresponding cache queue FIFO2, Bank Group3 has a corresponding cache queue FIFO3, and Bank Group4 has a corresponding cache queue FIFO4.

[0070] Further, the current storage unit 51 stores incremental logs wj1 - wjx (x is greater than or equal to 1). In this embodiment, the incremental logs wj1 - wjx can be allocated to corresponding cache queues based on their operation addresses. Optionally, in this embodiment, the incremental logs wj1 - wjx are sequentially read from the storage unit 51, and are allocated to corresponding cache queues based on the operation addresses of the incremental logs wj1 - wjx (such as LBA address information, etc.). For example, assume that the storage groups where the operation addresses corresponding to the incremental logs wj1, wj2, and wj5 are located are storage group Bank Group2. Then, the incremental logs wj1, wj2, and wj5 are allocated to the cache queue FIFO2 corresponding to the storage group BankGroup2. Assume that the storage groups where the operation addresses corresponding to the incremental logs wj3, wj4, and wj7 are located are storage group Bank Group1. Then, the incremental logs wj3, wj4, and wj7 are allocated to the cache queue FIFO1 corresponding to the storage group Bank Group1. Assume that the storage group where the operation address corresponding to the incremental log wj6 is located is storage group Bank Group3. Then, the incremental log wj6 is allocated to the cache queue FIFO3 corresponding to the storage group Bank Group3. Assume that the storage group where the operation address corresponding to the incremental log wj8 is located is storage group Bank Group4. Then, the incremental log wj8 is allocated to the cache queue FIFO4 corresponding to the storage group BankGroup4.

[0071] Further, if the cache of a certain cache queue is full, reading of incremental logs from the storage unit 51 can be paused. In other alternative implementation manners, if the cache of a certain cache queue is full, reading of the incremental logs to be allocated to this cache queue from the storage unit 51 can also be paused. That is, if the currently read incremental log is to be allocated to a cache queue with a full cache, this incremental log is not allocated, and subsequent incremental logs are continuously read. It should be understood that this embodiment does not limit the manner of reading and allocating incremental logs from the storage unit 51, as long as it does not affect the accuracy of subsequent L2P table periodic log reconstruction and update.

[0072] Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to respectively have corresponding cache queues, the burst traffic accessing the same storage group can be absorbed based on the cache queues with a certain depth, achieving macro - level uniformity in accessing each storage group. This effectively alleviates the burst traffic for accessing the same storage group, improves the reconstruction efficiency of the address mapping table, and further improves the system performance.

[0073] Step S42: Read at least one target incremental log from the cache queue.

[0074] In an alternative implementation, in this embodiment, the target cache queue is determined from each cache queue according to a predetermined scheduling algorithm, and at least one target incremental log is read from the target cache queue. Further optionally, in this embodiment, at least one target incremental log is read from the target cache queue based on a predetermined first interval granularity.

[0075] Since this embodiment has multiple cache queues, a certain scheduling algorithm is required to reasonably schedule each cache queue to ensure the reconstruction efficiency of the L2P table and system performance.

[0076] Further optionally, this embodiment adopts RR scheduling (Round-Robin scheduling), which divides the usage time into fixed time slices, and assigns a time slice to each cache queue in sequence to access each cache queue in turn. When the time slice of a certain cache queue is used up, the access switches to the next cache queue. Based on this, this embodiment can further control the uniformity of accessing each storage group in the DDR and further alleviate the burst traffic of accessing the same storage group. It should be understood that this embodiment does not limit the scheduling method of each cache queue. On the basis of ensuring the access uniformity of each storage group to a certain extent, other scheduling methods can be adopted, such as the multi-level feedback scheduling method, etc. This embodiment will not list them one by one here.

[0077] Furthermore, in the time slice of scheduling a certain cache queue in this embodiment, by controlling the interval granularity of reading the incremental log in the cache queue, the burst traffic of a single storage group can be further alleviated.

[0078] It should be understood that this embodiment does not limit the depth of each cache queue, the time slice length of the scheduling algorithm, and the interval granularity of reading a single cache queue. They can be configured based on actual situations to better prevent the burst traffic of accessing a single storage group, ensure the access uniformity of each storage group, and thus improve the reconstruction and update efficiency of the L2P table and the system performance.

[0079] Step S43: Update the mapping relationship of the same operation address in the address mapping table based on at least one target incremental log.

[0080] In an alternative implementation, in this embodiment, the address information of the same operation address in the address mapping table can be queried based on the operation address of the read target incremental log, the corresponding address mapping relationship can be parsed based on the target incremental log, and the address information of the same operation address in the address mapping table can be modified based on the address mapping relationship, or the address information of the same operation address in the address mapping table can be replaced with the address mapping relationship parsed based on the target incremental log to implement the update of the address mapping table.

[0081] Further optionally, in this embodiment, a cache unit is provided to implement the reconstruction and update of the address mapping table. In an optional implementation manner, the cache unit in this embodiment is used to cache address information within a certain range (that is, cache multiple L2P entries). The address information within the certain range cached in the cache unit can be the address information within the corresponding range read based on the access granularity of the storage unit during the previous incremental log update operation. It should be understood that this embodiment does not limit the caching mechanism of the cache unit. Further, after obtaining the target incremental log, it is determined whether the cache unit is hit (that is, whether there is address information in the cache unit with the same operation address as the incremental log). If the cache unit is hit, the corresponding address information in the cache unit is updated based on the address mapping relationship parsed from the target incremental log. If the cache is not hit, a certain range of address information including the operation address of the target incremental log is obtained from the storage unit to the cache unit based on the operation address of the target incremental log, and the corresponding address information in the cache unit is updated based on the address mapping relationship parsed from the target incremental log. Furthermore, when the cache in the cache unit reaches a predetermined condition (such as the cache is full or there is a cache conflict, etc.), the address information cached in the cache unit is written back to the L2P table in the storage unit to implement the update of the L2P table. Thus, since the amount of data read by a single DDR access granularity can include multiple L2P entries, this embodiment can naturally merge access scenarios with consecutive addresses through the design of the cache unit, that is, multiple consecutive L2P entries can be cached in the cache unit. Furthermore, by detecting the address continuity of multiple consecutive target incremental logs, multiple consecutive L2P entries with consecutive addresses can be updated simultaneously, so as to reduce the number of accesses to the storage unit and further improve the update efficiency of the L2P table and the system performance.

[0082] Further, the cache unit can also solve the problem of repeated access, that is, for multiple target incremental logs generated by repeatedly accessing the same operation address, they can be directly merged. That is, in the cache unit, the corresponding address information is updated based on the target incremental log corresponding to the latest access and written into the storage unit. Thus, multiple repeated accesses only require one DDR read / write operation, reducing the number of accesses to the storage unit and further improving the update efficiency of the L2P table and the system performance.

[0083] Further optionally, in this embodiment, the reconstruction and update of the address mapping table are implemented by setting multiple cache units. Taking the L2P table as an example, which is stored in a DRAM as a storage unit, assuming that the DRAM has N (N is greater than or equal to 1) storage groups (i.e., N Bank Groups), for example, a DDR5 chip has 8 storage groups and a DDR4 chip has 4 storage groups, then N cache units are configured in the SSD controller to cache L2P entries within a certain address range respectively. Thus, the embodiments of the present invention can isolate the access traffic of different storage groups based on multiple cache units, further reducing the burst access of the same storage group traffic and improving the reconstruction and update efficiency of the L2P table.

[0084] Figure 6 is a flowchart of the L2P entry update process according to the embodiments of the present invention. As Figure 6 shown, the update process of the L2P entry update according to the embodiments of the present invention includes the following steps:

[0085] Step S431, after reading the target incremental log, query the target cache unit corresponding to the target incremental log from multiple cache units. The target cache unit corresponds to the storage group where the target operation address in the target incremental log is located, that is, the target cache unit is used to cache at least part of the address information of the storage group where the target operation address of the target incremental log is located.

[0086] Step S432, send the target incremental log to the target cache unit and determine whether the target incremental log hits the target cache unit. If the address information corresponding to the target operation address is cached in the target cache unit, it is determined that the target incremental log hits the target cache unit. If the address information corresponding to the target operation address is not cached in the target cache unit, it is determined that the target incremental log does not hit.

[0087] Step S433, in response to the address information corresponding to the target operation address being cached in the target cache unit, that is, the target incremental log hits the target cache unit, update the address information of the target operation address in the target cache unit according to the target incremental log. Further, update the mapping relationship corresponding to the same operation address in the target cache unit according to the mapping relationship between the LBA and FPA parsed from the target incremental log.

[0088] Step S434, in response to the mapping relationship of the target operation address not being cached in the target cache unit, that is, the target incremental log does not hit the target cache unit, read the corresponding range of address information from the storage unit to the target cache unit according to the target operation address.

[0089] Step S435, update the address information of the target operation address in the target cache unit according to the target incremental log.

[0090] That is to say, when the mapping relationship of the target operation address is not cached in the target cache unit, a segment of address information including the mapping relationship of the target operation address is read from the storage unit to the target cache unit based on the access granularity of the storage unit, and the mapping relationship corresponding to the same operation address in the target cache unit is updated based on the mapping relationship between the LBA and the FPA obtained from the target incremental log.

[0091] Further optionally, the size of each cache unit can be designed based on an integer multiple of the access granularity of the storage unit. Assuming that the access granularity of the storage unit is 32B, the size of the cache unit can be designed as 32B, 64B, 128B, etc. Assuming that the access granularity of the storage unit is 64B, the size of the cache unit can be designed as 64B, 128B, etc. It should be understood that the present embodiment does not limit the size of each cache unit, as long as it can implement the corresponding data caching.

[0092] Further, usually the size of one L2P entry is 4B, so multiple L2P entries can be read by accessing the storage unit once. That is, the L2P entries cached in the cache unit have address continuity within a certain address range. Thus, the access scenarios with consecutive addresses can be naturally merged in each cache unit, that is, multiple consecutive L2P entries can be cached in the cache unit. Furthermore, by detecting the address continuity of multiple consecutive target incremental logs, multiple consecutive L2P entries with consecutive addresses can be updated simultaneously, thereby reducing the number of accesses to the storage unit and further improving the update efficiency of the L2P table and the system performance.

[0093] Further, this embodiment detects the address continuity of multiple target incremental logs sequentially read from the same cache queue, merges a predetermined number of target incremental logs with consecutive addresses to obtain an incremental log group, and updates the address information in the corresponding target cache unit according to the incremental log group. The target cache unit is used to cache the corresponding range of address information read from the storage unit. Optionally, if the incremental log group hits the target cache unit, the corresponding address information in the target cache unit is updated based on the address mapping relationships parsed from each target incremental log in the incremental log group. If the incremental log group does not hit the target cache unit, a segment of address information including each target operation address in the incremental log group is read from the storage unit to the target cache unit based on the target operation address of the target incremental log in the target log group, and the corresponding address information in the target cache unit is updated based on the incremental log group.

[0094] Further, this embodiment is also used to write back the updated address information in the target cache unit to the storage unit to update the L2P table in the storage unit.

[0095] Further optionally, in response to the cache unit satisfying a predetermined condition, the present embodiment writes back the address information in the cache unit to the storage unit. Optionally, the predetermined condition may be that the cache in the cache unit is full or there is a cache conflict in the cache unit, that is, multiple different L2P entries are mapped to the same cache location.

[0096] Further, in the present embodiment, each cache unit accesses the storage unit in a predetermined scheduling manner, and each cache unit accesses the storage unit at a predetermined second interval granularity within the corresponding access period.

[0097] The present embodiment adopts RR scheduling (Round-Robin scheduling), which divides the usage time into fixed time slices and allocates a time slice to each cache unit in sequence, so that each cache unit accesses the storage unit in turn. When the time slice of a certain cache unit is used up, it switches to the next cache unit for access. That is to say, within the time slice belonging to a certain cache unit, after the cache unit satisfies the above-mentioned predetermined condition, it can perform the write-back operation to the storage unit. If the current time slice does not belong to this cache unit, even if the cache unit satisfies the above-mentioned predetermined condition, it cannot perform the write-back operation. Based on this, the present embodiment can further control the uniformity of accessing each storage group in the DDR, and further alleviate the burst traffic of accessing the same storage group. It should be understood that the present embodiment does not limit the scheduling manner of each cache unit. On the basis of ensuring the access uniformity of each storage group to a certain extent, other scheduling manners can be adopted, such as the multi-level feedback scheduling manner, etc. The present embodiment will not list them one by one here.

[0098] Further, in the time slice (i.e., the access period) of scheduling a certain cache unit in the present embodiment, by controlling the interval granularity of the cache unit accessing the storage unit (i.e., the write-back operation), the burst traffic of a single storage group can be further alleviated.

[0099] It should be understood that the present embodiment does not limit the size of each cache unit, the time slice length of the scheduling algorithm, and the access interval granularity of a single cache unit within the access period. It can be configured based on the actual situation to better prevent the burst traffic of accessing a single storage group, ensure the access uniformity of each storage group, and then improve the efficiency of L2P table reconstruction and update, and improve the system performance.

[0100] In an embodiment of the present invention, incremental logs are read into corresponding cache queues, at least one target incremental log is read from the corresponding cache queue, and the mapping relationship of the same operation address in the address mapping table is updated based on the at least one target incremental log. Wherein, the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to each have a corresponding cache queue, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, the burst traffic of accessing the same storage group is effectively alleviated, the reconstruction efficiency of the address mapping table is improved, and thus the system performance is improved. Further, in an embodiment of the present invention, the influence of different storage groups on the cache unit is isolated by different cache units, and the interleaved and uniform access to multiple storage groups can be achieved in cooperation with multiple cache queues, further improving the access efficiency of the storage unit, and thus further improving the reconstruction efficiency of the address mapping table and the system performance.

[0101] Figure 7 It is a schematic diagram of a storage device controller according to an embodiment of the present invention. Figure 8 It is a flowchart of another address information update method according to an embodiment of the present invention. Wherein, in the storage device, the update process of the L2P table is controlled and executed by the storage device controller. As Figure 7 shown, the storage device controller includes a reconstruction module 72 and a storage unit. Further, the storage unit includes an incremental log storage unit 71 and an L2P table storage unit 73. It should be understood that the incremental log and the L2P table cycle log can be stored in the same storage unit or different storage units, and this embodiment does not limit this.

[0102] As Figure 7 shown, the reconstruction module 72 includes a cache queue unit 721, a control unit 722, and a cache area 723. Wherein, the cache queue unit 721 includes N cache queues FIFO 1 - FIFO N. Wherein, N is greater than or equal to 1. Each cache queue has a corresponding storage group, and each cache queue is used to cache incremental logs whose operation addresses are located in the corresponding storage group. The control unit 722 is configured to read incremental logs into the corresponding cache queue and read at least one target incremental log from the cache queue, so as to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log. Wherein, the cache queue can be implemented based on corresponding hardware or software, and this embodiment does not limit the specific implementation manner of the cache queue.

[0103] The cache area 723 includes N cache units Cache 1 - Cache N, where N is greater than or equal to 1. Each cache unit is configured to cache address information of a predetermined size read from the L2P table storage unit 73 and address information updated based on the incremental log in the corresponding cache queue. Each cache unit has a corresponding storage group, and the address information cached by the cache unit is located in the corresponding storage group. The control unit 722 is further configured to, in response to the target operation address of the target incremental log hitting the corresponding target cache unit, update the address information of the target operation address in the target cache unit according to the target incremental log; in response to the target operation address of the target incremental log not hitting the corresponding target cache unit, read the corresponding range of address information from the storage unit to the target cache unit, and update the address information of the target operation address in the target cache unit according to the target incremental log.

[0104] Further, in this embodiment, the number of cache queues and cache units is the same as the number of storage groups (Bank Group) in the storage unit storing L2P, that is, each storage group has its corresponding cache queue and cache unit. By making the operation addresses corresponding to different storage groups have corresponding cache queues respectively, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, this embodiment effectively alleviates the burst traffic of accessing the same storage group, and isolates the influence of different storage groups on the cache unit through different cache units, and can cooperate with multiple cache queues to achieve interleaved and uniform access to multiple storage groups as a whole, improving the access efficiency of the storage unit, and further improving the reconstruction efficiency of the address mapping table and system performance.

[0105] As Figure 8 shown, the address information update method of the embodiment of the present invention includes the following steps:

[0106] Step S81, read the incremental log wjx from the incremental log storage unit 71.

[0107] Step S82, determine the target cache queue according to the address information of the incremental log wjx. Further, in this embodiment, the target cache queue can be the cache queue corresponding to the storage group where the LBA address information of the incremental log wjx is located in the L2P table storage unit 73.

[0108] Step S83, cache the incremental log wjx into the target cache queue. For example, assume that the target cache queue corresponding to the incremental log wjx is the cache queue FIFO 1, then cache the incremental log wjx into the cache queue FIFO 1.

[0109] Further, after writing the incremental log wjx to the target cache queue, it is possible to determine whether the cache of the target cache queue is full. If the cache of the target cache queue is full, reading of incremental logs from the incremental log storage unit 71 can be paused. In other alternative implementation manners, if the cache of the target cache queue is full, reading of the incremental logs to be allocated to the target cache queue from the incremental log storage unit 71 can also be paused. That is, if the currently read incremental log is to be allocated to a cache queue with a full cache, the incremental log is not allocated, and subsequent incremental logs are continuously read. It should be understood that the present embodiment does not limit the manner of reading and allocating incremental logs from the incremental log storage unit 71, as long as it does not affect the accuracy of subsequent L2P table periodic log reconstruction and update.

[0110] Step S84: Read at least one target incremental log from the cache queue corresponding to the current reading cycle. In this embodiment, the RR scheduling algorithm is used to schedule cache queues FIFO 1 - FIFO N as an example. It should be understood that the scheduling algorithm of this embodiment is not limited thereto.

[0111] Optionally, in the current reading cycle of this embodiment, target incremental logs are read from the cache queue at a first interval granularity.

[0112] Figure 9 is a schematic diagram of a cache queue reading method according to an embodiment of the present invention. In an alternative implementation manner, in the current reading cycle of this embodiment, a reading operation is performed on the corresponding cache queue every first interval granularity, and each reading operation reads one target incremental log. As Figure 9 shown, if the cache queue corresponding to the current reading cycle is cache queue FIFO 1, wj3 is read from cache FIFO 1 at time t0, wj4 is read from cache FIFO 1 at time t1 after an interval of the first interval granularity, and wj7 is read from cache FIFO 1 at time t2 after an interval of the first interval granularity until the end of the current reading cycle.

[0113] Figure 10 is a schematic diagram of another cache queue reading method according to an embodiment of the present invention. In another alternative implementation manner, in the current reading cycle of this embodiment, a reading operation is performed on the corresponding cache queue every first interval granularity. During the current reading operation, the address continuity between adjacent incremental logs is judged. If the operation addresses of a predetermined number of consecutive incremental logs are continuous, then a predetermined number of incremental logs with continuous addresses are read at one time during the current reading operation. As Figure 10As shown, if the cache queue corresponding to the current read cycle is cache queue FIFO 1, at time t0, two incremental logs wj3 and wj4 are read from cache FIFO 1, and it is determined whether the operation addresses of incremental logs wj3 and wj4 are consecutive. If they are consecutive, the next incremental log wj7 is continuously read from cache FIFO 1, and it is determined whether the operation addresses of incremental logs wj4 and wj7 are consecutive until the addresses are detected to be non-consecutive or the number of read incremental logs reaches the maximum value. In this embodiment, as Figure 10 described, at time t0 in the current read cycle, address continuity detection is performed. If the operation addresses of incremental logs wj3, wj4, wj7, and wj9 are consecutive, then during the current read operation, incremental logs wj3, wj4, wj7, and wj9 are read at one time as target incremental logs, and at time t1 after an interval of the first interval granularity, the target incremental logs are continuously read based on the same method.

[0114] In other alternative implementation manners, in this embodiment, a data model that meets the address continuity condition can also be pre-constructed in advance. When it is detected that multiple consecutive incremental logs meet this data model, it is determined that these incremental logs have address continuity.

[0115] Further optionally, in this embodiment, it is sequentially detected whether the operation addresses corresponding to adjacent incremental logs are consecutive until the operation addresses corresponding to the currently detected adjacent incremental logs are non-consecutive, or the number of incremental logs with consecutive addresses reaches a predetermined value. In other alternative implementation manners, in this embodiment, it is detected whether the operation addresses corresponding to adjacent predetermined incremental logs read are consecutive. Among them, in this embodiment, the specific value of the number of the detected predetermined incremental logs is not limited, and it can be calculated and configured according to the actual situation of the storage device. Further, the number of the detected predetermined incremental logs can be determined according to system resources, for example, determined according to the number of commands aggregated by a command processing aggregation unit in a controller of the storage device, etc. Further, the number of the predetermined incremental logs in this embodiment can also be determined according to the maximum number of incremental logs that can be updated by a single read / write operation of a storage unit, for example, making it less than or equal to this maximum number, or the number of the predetermined incremental logs for address continuity detection includes multiple values (such as 2, 3,..., M), and each incremental log with the maximum predetermined value that meets address continuity is used as a target incremental log. For example, assume that incremental logs wj1 - wj10 are cached in the cache queue and the maximum number M is greater than or equal to 4. If it is detected that incremental logs wj1 - wj4 have address continuity and the addresses of incremental logs wj4 and wj5 are non-consecutive, then incremental logs wj1 - wj4 are read from this cache queue as target incremental logs. If it is detected that incremental logs wj1 - wj3 have address continuity and the addresses of incremental logs wj3 and wj4 are non-consecutive, then incremental logs wj1 - wj3 are read from this cache queue as target incremental logs.

[0116] It should be understood that this embodiment does not limit the specific manner of detecting whether the continuous incremental log has address continuity, and it is only necessary to be able to detect whether the operation addresses corresponding to the incremental log are continuous.

[0117] Step S85, after reading the target incremental log, query the target cache unit corresponding to the target incremental log from multiple cache units. Among them, the target cache unit corresponds to the storage group where the target operation address in the target incremental log is located, that is, the target cache unit is used to cache at least part of the address information of the storage group where the target operation address of the target incremental log is located.

[0118] Step S86, send the target incremental log to the target cache unit, and determine whether the target incremental log hits the target cache unit. If the address information corresponding to the target operation address is cached in the target cache unit, it is determined that the target incremental log hits the target cache unit. If the address information corresponding to the target operation address is not cached in the target cache unit, it is determined that the target incremental log does not hit.

[0119] Step S87, in response to the address information corresponding to the target operation address being cached in the target cache unit, that is, the target incremental log hits the target cache unit, update the address information of the target operation address in the target cache unit according to the target incremental log. Further, update the mapping relationship corresponding to the same operation address in the target cache unit according to the mapping relationship between the LBA and FPA parsed from the target incremental log.

[0120] Step S88, in response to the mapping relationship of the target operation address not being cached in the target cache unit, that is, the target incremental log does not hit the target cache unit, read the corresponding range of address information from the storage unit to the target cache unit according to the target operation address.

[0121] Step S89, update the address information of the target operation address in the target cache unit according to the target incremental log.

[0122] As Figure 7 shown, assume that the control unit 722 reads the target incremental log wjy from the cache queue FIFO 1, and the cache unit corresponding to the storage group where the target operation address of the target incremental log wjy is located is Cache 1. The control unit 722 parses the target incremental log wjy to obtain the corresponding mapping relationship LBAy - FPAy, and sends the mapping relationship LBAy - FPAy to the cache unit Cache 1 for hit detection.

[0123] Figure 11It is a schematic diagram of the update process of a cache unit in an embodiment of the present invention. This embodiment is used to describe the update process of the target cache unit Cache 1 corresponding to the hit of a single target incremental log wjy. As Figure 11 shown, the control unit 722 sends the mapping relationship LBAy-FPAy corresponding to the read target incremental log wjy to the target cache unit Cache 1. At the same time, there is an L2P entry LBAy-FPAy' in the target cache unit Cache 1, that is, the target incremental log wjy hits the cache unit Cache 1. Then, the address information of the same operation address in the target cache unit Cache 1 is updated based on the mapping relationship LBAy-FPAy corresponding to the target incremental log wjy. As Figure 11 shown, in the updated target cache unit Cache 1, the address mapping relationship of the address information LBAy is updated to LBAy-FPAy.

[0124] Figure 12 It is a schematic diagram of the update process of a cache unit in an embodiment of the present invention. This embodiment is used to describe the update process of the target cache unit Cache 1 corresponding to the miss of a single target incremental log wjy. As Figure 12 shown, the control unit 722 sends the mapping relationship LBAy-FPAy corresponding to the read target incremental log wjy to the target cache unit Cache 1. The address mapping relationship of the address LBAy is not cached in the target cache unit Cache 1, that is, the target incremental log wjy misses the target cache unit Cache 1. The control reads a segment of address information (the length of the address information is determined based on the access granularity of the L2P table storage unit 73) including the address mapping relationship LBAy-FPAy' of the address LBAy from the L2P table storage unit 73 based on the address LBAy and caches it in the target cache unit Cache 1. Further, the address information of the same operation address in the target cache unit Cache 1 is updated based on the mapping relationship LBAy-FPAy corresponding to the target incremental log wjy. As Figure 12 shown, in the updated target cache unit Cache 1, the address mapping relationship of the address information LBAy is updated to LBAy-FPAy.

[0125] Figure 13 It is a schematic diagram of another cache unit update process in an embodiment of the present invention. This embodiment is used to describe the update process of the target cache unit Cache 1 corresponding to the hits of multiple target incremental logs wjy1-wjy4 with consecutive addresses. As Figure 13As shown, the control unit 722 sends the mapping relationships LBAy1-FPAy1, LBAy2-FPAy2, LBAy3-FPAy3, and LBAy4-FPAy4 corresponding to the read target incremental logs wjy1-wjy4 to the target cache unit Cache 1. At the same time, there are L2P entries LBAy1-FPAy1', LBAy2-FPAy2', LBAy3-FPAy3', and LBAy4-FPAy4' in the target cache unit Cache1, that is, the target incremental logs wjy1-wjy4 hit the cache unit Cache1. Then, the address information of the same operation address in the target cache unit Cache 1 is updated based on the mapping relationships LBAy1-FPAy1, LBAy2-FPAy2, LBAy3-FPAy3, and LBAy4-FPAy4 corresponding to the target incremental logs wjy1-wjy4. As Figure 13 shown, in the updated target cache unit Cache 1, the address mapping relationships of the address information LBAy1, LBAy2, LBAy3, and LBAy4 are updated to LBAy1-FPAy1, LBAy2-FPAy2, LBAy3-FPAy3, and LBAy4-FPAy4.

[0126] Figure 14 It is a schematic diagram of another cache unit update process according to an embodiment of the present invention. This embodiment is used to describe the update process of the target cache unit Cache 1 when multiple target incremental logs wjy1-wjy4 with consecutive addresses miss. As Figure 14As shown, the control unit 722 sends the mapping relationships LBAy1 - FPAy1, LBAy2 - FPAy2, LBAy3 - FPAy3, LBAy4 - FPAy4 corresponding to the read target incremental logs wjy1 - wjy4 to the target cache unit Cache 1. There is no cached address mapping relationship for the addresses LBAy1 - LBAy4 in the target cache unit Cache 1, that is, the target incremental logs wjy1 - LBAy4 miss the target cache unit Cache 1. The control reads a segment of address information including the address mapping relationships LBAy1 - FPAy1', LBAy2 - FPAy2', LBAy3 - FPAy3', LBAy4 - FPAy4' of the addresses LBAy1 - LBAy4 from the L2P table storage unit 73 based on the address LBAy1 (the length of the address information is determined based on the access granularity of the L2P table storage unit 73, and the data volume of this access granularity is greater than the total data volume of 4 L2P entries), and caches it in the target cache unit Cache 1. Further, based on the mapping relationships LBAy1 - FPAy1, LBAy2 - FPAy2, LBAy3 - FPAy3, LBAy4 - FPAy4 corresponding to the target incremental logs wjy1 - wjy4, the address information of the same operation address in the target cache unit Cache 1 is updated. As Figure 14 shown, in the updated target cache unit Cache 1, the address mapping relationships of the address information LBAy1 - LBAy4 are updated to LBAy1 - FPAy1, LBAy2 - FPAy2, LBAy3 - FPAy3, LBAy4 - FPAy4.

[0127] It can be seen that in this embodiment, the cache unit can better handle the data operation scenario with consecutive addresses, realizes the function of simultaneously updating multiple incremental logs with consecutive addresses, reduces the access times of the storage unit, and improves the update efficiency of the L2P table and the system performance.

[0128] Further, this embodiment can also handle the consecutive operation scenario of the same address through the cache unit, so that the incremental logs corresponding to the data operations of this address can be updated to the latest address mapping relationship in the cache unit, avoiding frequent access to the storage unit, and further improving the update efficiency of the L2P table and the system performance.

[0129] Further, as shown in the figure, the address information update method of this embodiment further includes: step S8A, writing back the address information in the target cache queue corresponding to the current access cycle to the storage unit. This embodiment takes the RR scheduling algorithm as an example to execute the access scheduling of the cache units Cache 1 - Cache N. It should be understood that the scheduling algorithm of this embodiment is not limited to this.

[0130] Further optionally, in the current access cycle of this embodiment, the access operation of the corresponding cache unit is performed according to the second interval granularity. Assuming that the scheduling access of the cache unit Cache 1 needs to be performed in the current access cycle, the cache unit Cache 1 can be controlled to access the L2P table storage unit 73 every second interval granularity, so as to write back the address information cached in the cache unit Cache 1 to the L2P table storage unit 73, thereby realizing the update of the L2P table.

[0131] In an alternative implementation, this embodiment can also determine whether the corresponding cache unit meets a predetermined condition every second interval granularity, and write back the address information cached in the cache unit Cache 1 to the L2P table storage unit 73 when the predetermined condition is met (such as the cache unit is full or a cache conflict occurs, etc.). Thus, this embodiment can control the access frequency of a single storage group by controlling the access cycle and the size of the second interval granularity, thereby further avoiding the burst traffic of a single storage group access.

[0132] It should be understood that this embodiment does not limit the depths of the respective cache queues in the storage device controller, the read cycles of the cache queues, the first interval granularity, the depths of the respective cache units, the access cycles of the cache units, and the values of the second interval granularity. The depths of the respective cache queues, the read cycles of the cache queues, and the values of the first interval granularity can be the same or different, and the depths of the respective cache units, the access cycles of the cache units, and the values of the second interval granularity can be the same or different, and they can all be set based on specific hardware configurations and application scenarios.

[0133] Furthermore, the control unit 722 of this embodiment may include a front-end control module (FE, Front End), an intermediate control module (FTL, Flash Translation Layer), and a back-end control module (BE, Back End). The front-end control module is used to perform functions such as protocol parsing and request queue management on the received data processing requests. The intermediate control module is used to map the logical address corresponding to the data processing request to a specific physical storage unit, and implement functions such as wear leveling, garbage collection, bad block management, and partition structure planning. The back-end control module is used to perform interaction operations with the physical storage medium (i.e., the storage space 82), such as sending commands such as read / write, erase, and garbage collection to the storage space. The control unit 722 of this embodiment realizes the data reading function through the FE module, the FTL module, and the BE module.

[0134] Further, in this embodiment, corresponding control functions are added in the FE module or the FTL module to implement scheduling control of the cache queue and cache unit, as well as address continuity detection, etc. Alternatively, a corresponding control module can be independently set in the control unit 722 to implement the above functions. This embodiment does not limit this.

[0135] In the embodiment of the present invention, incremental logs are read into corresponding cache queues, at least one target incremental log is read from the corresponding cache queue, and the mapping relationship of the same operation address in the address mapping table is updated based on the at least one target incremental log. Among them, the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to each have a corresponding cache queue, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, the burst traffic of accessing the same storage group in various scenarios (such as random write scenario, sequential write scenario, random write + sequential write scenario, repeated write scenario, etc.) and the access frequency to the storage unit are effectively alleviated, the reconstruction efficiency of the address mapping table is improved, and thus the system performance is improved. Further, in the embodiment of the present invention, the influence of different storage groups on the cache unit is isolated by different cache units, and overall cooperation with multiple cache queues can achieve interleaved and uniform access to multiple storage groups, further improving the access efficiency of the storage unit, and thus further improving the reconstruction efficiency of the address mapping table and the system performance.

[0136] Figure 15 is a schematic diagram of the address mapping update device according to the embodiment of the present invention. As Figure 15 shown, the address mapping update device 15 of this embodiment includes a first reading unit 151, a second reading unit 152, and an update unit 153.

[0137] The first reading unit 151 is configured to read incremental logs into corresponding cache queues; the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. The second reading unit 152 is configured to read at least one target incremental log from the cache queue. The update unit 153 is configured to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

[0138] In an embodiment of the present invention, incremental logs are read into corresponding cache queues, at least one target incremental log is read from the corresponding cache queue, and the mapping relationship of the same operation address in the address mapping table is updated based on the at least one target incremental log. Among them, the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to have corresponding cache queues respectively, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, the burst traffic of accessing the same storage group and the access frequency to the storage unit in various scenarios are effectively alleviated, the reconstruction efficiency of the address mapping table is improved, and thus the system performance is improved.

[0139] Figure 16 is a schematic diagram of a storage device according to an embodiment of the present invention. As Figure 16 shown, the storage device of this embodiment includes a storage device controller 161 and a storage space 162. Among them, the storage space 162 is used to store data. Optionally, the storage device of this embodiment uses a non-volatile memory to store data. Further, the storage space 162 is implemented by using flash memory technology. For example, the storage space 162 can use NAND flash memory. It should be understood that this embodiment does not limit the flash memory technology used by the storage space 162. The storage device controller 161 can be an integrated circuit chip with corresponding signal processing capabilities, and is used to perform operations such as reading, writing, and erasing on the data in the storage space 162.

[0140] It should be understood that the specific structure of the storage device controller 161 in this embodiment is Figure 7 similar to the structure shown, and will not be described in detail here.

[0141] Figure 17 is a schematic diagram of an electronic device according to an embodiment of the present invention. As Figure 17 shown, the electronic device 17 of this embodiment includes a storage device 171 and a host 172. Among them, the host 172 is configured to send data processing commands to the storage device 171 and receive data processing results from the storage device 171. Optionally, the host 172 can be a data processing device capable of reading data in the storage device, and this embodiment does not limit the type of the host 172.

[0142] The storage device 171 in the electronic device 17 of this embodiment includes a controller and a storage space for storing data. Further, the specific structure of the controller in this embodiment Figure 7 is similar to the structure shown, and will not be described in detail here.

[0143] In the electronic device according to the embodiment of the present invention, the storage device of the electronic device reads the incremental logs into the corresponding cache queues, reads at least one target incremental log from the corresponding cache queue, and updates the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log. Wherein, the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue. Thus, in this embodiment, by enabling the operation addresses corresponding to different storage groups to respectively have corresponding cache queues, and caching each incremental log into the corresponding cache queue based on the storage group where the operation address of each incremental log is located, the burst traffic of accessing the same storage group is effectively alleviated, the reconstruction efficiency of the address mapping table is improved, and thus the system performance is improved.

[0144] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, and the computer-readable program is used for a computer to execute the above-mentioned partial or all method embodiments.

[0145] That is, those skilled in the art can understand that all or part of the steps of implementing the above-mentioned embodiment methods can be completed by instructing relevant hardware through a program. The program is stored in a storage medium, including several instructions for enabling a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0146] The foregoing are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for updating address information, characterized in that: The method comprises: Reading an incremental log into a corresponding cache queue; the incremental log has a corresponding operation address, and the storage group where the operation address of the incremental log is located has a corresponding cache queue; Reading at least one target incremental log from the cache queue; The mapping relationship of the same operation address in the address mapping table is updated based on the at least one target incremental log.

2. The method according to claim 1, characterized in that The updating of the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log includes: Querying a target cache unit corresponding to the target incremental log from multiple cache units, the target cache unit being used to cache at least part of the address information of the storage group where the target operation address of the target incremental log is located; In response to the address information of the target operation address being cached in the target cache unit, the address information of the target operation address in the target cache unit is updated according to the target incremental log.

3. The method according to claim 2, characterized in that The updating of the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log further includes: In response to a mapping relationship that the target operation address is not cached in the target cache unit, reading address information of a corresponding range from a storage unit according to the target operation address to the target cache unit; The address information of the target operation address in the target cache unit is updated according to the target incremental log.

4. The method according to claim 1, characterized in that: The updating of the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log includes: Detecting the address continuity of the plurality of target incremental logs read; Merge the predetermined target incremental logs with consecutive addresses to obtain an incremental log group; The address information in the corresponding target cache unit is updated according to the incremental log group, and the target cache unit is used to cache the address information of the corresponding range read from the storage unit.

5. The method according to claim 1, characterized in that The step of reading at least one target incremental log from the cache queue comprises: Determining a target cache queue from each of the cache queues according to a predetermined scheduling algorithm; At least one of the target incremental logs is read from the target cache queue.

6. The method according to claim 5, characterized in that The scheduling algorithm is a polling scheduling algorithm, and the reading of the target incremental log from the target cache queue includes: At least one of the target incremental logs is read from the target cache queue based on a predetermined first interval granularity.

7. The method according to any one of claims 2 to 4, characterized in that: The updating of the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log further includes: The updated address information in the target cache unit is written back to the storage unit.

8. The method according to claim 7, characterized in that Each of the cache units accesses the storage unit in a predetermined scheduling manner, and each of the cache units accesses the storage unit in a predetermined second interval granularity within a corresponding access cycle.

9. A storage device controller, characterized in that: The storage device controller comprises: A reconstruction module, wherein the reconstruction unit includes a cache queue unit and a control unit, wherein the cache queue unit includes at least one cache queue, each of the cache queues has a corresponding storage group, and each cache queue is used to cache an incremental log whose operation address is located in a corresponding storage group; A storage unit configured to store an address mapping table, wherein the address mapping table is used to record a mapping relationship between a logical address and a physical address; The control unit is configured to read the incremental log into the corresponding cache queue, and read at least one target incremental log from the cache queue to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

10. The storage device controller according to claim 9, characterized in that: The reconstruction module also includes: A cache area, the cache area comprising at least one cache unit, configured to cache address information of a predetermined size read from the storage unit and address information updated based on the incremental log in the cache queue, each of the cache units having a corresponding storage group, and the address information cached by the cache unit is located in the corresponding storage group; The control unit is also configured to, in response to the target operation address of the target incremental log hitting the corresponding target cache unit, update the address information of the target operation address in the target cache unit according to the target incremental log; in response to the target operation address of the target incremental log not hitting the corresponding target cache unit, read the address information of the corresponding range from the storage unit to the target cache unit according to the target operation address, and update the address information of the target operation address in the target cache unit according to the target incremental log.

11. A storage device, characterized in that: The storage device comprises: A storage space, wherein the storage space includes at least one storage group, and the storage group includes at least one storage area; A storage device controller as claimed in claim 9 or 10.

12. An electronic device, characterized in that: The electronic device comprises: The storage device as claimed in claim 11; The host is configured to send a data processing request to the storage device and receive a data processing result from the storage device.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program or data, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

14. An address information updating device, characterized in that: The device comprises: A first reading unit is configured to read an incremental log into a corresponding cache queue; the incremental log has a corresponding operation address, and a storage group where the operation address of the incremental log is located has a corresponding cache queue; A second reading unit is configured to read at least one target incremental log from the cache queue; An updating unit is configured to update the mapping relationship of the same operation address in the address mapping table based on the at least one target incremental log.

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