FPGA-based parallel anti-skid frame synchronization method and system

Abstract

A parallel anti-skid frame synchronization method based on FPGA, comprising: setting two delay adjustment modules at the entrance and exit of the parallel anti-skid frame synchronization module; setting the initial value of the delay amount of the two delay adjustment modules as 0; instantiating parallel N shift registers by a frame synchronization detection module, inputting the frame synchronization word of the frame synchronization data into the frame synchronization word pattern by correlating the stored data of the shift register with the frame synchronization word pattern, and entering the checking state of the state machine from the searching state after detecting the frame synchronization word pattern. In the checking state, the data in the current shift register is compared with the set frame synchronization word pattern, and when the continuously detected frame synchronization words are all correct, it is considered that the frame synchronization is locked, and the data frame starts to be received; when the skid occurs, that is, the detected frame header is within the range of the allowed skid, the positive or negative adjustment is performed on the basis of the current delay amount D1, the delay amount D2 is set as N / 2, and the frame synchronization data output is performed. The application saves the hardware memory resources, has stable performance, and is easy to implement in engineering.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of satellite TT&C and communication technology, and more particularly relates to a high-speed parallel anti-sliding frame synchronization method based on FPGA. BACKGROUND

[0002] Due to the demand of high data rate of high-speed data transmission baseband in a TT&C system, a parallel baseband signal processing architecture is generated. Since the starting position of a frame synchronization word can appear at any position of N parallel paths, in order to find the frame synchronization word head, N sliding windows are generally instantiated to traverse all positions of the frame synchronization word. In FPGA implementation, instantiating N sliding windows means that N memories need to be instantiated. In an actual TT&C system, sliding phenomenon occurs, which causes the frame synchronization word of the next frame to not necessarily appear at the end position of the previous frame. In this case, if the arbitrator judges that the frame is out of step and then re-performs frame synchronization, valid information will be wasted. Therefore, the frame synchronization word frame synchronization algorithm needs to resist such sliding. In order to resist sliding of ±k bits, 2k additional sliding windows need to be instantiated, thereby occupying more hardware resources. SUMMARY

[0003] The technical problem to be solved by the application is how to save the additional instantiated memory resources for resisting sliding, while realizing efficient high-speed parallel frame synchronization.

[0004] The application solves the above technical problems by the following technical means: constructing a parallel anti-sliding frame synchronization system, setting two delay adjustment modules with variable delay amounts at the entrance and exit of the parallel anti-sliding frame synchronization module, and after the frame synchronization enters a locked state, realizing high-speed parallel frame synchronization output by setting the two delay adjustment modules. Specifically,

[0005] A parallel anti-sliding frame synchronization method based on FPGA, comprising the following steps:

[0006] Step 1: setting two delay adjustment modules with variable delay amounts at the entrance and exit of the parallel anti-sliding frame synchronization module: a first delay adjustment module and a second delay adjustment module, the delay amounts of the first delay adjustment module and the second delay adjustment module being D1 and D2 respectively;

[0007] Step 2: setting the initial value of the delay amount D1 of the first delay adjustment module and the initial value of the delay amount D2 of the second delay adjustment module to 0 since the frame synchronization module has not started working;

[0008] Step 3: The frame synchronization process is divided into three states: search state, verification state and lock state. In the search state, the frame synchronization word position is detected, corresponding to N parallel inputs. The frame synchronization word head appears in any position of the parallel N roads. N sliding windows are needed to be established to correlate with the frame synchronization word pattern to find the frame synchronization word head. Each sliding window is shifted by one bit relative to the previous window to traverse all possible frame synchronization word head positions. The frame synchronization word detection process is to correlate the synchronization word head with the N sliding windows. After detecting the frame synchronization word, the search state enters the verification state.

[0009] Step 4: In the verification state, the data in the current shift register is correlated with the set frame synchronization word pattern every frame length bit. If it does not match, it returns to the search state to search for synchronization again. When the frame synchronization word is correctly detected in the verification state continuously, it is considered that the frame synchronization is locked, and enters the lock state to start receiving data frames.

[0010] Step 5: After entering the frame synchronization lock state, the delay D1 of the first delay adjustment module is set to the difference between the detected frame synchronization word position and the number N / 2 of parallel roads. When slip occurs, if the detected frame synchronization word position is within the allowed range of slip, the delay D1 is adjusted positively or negatively based on the current delay D1. The delay D2 of the second delay adjustment module is set to N / 2.

[0011] As a further optimized technical solution, the role of the two delay adjustment modules is to adjust the Mth parallel N road to any position of the parallel N road by setting a variable delay.

[0012] As a further optimized technical solution, in step 5, the adjusted frame synchronization word position is at the N / 2th position, and the input parallel N data is adjusted to the center position of the frame synchronization word head in the parallel N road.

[0013] As a further optimized technical solution, in step 2, the delay adjustment starts to work after detecting the frame synchronization word position.

[0014] As a further optimized technical solution, in step 5, due to the role of the first delay adjustment module, the frame synchronization word position always appears at the center position of the input parallel N data. The delay D2 of the delay adjustment 2 is fixedly set to N / 2, so that it is directly output as the 1st position of the parallel N road.

[0015] As a further optimized technical solution, in step 3, the process of finding the frame synchronization word is to perform bitwise exclusive OR operation between the input data of the N windows and the given frame synchronization word pattern, and then perform bitwise summation to obtain the Hamming distance between the input data of the N windows and the frame synchronization word pattern. When the Hamming distance is less than the given frame synchronization word search tolerance bit number, the frame synchronization word head is found, and the verification state is entered.

[0016] As a further optimization technical solution, in step 4, only the output data in the frame synchronization lock state is valid, when the frame synchronization word is compared in the checking state, if there is a slip, the bit number of the frame header is not matched, therefore the slip bit number in the frame synchronization word position detected in the lock state is allowed to be shifted.

[0017] As a further optimization technical solution, in step 4, in the lock state, whether the frame synchronization word is normally present is also checked, if the frame synchronization word is not continuously detected, the search state is re-entered.

[0018] As a further optimization technical solution, in step 1, a parallel anti-slip frame synchronization system is first constructed, the parallel anti-slip frame synchronization system comprises a first delay adjustment module, a second delay adjustment module, a frame synchronization detection module and a frame synchronization state machine, wherein the input end of the first delay adjustment module receives parallel N-way frame synchronization input, the output end of the first delay adjustment module is connected to the second delay adjustment module and the frame synchronization detection module at the same time, the frame synchronization detection module is connected to the first delay adjustment module and the frame synchronization state machine at the same time, the frame synchronization state machine is connected to the frame synchronization detection module and a frame synchronization output valid identification, and the output of the second delay adjustment module is parallel N-way frame synchronization output data.

[0019] The application also provides a synchronization system adopting the parallel anti-slip frame synchronization method based on FPGA according to any one of the above solutions, comprising a first delay adjustment module, a second delay adjustment module, a frame synchronization detection module and a frame synchronization state machine, wherein the input end of the first delay adjustment module receives parallel N-way frame synchronization input, the output end of the first delay adjustment module is connected to the second delay adjustment module and the frame synchronization detection module at the same time, the frame synchronization detection module is connected to the first delay adjustment module and the frame synchronization state machine at the same time, the frame synchronization state machine is connected to the frame synchronization detection module and a frame synchronization output valid identification, and the output of the second delay adjustment module is parallel N-way frame synchronization output data.

[0020] The application has the advantages that a high-speed parallel anti-slip frame synchronization scheme based on FPGA is provided, the method can save the shift memory resources due to the anti-slip additional instantiation, and by adjusting the delay of the input parallel data, the slip can be resisted to the maximum extent. The scheme can be applied to architectures with different parallel numbers on the basis of saving the hardware memory resources, has high expandability and is easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A flowchart of a parallel anti-slip frame synchronization method based on FPGA according to an embodiment of the application is shown in the figure.

[0022] Figure 2The schematic diagram of the delay adjustment module in the embodiment of the present application;

[0023] Figure 3 The frame synchronization state transition diagram in the embodiment of the present application;

[0024] Figure 4 The shift register data moving-in process in the frame synchronization detection in the embodiment of the present application;

[0025] Figure 5 The shift register storage data after the action of the delay adjustment module 1 in the embodiment of the present application;

[0026] Figure 6 The shift register schematic diagram when the slip occurs in the embodiment of the present application;

[0027] Figure 7 The frame synchronization output data after the action of the delay adjustment module 2 in the embodiment of the present application. DETAILED DESCRIPTION

[0028] To make the purpose, technical scheme and advantages of the embodiment of the present application more clear, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the embodiment of the present application. Obviously, the described embodiment is a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiment in the present application, all the other embodiments obtained by the person of ordinary skill in the art without making the creative labor belong to the protection scope of the present application.

[0029] Referring to Figure 1 , the step flow chart of the parallel anti-slip frame synchronization method based on FPGA in the embodiment of the present application is shown. In the embodiment, the parallel anti-slip frame synchronization method based on FPGA comprises:

[0030] Step 1: constructing the parallel anti-slip frame synchronization system, as shown in Figure 1 , the parallel anti-slip frame synchronization system comprises a delay adjustment module 1, a delay adjustment module 2, a frame synchronization detection module and a frame synchronization state machine, wherein the input end of the delay adjustment module 1 receives the parallel N-way frame synchronization input, the output end of the delay adjustment module 1 is connected to the delay adjustment module 2 and the frame synchronization detection module at the same time, the frame synchronization detection module is connected to the delay adjustment module 1 and the frame synchronization state machine at the same time, the frame synchronization state machine is connected to the frame synchronization detection module and the frame synchronization output valid identification, and the output of the delay adjustment module 2 is the parallel N-way frame synchronization output data.

[0031] The present application sets two variable delay adjustment modules at the entrance and exit of the parallel anti-slip frame synchronization module: the delay adjustment module 1 and the delay adjustment module 2, and the delay amounts of the delay adjustment module 1 and the delay adjustment module 2 are D1 and D2 respectively.

[0032] The two delay adjustment modules are used to adjust the Mth path in the N parallel paths to any position within the N parallel paths by setting a variable delay, such as... Figure 2 As shown, the delay adjustment module can adjust the second data in the parallel N-path to the position of the first data in the parallel N-path.

[0033] Step 2: Since frame synchronization detection has not yet started, set the initial values ​​of delay D1 of delay adjustment module 1 and delay D2 of delay adjustment module 2 to 0.

[0034] The purpose of setting up the delay adjustment module is to adjust the input parallel data, adjusting the frame synchronization word position to the N / 2th position of the N parallel channels, thus resisting a maximum slippage from -N / 2 to +N / 2 bits. The delay adjustment only operates after the frame synchronization word position is detected. The initial values ​​of the delay amount D1 of delay adjustment module 1 and the initial values ​​of the delay amount D2 of delay adjustment module 2 are both set to 0.

[0035] Step 3: Using the transitions between frame synchronization state machines to realize the frame synchronization process of the system is the current common practice. Generally, the synchronization process is divided into three states: search state, verification state, and lock state.

[0036] See Figure 3 In the search state, the frame synchronization word position is detected by the frame synchronization detection module. For N parallel inputs, the frame synchronization word header may appear at any position in the N parallel inputs. N sliding windows need to be established and correlated with the frame synchronization word pattern to find the frame synchronization word header. Each sliding window is shifted one bit relative to the previous window to traverse all possible frame synchronization word header positions. The frame synchronization word detection process involves correlating the synchronization word header with these N sliding windows.

[0037] The process of finding the frame synchronization word involves bitwise XORing the input data of N windows with the given frame synchronization word pattern, and then summing the XOR results bitwise to obtain the Hamming distance between the input data of N windows and the frame synchronization word pattern. When the Hamming distance is less than the given frame synchronization word search tolerance bit number, the frame synchronization word header is found and the system enters the verification state.

[0038] by Figure 4 For example, if the input data is 16 parallel channels and the frame synchronization word width is 32 bits, then 16 32-bit shift registers are instantiated. The data shifting process of the shift registers is as follows: Figure 4 As shown. After the data is shifted in, the values ​​of the 16 shift registers are XORed with the 32-bit frame synchronization word pattern to obtain 16 Hamming distances. The register position corresponding to the Hamming distance that satisfies the frame synchronization word search tolerance bits is the position where the frame synchronization word appears. After the frame synchronization word pattern is detected, the state machine enters the verification state.

[0039] Step 4: In the verification state, the data in the current shift register is compared with the set frame synchronization word pattern every few bits of the frame length. If they do not match, the system returns to the search state to re-search for synchronization. When all comparisons in the verification state are correct, the frame synchronization is considered locked, and the system enters the locked state to begin receiving data frames.

[0040] by Figure 5 For example, if the input data is 16 parallel channels, the frame synchronization word has a bit width of 32 bits, and the frame length is 64 bits, if the matched frame synchronization word is located in register 2, then without any loss of lock or slippage, the next frame synchronization word will appear in register 2 after 64 (frame length) / 16 (number of parallel channels) = 4 clock cycles. If the frame synchronization word position is correctly detected consecutively, the state machine enters the locked state; if no frame synchronization word is detected consecutively, the state machine re-enters the search state.

[0041] Step 5: In the locked state, the input parallel N data is adjusted so that the frame synchronization word position appears at the / 2 parallel path. That is, the delay amount D1 of delay adjustment module 1 is set to the difference between the detected frame synchronization word position and N / 2. This theoretically can resist ±N / 2 bit slippage, meaning slippage within the ±N / 2 bit range can be detected. In the locked state, the frame synchronization word is checked every few bits of the frame length to ensure its normal appearance. Under the previous settings, the frame synchronization word position in the next frame appears at the N / 2 parallel path. If slippage occurs, ±k bit slippage is allowed. Subsequent frame synchronization words appearing at paths N / 2+k to N / 2-k are considered normal frame synchronization word detection, maintaining the locked state. Simultaneously, the slippage bits are adjusted based on the current delay amount D1 to ensure the frame synchronization word is always at the N / 2 parallel path position. If no frame synchronization word is continuously detected, the search state is re-entered.

[0042] Due to the function of delay adjustment module 1, the frame synchronization word is always in the N / 2 parallel path. The delay amount D2 of delay adjustment 2 is fixed to N / 2. In this way, the actual transmitted data excluding the frame synchronization word in the output data of the frame synchronization module will appear in the first path of the N parallel paths.

[0043] by Figure 5 For example, if the frame synchronization word is detected at position 2 in register 2, corresponding to the second parallel input channel, to maximize resistance to slippage, the position of the frame synchronization word is adjusted to 16 (number of parallel channels) / 2, which is the eighth parallel input channel. This means the delay amount D1 of delay adjustment module 1 is set to 16 (number of parallel channels) / 2 - 2 (number of detected frame synchronization words), i.e., D1 is set to 6. Under this setting, if the subsequent frame synchronization word header appears at any position from the first to the sixteenth parallel channel, the difference between it and the current frame synchronization word will be between -7 and 8 bits. In other words, as long as the slippage is within this range, it can be detected.

[0044] After entering the locked state, the frame synchronization word appears at the 8th position of the 16 parallel inputs after adjustment by the delay adjustment module 1. If a slip occurs at this point, and if a 3-bit slip is allowed, the frame synchronization word will appear at positions 8-3 to 8+3 (parallel inputs 5 to 11), maintaining the frame synchronization locked state. Furthermore, based on the detected frame synchronization word position, the delay amount D1 of the delay adjustment module 1 continues to be adjusted according to the previous strategy to ensure the frame synchronization word position remains in the middle of the parallel input range. Figure 6 As shown, the frame synchronization words matched in frame I and frame I+1 are both at the position of parallel path 8, while the frame synchronization word matched in frame I+2 is at the position of parallel path 7. At this time, a slip of -1 occurs. In this case, D1 is adjusted by adding 1 to the original D1 so that the subsequently matched frame synchronization words still remain at the position of parallel path 8.

[0045] Under the action of the detection branch and delay adjustment module 1, the frame synchronization word position is always maintained at the middle position of the parallel path count. After processing by the execution branch delay adjustment module 2, the final output parallel frame synchronization data can be obtained. Figure 7 As shown, the delay amount D2 of the delay adjustment module 2 is set to 16 (number of parallel paths) / 2, that is, D2 is set to 8. In this way, in the actual output frame synchronization data, the valid data in the data frame other than the frame synchronization word will appear in the first position of the 16 parallel paths, which is convenient for subsequent data processing.

[0046] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parallel anti-walk frame synchronization method based on FPGA, characterized in that: The method comprises the following steps: Step 1: setting two delay adjustment modules with variable delay at the entrance and exit of the parallel anti-sliding frame synchronization module: a first delay adjustment module and a second delay adjustment module, the delay of the first delay adjustment module and the second delay adjustment module is D1 and D2 respectively; Step 2: setting the initial value of the delay D1 of the first delay adjustment module and the initial value of the delay D2 of the second delay adjustment module as 0 since the frame synchronization module has not started working; Step 3: the frame synchronization process is divided into three states: searching state, checking state and locking state, in the searching state, the frame synchronization word position is detected, corresponding to N parallel inputs, the frame synchronization word head appears at any position of the parallel N roads, it is necessary to establish N sliding windows and correlate with the frame synchronization word pattern to find the frame synchronization word head, each sliding window is shifted by one bit relative to the previous window to traverse all possible frame synchronization word head positions, the frame synchronization word detection process is to correlate the synchronization word head with the N sliding windows, after detecting the frame synchronization word, the searching state enters the checking state; Step 4: in the checking state, the data in the current shift register is correlated with the set frame synchronization word pattern every frame length bit, if it does not match, it returns to the searching state to search for synchronization again, when the frame synchronization word is continuously detected correctly in the checking state, it is considered that the frame synchronization is locked, and the locking state is entered to start receiving data frames; Step 5: after entering the frame synchronization locking state, the delay D1 of the first delay adjustment module is set as the difference between the detected frame synchronization word position and the number N / 2 of parallel roads, when sliding occurs, if the detected frame synchronization word position is within the sliding allowed range, the current delay D1 is adjusted positively or negatively, and the delay D2 of the second delay adjustment module is set as N / 2.

2. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: The function of the two delay adjustment modules is to adjust the Mth parallel N road to any position of the parallel N roads by setting the variable delay.

3. The FPGA-based parallel anti-runout frame synchronization method of claim 2, wherein: In step 5, the adjusted frame synchronization word position is at the N / 2th position, and the input parallel N data is adjusted to the center position of the frame synchronization word head in the parallel N roads.

4. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: In step 2, the delay adjustment starts to work after detecting the frame synchronization word position.

5. The FPGA-based parallel anti-runout frame synchronization method of claim 3, wherein: In step 5, due to the function of the first delay adjustment module, the frame synchronization word position always appears at the center position of the input parallel N data, the delay D2 of the second delay adjustment module is fixedly set as N / 2, so that the output is directly the 1st position of the parallel N roads.

6. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: In step 3, the process of finding the frame synchronization word is to perform bitwise exclusive OR operation on the input data of the N windows and the given frame synchronization word pattern, and then perform bitwise summation to obtain the Hamming distance between the input data of the N windows and the frame synchronization word pattern, when the Hamming distance is less than the given frame synchronization word search tolerance bit number, the frame synchronization word head is found, and the checking state is entered.

7. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: In step 4, only the output data in the frame synchronization locking state is valid, when the frame synchronization word comparison is performed in the checking state, if there is sliding, the frame head is not matched every frame length bit, therefore, the frame synchronization word position detected in the locking state allows the sliding of the number of bits.

8. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: In step 4, the frame synchronization word is also checked in the locked state, and if the frame synchronization word is not continuously detected, the system re-enters the search state.

9. The FPGA-based parallel anti-runout frame synchronization method of claim 1, wherein: In step 1, a parallel anti-skid frame synchronization system is first constructed, which comprises a first delay adjustment module, a second delay adjustment module, a frame synchronization detection module and a frame synchronization state machine, wherein the input end of the first delay adjustment module receives parallel N-way frame synchronization input, the output end of the first delay adjustment module is connected to the second delay adjustment module and the frame synchronization detection module at the same time, the frame synchronization detection module is connected to the first delay adjustment module and the frame synchronization state machine at the same time, the frame synchronization state machine is connected to the frame synchronization detection module and a frame synchronization output valid identification, and the output of the second delay adjustment module is parallel N-way frame synchronization output data.

10. A synchronization system employing the FPGA-based parallel anti-runout frame synchronization method according to any one of claims 1 to 9, characterized in that: In step 1, a parallel anti-skid frame synchronization system is first constructed, which comprises a first delay adjustment module, a second delay adjustment module, a frame synchronization detection module and a frame synchronization state machine, wherein the input end of the first delay adjustment module receives parallel N-way frame synchronization input, the output end of the first delay adjustment module is connected to the second delay adjustment module and the frame synchronization detection module at the same time, the frame synchronization detection module is connected to the first delay adjustment module and the frame synchronization state machine at the same time, the frame synchronization state machine is connected to the frame synchronization detection module and a frame synchronization output valid identification, and the output of the second delay adjustment module is parallel N-way frame synchronization output data.

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