Branch predictor performance simulation method, device and program product

Abstract

The invention relates to the field of processor branch prediction, in particular to a branch predictor performance simulation method and device and a program product. Comprising the following steps: acquiring a retirement instruction stream; a branch instruction is screened out from the retirement instruction stream, key information of the branch instruction is used for forming a branch instruction stream file, and the key information of the branch instruction comprises a PC, a branch behavior and a target address of the branch instruction; constructing a predictor model according to the branch predictor to be simulated; inputting the branch instruction stream file into a predictor model; the predictor model simulates prediction logic according to an algorithm mechanism of a branch predictor to be simulated so as to output a prediction result and update a state; and counting simulation results of each predictor model, wherein the simulation results comprise correct and wrong conditions of each prediction result. According to the method, the problems of high system-level simulation complexity, long operation time, slow parameter iteration, difficult debugging and the like in the branch predictor parameter debugging process are solved.

Description

Technical Field

[0001] The present invention relates to the field of processor branch prediction, and in particular to a method, device, and program product for simulating the performance of a branch predictor. Background Art

[0002] In the design of the CPU branch prediction subsystem, the prediction accuracy rate of the branch predictor is an important indicator. Currently, system-level simulators such as Gem5 are widely used in the industry to analyze the performance of branch predictors. When using Gem5 for branch prediction simulation, Gem5 simulates the processor pipeline through a detailed processor model, including key components such as the branch prediction unit, branch target buffer (BTB), and return address stack (RAS). Gem5 can capture the dynamic behavior of branch instructions during the simulation process, such as branch jumps, mispredictions, pipeline flushes, etc., and evaluate the performance of the branch predictor in the actual hardware environment.

[0003] However, there are certain problems with system-level simulation tools such as Gem5:

[0004] 1. The simulation complexity is high, and it is necessary to simulate the complete processor, memory hierarchy, and I / O devices, resulting in a long development and configuration time.

[0005] 2. The simulation speed is slow, especially in multi-core and multi-thread scenarios. The complete system-level simulation may take a lot of time and it is difficult to get feedback quickly.

[0006] 3. Gem5 consumes a large amount of resources and requires more computing power and storage to support large-scale simulations, which will cause limitations in the actual development process due to hardware resources.

[0007] 4. The debugging of Gem5 is difficult. Due to the complexity of the simulation, it is often difficult to locate the performance bottlenecks or errors caused by the interaction of various components in the system. Summary of the Invention

[0008] Due to problems such as high usage complexity, slow simulation speed, and large resource consumption of system-level simulation tools such as Gem5, and the need for a large number of iterations to determine the optimal parameters for predictor parameter debugging, the simulation time overhead of using Gem5 is unacceptable.

[0009] The present invention provides a method for simulating the performance of a branch predictor, including the following steps:

[0010] S1: Obtain the retired instruction stream;

[0011] The retired instruction stream includes the PC, instruction content, and instruction type of each instruction;

[0012] From the retirement instruction stream, filter out the branch instructions, and use the key information of the branch instructions to form a branch instruction stream file. The key information of the branch instructions includes the PC, branch behavior, and target address of the branch instruction.

[0013] S2: Construct a predictor model according to the branch predictor to be simulated.

[0014] Input the branch instruction stream file into the predictor model.

[0015] The predictor model simulates the prediction logic according to the algorithm mechanism of the branch predictor to be simulated to output the prediction result and update the state.

[0016] S3: Statistically analyze the simulation results of each predictor model. The simulation results include the correct / incorrect situation of each prediction result.

[0017] Preferably, the retirement instruction stream is sourced from the instruction log after actual processor execution or from the instruction log at the system-level simulation submission level.

[0018] Preferably, the predictor model includes one or more of TAGE, ITTAGE, RAS, and BTB.

[0019] The present invention also provides a device for simulating the performance of a branch predictor, including the following modules:

[0020] Instruction acquisition module: Used to acquire the retirement instruction stream.

[0021] The retirement instruction stream includes the PC, instruction content, and instruction type of each instruction.

[0022] From the retirement instruction stream, filter out the branch instructions, and use the key information of the branch instructions to form a branch instruction stream file. The key information of the branch instructions includes the PC, branch behavior, and target address of the branch instruction.

[0023] Branch simulation module: Used to construct a predictor model according to the branch predictor to be simulated.

[0024] Input the branch instruction stream file into the predictor model.

[0025] The predictor model simulates the prediction logic according to the algorithm mechanism of the branch predictor to be simulated to output the prediction result and update the state.

[0026] Result statistics module: Used to statistically analyze the simulation results of each predictor model. The simulation results include the correct / incorrect situation of each prediction result.

[0027] Preferably, the retirement instruction stream is sourced from the instruction log after actual processor execution or from the instruction log at the system-level simulation submission level.

[0028] Preferably, the predictor model includes one or more of TAGE, ITTAGE, RAS, and BTB.

[0029] The present invention also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0030] Beneficial effects: The present invention directly uses the retired instruction stream output at the processor submission level in the system and simulation as the input file for branch predictor simulation. Build an instruction decoding program and a branch predictor using software languages such as C++ for branch predictor simulation. First, it simplifies the simulation complexity and does not require simulating the entire processor system. Reduces the difficulty of implementation and deployment. Second, the device has a fast simulation speed, can quickly feedback the performance of the branch predictor, and avoids the long waiting time of the Gem5 system-level simulation. Greatly reduces the computing resource requirements and no longer processes the interactions of complex hardware such as caches and memories. At the same time, this solution provides a highly consistent and repeatable test environment, which is easy to debug and analyze the reasons for mispredictions.

[0031] The branch prediction simulator made by this solution solves the problems of high complexity, long running time, slow parameter iteration, and difficult debugging in system-level simulation during the parameter debugging process of the branch predictor by simplifying the simulation complexity, accelerating the feedback speed, reducing resource consumption, and providing a repeatable test environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the simulation system architecture. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] By directly obtaining the retired instruction stream output at the processor submission level as the input of the simulator, this technology can make full use of the branch behavior in the real workload, thereby providing a highly realistic test scenario for the evaluation of the branch predictor. These instruction streams directly come from the actual execution of the processor and fully reflect various complex branch patterns in real application programs, such as conditional branches, loop controls, and function calls. This data input based on the real environment ensures that the optimizations obtained by the branch predictor during the development stage can be effectively transferred to the actual system, making the prediction more practical.

[0035] Since the result of each branch in the retirement instruction stream is known, the output of the predictor can be accurately compared with the actual result, and then its prediction accuracy can be accurately evaluated. In addition, the instruction sequence of the retirement instruction stream is determined and repeatable, and the same instruction stream sequence can be adopted by different predictors. Such stable input can ensure the credibility of the test results.

[0036] As Figure 1 shown, a method for simulating the performance of a branch predictor includes the following steps:

[0037] S1: Obtain a retirement instruction stream, where the retirement instruction stream is sourced from the instruction log after actual processor execution or from the instruction log at the system-level simulation submission level;

[0038] The retirement instruction stream includes the PC, instruction content, and instruction type of each instruction;

[0039] From the retirement instruction stream, filter out branch instructions, and use the key information of the branch instructions to form a branch instruction stream file. The key information of the branch instructions includes the PC, branch behavior (jump / no jump), and target address of the branch instruction;

[0040] S2: According to the branch predictor to be simulated, construct a predictor model, where the predictor model includes one or more of TAGE, ITTAGE, RAS, and BTB;

[0041] Input the branch instruction stream file into the predictor model;

[0042] The predictor model simulates the prediction logic to output a prediction result and update the state according to the algorithm mechanism of the branch predictor to be simulated;

[0043] S3: Statistically analyze the simulation results of each predictor model, where the simulation results include the correct / incorrect situation of each prediction result.

[0044] Developers can optimize according to the simulation results.

[0045] The following introduces the predictor model:

[0046] 1. TAGE predictor. First, calculate the index and tag of each level of branch history table according to the PC, obtain predictions from different history tables using the global history information, and select the best prediction result. Then update the prediction table according to the actual branch jump result. After the prediction is completed, decide whether to perform table entry replacement and allocation according to the actual result and the prediction result.

[0047] 2. ITTAGE Predictor. First, predict the branch target address based on the PC and the global history. Use history tables of different lengths to capture the target addresses of indirect branches. After prediction, decide whether to perform entry replacement and allocation based on the actual result and the prediction result.

[0048] 3. RAS, Return Address Stack. The RAS usually exists in the form of a stack. Each time a call instruction is encountered, the return address is pushed onto the stack. When a return instruction is encountered, predict its return address as the top element of the stack.

[0049] 4. BTB, Branch Target Buffer. Each time a branch instruction arrives, find the corresponding entry in the BTB based on the PC and read the target address of the previous branch. If the target address prediction is incorrect, update the BTB entry; if not hit, insert a new entry.

[0050] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for simulating branch predictor performance, characterized in that: The following steps are involved: S1: Get the retired instruction stream; The retired instruction stream includes the PC, instruction content, and instruction type of each instruction; Filter out branch instructions from the retired instruction stream, and use key information of the branch instructions to form a branch instruction stream file, wherein the key information of the branch instructions includes a PC, a branch behavior, and a target address of the branch instruction; S2: construct a predictor model according to the branch predictor to be simulated; Inputting the branch instruction stream file into the predictor model; The predictor model simulates the prediction logic according to the algorithm mechanism of the branch predictor to be simulated to output the prediction result and perform status update; S3: Counting simulation results of each predictor model, wherein the simulation results include the correctness or error of each prediction result.

2. A method for simulating branch predictor performance according to claim 1, characterized in that: The retired instruction stream is derived from an instruction log after execution by an actual processor, or from an instruction log at a system-level simulation submission level.

3. The method for simulating branch predictor performance according to claim 1, characterized in that: The predictor model includes one or more of TAGE, ITTAGE, RAS, BTB.

4. A device for simulating branch predictor performance, characterized in that: Includes the following modules: Instruction acquisition module: used to obtain retired instruction stream; The retired instruction stream includes the PC, instruction content, and instruction type of each instruction; Filter out branch instructions from the retired instruction stream, and use key information of the branch instructions to form a branch instruction stream file, wherein the key information of the branch instructions includes a PC, a branch behavior, and a target address of the branch instruction; Branch simulation module: used to construct a predictor model according to the branch predictor to be simulated; Inputting the branch instruction stream file into the predictor model; The predictor model simulates the prediction logic according to the algorithm mechanism of the branch predictor to be simulated to output the prediction result and perform status update; Result statistics module: used to count the simulation results of each predictor model, and the simulation results include the correctness and error conditions of each prediction result.

5. The device for simulating branch predictor performance according to claim 4, characterized in that: The retired instruction stream is derived from an instruction log after execution by an actual processor, or from an instruction log at a system-level simulation submission level.

6. The device for simulating branch predictor performance according to claim 4, characterized in that: The predictor model includes one or more of TAGE, ITTAGE, RAS, BTB.

7. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 3 is implemented.

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