In-memory calculation circuit based on Booth coding

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an SRAM (Static Random Access Memory) in-memory computing circuit based on Booth coding. On the basis of a traditional 6T-SRAM storage unit, N Booth decoders are added in each row of storage array; meanwhile, performing Booth coding on an input signal, obtaining a corresponding partial product through a Booth decoder under the control of a Booth coding signal, and adding a plurality of rows of partial products through an adder tree; for an 8-bit input signal, Booth coding is carried out to obtain four groups of coded signals, coding of the input signal is carried out in four periods, and finally, shift accumulation is carried out on partial product sums obtained by the SRAM in each period to obtain multiplication accumulation sums of a plurality of 8-bit data. The characteristic that the SRAM storage array simultaneously stores a 1-bit weight and the inverse of the 1-bit weight is utilized, a novel Booth decoder is combined into the SRAM storage array, bit parallel multiplication and accumulation operation based on Booth coding and decoding is completed, and the method is different from traditional in-memory calculation based on bit serials, and is simple in structure and convenient to operate. On the basis that the area is not increased to a great extent, the operation speed of multi-bit multiplication can be improved, and power consumption is reduced. The method can be used for a neural network hardware accelerator, and the operation speed and energy efficiency of the system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and specifically relates to an in-memory computing circuit based on Booth encoding. Background Art

[0002] With the rapid development of artificial intelligence technology, for precise artificial intelligence work, the computing load is shifting from large server clusters to edge devices to achieve richer and more personalized applications. However, neural network models often require a large number of matrix operations. If the traditional von Neumann architecture is still used, frequently fetching data from memory and then transmitting it to the processor for operation will result in large-scale data movement, which is obviously not conducive to the deployment of neural networks in edge devices with low power consumption as an important goal. In recent years, in-memory computing technology has emerged, aiming to break through the bottleneck of the "memory wall" brought by the traditional von Neumann architecture, thereby promoting the development of artificial intelligence in edge devices.

[0003] In-memory computing technology reduces the significant power consumption caused by data transmission from storage units to computing units by placing computing units in the storage array. However, achieving better power consumption, performance, area, and high precision is a huge challenge for in-memory computing technology. Research shows that in digital-domain in-memory computing circuits, using an SRAM storage array can achieve large-scale parallel computing without loss of precision and has good PPA metrics. However, existing in-memory computing circuits based on SRAM storage arrays often adopt a serial computing method, resulting in low computing speed when the data bit width is large. Summary of the Invention

[0004] Aiming at the serial computing method adopted by traditional SRAM in-memory computing circuits, the present invention proposes an in-memory computing circuit based on Booth encoding, which realizes high-speed in-memory computing functions through innovations in the SRAM storage array and the computing method.

[0005] The technical solution of the present invention is as follows:

[0006] An in-memory computing circuit based on Booth encoding, the in-memory computing circuit includes 64 Booth encoders, 32 SRAM in-memory computing storage arrays with a size of 64 * 8bit and embedded with 64 * 8 Booth decoding units, 32 adder trees, and 32 shift-accumulation circuits, and finally can realize the multiplication and accumulation operation of 64 8-bit inputs and 32 groups of 8-bit weights.

[0007] Each operator array in the SRAM storage array includes 64 rows and 8 columns of storage cells, 64 rows and 8 columns of Shifter cells, and 64 rows and 9 columns of Mux cells. Each row of storage cells shares the WL word line, and each column of storage cells shares two read / write operation bit lines, BL and BLB. By enabling different row word lines, in the write mode, the values on the bit lines are written into the storage cells of different rows. The values on BL and BLB are opposite, and are written into Q and QB respectively. In the read mode, the stored weight values are read out to the corresponding bit lines, that is, the value stored at Q is read out to BL, and the value stored at QB is read out to BLB. In the calculation mode, each storage cell stores 1 bit of weight value. Through the t signal that is turned off during read and write and shared by each row, the weight value required in the calculation mode and its inverse are connected to the Shifter cell corresponding to each storage cell. Each row of Shifter cells is connected to a row of Mux cells, and together with the three control signals output by the Booth encoder corresponding to each row, the generation of a 9-bit partial product is completed.

[0008] The in-memory computing circuit includes a read / write mode and a calculation mode. In the read / write mode, the SRAM acts as a storage array, and each bit of weight value is written and read through the sense amplifiers connected to each group of BL and BLB. In the calculation mode, the 64*8 SRAM array can achieve the multiplication and accumulation of 64 8-bit inputs and 8-bit weight values every four operation cycles. First, each 8-bit input passes through the Booth encoder, and four operation cycles can generate 4 groups of encoded signals. One group of encoded signals has three 1-bit signals, namely the o signal, the s signal, and the t signal, which are connected to the SRAM array of the corresponding row. During calculation, the word lines and bit lines related to read and write are turned off, and the t signal is enabled to give the stored weight value. Each row of weight values and their inverses generate the corresponding 9-bit partial product q and 1-bit sign bit compensation value under the control of the encoded signals. The 64 partial products obtained by each storage array are added using a 6-level compression tree, and the sign compensation values are directly added using an adder. The two parts are then added using an adder to obtain the response sum. Since the weight values of the partial product sums generated in 4 cycles are different, finally, shift accumulation is required to add the four sums to obtain the multiplication and accumulation value of 64 8-bit inputs and 8-bit weight values.

[0009] The memory array structure in the in-memory computing circuit based on Booth encoding uses a standard 6-transistor SRAM memory cell. The source of the first PMOS in the 6-transistor memory cell is connected to the power supply voltage, the drain is connected to the drain of the first NMOS, the gate of the second PMOS, the gate of the second NMOS, the drain of the third NMOS (denoted as node QB, connected to the corresponding wb of the decoding unit), the gate is connected to the gate of the first NMOS, the drain of the second PMOS, the drain of the second NMOS, the drain of the fourth NMOS (denoted as node Q, connected to the corresponding w of the decoding unit), the source of the second PMOS is connected to the power supply, the sources of the first NMOS and the second NMOS are connected to the ground, the gates of the third NMOS and the fourth NMOS are connected to the bit line WL, and the sources of the third NMOS and the fourth NMOS are respectively connected to BLB and BL of the read / write bit lines.

[0010] The Booth encoder in the in-memory computing circuit based on Booth encoding serially encodes a group of 8-bit inputs in 64 rows simultaneously. Among them, for each 8-bit input, in the first calculation cycle, the fifth, sixth, and seventh bits are connected to a Booth encoder, in the second operation cycle, the third, fourth, and fifth bits are connected to this Booth encoder, in the third operation cycle, the first, second, and third bits are connected to this Booth encoder, and in the fourth operation cycle, the fixed 0, the zeroth bit, and the first bit are connected to this Booth encoder.

[0011] The Booth decoding unit in the in-memory computing circuit based on Booth encoding uses six MOS transistors. For the i-th Booth decoding unit, the t signal output by the Booth encoder is connected to the gates of the first PMOS and the second PMOS, the s signal output by the Booth encoder is connected to the gates of the third PMOS and the first NMOS, the o signal output by the Booth encoder is connected to the gates of the fourth PMOS and the second NMOS, the wb signal output by the memory cell is connected to the source of the first PMOS, the w signal output by the memory cell is connected to the source of the second PMOS, the drain of the first PMOS is connected to the source of the third PMOS, the drain of the second PMOS is connected to the source of the first NMOS, the drain of the third PMOS is connected to the drain of the first NMOS, the source of the fourth PMOS, and the source of the second NMOS, the output signal on the drain of the fourth PMOS is denoted as p<i + 1>, and the output signal on the drain of the second NMOS is denoted as p ; The adjacent two Shifter circuits connect p in a wired-AND manner Connected together. The Mux unit in the resulting Booth-encoded SRAM in-memory computing circuit is implemented using a NOR gate, and the input signals are p respectively The output signal t of the Booth encoder, and the output is q ;In summary, each SRAM generates 64 9-bit partial products, and after passing through the adder tree and shift accumulator, the multiplication accumulation sum of 64 8-bit inputs and 8-bit weights is obtained.

[0012] Each row of SRAM and the input with the corresponding weight obtain 9-bit partial products. 64 rows of 9-bit signed partial products pass through a binary adder tree to obtain a 15-bit sum. The full adders and half adders used are not required in the present invention. Specifically, a 15-bit partial product is obtained through 6 levels of addition. First, 32 9-bit adders are used to obtain 32 10-bit first-level outputs, then 16 10-bit adders are used to obtain 16 11-bit outputs, then 8 11-bit adders are used to obtain 8 12-bit outputs, then 4 12-bit adders are used to obtain 4 13-bit outputs, then 2 13-bit adders are used to obtain 2 14-bit outputs, and finally 1 14-bit adder is used to obtain a 15-bit output. In addition, each row of SRAM and the input with the corresponding weight, in addition to obtaining 9-bit partial products, also obtain a 1-bit sign compensation bit for sign correction. When the encoding result is -2 or -1, that is, when the obtained partial product is -2W or -W, the sign compensation bit takes 1'b1. 64 1-bit sign compensation bits pass through an adder to obtain a 7-bit sum, and then the 7-bit sum and the 15-bit obtained from the sum of 64 rows of partial products are added through a 15-bit adder to obtain a 16-bit partial product sum. The Booth encoding signal weights input by 4 SRAMs are different, and the difference between adjacent partial product sums is two bits. 4 groups of 16-bit partial product sums are shifted and accumulated, and finally a 22-bit output is obtained.

[0013] The beneficial effects of the present invention are as follows: The present invention utilizes the characteristic that the SRAM storage array stores 1-bit weight and its inverse at the same time, combines a new type of Booth decoder into the SRAM array, and completes the bit-parallel multiplication accumulation operation based on Booth encoding and decoding. This is different from the traditional in-memory computing based on bit-serial, and can improve the operation speed of multi-bit multiplication without significantly increasing the area, and reduce the power consumption. The present invention can be used in neural network hardware accelerators to improve the operation speed and energy efficiency of the system. Description of the Drawings

[0014] Figure 1 It is a schematic diagram of an in-memory computing circuit based on Booth encoding proposed by the present invention.

[0015] Figure 2 It is a schematic diagram of the operation sub-array structure.

[0016] Figure 3 It is a schematic diagram of Booth encoding grouping.

[0017] Figure 4 Schematic diagram of the detailed structure of the SRAM storage array, including a standard 6T storage cell and a Booth decoding circuit.

[0018] Figure 5 Schematic diagram of the standard 6T-SRAM structure.

[0019] Figure 6 Schematic diagram of the Booth decoder. Specific implementation manner

[0020] The present invention will be described in detail below with reference to the accompanying drawings.

[0021] Figure 1 Schematic diagram of an in-memory computing circuit based on Booth encoding proposed by the present invention. The circuit structure includes 32 operator arrays and related peripheral circuits for SRAM and computing modes, with a size of 64 * 256 = 16Kb. All operator arrays share 64 Booth encoders. Each operator array includes a 64-row and 8-column SRAM storage array and a corresponding addition circuit. In the computing mode, the multiplication and accumulation process of 64 8-bit signed inputs and 8-bit weights is completed in 4 cycles.

[0022] Figure 2 Schematic diagram of the operator array structure. Each operator array contains 64 * 8 standard 6T-SRAM storage cells, 64 groups of Booth decoding circuits, 1 six-stage adder tree, 1 15Bit adder, and 1 shift accumulator. One row of the SRAM storage array stores 8-bit weights w<7:0>. Each row has a group of Booth decoders and a sign compensation bit generation circuit integrated in the storage array. In each cycle, the encoded signals of each of the 64 channels, together with the Booth decoder and the sign compensation bit generation circuit, generate a 9-bit signed partial product and a 1-bit sign compensation bit. The adder tree adds the partial products and sign compensations of all channels under the control of the cpt_vld and cycle_cnt signals to obtain a 16-bit partial product sum.

[0023] Figure 3 Schematic diagram of Booth encoding grouping. An 8-bit signed input (multiplier) is padded with 0 at the least significant bit. In the first computing cycle, the fifth, sixth, and seventh bits are connected to the Booth encoding. In the second computing cycle, the third, fourth, and fifth bits are connected to the Booth encoder. In the third computing cycle, the first, second, and third bits are connected to the Booth encoder. In the fourth computing cycle, the fixed 0, the zeroth bit, and the first bit are connected to the Booth encoder.

[0024] Figure 4 It is a schematic diagram of the detailed structure of the SRAM storage array, including a standard 6T storage cell, a detailed Booth decoding circuit, and a sign compensation generation circuit. A group of Booth decoders can be divided into a group of Shifter circuits and a group of Mux circuits according to the working principle. The Shifter, Mux units, and sign compensation bit generation circuit in each row are controlled by the same group of Booth encoding signals. Each Booth decoder is connected to the corresponding 1-bit storage cell. A group of Shifter units complete the reading of the weight or its inverse and left shift or remain unchanged to obtain p<8:0>. All Muxs select p<8:0> or 9’b0 as the partial product q<8:0> under the control of the Booth encoding signal.

[0025] Figure 5 It is a schematic diagram of the standard 6T-SRAM structure. Each structure stores 1-bit weight. In the SRAM storage mode, the Booth decoding circuits connected to Q and QB are disconnected due to the turn-off of the PMOS transistors, avoiding the interference of the Booth decoding circuit and others on the storage structure; in the in-memory computing mode, the PMOS transistors connected to Q and QB are turned on, and the weight and the Booth encoding signal are sent into the decoding circuit together to complete the generation of the partial product and the sign compensation bit.

[0026] Figure 6 It is a schematic diagram of the Booth encoder. For each 8-bit input, every adjacent 3-bit input corresponds to a Booth encoder, obtaining three encoding signals s, t, and o. These three encoding signals are given to the corresponding rows of the corresponding block of SRAM to control the Booth decoder and the MNX unit to cooperate to complete the generation of a partial product q<8:0>.

[0027] In the SRAM in-memory computing circuit based on Booth encoding proposed by the present invention, the substrates of all NMOS transistors are connected to the ground voltage GND, and the substrates of all PMOS transistors are connected to the power supply voltage VDD.

[0028] In order to realize the multi-bit multiplication operation inside the storage array, the present invention correspondingly embeds a Booth decoding unit and a sign compensation bit generation unit in each row based on the traditional 6-transistor SRAM storage cell. In the computing mode, the t signal is pulled low to read out the weight to complete the subsequent operations. In the read-write mode, the t signal is pulled high to turn off the subsequent multiplication operation, thereby reducing power consumption.

[0029] To improve the speed of multi-bit multiplication operations, Booth multiplication is adopted to reduce the number of partial products. In the present invention, 8-bit inputs are subjected to radix-4 Booth encoding to obtain four sets of encoded signals, which are respectively fed into the Booth decoding units in the same row of the SRAM in different cycles. The Booth decoding units in each row operate on w and wb input from the SRAM storage units under the control of the encoded signals to generate partial products q<8:0>. Then, the sum of 64 rows of partial products is generated by the adder array outside each SRAM. Finally, the sums of the 4 sets of 64 rows of partial products corresponding to the four sets of encoded signals are fed into a shift accumulator for shift accumulation, thereby obtaining the multiplication accumulation result of 64 8-bit inputs and 8-bit weights and completing a dot product operation with an 8-bit width.

[0030] The following specifically describes the working principle of the in-memory computing circuit of the present invention in conjunction with Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Table 1:

[0031] 1. SRAM mode:

[0032] (1) Hold operation:

[0033] During the period when the storage unit holds data, the write word line WL remains at a low level. At this time, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the third PMOS transistor MN7, and the fourth PMOS transistor MN8 are all turned off, and the read bit lines BL and BLB will not affect the storage nodes Q or QB. The latch structure composed of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 will latch the data of the storage nodes Q and QB.

[0034] (2) Write operation:

[0035] Assume that before the write operation, the storage node Q of the 8-transistor storage unit is at a high level and QB is at a low level, that is, the stored data is '1'. When writing the data '0', the write operation word line is pulled high to select the unit, and at the same time, the data '0' to be written is loaded onto the write bit line, that is, BL is at a low level and BLB is at a high level. BL pulls down the node Q through the fourth NMOS transistor MN4, and BLB pulls up the node QB through the third NMOS transistor MN3, and the feedback loop of the latch structure is broken, and the data '0' is written into the storage unit. The process of writing the data '1' is the same as the above.

[0036] (3) Read operation

[0037] Assume that before the read operation, the storage node Q of the memory cell stores a high level and QB stores a low level, that is, the stored data is '1'. At the beginning of the read operation, the bit lines BL and BLB are pre-charged to a high level, the word line WL is pulled high to a high level, and the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on. Since the storage node Q is at a high level, the first NMOS transistor MN1 is turned on, and the bit line BLB discharges through the third NMOS transistor MN3 and the first NMOS transistor N1 and is pulled down to a low level. The difference between BL and BLB is amplified by the sense amplifier, and the read result is '1'. When the stored data is '0', the storage node QB is at a high level, the second NMOS transistor MN2 is turned on, and BL discharges through the fourth NMOS transistor MN4 and the second NMOS transistor N2 and is pulled down to a low level. After the difference between BL and BLB is amplified by the sense amplifier, the read result is '0'.

[0038] 2. In-memory computing mode:

[0039] (1) Booth encoding

[0040] In the in-memory computing mode, the input is encoded in radix-4 Booth encoding. An 8-bit input generates four groups of Booth encoding signals after encoding, and together with the 8-bit weights after decoding, four groups of partial products are generated. Among them, for an 8-bit input, the rule of radix-4 Booth encoding requires adding 1'b0 to the least significant bit and then encoding adjacent three bits. The specific Booth encoding rules are shown in Table 1.

[0041] Table 1 Booth encoding rule table

[0042]

[0043] According to Table 1, it can be obtained that

[0044] s = X 2i+1

[0045]

[0046] Thus, the schematic diagram of the Booth encoder is drawn as Figure 6 shown.

[0047] (2) Booth decoding

[0048] In the in-memory computing mode, the word line WL of the SRAM memory array is turned off, and the weight reading and writing operations are not performed. The Q and QB latched in each memory cell remain unchanged. When the partial product is not 0, the t signal is pulled low, and the stored w and wb are taken out and given to the corresponding decoding unit. As can be seen from Table 1, when the s signal is 0, the partial product q When the sign of is positive and the s signal is 1, the partial product q The symbol of is negative; when the t signal is 1, the partial product q Directly taken as 0, when the t signal is 0 and the o signal is 1, the partial product q Take the current weight bit. When the o signal is 0, the current weight bit is shifted left. Thus, the Booth decoding circuit within the array is obtained as shown in Figure 4 as follows. Specifically, when the t signal takes 1, q All take 0 under the control of the Mux unit. When the t signal is 0, then, when s takes 1, the first NMOS transistor MN1 in the decoder is turned on, and w Transmitted to the intermediate node of the Booth decoder, and vice versa, wb is transmitted to the intermediate node, and then, under the control of the o signal, w or wb Transfer to p<i + 1> or p , and then there is q equal to p Note that when the weight is shifted left, the least significant bit q<0> is filled with 1, and when the weight remains unchanged, the most significant bit q<8> is filled with 1, which are implemented by a PMOS transistor and an NMOS transistor respectively.

[0049] (3) Partial accumulation addition

[0050] To calculate the product sum of 64 8-bit inputs and 8-bit weights, a bit-serial calculation method is adopted. Since the Booth encoding and decoding algorithm is used, the operation cycle is shortened by half, and only 4 cycles are needed to generate 4 groups of multi-channel partial products. After each operation sub-array generates 64 9-bit partial products per cycle, a 15-bit sum is obtained through an adder tree. In addition, each row of SRAM and the input with the corresponding weight obtain a 1-bit sign compensation in addition to the 9-bit partial product. The 64 1-bit sign compensation bits are summed to obtain a 7-bit sum through an adder, and then the sum of the 64 sign compensation bits and the sum of the 64 partial products are added to obtain a 16-bit partial product sum. The Booth encoding signal weights of the inputs in different cycles are different, and the adjacent partial product sums differ by two bits. The 4 groups of 16-bit partial product sums are shifted and accumulated to finally obtain a 22-bit output.

[0051] In summary, a memory-in-computation circuit based on Booth encoding proposed by the present invention improves the traditional SRAM storage structure and utilizes its storage characteristics, and introduces Booth encoding to complete multi-bit dot product operations. Compared with the traditional bit-serial memory-in-computation, although the area of the present invention increases, the calculation speed is doubled, and the reduction of the number of partial products also reduces the power consumption and improves the energy efficiency ratio of multi-bit dot product operations.

Claims

1. An SRAM in-memory computing circuit based on Booth coding, the in-memory computing circuit includes 64 Booth encoders, a 32*64*8bit SRAM in-memory computing storage array embedded with 64 Booth decoding units, 32*1 compression trees and 32*1 shift accumulation circuits, which can ultimately realize the multiplication and accumulation of 64 8-bit signed inputs and 32*8-bit signed weights. It is characterized in that: Each operator array in the SRAM storage array includes 64 rows and 8 columns of storage cells, 64 Booth decoding units and 64 sign compensation bit generation units. Each row of storage cells shares a WL word line, and each column of storage cells shares two read and write operation bit lines BL and BLB. By turning on word lines in different rows, in write mode, the values ​​on the bit lines are written into storage cells in different rows, wherein BL and BLB have opposite values, and are written to Q and QB respectively. In read mode, the stored weight values ​​are read out to the corresponding bit lines, that is, the value stored at Q is read out to BL, and the value stored at QB is read out to BLB. In calculation mode, each storage cell stores a 1-bit weight value, and the weight value required in the calculation mode and its inverse are connected to the decoding unit corresponding to each storage cell through the t signal that is closed during reading and writing shared by each row. Each row of decoding units includes a row of Shifter units and a row of Mux units. In addition, three control signals {o, s, t} output by the Booth encoder corresponding to each row are added to complete the generation of a 9-bit partial product and a 1-bit sign compensation bit.

2. The SRAM in-memory computing circuit based on Booth coding according to claim 1, characterized in that: The Booth encoder and the Booth decoder adopt radix-4 Booth encoding and decoding, and the Booth encoder in the SRAM memory calculation circuit based on Booth encoding encodes 64 8-bit inputs simultaneously; wherein, for each 8-bit input, the fifth, sixth and seventh bits are connected to a Booth encoder in the first calculation cycle, the third, fourth and fifth bits are connected to the Booth encoder in the second calculation cycle, the first, second and third bits are connected to the Booth encoder in the third calculation cycle, and the fixed 0, the zeroth bit and the first bit are connected to the Booth encoder in the fourth calculation cycle. Each Booth encoder is composed of two XOR gates and one NOR gate to obtain three coded signals; the Booth decoding unit in the SRAM memory calculation circuit based on Booth encoding uses six MOS tubes. For the i-th Booth decoding unit, the t signal output by the Booth encoder is connected to the gates of the first PMOS and the second PMOS, the s signal output by the Booth encoder is connected to the gates of the third PMOS and the first NMOS, the o signal output by the Booth encoder is connected to the gates of the fourth PMOS and the second NMOS, the wb signal output by the storage unit is connected to the source of the first PMOS, the w signal output by the storage unit is connected to the source of the second PMOS, the drain of the first PMOS is connected to the source of the third PMOS, the drain of the second PMOS is connected to the source of the first NMOS, the drain of the third PMOS is connected to the drain of the first NMOS, the source of the fourth PMOS and the source of the second NMOS, and the output signal on the drain of the fourth PMOS is recorded as p<i+1> , the output signal on the drain of the second NMOS is denoted as p ; The adjacent two-bit Shifter circuits connect p The Mux unit in the SRAM memory calculation circuit based on Booth coding is implemented using an NOR gate, and the input signals are p and the output signal t of the Booth encoder, the output is q In summary, each SRAM generates 64 9-bit partial products, which, after passing through the adder tree and the shift accumulator, are the multiplication and accumulation sums of 64 8-bit inputs and 8-bit weights.

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