Double-channel clock source switching management system and method

Abstract

The invention belongs to the field of system clock management, and particularly discloses a double-channel clock source switching management system and method.If a gating mode signal is in an automatic working mode, a control module obtains a first gating control signal and a second gating control signal according to a locking signal, a first mark damage signal and a second mark damage signal; if the gating mode signal is in an intervention working mode, the control module obtains a first gating control signal and a second gating control signal according to the gating mode signal, the first gating control signal is accessed to the control end of the first multiplexer, and the second gating control signal is accessed to the control end of the second multiplexer. According to the invention, switching of the clock source is realized without intervention of a processor, and stability and high efficiency of system operation are ensured.

Description

Technical Field

[0001] The present invention belongs to the field of system clock management, and particularly relates to a dual-channel clock source switching management system and method. Background Art

[0002] In the design of electronic systems, the design of power supply and clock is indispensable. With the increasing integration and computing speed of electronic systems, in the clock part, a single clock source is difficult to meet the design requirements of the system. In a load electronic system, there are generally multiple clock sources. For example, two clock sources are set so that each part of the system has both independence and can cooperate with each other.

[0003] The stability and reliability of the clock source affect the overall performance and stability of the system. For a dual-channel clock source system, when one of the clock sources fails, it can quickly and stably switch to the other clock source, which has a great impact on the stability and reliability of the clock source. Traditional clock switching schemes rely on the processor for control and switching. However, when the processor is busy or fails, it may not be able to respond to the clock source switching demand in time, thus threatening the normal operation of the system. Therefore, the scheme of using the processor to execute control switching increases the complexity and cost of the system on the one hand, and may introduce additional delays and uncertainties on the other hand, affecting the real-time performance and stability of the system. Summary of the Invention

[0004] To solve the above problems, the present invention provides a dual-channel clock source switching management system and method, which realizes the switching of the clock source without the intervention of the processor, and ensures the stability and efficiency of the system operation.

[0005] In a first aspect, the technical solution of the present invention provides a dual-channel clock source switching management system, including a first multiplexer, a second multiplexer, a phase-locked loop, a first watchdog, a second watchdog, and a control module; A first clock source and a second clock source are connected to the input end of the first multiplexer. The output end of the first multiplexer is connected to the input end of the phase-locked loop. The phase-locked loop performs frequency multiplication processing on the first selected clock source output by the first multiplexer to output a frequency-multiplied clock source; at the same time, the phase-locked loop performs locking detection on the first selected clock source output by the first multiplexer to output a locking signal; The first clock source, the second clock source, and the frequency-multiplied clock source are connected to the input end of the second multiplexer, and the second multiplexer outputs a second selected clock source; The first clock source outputs a first monitoring signal through the first watchdog, and the second clock source outputs a second monitoring signal through the second watchdog; the locking signal and the first monitoring signal output a first flag damage signal through an AND gate, and the locking signal and the second monitoring signal output a second flag damage signal through an AND gate; The locking signal, the first flag damage signal, and the second flag damage signal input control module. At the same time, the control module receives the strobe mode signal input by the processor. If the strobe mode signal is the automatic working mode, the control module obtains the first strobe control signal and the second strobe control signal according to the locking signal, the first flag damage signal, and the second flag damage signal. If the strobe mode signal is the intervention working mode, the control module obtains the first strobe control signal and the second strobe control signal according to the strobe mode signal. The first strobe control signal is connected to the control terminal of the first multiplexer, and the second strobe signal is connected to the control terminal of the second multiplexer.

[0006] In an alternative embodiment, the phase-locked loop includes a phase detector, a charge pump, a voltage-controlled crystal oscillator, and a locking detection circuit; The first strobe clock source is input to the first input terminal of the phase detector through the frequency division coefficient, and the frequency-multiplied clock source output by the voltage-controlled crystal oscillator is input to the second input terminal of the phase detector through the feedback frequency division coefficient. The phase detector outputs the UP signal and the DN signal to the charge pump, which are processed by the charge pump and then input to the voltage-controlled crystal oscillator. At the same time, the voltage-controlled crystal oscillator is connected to the voltage-controlled control signal through the frequency multiplication coefficient; The UP signal and the DN signal are input to the locking detection circuit for locking detection.

[0007] In an alternative embodiment, the locking detection circuit includes an exclusive-OR gate, a delay unit, a NAND gate, a first D flip-flop, a shift register unit, a third multiplexer, a second D flip-flop, and an OR gate; The UP signal and the DN signal are input to the exclusive-OR gate. The output terminal of the exclusive-OR gate is connected to the input terminal of the delay unit. At the same time, the output terminal of the exclusive-OR gate and the output terminal of the delay unit are respectively connected to the input terminals of the NAND gate. The output terminal of the NAND gate is connected to the first input terminal of the first D flip-flop. The second input terminal of the first D flip-flop is connected to the locking detection clock signal. The output terminal of the first D flip-flop is connected to the first input terminal of the shift register unit. The second input terminal of the shift register unit is connected to the locking detection clock signal; The output terminal of the shift register unit is connected to the first input terminal of the third multiplexer. The second input terminal of the third multiplexer is connected to the phase-locked loop operating voltage. The output terminal of the third multiplexer is connected to the first input terminal of the second D flip-flop. The second input terminal of the second D flip-flop is connected to the locking detection clock signal; The output terminal of the second D flip-flop is connected to the control terminal of the third multiplexer and the first input terminal of the OR gate. The second input terminal of the OR gate is connected to the forced locking signal, and the output terminal of the OR gate outputs the locking signal.

[0008] In an alternative embodiment, the shift register unit includes a shift register and a plurality of AND gates, wherein the shift register includes a plurality of serially connected D flip-flops; the outputs of each D flip-flop, every two adjacent ones are grouped and input into an AND gate, and the outputs of every two adjacent AND gates are input into an AND gate until connected to the last AND gate, and one of the input terminals of the last AND gate is connected to the PLL operating voltage, and the output terminal is used as the input terminal of the shift register unit.

[0009] In an alternative embodiment, the lock detection circuit further includes a lock detection clock signal generation sub-circuit, and the lock detection clock signal generation sub-circuit includes an AND gate and a buffer; The UP signal is connected to the first input terminal of the AND gate, the DN signal is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the buffer, and the output terminal of the buffer outputs the lock detection clock signal.

[0010] In an alternative embodiment, the system further includes a PLL operating voltage generation circuit, and the PLL operating voltage generation circuit includes a resistor R1, a resistor R2, an N-type MOS transistor Q1, and a P-type MOS transistor Q2; The first end of the resistor R1 is connected to the power supply voltage, the second end is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded; The gate of the P-type MOS transistor Q2 is connected to the first end of the resistor R2, the source is grounded, the drain is connected to the gate of the N-type MOS transistor Q1, the source of the N-type MOS transistor Q1 is connected to the power supply voltage, and the drain outputs the PLL operating voltage.

[0011] In a second aspect, the technical solution of the present invention provides a dual-channel clock source switching management method, which is implemented based on the system described in any one of the above, and includes the following steps: Step 1, obtain input signals, including a lock signal, a first flag damage signal, a second flag damage signal, and a gating mode signal; Step 2, perform lock detection through the lock signal. If not locked, execute Step 3. If locked, execute Step 4; Step 3, detect whether the lock times out. If not timed out, continue with the lock detection. If timed out, detect whether the first clock source and the second clock source are valid through the first flag damage signal and the second flag damage signal. If both clock sources are invalid, enter an error state. If one of the clock sources is valid and the other is invalid, execute Step 5; Step 4, detect whether the first clock source and the second clock source are valid through the first flag damage signal and the second flag damage signal. If there is a valid clock source, execute Step 5; Step 5: Determine the working mode according to the strobe mode signal. If it is the automatic working mode, obtain the first strobe control signal and the second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal; if it is the intervention working mode, obtain the first strobe control signal and the second strobe control signal according to the strobe mode signal. Step 6: Transmit the first strobe control signal to the control terminal of the first multiplexer, and transmit the second strobe signal to the control terminal of the second multiplexer.

[0012] In an optional implementation, step S5 specifically includes: Analyze the strobe mode signal to obtain the status of the strobe mode flag bit included in the strobe mode signal; If the status of the strobe mode flag bit is the first mode status, it is determined as the automatic working mode. In the automatic working mode, obtain the first strobe control signal and the second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal; If the status of the strobe mode flag bit is the second mode status, it is determined as the intervention working mode. In the intervention working mode, obtain the status of the strobe channel flag bit included in the strobe mode signal, and obtain the first strobe control signal and the second strobe control signal according to the status of the strobe channel flag bit.

[0013] In an optional implementation, obtaining the first strobe control signal and the second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal specifically includes: Calculate N1 = (~bad1) & lock and N2 = (~bad2) & lock, where bad1 is the first flag damage signal, a low level indicates that the first clock source is valid, a high level indicates that the first clock source is invalid, bad2 is the second flag damage signal, a low level indicates that the second clock source is valid, a high level indicates that the second clock source is invalid, lock is the lock signal, a high level indicates locked, a low level indicates unlocked, ~ represents taking the inverse, and & represents the AND operation; If N1 is at a high level, the first strobe control signal is to select the first clock source, and the second strobe control signal is to select the first clock source; If N2 is at a high level, the first strobe control signal is to select the second clock source, and the second strobe control signal is to select the second clock source.

[0014] In an optional implementation, obtaining the first strobe control signal and the second strobe control signal according to the status of the strobe channel flag bit specifically includes: If the status of the strobe channel flag bit is the first strobe status, the first strobe control signal is to select the first clock source, and the second strobe control signal is to select the frequency - doubled clock source; If the status of the selected channel flag bit is the second selected status, the first selection control signal is to select the second clock source, and the second selection control signal is to select the frequency-multiplied clock source; If the status of the selected channel flag bit is the third selected status, the first selection control signal is to select the first clock source, and the second selection control signal is to select the second clock source; If the status of the selected channel flag bit is the fourth selected status, the first selection control signal is to select the second clock source, and the second selection control signal is to select the second clock source; If the status of the selected channel flag bit is the fifth selected status, the first selection control signal is to select the first clock source, and the second selection control signal is to select the first clock source; If the status of the selected channel flag bit is the sixth selected status, the first selection control signal is to select the second clock source, and the second selection control signal is to select the first clock source.

[0015] A dual-channel clock source switching management system and method provided by the present invention has the following beneficial effects compared with the prior art: two multiplexers, two watchdog timers, a phase-locked loop, and a control module are provided. The validity signals of the two clock sources are obtained through the watchdog timers, and the locking signal is obtained according to the phase-locked loop, so that the control module can automatically switch to another clock source when one clock source loses lock according to the validity signal and the locking signal, without the need for the processor to participate in the control, effectively ensuring the stability and efficiency of the system operation. At the same time, the circuit is simple, convenient for transplantation, low in cost, reduces the workload of the processor, and meets the needs in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings according to these drawings without creative efforts.

[0017] Figure 1 It is a schematic structural diagram of a dual-channel clock source switching management system provided by an embodiment of the present invention.

[0018] Figure 2 It is a schematic structural diagram of a phase-locked loop.

[0019] Figure 3 It is a schematic structural diagram of a locking detection circuit.

[0020] Figure 4 It is a waveform of the phase-locked loop locking detection in the unlocked state.

[0021] Figure 5 It is a waveform of the phase-locked loop locking detection in the locked state.

[0022] Figure 6 Schematic diagram of the working voltage generation circuit for the phase-locked loop.

[0023] Figure 7 Schematic diagram of the flow of a dual-channel clock source switching management method provided by an embodiment of the present invention.

[0024] Figure 8 Schematic diagram of the flow of a specific embodiment of the dual-channel clock source switching management method of an embodiment of the present invention. Detailed implementation manners

[0025] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the specific embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0027] Figure 1 Schematic diagram of the structure of a dual-channel clock source switching management system provided by an embodiment of the present invention. The system includes a first multiplexer, a second multiplexer, a phase-locked loop, a first watchdog, a second watchdog, and a control module. Figure 1 In the figure, MUX1 is the first multiplexer, MUX2 is the second multiplexer, PLL is the phase-locked loop, CLK1 is the first clock source, and CLK2 is the second clock source.

[0028] In this system, the first clock source and the second clock source are connected to the input end of the first multiplexer. The output end of the first multiplexer is connected to the input end of the phase-locked loop. The phase-locked loop performs frequency doubling processing on the first selected clock source output by the first multiplexer to output a frequency-doubled clock source. At the same time, the phase-locked loop performs locking detection on the first selected clock source output by the first multiplexer to output a locking signal. The first clock source, the second clock source, and the frequency-doubled clock source are connected to the input end of the second multiplexer. The second multiplexer outputs a second selected clock source. It should be noted that the second selected clock source output by the second multiplexer is output as the clock source CLOCK used by the system after passing through the BUFFER.

[0029] The first clock source outputs a first monitoring signal through the first watchdog, and the second clock source outputs a second monitoring signal through the second watchdog; the lock signal and the first monitoring signal output a first flag damage signal through an AND gate, and the lock signal and the second monitoring signal output a second flag damage signal through an AND gate. At the same time, the lock signal, the first flag damage signal, and the second flag damage signal are input to the control module. At the same time, the control module receives the strobe mode signal input by the processor. If the strobe mode signal is the automatic working mode, the control module obtains a first strobe control signal and a second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal. If the strobe mode signal is the intervention working mode, the control module obtains a first strobe control signal and a second strobe control signal according to the strobe mode signal. The first strobe control signal is connected to the control end of the first multiplexer, and the second strobe signal is connected to the control end of the second multiplexer.

[0030] As Figure 1 shown, CLK1 and CLK2 are connected to MUX1. MUX1 selects one path to output to the PLL under the control of the Mux1_set control signal. MUX1 selects and outputs between CLK1 and CLK2. The PLL processes the signal input from MUX1 and outputs a frequency-multiplied signal PLL_CLK and a lock signal lock. CLK1, CLK2, and PLL_CLK are jointly input to MUX2. MUX2 performs a selection output under the Mux2_set control signal. MUX2 selects and outputs between CLK1, CLK2, and PLL_CLK.

[0031] CLK1 outputs a monitoring signal Watch1 through watchdog 1, CLK2 outputs a monitoring signal Watch2 through watchdog 2. Watch1 and lock output a flag damage signal bad1 through an AND gate, and Watch2 and lock output a flag damage signal bad2 through an AND gate. Lock, bad1, and bad2 are input to the control module. At the same time, the processor CPU sends a strobe mode signal Select[3:1] to the control module. The control module obtains the working mode according to Select[3:1], including the automatic working mode and the intervention working mode. In the automatic working mode, the control module performs logical processing according to Lock, bad1, and bad2 to output Mux1_set and Mux2_set without the participation of the processor. In the intervention working mode, the control module performs logical processing according to Select[3:1] to output Mux1_set and Mux2_set, and selects the clock source under the intervention of the processor.

[0032] The CPU realizes the gating control of the dual-channel clock source in the intervention working mode. In an optional implementation, lock, bad1, and bad2 are input to the CPU, and the CPU can perform intervention adjustment control according to lock, bad1, and bad2. In an optional implementation, the host computer communicates with the processor through the serial port. The register is written in the host computer software. After being processed by the CPU, the dual-channel clock source system can be controlled.

[0033] In this embodiment, the phase-locked loop performs frequency doubling processing on a clock source output by the first multiplexer and performs locking detection. Figure 2 It is a schematic diagram of the phase-locked loop structure, as Figure 2 shown. The phase-locked loop includes a phase detector, a charge pump, a voltage-controlled crystal oscillator, and a locking detection circuit. The first gated clock source is input to the first input terminal of the phase detector through the frequency division coefficient, and the frequency-doubled clock source output by the voltage-controlled crystal oscillator is input to the second input terminal of the phase detector through the feedback frequency division coefficient. The UP signal and the DN signal output by the phase detector are input to the charge pump, and after being processed by the charge pump, they are input to the voltage-controlled crystal oscillator. At the same time, the voltage-controlled crystal oscillator is connected to the voltage control signal with the frequency doubling coefficient; the UP signal and the DN signal are input to the locking detection circuit LDC for locking detection.

[0034] Figure 2 In, Fref is the reference clock, which is one of the signals of CLK1 and CLK2. PFD is the phase detector, CP is the charge pump for filtering and generating the voltage control voltage, and VCO is the voltage-controlled crystal oscillator. DIV is the feedback frequency division coefficient, N is the input frequency division coefficient, M is the frequency doubling coefficient, and the output frequency fout of the phase-locked loop = Fref*M / N. The CPU sets the frequency doubling coefficient M by writing the value of the register PLL_SET, and the corresponding fout of the output frequency of the phase-locked loop is the frequency-doubled clock source PLL_CLK. The fdiv of the feedback output and the reference clock Fref / N are the two input signals of the phase detector PFD. After being filtered, the voltage signal Vctr proportional to the phase difference between the output and the two input signals is output. When the fdiv of the feedback output and the reference clock Fref / N are of the same frequency and in phase, the CP output Vctr is the intermediate value of the VCO voltage.

[0035] Figure 3 It is a schematic diagram of the locking detection circuit structure, including an exclusive OR gate, a delay unit, a NAND gate, the first D flip-flop ( Figure 3 the first D flip-flop in), a shift register unit, the third multiplexer ( Figure 3 MUX3 in), the second D flip-flop ( Figure 3 the last D flip-flop in) and an OR gate.

[0036] In this embodiment, the shift register unit includes a shift register and multiple AND gates (by Figure 3It consists of 8 flip - flops that output d0~d7 and 7 AND gates that process d0~d7. Among them, the shift register includes multiple cascaded D flip - flops. The outputs of each D flip - flop, with every two adjacent ones as a group, are input into an AND gate. The outputs of every two adjacent AND gates are then input into another AND gate until it is connected to the last AND gate. One of the input terminals of the last AND gate is connected to the working voltage of the phase - locked loop, and the output terminal serves as the input terminal of the shift register unit.

[0037] The UP signal and the DN signal are input into the XOR gate. The output terminal of the XOR gate is connected to the input terminal of the delay unit. At the same time, the output terminal of the XOR gate and the output terminal of the delay unit are respectively connected to the input terminals of the NAND gate. The output terminal of the NAND gate is connected to the first input terminal of the first D flip - flop. The second input terminal of the first D flip - flop is connected to the lock - detection clock signal. The output terminal of the first D flip - flop is connected to the first input terminal of the shift register unit. The second input terminal of the shift register unit is connected to the lock - detection clock signal; the output terminal of the shift register unit is connected to the first input terminal of the third multiplexer. The second input terminal of the third multiplexer is connected to the working voltage of the phase - locked loop. The output terminal of the third multiplexer is connected to the first input terminal of the second D flip - flop. The second input terminal of the second D flip - flop is connected to the lock - detection clock signal; the output terminal of the second D flip - flop is connected to the control terminal of the third multiplexer on one hand and the first input terminal of the OR gate on the other hand; the second input terminal of the OR gate is connected to the forced lock signal, and the output terminal of the OR gate outputs the lock signal.

[0038] As Figure 3 shown, DN is the divided - by - two frequency of the reference clock Fref / N, and UP is the divided - by - two frequency of the feedback output fdiv. After the UP and DN signals pass through the XOR gate and the delay unit dly, and then through the NAND gate, the D flip - flop, under the action of the lock - detection clock signal, determines whether the system is locked. Among them, the lock - detection clock signal is generated by the lock - detection clock signal generation sub - circuit. The lock - detection clock signal generation sub - circuit includes an AND gate and a buffer. The UP signal is connected to the first input terminal of the AND gate, the DN signal is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the input terminal of the buffer, and the output terminal of the buffer outputs the lock - detection clock signal, that is, the DN and UP signals generate the lock - detection clock signal after passing through the AND gate and the NOT gate.

[0039] After the system is locked, the UP and DN signals are of the same frequency and in - phase. The XOR gate outputs a low level. The signal delayed for a period of time (the delay is equal to 2 times the delay of the PFD reset unit) and the undelayed signal pass through the NAND gate and are sent to the data input terminal of the D flip - flop. Therefore, the lock - in error can be controlled within 2 times the unit delay. After locking, the C point is set to high level and sent to the shift register to prevent false locking.

[0040] In this embodiment, the shift register unit consists of 8 D flip - flops ( Figure 3A shift register composed of 8 flip - flops that output d0 to d7) and multiple AND gates ( Figure 3 7 AND gates that process d0 to d7). When the output of port C is always high for 9 consecutive clock cycles, all of the d<7:0> output by the flip - flops are set to high. After logical combination through several AND gates, a high level is output at the J terminal. During this period, as long as one of d<7:0> is low, the output at the J terminal is low, effectively preventing false locking.

[0041] When the UP and DN signals are of the same frequency and in phase, the output point C of flip - flop 1 is set to high. After 8 clock rising edges for voltage boost, all of the output ports d<7:0> of the flip - flops are set to high. d0 and d1 output D after passing through an AND gate, d2 and d3 output F after passing through an AND gate, d4 and d5 output G after passing through an AND gate, d6 and d7 output I after passing through an AND gate, D and F output E after passing through an AND gate, G and I output H after passing through an AND gate, and E, H, and Vddcache output J after passing through a three - input AND gate. Since d<7:0> are all set to high and Vddcache is also high, the J point is set to high.

[0042] After power - on reset, the L point is defaulted to low. L feedback - controls the multiplexer to select the Vddcache side of port 2. Since Vddcache is high, L is set to high. After L is set to high, the multiplexer selects the J side of port 1. That is, after the Vddcache level is stable, the multiplexer initially selects port 2. According to positive feedback control, after one clock cycle, it selects port 1 and then always selects port 1 until power - off or reset.

[0043] The signals J and Vddcache pass through a multiplexer and output signal K. K passes through a flip - flop and outputs L, and then outputs lock after passing through an OR gate. When the UP and DN signals are of the same frequency and in phase, the output of J is high, K is also high. After passing through the flip - flop, L is also set to high. Since Force_lock is always low, the lock output is high. When the UP and DN signals are not of the same frequency and in phase, or in the case of occasional same - frequency and in - phase, d<7:0> will not all be set to high, and then the lock output is low.

[0044] The waveforms for phase - locked loop lock detection are as Figure 4 and Figure 5 shown. Among them, Figure 4 the example in Figure 5 shows the unlocked state, and the lock output is low.

[0045] In this embodiment, the power supply voltage VDD is buffered by a MOS to output Vddcache. The buffering of the MOS reduces the impact of power supply noise on digital signals, and Vddcache is used as the operating voltage of the PLL. Figure 6 It is a schematic diagram of a phase-locked loop operating voltage generation circuit. The phase-locked loop operating voltage generation circuit includes a resistor R1, a resistor R2, an N-type MOS transistor Q1, and a P-type MOS transistor Q2. The first end of the resistor R1 is connected to the power supply voltage, the second end is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded; the gate of the P-type MOS transistor Q2 is connected to the first end of the resistor R2, the source is grounded, the drain is connected to the gate of the N-type MOS transistor Q1, the source of the N-type MOS transistor Q1 is connected to the power supply voltage, and the drain outputs the phase-locked loop operating voltage.

[0046] In the above text, an embodiment of a dual-channel clock source switching management system has been described in detail. Based on the dual-channel clock source switching management system described in the above embodiment, the embodiment of the present invention also provides a dual-channel clock source switching management method corresponding to this system.

[0047] Figure 7 It is a schematic diagram of the flow of a dual-channel clock source switching management method provided by the embodiment of the present invention. This method is executed by a control module and includes the following steps.

[0048] S1, Obtain input signals, including a lock signal, a first flag damage signal, a second flag damage signal, and a strobe mode signal.

[0049] When the control module obtains the input signals, it performs logical control to achieve clock source switching. The input signals include a lock signal transmitted from the PLL, a first flag damage signal and a second flag damage signal transmitted from an AND gate, and a strobe mode signal transmitted from the CPU.

[0050] S2, Perform lock detection through the lock signal. If not locked, execute step S3; if locked, execute step S4.

[0051] S3, Detect whether the lock times out. If not timed out, continue with the lock detection. If timed out, detect whether the first clock source and the second clock source are valid through the first flag damage signal and the second flag damage signal. If both clock sources are invalid, enter the error state. If one clock source is valid and the other is invalid, execute step S5.

[0052] S4, Detect whether the first clock source and the second clock source are valid through the first flag damage signal and the second flag damage signal. If there is a valid clock source, execute step S5.

[0053] S5. Determine the working mode according to the strobe mode signal. If it is the automatic working mode, obtain the first strobe control signal and the second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal; if it is the intervention working mode, obtain the first strobe control signal and the second strobe control signal according to the strobe mode signal.

[0054] In this embodiment, the strobe mode signal is used to determine the working mode, including the automatic working mode and the intervention working mode. And in the intervention working mode, the strobe mode signal contains the channel information to be strobed. Specifically, first, analyze the strobe mode signal to obtain the status of the strobe mode flag bit included in the strobe mode signal; if the status of the strobe mode flag bit is the first mode status, it is determined as the automatic working mode. In the automatic working mode, the control module obtains the first strobe control signal and the second strobe control signal according to the lock signal, the first flag damage signal, and the second flag damage signal. If the status of the strobe mode flag bit is the second mode status, it is determined as the intervention working mode. In the intervention working mode, the control module obtains the status of the selected channel flag bit included in the strobe mode signal, and obtains the first strobe control signal and the second strobe control signal according to the status of the selected channel flag bit.

[0055] In the automatic working mode, the control logic of the control module is as follows: (1) Calculate N1 = (~bad1) & lock and N2 = (~bad2) & lock, where bad1 is the first flag damage signal, the low level indicates that the first clock source is valid, the high level indicates that the first clock source is invalid, bad2 is the second flag damage signal, the low level indicates that the second clock source is valid, the high level indicates that the second clock source is invalid, lock is the lock signal, the high level indicates locked, the low level indicates unlocked, ~ represents taking the inverse, and & represents the AND operation; (2) If N1 is at a high level, the first strobe control signal is to select the first clock source, and the second strobe control signal is to select the first clock source; (3) If N2 is at a high level, the first strobe control signal is to select the second clock source, and the second strobe control signal is to select the second clock source.

[0056] In the intervention working mode, the control logic of the control module is as follows: (1) If the status of the selected channel flag bit is the first selection status, the first strobe control signal is to select the first clock source, and the second strobe control signal is to select the frequency - doubled clock source; (2) If the status of the selected channel flag bit is the second selection status, the first strobe control signal is to select the second clock source, and the second strobe control signal is to select the frequency - doubled clock source; (3) If the status of the selected channel flag bit is the third selected status, the first selection control signal is to select the first clock source, and the second selection control signal is to select the second clock source; (4) If the status of the selected channel flag bit is the fourth selected status, the first selection control signal is to select the second clock source, and the second selection control signal is to select the second clock source; (5) If the status of the selected channel flag bit is the fifth selected status, the first selection control signal is to select the first clock source, and the second selection control signal is to select the first clock source; (6) If the status of the selected channel flag bit is the sixth selected status, the first selection control signal is to select the second clock source, and the second selection control signal is to select the first clock source.

[0057] S6. Transmit the first selection control signal to the control terminal of the first multiplexer, and transmit the second selection signal to the control terminal of the second multiplexer.

[0058] The control module transmits the calculated selection control signal to the control terminal of the multiplexer, and the multiplexer outputs the signal of the selected channel according to the selection control signal.

[0059] Figure 8 It is a schematic flowchart of a specific embodiment of the dual-clock-source switching management method according to an embodiment of the present invention. After power-on or reset, the initial values of the input variables are bad1 = 0, bad = 0, lock = 0, select[3:0] = 1xx1; select[3:0] being equal to 1xxx indicates that after system initialization, the system defaults to working in the automatic mode. Then the circuit performs a lock detection. If lock is equal to 1, it means that the PLL has been locked, and then according to the values of bad1 and bad2, it is determined whether the clock source CLK1 or CLK2 is valid. If lock is equal to 0, it means that the current is not locked, and it is judged whether it times out. If it does not time out, return to continue the lock detection; if it times out, bad1 is equal to 1 and bad2 is equal to 0, indicating that CLK1 is invalid and is ready to switch to CLK2; if it times out, bad2 is equal to 1 and bad1 is equal to 0, indicating that CLK2 is invalid and is ready to switch to CLK1; if it times out, bad2 is equal to 1 and bad1 is equal to 1, indicating that both CLK1 and CLK2 are invalid, enter an error state, and the system needs to be reset or powered on again.

[0060] If select[3:0] equals 1xxx, it indicates that in the automatic working mode, CPU participation in control is not required; otherwise, it means the system is working in the CPU intervention mode. In the automatic working mode, Mux1_set and Mux2_set are determined by N1 and N2. Mux1_set[2:0] = {x, N1, N2}. If N1 is high, Mux1_set[2:0] = x1x, which selects the clock source CLK1; if N2 is high, Mux1_set[2:0] = xx1, which selects the clock source CLK2. In the automatic working mode, Mux2_set[4:0] = {1, select[2:1], N1, N2}. If N1 is high, Mux2_set[4:0] = {1, select[2:1], 1, N2}, which selects the clock source CLK1; if N2 is high, Mux2_set[4:0] = {1, select[2:1], N1, 1}, which selects the clock source CLK2.

[0061] In the CPU intervention mode, select[3:0]=0XXX, and Mux1_set and Mux2_set are determined by select. Mux1_set[2:0]={select[0], N1, N2}, and Mux2_set[4:0]={0, select[2:1], N1, N2}. If select[3:0]=0111, Mux2_set[4:0]={011, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK1, and MUX2 selects the 3-channel; if select[3:0]=0110, Mux2_set[4:0]={010, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK2, and MUX2 selects the 3-channel; if select[3:0]=0101, Mux2_set[4:0]={010, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK1, and MUX2 selects the 2-channel; if select[3:0]=0100, Mux2_set[4:0]={010, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK2, and MUX2 selects the 2-channel; if select[3:0]=0011, Mux2_set[4:0]={010, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK1, and MUX2 selects the 1-channel; if select[3:0]=0010, Mux2_set[4:0]={010, N1, N2}, and Mux1_set[2:0]={1, N1, N2}, that is, MUX1 selects the clock source CLK2, and MUX2 selects the 1-channel; if select[3:0] is equal to 0000 or 0001, MUX1 and MUX2 maintain the current selection unchanged.

[0062] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dual-channel clock source switching management system, characterized in that: It includes a first multiplexer, a second multiplexer, a phase-locked loop, a first watchdog, a second watchdog and a control module; The first clock source and the second clock source are connected to the input end of the first multiplexer, the output end of the first multiplexer is connected to the input end of the phase-locked loop, the phase-locked loop performs frequency multiplication processing on the first selection clock source output by the first multiplexer and outputs the frequency multiplication clock source; at the same time, the phase-locked loop performs lock detection on the first selection clock source output by the first multiplexer and outputs a lock signal; The first clock source, the second clock source, and the frequency-multiplied clock source are connected to the input end of the second multiplexer, and the second multiplexer outputs a second gated clock source; The first clock source outputs a first monitoring signal via a first watchdog, and the second clock source outputs a second monitoring signal via a second watchdog; the locking signal and the first monitoring signal output a first flag damage signal via an AND gate, and the locking signal and the second monitoring signal output a second flag damage signal via an AND gate; The locking signal, the first mark damage signal, and the second mark damage signal are input into the control module, and the control module receives the selection mode signal input by the processor at the same time. If the selection mode signal is the automatic working mode, the control module obtains the first selection control signal and the second selection control signal according to the locking signal, the first mark damage signal, and the second mark damage signal. If the selection mode signal is the intervention working mode, the control module obtains the first selection control signal and the second selection control signal according to the selection mode signal. The first selection control signal is connected to the control end of the first multiplexer, and the second selection signal is connected to the control end of the second multiplexer.

2. The dual-channel clock source switching management system according to claim 1, characterized in that: The phase-locked loop includes a phase detector, a charge pump, a voltage-controlled crystal oscillator, and a lock detection circuit; The first selection clock source is input into the first input terminal of the phase detector through the frequency division coefficient, the frequency multiplication clock source output by the voltage-controlled crystal oscillator is input into the second input terminal of the phase detector through the feedback frequency division coefficient, the UP signal and the DN signal output by the phase detector are input into the charge pump, and then input into the voltage-controlled crystal oscillator after being processed by the charge pump, and at the same time, the voltage-controlled crystal oscillator is connected to the voltage-controlled control signal through the frequency multiplication coefficient; The UP signal and the DN signal are input to the lock detection circuit for lock detection.

3. The dual-channel clock source switching management system according to claim 2, characterized in that: The lock detection circuit includes an XOR gate, a delay unit, a NAND gate, a first D flip-flop, a shift register unit, a third multiplexer, a second D flip-flop and an OR gate; The UP signal and the DN signal are input to the XOR gate, the output end of the XOR gate is connected to the input end of the delay unit, and the output end of the XOR gate and the output end of the delay unit are respectively connected to the input end of the NAND gate, the output end of the NAND gate is connected to the first input end of the first D flip-flop, the second input end of the first D flip-flop is connected to the lock detection clock signal, the output end of the first D flip-flop is connected to the first input end of the shift register unit, and the second input end of the shift register unit is connected to the lock detection clock signal; The output end of the shift register unit is connected to the first input end of the third multiplexer, the second input end of the third multiplexer is connected to the phase-locked loop working voltage, the output end of the third multiplexer is connected to the first input end of the second D flip-flop, and the second input end of the second D flip-flop is connected to the lock detection clock signal; The output end of the second D flip-flop is connected to the control end of the third multiplexer and to the first input end of the OR gate; the second input end of the OR gate is connected to the forced locking signal, and the output end of the OR gate outputs the locking signal.

4. The dual-channel clock source switching management system according to claim 3, characterized in that: The shift register unit includes a shift register and a plurality of AND gates, wherein the shift register includes a plurality of D flip-flops connected in series; the outputs of the respective D flip-flops are input into an AND gate in groups of two adjacent ones, and the outputs of each two adjacent AND gates are input into an AND gate again until they are connected to the last AND gate, one of the input ends of the last AND gate is connected to the phase-locked loop working voltage, and the output end serves as the input end of the shift register unit.

5. The dual-channel clock source switching management system according to claim 4, characterized in that: The lock detection circuit also includes a lock detection clock signal generating subcircuit, and the lock detection clock signal generating subcircuit includes an AND gate and a buffer; The UP signal is connected to the first input terminal of the AND gate, the DN signal is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the input terminal of the buffer, and the output terminal of the buffer outputs the lock detection clock signal.

6. The dual-channel clock source switching management system according to claim 4, characterized in that: The system also includes a phase-locked loop working voltage generating circuit, which includes a resistor R1, a resistor R2, an N-type MOS tube Q1, and a P-type MOS tube Q2; The first end of the resistor R1 is connected to the power supply voltage, the second end is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded; The gate of the P-type MOS transistor Q2 is connected to the first end of the resistor R2, the source is grounded, the drain is connected to the gate of the N-type MOS transistor Q1, the source of the N-type MOS transistor Q1 is connected to the power supply voltage, and the drain outputs the phase-locked loop operating voltage.

7. A dual-channel clock source switching management method, characterized in that: The system according to any one of claims 1 to 6 is implemented, comprising the following steps: Step 1, obtaining input signals, including a lock signal, a first mark damage signal, a second mark damage signal, and a strobe mode signal; Step 2, perform lock detection through the lock signal, if not locked, execute step 3, if locked, execute step 4; Step 3, detect whether the lock has timed out. If not, continue the lock detection. If it has timed out, detect whether the first clock source and the second clock source are valid through the first mark damage signal and the second mark damage signal. If both clock sources are invalid, enter the error state. If one of the clock sources is valid and the other is invalid, execute step 5. Step 4, detecting whether the first clock source and the second clock source are valid through the first flag damage signal and the second flag damage signal, and if there is a valid clock source, executing step 5; Step 5, judging the working mode according to the strobe mode signal, if it is the automatic working mode, obtaining the first strobe control signal and the second strobe control signal according to the lock signal, the first mark damage signal and the second mark damage signal; if it is the intervention working mode, obtaining the first strobe control signal and the second strobe control signal according to the strobe mode signal; Step 6: Transmit the first selection control signal to the control end of the first multiplexer, and transmit the second selection signal to the control end of the second multiplexer.

8. The dual-channel clock source switching management method according to claim 7, characterized in that: Step S5 specifically includes: Parsing the strobe mode signal to obtain the strobe mode flag bit state contained in the strobe mode signal; If the state of the strobe mode flag is the first mode state, it is determined to be an automatic working mode, and in the automatic working mode, the first strobe control signal and the second strobe control signal are obtained according to the lock signal, the first flag damage signal, and the second flag damage signal; If the selection mode flag state is the second mode state, it is determined to be an intervention working mode, and the selection channel flag state included in the selection mode signal is obtained in the intervention working mode, and the first selection control signal and the second selection control signal are obtained according to the selection channel flag state.

9. The dual-channel clock source switching management method according to claim 8, characterized in that: Acquiring a first gating control signal and a second gating control signal according to a locking signal, a first flag damage signal, and a second flag damage signal specifically includes: Calculate N1=(~bad1)&lock and N2=(~bad2)&lock, where bad1 is the first flag damage signal, low level indicates that the first clock source is valid, high level indicates that the first clock source is invalid, bad2 is the second flag damage signal, low level indicates that the second clock source is valid, high level indicates that the second clock source is invalid, lock is the lock signal, high level indicates that it is locked, low level indicates that it is unlocked, ~ indicates negation, & indicates AND operation; If N1 is at a high level, the first gating control signal is for gating the first clock source, and the second gating control signal is for gating the first clock source; If N2 is at a high level, the first selection control signal is used to select the second clock source, and the second selection control signal is used to select the second clock source.

10. The dual-channel clock source switching management method according to claim 8, characterized in that: Acquiring a first gating control signal and a second gating control signal according to a gating channel flag bit state specifically includes: If the state of the strobe channel flag bit is the first strobe state, the first strobe control signal is to select the first clock source, and the second strobe control signal is to select the multiplied frequency clock source; If the state of the strobe channel flag bit is the second strobe state, the first strobe control signal is to select the second clock source, and the second strobe control signal is to select the multiplied frequency clock source; If the state of the strobe channel flag bit is the third strobe state, the first strobe control signal is to strobe the first clock source, and the second strobe control signal is to strobe the second clock source; If the state of the strobe channel flag bit is the fourth strobe state, the first strobe control signal is to strobe the second clock source, and the second strobe control signal is to strobe the second clock source; If the state of the strobe channel flag bit is the fifth strobe state, the first strobe control signal is to strobe the first clock source, and the second strobe control signal is to strobe the first clock source; If the state of the select channel flag bit is the sixth select state, the first select control signal is for selecting the second clock source, and the second select control signal is for selecting the first clock source.

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