Display device and pixel driving circuit

Abstract

The embodiment of the invention belongs to the display circuit technology, and provides a display device and a pixel driving circuit, and the display device comprises a display panel and the pixel driving circuit. The display panel comprises a plurality of pixels, and each pixel comprises at least one LED; the pixel driving circuit comprises a first transistor, the control end of which is connected with the first end of a first capacitor and the output end of a data input circuit, the first end receives a light-emitting control signal, and the second end is connected with the first end of a light-emitting control circuit; the data input circuit receives a first data signal, and writes the voltage variation generated by level conversion of the first data signal into the control end of the first transistor; based on the first capacitor, the voltage of the control end of the first transistor changes along with the target reference signal; the light-emitting control circuit controls the LED according to the voltage of the second end of the first transistor; according to the invention, gray scale control is realized based on the first data signal and the target reference signal, and the uniformity of the light emitting wavelength of the LED is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to display circuit technologies. More specifically, it relates to a display device and a pixel driving circuit. Background Art

[0002] Compared with AMOLED (Active matrix organic light emitting diode), μLED has advantages such as smaller size, faster response speed, higher luminous efficiency, stronger stability, and longer service life. Therefore, the display application fields based on μLED have developed rapidly.

[0003] In some related technologies, Figure 1 For a schematic diagram of a pixel circuit, the brightness of μLED can be controlled through the Figure 1 shown pixel circuit. This pixel circuit is configured with 7T1C and a dual-EM signal selection circuit, and controls the output of EM1 and EM2 by controlling the voltages written to C2 and C3, and controls the LED based on EM1 and EM2.

[0004] Since the pulse width ratios of EM1 and EM2 are not adjustable during panel display, this method needs to control the brightness of the LED by controlling the on-state current of T2, resulting in poor uniformity of the LED emission wavelength. Summary of the Invention

[0005] Embodiments of the present application provide a display device and a pixel driving circuit, which are used to solve the problem in the related art that the brightness of the LED is controlled by controlling the on-state current of the transistor T2, resulting in poor uniformity of the LED emission wavelength.

[0006] In a first aspect, embodiments of the present application provide a display device, which includes: a display panel and a pixel driving circuit;

[0007] The display panel includes a plurality of pixels, and each pixel includes at least one LED;

[0008] The pixel driving circuit includes:

[0009] A first transistor, whose control terminal is connected to the first end of a first capacitor and the output terminal of a data input circuit, the first end receives a light emission control signal, and the second end is connected to the first end of a light emission control circuit;

[0010] The input terminal of the data input circuit receives a first data signal, and is configured to write a voltage change amount corresponding to the level conversion of the first data signal to the control terminal of the first transistor;

[0011] The second terminal of the first capacitor receives a target reference signal, which is used to control the voltage at the control terminal of the first transistor to change when the target reference signal changes;

[0012] The second terminal of the light emission control circuit is connected to the LED, and is used to control the LED according to the voltage at the second terminal of the first transistor;

[0013] Among them, the light emission control signal, the first data signal, and the target reference signal are periodic signals, and the light emission control signal and the first data signal have high and low level transitions within a period. When the light emission control signal is at a level that controls the first transistor to conduct, the target reference signal changes linearly.

[0014] In a second aspect, an embodiment of the present application provides a display device, including: a display panel and a pixel driving circuit;

[0015] The pixel driving circuit is configured to:

[0016] When the first data signal undergoes a level conversion, the data input circuit writes the voltage change amount corresponding to the level conversion into the control terminal of the first transistor;

[0017] When the light emission control signal is at a level that controls the first transistor to conduct, a linearly changing target reference signal is received through the first terminal of the first capacitor, the first terminal of the first transistor receives the light emission control signal, the first transistor is controlled to conduct, and the light emission control circuit controls the LED to emit light according to the voltage at the second terminal of the first transistor;

[0018] After the light emission control signal undergoes a level conversion from the level that controls the first transistor to conduct, the first transistor is turned off, and the light emission control circuit controls the LED to stop emitting light according to the voltage at the second terminal of the first transistor;

[0019] Among them, the light emission control signal, the first data signal, and the target reference signal are periodic signals, and the light emission control signal and the first data signal have high and low level transitions within a period. When the light emission control signal is at a level that controls the first transistor to conduct, the target reference signal changes linearly.

[0020] In a third aspect, an embodiment of the present application provides a pixel driving circuit, including:

[0021] A first transistor, the control terminal of which is connected to the first terminal of the first capacitor and the output terminal of the data input circuit, the first terminal receives the light emission control signal, and the second terminal is connected to the first terminal of the light emission control circuit;

[0022] The input terminal of the data input circuit receives the first data signal, and is used to write the voltage change amount corresponding to the level conversion of the first data signal into the control terminal of the first transistor;

[0023] The second terminal of the first capacitor receives a target reference signal, which is used to control the voltage at the control terminal of the first transistor to change when the target reference signal changes;

[0024] The second terminal of the light-emitting control circuit is connected to the LED, and is used to control the LED according to the voltage at the second terminal of the first transistor;

[0025] Among them, the light-emitting control signal, the first data signal, and the target reference signal are periodic signals, and there are high and low level conversions of the light-emitting control signal and the first data signal within a period. When the light-emitting control signal is at a level that controls the first transistor to conduct, the target reference signal changes linearly.

[0026] The present application provides a display device and a pixel driving circuit. The display device includes a display panel and a pixel driving circuit. Among them, the display panel includes a plurality of pixels, and each pixel includes at least one LED. When the level of the first data signal changes, the voltage change amount corresponding to the first data signal is written into the control terminal of the first transistor. When the light-emitting control signal is at a level that controls the first transistor to conduct, as the target reference signal changes linearly, the first transistor conducts, and the light-emitting control circuit can control the LED to emit light according to the current voltage at the second terminal of the first transistor. When the light-emitting control signal changes from the level that controls the first transistor to conduct, the first transistor turns off, and the light-emitting control circuit controls the LED to stop emitting light based on the current voltage at the second terminal of the first transistor. Since the pixel driving circuit of the present application can control the conduction duration of the first transistor through the voltage change amount of the first data signal, the change of the target reference signal, and the light-emitting control signal, and then control the light-emitting time of the LED, realize gray-scale control, without changing the magnitude of the current flowing through the LED, effectively ensuring the uniformity of the light-emitting wavelength of the LED, and at the same time improving the accuracy of gray-scale control and the display effect. Description of the Drawings

[0027] In order to more clearly illustrate the embodiments of the present application or the implementation manners in the related art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the related art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

[0028] Figure 1 It is a schematic diagram of a pixel circuit;

[0029] Figure 2 It is a schematic diagram of a display device provided by an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of a display device provided by an embodiment of the present application;

[0031] Figure 4Schematic diagram of a pixel driving circuit provided by an embodiment of the present application Figure 1 ;

[0032] Figure 5 Schematic diagram of a pixel driving circuit provided by an embodiment of the present application Figure 2 ;

[0033] Figure 6 Timing diagram of control signals corresponding to a P-type thin film transistor provided by an embodiment of the present application;

[0034] Figure 7 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor during a reset stage provided by an embodiment of the present application;

[0035] Figure 8 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor during a threshold voltage compensation stage provided by an embodiment of the present application;

[0036] Figure 9 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor during a data voltage writing stage provided by an embodiment of the present application;

[0037] Figure 10 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor in the early stage of a light emitting stage provided by an embodiment of the present application;

[0038] Figure 11 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor in the later stage of a light emitting stage provided by an embodiment of the present application;

[0039] Figure 12 Schematic diagram of a pixel driving circuit corresponding to an N-type thin film transistor provided by an embodiment of the present application;

[0040] Figure 13 Timing diagram of control signals corresponding to an N-type thin film transistor provided by an embodiment of the present application. Detailed implementation manners

[0041] To make the objectives, implementation manners, and advantages of the present application clearer, the following will clearly and completely describe the exemplary implementation manners of the present application with reference to the accompanying drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0042] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the subsequent described implementation manners, rather than intending to limit the implementation manners of the present application. Unless otherwise specified, these terms should be understood in their ordinary and common meanings.

[0043] In addition, the terms "comprising" and "having" and any variations thereof are intended to cover inclusion but not exclusive inclusion. For example, a product or device comprising a series of components need not be limited to those components clearly listed, but may include other components not clearly listed or inherent to such products or devices.

[0044] Compared with AMOLED (Active matrix organic light emitting diode), μLED has the advantages of smaller size, faster response speed, higher luminous efficiency, stronger stability, and longer service life. Therefore, the display application field based on μLED has developed rapidly.

[0045] In this field, thin film transistors (TFTs) represented by low-temperature polycrystalline silicon (LTPS) have become an important material in the display industry due to their high electron mobility, enabling high-resolution driving, fast panel response time, and low power consumption.

[0046] Currently, for the active μLED display technology, there are two problems that need to be solved urgently, as follows:

[0047] 1. The mass transfer technology of μLED. In order to reduce costs and maximize the advantages of μLED, the mass transfer technology of μLED is crucial.

[0048] 2. The gray-scale expansion design scheme of μLED. Since the IV characteristic curve of μLED is relatively steep, that is, the voltage change amount between the two levels corresponding to the low-gray-scale current to the high-gray-scale current of μLED is small, it is difficult to expand the gray scale by the traditional analog voltage drive (PAM) method.

[0049] In the μLED display circuit based on LTPS thin film transistors, the existing technology usually adopts a 2T1C pixel circuit combined with a micro silicon-based CMOS drive to achieve high-gray-scale display. In addition, the digital pulse width modulation (PWM) drive method has also received extensive attention. PWM drive controls the brightness sensed by the human eye by controlling the light-emitting time of μLED. Under the conditions of the same drive current and the same refresh frequency, the larger the proportion of the light-emitting time of μLED in the total refresh time, the higher the brightness sensed by the human eye. Through this method, precise control of the gray-scale brightness can be achieved.

[0050] However, due to the high cost of the active μLED display technology based on micro silicon-based CMOS drive, following the PAM drive method means that the drive circuit requires an extremely fast clock signal to meet the extremely high voltage resolution. At the same time, using CMOS drive has certain impacts on the flexibility, transparency, and thickness of the panel.

[0051] With the PWM scheme, a driving control signal can be generated by using a gate-on-array (GOA) circuit on the panel. The PWM scheme divides each frame display time into n sub-frames with equal proportions. Each pixel unit needs to be turned on once within each sub-frame time, and the data voltage input by the IC (integrated circuit) each time determines whether the μLED corresponding to this sub-frame emits light. This method can achieve a relatively high gray scale. However, the driving speed of the GOA circuit is limited. When the resolution is relatively high, multiple turn-ons result in a relatively long period of time that cannot be used for light emission, thus limiting the improvement of the gray scale number.

[0052] In some related technologies, PWM and PAM can be combined, which not only achieves a relatively high gray scale but also reduces the requirements for the driving speed of the GOA circuit. Combining Figure 1 It can be known that this scheme is an 11T3C circuit with a 7T1C architecture and a dual-EM selection circuit. The outputs of EM1 and EM2 are realized by controlling the voltages written to C2 and C3. Since the pulse width ratios of EM1 and EM2 are not adjustable during panel display, the control of the LED lighting time in this scheme is not flexible. The brightness of the LED needs to be controlled by controlling the on-state current of T2, resulting in relatively poor uniformity of the LED emission wavelength, relatively poor accuracy in controlling the LED brightness based on the on-state current, and relatively poor gray scale control effect.

[0053] Meanwhile, due to the relatively large number of TFTs, the wiring area of the pixel circuit is relatively large, and the PPI (Pixels Per Inch, a unit of pixel density) is relatively low, resulting in a relatively low panel resolution and relatively poor display effect. Meanwhile, there are relatively many types of driving signals, which requires support from relatively many driving circuits.

[0054] The present application provides a display device, which includes a display panel and a pixel driving circuit. Among them, the display panel includes a plurality of pixels, and each pixel includes at least one LED. The pixel driving circuit can control the LED based on a light emission control signal, a first data signal, and a target reference signal. When the level of the first data signal received by the data input circuit changes, the voltage change amount corresponding to the first data signal can be written into the control terminal of the first transistor to change the voltage of the control terminal of the first transistor. When the light emission control signal is at a level that controls the first transistor to conduct, it linearly changes with the target reference signal, causing the first transistor to conduct. The light emission control circuit can control the LED to emit light according to the voltage at the second terminal of the current first transistor. After the light emission control signal undergoes a level conversion from the level that controls the first transistor to conduct, the first transistor is controlled to turn off, and further, the light emission control circuit controls the LED to stop emitting light based on the voltage at the control terminal of the current first transistor. The pixel driving circuit of the present application can control the conduction duration of the first transistor through the voltage change amount of the first data signal, the change of the target reference signal, and the light emission control signal, thereby controlling the light emission time of the LED, achieving gray-scale control, without changing the magnitude of the current flowing through the LED, effectively ensuring the uniformity of the light emission wavelength of the LED, and at the same time improving the accuracy of gray-scale control and the display effect.

[0055] The display device provided by the embodiments of the present application can have various implementation forms. For example, it can be a television, a smart television, a monitor, etc. The present application does not limit this.

[0056] Figure 2 Schematic diagram of a display device provided by an embodiment of the present application, as Figure 2 shown, the display device may include: a display panel, a timing controller, a data driver, etc. Among them, the display panel includes a plurality of pixels P defined by the intersection of a plurality of scan lines and a plurality of data lines DL. The data driver is used to drive the data lines.

[0057] The timing controller is used to process externally input image data, generate a data control signal, and output the data control signal and the image data to the data driver.

[0058] The data driver can use a reference gamma voltage and the data control signal to convert the image data into a data signal in analog form and provide the data signal in analog form to the corresponding data line. The data signal in analog form is the first data signal Date_PWM of the present application.

[0059] The driving control signal of the present application can be generated by using the gate-on-array (GOA) circuit provided on the display panel. The gate-on-array (GOA) circuit is not shown in Figure 2It is displayed in []. The driving control signals include, but are not limited to, the first reference signal, the second reference signal, the third reference signal, the light emission control signal, the target reference signal, etc. of the present application.

[0060] The technical solution of the present application will be described in detail below in conjunction with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0061] Figure 3 It is a schematic diagram of a display device provided by an embodiment of the present application, as Figure 3 shown, the display device includes: a display panel 10 and a pixel driving circuit 20;

[0062] The display panel 10 includes a plurality of pixels, and each pixel includes at least one LED;

[0063] The pixel driving circuit 20 includes:

[0064] The first transistor T1, the control end is connected to the first end of the first capacitor C1 and the output end of the data input circuit 201, the first end receives the light emission control signal EM, and the second end is connected to the first end of the light emission control circuit 202;

[0065] The input end of the data input circuit 201 receives the first data signal Date_PWM, and is used to write the voltage change amount corresponding to the level conversion of the first data signal Date_PWM into the control end of the first transistor T1;

[0066] The second end of the first capacitor C1 receives the target reference signal sweep, and is used to control the voltage at the control end of the first transistor T1 to change when the target reference signal sweep changes;

[0067] The second end of the light emission control circuit 202 is connected to the LED, and is used to control the LED according to the voltage at the second end of the first transistor T1;

[0068] Among them, the light emission control signal EM, the first data signal Date_PWM, and the target reference signal sweep are periodic signals, and the light emission control signal EM and the first data signal Date_PWM have high and low level conversions within the period. When the light emission control signal EM is at the level that controls the first transistor T1 to conduct, the target reference signal sweep changes linearly.

[0069] In some embodiments, the display panel 10 may be a glass panel.

[0070] In some embodiments, the first transistor T1 can be a P-type thin film transistor or an N-type thin film transistor. Both the P-type thin film transistor and the N-type thin film transistor include a gate, a source, and a drain. Among them, the control terminal of the transistor in the present application is the gate of the transistor. The first terminal can be the source, and the second terminal is the drain, or the first terminal is the drain and the second terminal is the source, as long as the transistor can be turned on or off.

[0071] There are certain conditions for the thin film transistor to conduct. For a P-type thin film transistor, its conduction condition is Vgs - Vth < 0, where Vgs represents the voltage difference between the gate and the source of the transistor, and Vth represents the threshold voltage of the transistor. For an N-type thin film transistor, its conduction condition is Vgs - Vth > 0.

[0072] The light emission control signal EM is a periodic signal. When the light emission control signal EM is at a level that controls the first transistor T1 to conduct, as the target reference signal sweep continuously changes, based on the coupling effect of the first capacitor C1, the voltage at the control terminal of the first transistor T1 also changes, causing the first transistor T1 to conduct. At this time, the voltage at the second terminal of the first transistor T1 is the voltage V of the first transistor T1. EM 。

[0073] Since the second terminal of the first transistor T1 is connected to the first terminal of the light emission control circuit 202, that is, the voltage at the first terminal of the light emission control circuit 202 is also V. EM 。The LED is connected to the second terminal of the light emission control circuit 202, and the other end can receive a voltage signal VSS. The light emission control circuit 202 can control the LED to emit light according to the current voltage V at the first terminal. EM Control the LED to emit light.

[0074] In one implementation scenario, if the first transistor T1 is a P-type thin film transistor, based on the conduction condition of the P-type thin film transistor, when the light emission control signal EM is at a level that controls the first transistor T1 to conduct, the target reference signal sweep can be controlled to linearly decrease, so that the first transistor T1 changes from the off state to the on state.

[0075] Since the light emission control signal EM changes between high and low levels in each cycle, when the light emission control signal EM undergoes a level conversion from the level that controls the first transistor T1 to conduct, at this time the first transistor T1 is turned off, and there is no voltage at the second terminal of the first transistor T1, that is, there is no voltage at the first terminal of the light emission control circuit 202. Therefore, the light emission control circuit 202 can control the LED to stop emitting light.

[0076] In some embodiments, the first data signal Date_PWM is a voltage value that changes according to the emission brightness of the LED. The level transition of the first data signal Date_PWM occurs before the control signal becomes the level for turning on the first transistor T1. That is, based on the level transition of the first data signal Date_PWM, the data input circuit 201 adjusts the voltage at the control terminal of the first transistor T1. Thereafter, when the emission control signal EM is at the level for turning on the first transistor T1, the voltage at the control terminal of the first transistor T1 is changed based on the changing target reference signal sweep to turn on the first transistor T1, and the emission control circuit 202 can control the LED to emit light. As can be seen from the above, the voltage change amount of the first data signal Date_PWM affects the conduction duration of the first transistor T1, and thus affects the emission duration of the LED.

[0077] An embodiment of the present application provides a display device, including a display panel 10 and a pixel driving circuit 20. The display panel 10 includes a plurality of pixels, and each pixel includes at least one LED. The pixel driving circuit 20 may include a first transistor T1, a data input circuit 201, a first capacitor C1, and an emission control circuit 202. When a level transition occurs in the first data signal Date_PWM, the data input circuit 201 can write the voltage change amount corresponding to the first data signal Date_PWM to the control terminal of the first transistor T1 to change the voltage at the control terminal of the first transistor T1. When the emission control signal EM is at the level for turning on the first transistor T1, due to the linear change of the target reference signal sweep, based on the coupling effect of the first capacitor C1, the voltage at the control terminal of the first transistor T1 also changes accordingly to turn on the first transistor T1, and the emission control circuit 202 controls the LED to emit light according to the voltage at the second terminal of the current first transistor T1. When the level transition of the emission control signal EM occurs from the level for turning on the first transistor T1, the first transistor T1 is turned off, there is no voltage at the second terminal of the first transistor T1, and the emission control circuit 202 controls the LED to stop emitting light. The pixel driving circuit 20 of the present application controls the conduction time of the first transistor based on the emission control signal EM, the first data signal Date_PWM, and the target reference signal sweep, controls the emission time of the LED, and thus realizes brightness adjustment, i.e., gray scale control. The flexibility of controlling the emission time of the LED is improved, the size of the current flowing through the LED does not need to be adjusted, the uniformity of the emission wavelength of the LED is effectively guaranteed. At the same time, gray scale control based on controlling the conduction time of the first transistor also effectively improves the accuracy of gray scale control and enhances the display effect.

[0078] Figure 4 Schematic diagram of a pixel driving circuit provided by an embodiment of the present application Figure 1 , such as Figure 4As shown, the light emission control circuit 202 includes:

[0079] A second transistor T2, whose control terminal is connected to the second terminal of the first transistor T1, whose first terminal receives a first voltage signal VDD, and whose second terminal is connected to the first terminal of a third transistor T3; the second terminal of the third transistor T3 is connected to the first terminal of a fourth transistor T4;

[0080] The control terminal of the fourth transistor T4 receives a light emission control signal EM, and its second terminal is connected to the LED;

[0081] The period of the light emission control signal EM includes at least a light emission stage, and in the light emission stage, the light emission control signal EM is at a level that controls the first transistor T1 to conduct.

[0082] The second transistor T2, the third transistor T3, and the fourth transistor T4 can be P-type thin film transistors or N-type thin film transistors. Among them, the second terminal of the fourth transistor T4 is connected to the anode of the LED, and the cathode of the LED receives a second voltage signal VSS.

[0083] In the light emission stage, the light emission control signal EM is at a level that controls the first transistor T1 to conduct, and the first transistor T1 conducts, which is used to set the voltage at the control terminal of the second transistor T2 to V EM , to control the second transistor T2 to conduct.

[0084] The second transistor T2 conducts, and sets the voltage at the first terminal of the third transistor T3 to the voltage corresponding to the first voltage signal VDD, to control the third transistor T3 to conduct. Among them, the first voltage signal VDD is a fixed voltage value.

[0085] The third transistor T3 conducts, and sets the voltage at the first terminal of the fourth transistor T4 to VDD, to control the fourth transistor T4 to conduct, and sets the voltage at the second terminal of the fourth transistor T4, that is, the anode voltage of the LED, to VDD. The cathode voltage of the LED is VSS, to control the LED to emit light.

[0086] When the light emission control signal EM undergoes a level conversion from the level that controls the first transistor T1 to conduct, the first transistor T1 turns off, and there is no voltage at the first terminal of the first transistor T1, that is, the control terminal of the second transistor T2. The second transistor T2 turns off, and further controls the third transistor T3 and the fourth transistor T4 to turn off. There is no voltage at the anode of the LED, and the LED stops emitting light.

[0087] In some embodiments, the pixel driving circuit 20 further includes: a ninth transistor T9, a third capacitor C3, and a tenth transistor T10;

[0088] The control terminal of the ninth transistor T9 receives a third reference signal S3, the first terminal receives a reset signal REF, and the second terminal is connected to the first terminal of a third capacitor C3 and the control terminal of a third transistor T3 respectively, for resetting the voltage at the control terminal of the third transistor T3;

[0089] The second terminal of the third capacitor C3 receives a first voltage signal VDD for storing voltage;

[0090] The control terminal of the tenth transistor T10 receives a third reference signal S3, the first terminal receives a reset signal REF, and the second terminal is connected to the control terminal of the first transistor T1, for resetting the voltage at the control terminal of the first transistor T1;

[0091] The third reference signal S3 is a periodic signal with high and low level transitions within a period, and the period at least includes a reset stage, a threshold voltage compensation stage, a data voltage writing stage, and a light emitting stage, and the reset stage is before the threshold voltage compensation stage;

[0092] In the reset stage, the third reference signal S3 is a level for turning on the ninth transistor T9 and the tenth transistor T10, and is different from the levels in the threshold voltage compensation stage, the data voltage writing stage, and the light emitting stage.

[0093] The ninth transistor T9 and the tenth transistor T10 can be P-type thin film transistors or N-type thin film transistors.

[0094] In the reset stage, based on the third reference signal S3 and the reset signal REF, the ninth transistor T9 and the tenth transistor T10 are turned on. Based on the ninth transistor T9, the voltage at the control terminal of the third transistor T3, that is, Figure 4 point A in is set to V REF , to reset the voltage at the control terminal of the third transistor T3 and eliminate the influence of the remaining voltage at the control terminal of the third transistor T3 in the previous period.

[0095] Among them, the reset signal REF is a fixed voltage. At the same time, the third capacitor C3 can store voltage, so that after the ninth transistor T9 is turned off, the voltage at point A still remains at V REF .

[0096] Similarly, based on the tenth transistor T10, the voltage at the control terminal of the first transistor T1, that is, Figure 4 point B in is set to V REF , to reset the voltage at the control terminal of the first transistor T1 and eliminate the influence of the remaining voltage at the control terminal of the first transistor T1 in the previous period.

[0097] In one or more embodiments of the present application, the pixel driving circuit 20 further includes: a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8;

[0098] The control terminal of the sixth transistor T6 receives the second reference signal S2, the first terminal receives the second data signal Date_PAM, and the second terminal is connected to the first terminal of the third transistor T3, and is configured to set the voltage at the first terminal of the third transistor T3 to the voltage corresponding to the second data signal Date_PAM;

[0099] The control terminal of the seventh transistor T7 receives the second reference signal S2, the first terminal is connected to the control terminal of the third transistor T3, and the second terminal is connected to the second terminal of the third transistor T3, and is configured to perform threshold voltage compensation on the third transistor T3;

[0100] The control terminal of the eighth transistor T8 receives the second reference signal S2, the first terminal is connected to the control terminal of the first transistor T1, and the second terminal is connected to the second terminal of the first transistor T1, and is configured to perform threshold voltage compensation on the first transistor T1;

[0101] Wherein, the second data signal Date_PAM and the second reference signal S2 are periodic signals and have high and low level transitions within a period, and the period at least includes a threshold voltage compensation stage, a data voltage writing stage, and a light emitting stage, and the threshold voltage compensation stage is located before the data voltage writing stage;

[0102] The levels of the second data signal Date_PAM are the same during the data voltage writing stage and the light emitting stage, and are different from the level during the threshold voltage compensation stage; during the threshold voltage compensation stage, the data voltage writing stage, and the light emitting stage, the level of the second reference signal S2 is the same as that of the second data signal Date_PAM.

[0103] The second data signal Date_PAM is a fixed voltage value to ensure the uniformity of the LED emission wavelength.

[0104] The sixth transistor T6 is configured to set the voltage at the first terminal of the third transistor T3 to the voltage corresponding to the second data signal Date_PAM, and the seventh transistor T7 is configured to perform threshold voltage compensation on the third transistor T3 to eliminate the influence of the threshold voltage, improve the accuracy of controlling the on / off of the third transistor T3, and is beneficial to improving the display effect.

[0105] Similarly, the eighth transistor T8 is configured to perform threshold voltage compensation on the first transistor T1 to eliminate the influence of the threshold voltage and improve the accuracy of controlling the on / off of the first transistor T1.

[0106] The second data signal Date_PAM and the second reference signal S2 may further include a reset stage, and the level of the second reference signal S2 during the reset stage is the same as the levels during the data voltage writing stage and the light emitting stage. The level of the second data signal Date_PAM during the reset stage is the same as the levels during the data voltage writing stage and the light emitting stage, and is different from the level during the threshold voltage compensation stage.

[0107] In some embodiments, the data input circuit 201 includes: a fifth transistor T5 and a second capacitor C2;

[0108] The control terminal of the fifth transistor T5 receives a first reference signal S1, the first terminal receives a first data signal Date_PWM, and the second terminal is connected to the first terminal of the second capacitor C2;

[0109] The other end of the second capacitor C2 is connected to the control terminal of the first transistor T1, and is used to write the voltage change amount corresponding to the level conversion into the control terminal of the first transistor T1 when the first data signal Date_PWM undergoes a high-low level conversion;

[0110] The first reference signal S1 has the same period as the first data signal Date_PWM, and there are high-low level conversions within the period. The period at least includes a data voltage writing stage and a light emitting stage, and the data voltage writing stage is located before the light emitting stage;

[0111] In the data voltage writing stage, the first reference signal S1 is a level for controlling the fifth transistor T5 to conduct, and is different from the level in the light emitting stage; the first data signal Date_PWM has the same level as the first reference signal S1 in the data voltage writing stage and the same level as the first reference signal S1 in the light emitting stage.

[0112] The fifth transistor T5 is used to couple the voltage change value of the Date_PWM signal to the control terminal of the first transistor T1 through the second capacitor C2 when the Date_PWM signal undergoes a level conversion, that is, to change the voltage of the control terminal of the first transistor T1, and further adjust the conduction time of the first transistor T1.

[0113] In summary, in the light emitting stage, the light emitting control signal EM is a level for controlling the first transistor T1 to conduct, the first transistor T1 conducts, and then controls the second transistor T2, the third transistor T3, and the fourth transistor T4 to conduct, and the LED emits light. Before the light emitting stage, the voltage of the control terminal of the third transistor T3 can be reset through the ninth transistor T9, and the voltage of the control terminal of the first transistor T1 can be reset through the tenth transistor T10, eliminating the influence of the remaining charges in the previous cycle, which is beneficial to improving the accuracy of controlling the on-off of the third transistor T3 and the first transistor T1. At the same time, the threshold voltage of the third transistor T3 can be compensated through the seventh transistor T7, and the threshold voltage of the first transistor T1 can be compensated through the eighth transistor T8, eliminating the influence of the threshold voltage, which is beneficial to improving the display effect.

[0114] Figure 5 Schematic diagram of a pixel driving circuit provided by an embodiment of the present application Figure 2 , reference Figure 5As shown, the light-emitting control circuit may include:

[0115] A second transistor T2, whose control terminal receives a light-emitting control signal EM, a first terminal receives a first voltage signal VDD, and a second terminal is connected to a first terminal of a third transistor T3; a second terminal of the third transistor T3 is connected to a first terminal of a fourth transistor T4;

[0116] A control terminal of the fourth transistor T4 is connected to a second terminal of the first transistor T1, and a second terminal is connected to an LED;

[0117] The period of the light-emitting control signal EM includes at least a light-emitting stage. During the light-emitting stage, the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct.

[0118] The pixel driving circuit further includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The specific driving process can refer to other embodiments, and will not be elaborated here in this application.

[0119] Still referring to the above Figure 3 As shown, in one or more embodiments of the present application, a display device includes: a display panel 10 and a pixel driving circuit 20;

[0120] The pixel driving circuit 20 is configured to:

[0121] When a level conversion occurs in the first data signal Date_PWM, the data input circuit 201 writes the voltage change amount corresponding to the level conversion into the control terminal of the first transistor T1;

[0122] When the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct, a target reference signal sweep that linearly changes is received through a first terminal of a first capacitor C1. A first terminal of the first transistor T1 receives the light-emitting control signal EM to control the first transistor T1 to conduct. The light-emitting control circuit 202 controls the LED to emit light according to the voltage at the second terminal of the first transistor T1;

[0123] After the light-emitting control signal EM is level-converted from the level that controls the first transistor T1 to conduct, the first transistor T1 is turned off, and the light-emitting control circuit 202 controls the LED to stop emitting light according to the voltage at the second terminal of the first transistor T1;

[0124] Among them, the light-emitting control signal EM, the first data signal Date_PWM, and the target reference signal sweep are periodic signals, and there are high and low level conversions in the period of the light-emitting control signal EM and the first data signal Date_PWM. When the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct, the target reference signal sweep linearly changes.

[0125] Referring to the aboveFigure 4 As shown, in some embodiments, the light-emitting control circuit 202 is configured to:

[0126] In the light-emitting stage, the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct. Based on the first transistor T1, the voltage at the control terminal of the second transistor T2 is set to the voltage corresponding to the light-emitting control signal EM. The first terminal of the second transistor T2 receives the first voltage signal VDD, and the second transistor T2 conducts;

[0127] Based on the second transistor T2, the voltage at the first terminal of the third transistor T3 is set to the voltage corresponding to the first voltage signal VDD to make the third transistor T3 conduct;

[0128] Based on the third transistor T3, the voltage at the first terminal of the fourth transistor T4 is set to the voltage corresponding to the first voltage signal VDD. The control terminal of the fourth transistor T4 receives the light-emitting control signal EM, and the fourth transistor T4 conducts to control the LED to emit light;

[0129] After the light-emitting control signal EM is level-converted from the level that controls the first transistor T1 to conduct, the first transistor T1 turns off, so that the second transistor T2, the third transistor T3, and the fourth transistor T4 turn off, and the LED stops emitting light;

[0130] The period of the light-emitting control signal EM includes at least the light-emitting stage. In the light-emitting stage, the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct.

[0131] Referring to the above Figure 5 As shown, in some embodiments, the light-emitting control circuit is configured to:

[0132] In the light-emitting stage, the light-emitting control signal EM is at a level that controls the first transistor T1 to conduct. The control terminal of the second transistor T2 receives the light-emitting control signal EM, and the first terminal receives the first voltage signal VDD. The second transistor T2 conducts to set the voltage at the first terminal of the third transistor T3 to the voltage corresponding to the first voltage signal VDD to make the third transistor T3 conduct;

[0133] Based on the third transistor T3, the voltage at the first terminal of the fourth transistor T4 is set to the voltage corresponding to the first voltage signal VDD. Based on the first transistor T1, the voltage at the control terminal of the fourth transistor T4 is set to the voltage corresponding to the light-emitting control signal EM, and the fourth transistor T4 conducts to control the LED to emit light;

[0134] After the light-emitting control signal EM is level-converted from the level that controls the first transistor T1 to conduct, the first transistor T1 and the second transistor T2 turn off; based on the second transistor T2, the third transistor T3 turns off; based on the third transistor T3 and the first transistor T1, the fourth transistor T4 turns off, and the LED stops emitting light;

[0135] The period of the light emission control signal EM includes at least a light emission stage, during which the light emission control signal EM is at a level for controlling the first transistor T1 to conduct.

[0136] In an implementation scenario, the periods of the light emission control signal EM, the first data signal Date_PWM, and the target reference signal sweep each include at least a reset stage, a threshold voltage compensation stage, a data voltage writing stage, and a light emission stage.

[0137] Among them, the reset stage is a process of resetting the voltage of the pixel driving circuit 20 to eliminate the influence of the remaining charges in the previous cycle, and is located before the threshold voltage compensation stage. The threshold voltage compensation stage is located before the data voltage writing stage and is a process of compensating the threshold voltages of the transistors included in the pixel driving circuit 20. The data voltage writing stage is located before the light emission stage and is a process of writing the data voltage, that is, a process in which the first data signal Date_PWM undergoes a level transition and the corresponding voltage change amount is written into the control terminal of the first transistor T1. The light emission stage is a process of controlling the LED to emit light.

[0138] During the light emission stage, the light emission control signal EM is at a level for controlling the first transistor T1 to conduct, and the target reference signal sweep linearly changes. In an implementation scenario, the levels of the light emission control signal EM in the reset stage, the threshold voltage compensation stage, and the data voltage writing stage are the same and different from the level in the light emission stage.

[0139] In some embodiments, the data input circuit 201 is configured to:

[0140] During the data voltage writing stage, the control terminal of the fifth transistor T5 receives the first reference signal S1, the first terminal receives the first data signal Date_PWM, the fifth transistor T5 conducts, and based on the coupling effect of the second capacitor C2, the voltage change amount corresponding to the high and low level transition of the first data signal Date_PWM is written into the control terminal of the first transistor T1;

[0141] During the data voltage writing stage, the first reference signal S1 is at a level for controlling the fifth transistor T5 to conduct and is different from the level in the light emission stage; the first data signal Date_PWM has the same level as the first reference signal S1 during the data voltage writing stage and the same level as the first reference signal S1 during the light emission stage.

[0142] The periods of the first data signal Date_PWM and the first reference signal S1 may also include a reset phase and a threshold voltage compensation phase. Since the first reference signal S1 is mainly used to control the conduction of the first transistor T1 during the data voltage writing phase, the first reference signal S1 is at a level that controls the conduction of the fifth transistor T5 during the data voltage writing phase. At the same time, in order to charge the second capacitor C2 and reset the voltage at one end of the second capacitor C2 close to the fifth transistor T5, the first reference signal S1 may have the same level as that in the data voltage writing phase during the reset phase, and be different from the levels in the threshold voltage compensation phase and the light emitting phase.

[0143] In an implementation scenario, the levels of the first data signal Date_PWM are consistent during the reset phase, the threshold voltage compensation phase, and the light emitting phase, and are different from the level in the data voltage writing phase.

[0144] In some embodiments, the pixel driving circuit 20 is further configured to:

[0145] During the reset phase, the control terminal of the ninth transistor T9 receives the third reference signal S3, the first terminal receives the reset signal REF, the ninth transistor T9 conducts, and based on the third capacitor C3, the voltage at the control terminal of the third transistor T3 is set to the voltage corresponding to the reset signal REF;

[0146] The control terminal of the tenth transistor T10 receives the third reference signal S3, the first terminal receives the reset signal REF, the tenth transistor T10 conducts, so as to set the voltage at the control terminal of the first transistor T1 to the voltage corresponding to the reset signal REF;

[0147] The third reference signal S3 is a periodic signal and has a high-low level transition within the period. The period includes at least a reset phase, a threshold voltage compensation phase, a data voltage writing phase, and a light emitting phase, and the reset phase is before the threshold voltage compensation phase;

[0148] During the reset phase, the third reference signal S3 is at a level that controls the conduction of the ninth transistor T9 and the tenth transistor T10, and is different from the levels in the threshold voltage compensation phase, the data voltage writing phase, and the light emitting phase.

[0149] In some embodiments, the pixel driving circuit 20 is further configured to:

[0150] During the threshold voltage compensation phase, the control terminal of the sixth transistor T6 receives the second reference signal S2, the first terminal receives the second data signal Date_PAM, the sixth transistor T6 conducts, and the voltage at the first terminal of the third transistor T3 is set to the voltage corresponding to the second data signal Date_PAM, so that the third transistor T3 conducts;

[0151] Receiving a second reference signal S2 through a control terminal of a seventh transistor T7 to turn on the seventh transistor T7, compensating a threshold voltage of a third transistor T3, setting a voltage of a control terminal of the third transistor T3 to a sum of a voltage corresponding to a second data signal Date_PAM and the threshold voltage, and turning off the third transistor T3;

[0152] Receiving the second reference signal S2 through a control terminal of an eighth transistor T8 to turn on the eighth transistor T8, compensating a threshold voltage of a first transistor T1, and setting a voltage of a control terminal of the first transistor T1 to a sum of a voltage corresponding to a light emission control signal EM and the threshold voltage;

[0153] Wherein, the second data signal Date_PAM and the second reference signal S2 are periodic signals and have high and low level transitions within a period, and the period at least includes a threshold voltage compensation stage, a data voltage writing stage, and a light emission stage, and the threshold voltage compensation stage is before the data voltage writing stage;

[0154] The second data signal Date_PAM has the same level in the data voltage writing stage and the light emission stage, and is different from the level in the threshold voltage compensation stage; in the threshold voltage compensation stage, the data voltage writing stage, and the light emission stage, the second reference signal S2 has the same level as the second data signal Date_PAM.

[0155] The period of the second data signal Date_PAM and the second reference signal S2 may further include a reset stage. Since the second reference signal S2 is mainly used to turn on the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 in the threshold compensation stage, in the threshold voltage compensation stage, the second reference signal S2 is a level for turning on the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The second reference signal S2 has the same level in the reset stage, the data voltage writing stage, and the light emission stage, and is different from the level in the threshold voltage compensation stage.

[0156] For the second data signal Date_PAM, it is used to write a data voltage of the second data signal Date_PAM to a first end of the third transistor T3 when the sixth transistor T6 is turned on. Therefore, the level of the second data signal Date_PAM in the threshold voltage compensation stage is different from the levels in the reset stage, the data voltage writing stage, and the light emission stage.

[0157] In summary, the pixel driving circuit 20 of the present application controls the conduction time of the second transistor T2 through the first data signal Date_PWM, the light emission control signal EM, the target reference signal sweep, etc., to control the light emission duration of the LED, realizing gray scale control, improving the accuracy of gray scale control. At the same time, it is not necessary to change the magnitude of the current flowing through the LED, effectively ensuring the uniformity of the light emission wavelength of the LED. The light emission driving circuit of the present application can realize gray scale control with ten transistors and three capacitors, reducing the number of transistors, saving the area occupied by the pixel driving circuit 20 in the panel, thereby effectively improving the pixel density and the panel resolution.

[0158] Based on the above embodiments, a specific embodiment is provided below. The process of controlling the LED in stages when the first transistor T1 to the tenth transistor T10 are all P-type thin film transistors is described in detail. Among them, it may include four stages: a reset stage, a threshold voltage compensation stage, a data voltage writing stage, and a light emission stage. Figure 6 It is a timing diagram of control signals corresponding to a P-type thin film transistor provided by an embodiment of the present application. The control signals may include a first reference signal S1, a second reference signal S2, a third reference signal S3, a light emission control signal EM, a target reference signal sweep, a first data signal Date_PWM, and a second data signal Date_PAM. Refer to Figure 6 As shown, (1), (2), (3), and (4) correspond to the reset stage, the threshold voltage compensation stage, the data voltage writing stage, and the light emission stage in sequence. The driving process of the pixel driving circuit 20 is specifically as follows:

[0159] Reset stage:

[0160] Figure 7 It is a schematic diagram of a pixel driving circuit corresponding to a reset stage provided by an embodiment of the present application. Combining Figure 6 and Figure 7 As shown, for the ninth transistor, since the third reference signal S3 is at a low level, Vgs - Vth9 = V S3 -V REF -Vth9 < 0, the ninth transistor T9 is turned on. Based on the ninth transistor T9, the third capacitor C3 is charged, and the voltage at the control terminal of the third transistor T3, that is, the voltage at point A, V A = V REF , realizes the reset of the voltage at point A.

[0161] It should be noted that the present application involves multiple transistors. Vgs is used to represent the voltage difference between the gate and the source of the transistor, and Vth is used to represent the threshold voltage of the transistor. The threshold voltage of the Nth transistor can be denoted as Vth N, for example, the above Vth9 represents the threshold voltage of the ninth transistor, which will not be elaborated in detail hereinafter.

[0162] For the tenth transistor, since the third reference signal S3 is at a low level, Vgs - Vth 10 = V S3 - V REF - Vth 10 < 0, the tenth transistor T10 is turned on. Based on the tenth transistor T10, the voltage at the control terminal of the first transistor T1, i.e., the voltage V B = V REF realizes the reset of the voltage at point B and also charges the first capacitor C1.

[0163] For the first transistor T1, since the light emission control signal EM received at the first end of the first transistor T1 is at a high level at this time, its voltage can be denoted as V EM-high , Vgs - Vth1 = V REF – V EM-high - Vth1 < 0, the first transistor T1 is turned on, and the voltage at the second end of the second transistor T2 is set to V EM-high . For the second transistor T2, since Vgs - Vth2 = V EM-high - VDD - Vth2 > 0, the second transistor T2 is turned off.

[0164] For the sixth transistor T6, since the second reference signal S2 is at a high level and the second data signal Date_PAM is at a high level, but Vgs - Vth6 = V S2 - V Date_PAM - Vth6 > 0, the sixth transistor T6 is turned off. For the seventh transistor T7, since Vgs - Vth7 = V S2 - V REF - Vth7 > 0, the seventh transistor T7 is turned off. For the eighth transistor T8, since Vgs - Vth8 = V S2 - V REF - Vth8 > 0, the eighth transistor T8 is turned off.

[0165] Since both the second transistor T2 and the sixth transistor T6 are turned off, there is no voltage at the first end of the third transistor T3, so the third transistor T3 is turned off. Further, there is no voltage at the first end of the fourth transistor T4, and the fourth transistor T4 is turned off. The LED does not emit light at this stage.

[0166] Since the first reference signal S1 is at a low level and the first data signal Date_PWM is at a high level, for the fifth transistor T5, Vgs - Vth5 = V S1 - V Date_PWM-Vth5 < 0, the fifth transistor T5 is turned on, charging the second capacitor C2. At the same time, the first end of the second capacitor C2, i.e., the end close to the fifth transistor T5, is reset to eliminate the voltage of the previous cycle, i.e., the previous frame.

[0167] Threshold voltage compensation stage:

[0168] Figure 8 This is a schematic diagram of a pixel driving circuit corresponding to a P-type thin-film transistor provided in an embodiment of the present application for a threshold voltage compensation stage. Combining Figure 6 and Figure 8 As shown, since the third reference signal S3 is at a high level in this stage, Vgs - Vth9 = V S3 -V REF -Vth9 > 0, the ninth transistor T9 is turned off, and Vgs - Vth 10 = V S3 -V REF -Vth 10 > 0, the tenth transistor T10 is turned off.

[0169] Since the first reference signal S1 is at a high level and the first data signal Date_PWM is at a high level, but Vgs - Vth5 = V S1 -V Date_PWM -Vth5 > 0, so the fifth transistor T5 is in the off state.

[0170] Since the second reference signal S2 is at a low level and the second data signal Date_PAM is at a low level, but Vgs - Vth6 = V S2 -V Date_PAM -Vth6 < 0, the sixth transistor T6 is turned on, setting the voltage at the first end of the third transistor T3 to V Date_PAM . Based on the voltage stored in the third capacitor C3, so after the reset stage ends, i.e., the ninth transistor T9 is turned off, the voltage at point A is still V REF . Since Vgs - Vth3 = V REF -V Date_PAM -Vth3 < 0, the third transistor T3 is turned on.

[0171] For the seventh transistor T7, since Vgs - Vth7 = V S2 -V REF -Vth7 < 0, the seventh transistor T7 is turned on, causing the control end and the second end of the third transistor T3 to be connected. At this time, the control end of the third transistor T3 is the gate, and the second end is the drain, enabling threshold voltage compensation for the third transistor T3. Since the voltage at the current first end of the third transistor T3 is V Date_PAM , so the voltage at the control end of the third transistor T3, i.e., the voltage at point A, changes from V REF to VDate_PAM +Vth3, where Vth3 is the threshold voltage of the third transistor T3.

[0172] For the third transistor T3, at this time Vgs - Vth3 = (V Date_PAM +Vth3) - V Date_PAM -Vth3 = 0. Therefore, after performing threshold voltage compensation on the third transistor T3, that is, the potential at point A becomes V Date_PAM +Vth3, the third transistor T3 turns off.

[0173] Since the third transistor T3 is off, there is no voltage at the first end of the fourth transistor T4, and the fourth transistor T4 is off, and the LED does not emit light.

[0174] Similarly, based on the voltage stored in the first capacitor C1, after the tenth transistor T10 turns off, the voltage at point B, that is, the control terminal of the first transistor T1 and the first end of the eighth transistor T8, is still V REF . For the eighth transistor T8, since Vgs - Vth8 = V S2 -V REF -Vth8 < 0, the eighth transistor T8 is on.

[0175] Since the first transistor T1 is on during the reset stage, the conduction of the eighth transistor T8 connects the control terminal and the second terminal of the first transistor T1. The control terminal is the gate, and the second terminal is the drain, and threshold voltage compensation can be performed on the first transistor T1. Since the first end of the first transistor T1 currently receives the light emission control signal EM, and the light emission control signal EM is at a high level, the voltage at the control terminal of the first transistor T1, that is, the voltage at point B, changes from V REF to V EM-high +Vth1.

[0176] For the first transistor T1, Vgs - Vth1 = (V EM-high +Vth1) - V EM-high -Vth1 = 0. Therefore, after performing threshold voltage compensation on the first transistor T1, that is, the voltage at point B becomes V EM-high +Vth1, the first transistor T1 turns off. Where Vgs represents the voltage difference between the control terminal and the second terminal of the first transistor T1, V EM-high represents the voltage when the light emission control signal EM is at a high level, and Vth1 represents the threshold voltage of the first transistor T1.

[0177] Since the first transistor T1 is off, there is no voltage at the control terminal of the second transistor T2, so the second transistor T2 remains off.

[0178] Data voltage writing stage:

[0179] Figure 9 Schematic diagram of a pixel driving circuit corresponding to a P-type thin film transistor in a data voltage writing stage provided by an embodiment of the present application, in combination with Figure 6 and Figure 9 As shown, since the third reference signal S3 is at a high level in this stage, Vgs-Vth9 = V S3 -V REF -Vth9 > 0, the ninth transistor T9 remains off, and Vgs-Vth 10 = V S3 -V REF -Vth 10 > 0, and the tenth transistor T10 remains in the off state.

[0180] Since the second reference signal S2 is at a high level and the second data signal Date_PAM is at a high level, but Vgs-Vth6 = V S2 -V Date_PAM -Vth6 > 0, the sixth transistor T6 is off.

[0181] For the seventh transistor T7, the voltage at its first end is the voltage V at point A Date_PAM + Vth3. Since Vgs-Vth7 = V S2 -(V Date_PAM + Vth3)-Vth7 > 0, the seventh transistor T7 is off.

[0182] For the eighth transistor T8, the voltage at its first end is the voltage V at point B EM-high + Vth1. Since Vgs-Vth8 = V S2 -(V EM-high + Vth1)-Vth8 > 0, the eighth transistor T8 is off.

[0183] For the first data signal Date_PWM, it is at a high level in the threshold voltage compensation stage and at a low level in the data voltage writing stage. Since the fifth transistor T5 needs to be turned on first and then the high and low levels are switched to enable the second capacitor C2 to sense the voltage change, that is, after the threshold voltage compensation stage ends, the first data signal Date_PWM can remain at a high level for a preset time.

[0184] Within the preset time, since the first reference signal S1 is at a low level and the first data signal Date_PWM remains at a high level, Vgs-Vth5 = V S1 -V Date_PWM -Vth5 < 0, and the fifth transistor T5 is turned on. After the preset time, the first data signal Date_PWM undergoes a level conversion from a high level to a low level, but currently Vgs-Vth5 = V S1 -V Date_PWM-Vth5 < 0, and the fifth transistor T5 remains in the conducting state.

[0185] Due to the level conversion of the first data signal Date_PWM, a voltage change value is written based on the coupling effect of the second capacitor C2. The voltage at the control terminal of the first transistor T1, that is, the voltage at point B, changes from V EM-high +Vth1 to V EM-high +Vth1+△V Date_PWM , where △V Date_PWM is the voltage change value when the first data signal Date_PWM changes from high level to low level.

[0186] Since the voltage change values of the first data signal Date_PWM in different cycles are different, in one implementation scenario, the high level of the first data signal Date_PWM can be set to a fixed value, and the voltage value of the low level of the first data signal Date_PWM can be changed in different cycles to change the voltage change value of the first data signal Date_PWM. Further, after the data voltage is written at the control terminal of the first transistor T1 in different cycles, the voltages at the control terminals are different, and the conduction times of the first transistor T1 in different cycles are different, thereby controlling the conduction time of the second transistor T2 and realizing the control of the LED lighting time.

[0187] For the first transistor T1, since the first data signal Date_PWM changes from high level to low level, the voltage change value △V Date_PWM is negative, and the level of the light emission control signal EM received at its first end is high level, that is, V EM-high . Therefore, currently Vgs - Vth1 = (V EM-high +Vth1+△V Date_PWM ) - V EM-high -Vth1 = △V Date_PWM < 0, so the first transistor T1 conducts.

[0188] Since the first transistor T1 conducts, the voltage at the control terminal of the second transistor T2 is set to V EM-high , and Vgs - Vth2 = V EM - high -VDD - Vth2 > 0, so the second transistor T2 is in the off state.

[0189] Since both the second transistor T2 and the sixth transistor T6 are off, there is no voltage at the first end of the third transistor T3, so the third transistor T3 is off. Further, since the third transistor T3 is off, there is no voltage at the first end of the fourth transistor T4, so the fourth transistor T4 is off, and the LED does not emit light during the data voltage input stage.

[0190] Light emission stage:

[0191] During the light-emitting stage, based on whether the LED emits light, the light-emitting stage can be divided into two stages: the early stage of the light-emitting stage and the late stage of the light-emitting stage.

[0192] Figure 10 The following is a schematic diagram of the pixel driving circuit corresponding to the P-type thin-film transistor in the early stage of the light-emitting stage provided by the embodiments of the present application. Figure 6 And Figure 10 , the driving process of the pixel driving circuit 20 in the early stage of the light-emitting stage will be described in detail.

[0193] Since the third reference signal S3 is at a high level in this stage, Vgs-Vth9 = V S3 -V REF -Vth9 > 0, the ninth transistor T9 remains in the off state, and Vgs-Vth 10 = V S3 -V REF -Vth 10 > 0, the tenth transistor T10 remains in the off state.

[0194] Since the second reference signal S2 is at a high level, the second data signal Date_PAM is at a high level, but Vgs-Vth6 = V S2 -V Date_PAM -Vth6 > 0, the sixth transistor T6 is turned off.

[0195] For the seventh transistor T7, the voltage at its first end, which is the voltage at point A, is still V Date_PAM +Vth3. Since Vgs-Vth7 = V S2 -(V Date_PAM +Vth3)-Vth7 > 0, the seventh transistor remains in the off state.

[0196] For the eighth transistor T8, the voltage at its current first end, which is the voltage at point B, is V EM -high+Vth1+△V Date_PWM , since Vgs-Vth8 = V S2 -(V EM-high +Vth1+△V date_PWM )-Vth8 > 0, the eighth transistor T8 is turned off.

[0197] Since the first reference signal S1 is at a high level in this stage, the first data signal Date_PWM is at a high level, but Vgs-Vth5 = V S1 -V Date_PWM -Vth5 > 0, so the fifth transistor T5 is in the off state.

[0198] During the light-emitting stage, the light-emitting control signal EM is at a low level, and its voltage can be denoted as V EM-lowFor the first transistor T1, Vgs - Vth1 = (V EM-high + Vth1 + △V date_PWM ) - V EM-low - Vth1 > 0, and the first transistor T1 is in the off state.

[0199] Since during the light-emitting stage, the target reference signal sweep linearly decreases, based on the coupling effect of the first capacitor C1, the voltage at the control terminal of the first transistor T1, i.e., point B, decreases from V EM-high + Vth1 + △V Date_PWM gradually. When the target reference signal sweep decreases to a certain threshold, the voltage at the control terminal of the first transistor T1 and the voltage at the first terminal V EM-low satisfy the transistor conduction condition, and the first transistor T1 conducts.

[0200] Before the target reference signal sweep decreases to this threshold, the first transistor T1 remains in the off state. This stage is the early stage of the light-emitting stage. During this time, since the first transistor T1 is off, there is no voltage at the control terminal of the second transistor T2, causing the second transistor T2 to be off, and further causing the third transistor T3 and the fourth transistor T4 to be off, and the LED does not emit light.

[0201] When the target reference signal sweep decreases to this threshold and the first transistor T1 conducts, this stage can be regarded as the late stage of the light-emitting stage.

[0202] It should be noted that the rate of linear change, i.e., the slope, of the target reference signal sweep can be set according to actual requirements.

[0203] Figure 11 FIG. shows a schematic diagram of a pixel driving circuit corresponding to a P-type thin-film transistor in the late stage of the light-emitting stage provided by an embodiment of the present application. With reference to Figure 6 and Figure 11 shown, the specific driving process of the pixel driving circuit 20 in the late stage of the light-emitting stage can be described in detail.

[0204] Since in the late stage of the light-emitting stage, the level state of the third reference signal S3 is the same as that in the early stage of the light-emitting stage, still being high level, Vgs - Vth9 = V S3 - V REF - Vth9 > 0, and the ninth transistor T9 remains in the off state, Vgs - Vth 10 = V S3 - V REF - Vth 10 > 0, and the tenth transistor T10 remains in the off state.

[0205] Since the second reference signal S2 also remains high, the second data signal Date_PAM is high, and Vgs-Vth6 = V S2 -V Date_PAM -Vth6 > 0, and the sixth transistor T6 remains in the off state.

[0206] For the seventh transistor T7, the voltage at its first terminal, which is the voltage at point A, remains V Date_PAM +Vth3. Since Vgs-Vth7 = V S2 -(V Date_PAM +Vth3)-Vth7 > 0, the seventh transistor remains in the off state.

[0207] For the eighth transistor T8, as the target reference signal sweep linearly decreases, the voltage at its first terminal, which is the voltage at point B, decreases from V EM-high +Vth1+△V date_PWM gradually. Since Vgs-Vth8 = V S2 -(V EM-high +Vth1+△V date_PWM +△V Sweep )-Vth8 > 0, the eighth transistor T8 is turned off, where △V Sweep represents the voltage value by which the target reference signal sweep decreases.

[0208] Since the first reference signal S1 is high in this stage, the first data signal Date_PWM is high, but Vgs-Vth5 = V S1 -V Date_PWM -Vth5 > 0, so the fifth transistor T5 is in the off state.

[0209] In the later stage of the light-emitting stage, the target reference signal sweep has decreased to a certain threshold, such that the voltage at the control terminal of the first transistor T1 and the voltage at its first terminal V EM-low satisfy the transistor conduction condition, and the first transistor T1 is turned on.

[0210] Based on the first transistor T1, the voltage at the control terminal of the second transistor T2 is set to V EM -low. Since Vgs-Vth2 = V EM - low -VDD-Vth2 < 0, the second transistor T2 is turned on, and the voltage at the first terminal of the third transistor T3 is set to VDD.

[0211] For the third transistor T3, the voltage at its control terminal, which is the voltage at point A, is V Date_PAM +Vth3, and Vgs-Vth3 = (V Date_PAM+Vth3) - VDD - Vth3 < 0, the third transistor T3 conducts, setting the voltage at the first end of the fourth transistor T4 to VDD.

[0212] For the fourth transistor T4, its control terminal receives the light emission control signal EM. At this stage, the light emission control signal EM is at a low level, and its voltage is V EM-low , since Vgs - Vth4 = V EM-low -VDD - Vth4 < 0, so the fourth transistor T4 conducts, controlling the LED to emit light until the light emission control signal EM becomes high level, that is, entering the reset stage of the next cycle, and the LED stops emitting light.

[0213] When entering the reset stage of the next cycle, for the target reference signal sweep, it needs to change from a low level to a high level. To avoid the voltage mutation at one end of the first capacitor, the target reference signal can be delayed for a certain time before changing from a low level to a high level.

[0214] As can be seen from the above, the first data signal Date_PWM, the light emission control signal EM, and the target reference signal sweep, etc., can control the light emission time of the LED, and thus realize the control of gray scale.

[0215] It should be noted that this embodiment is described with the first transistor T1 to the tenth transistor T10 all being P-type thin film transistors. In another implementation scenario, the first transistor T1 to the tenth transistor T10 can also all be N-type thin film transistors. In this case, based on the conduction principle of N-type thin film transistors, the schematic diagram of the pixel driving circuit corresponding to the N-type thin film transistors can be referred to Figure 12 as shown, and the timing diagram of the control signals corresponding to the N-type thin film transistors can be referred to Figure 13 as shown. The process and principle of the pixel driving circuit corresponding to the N-type thin film transistors can refer to the process and principle of the P-type thin film transistor pixel driving circuit above, and will not be elaborated here in this application.

[0216] In another implementation scenario, for the pixel driving circuit corresponding to the N-type thin film transistors, the control terminal of the second transistor T2 can also receive the light emission control signal EM, the control terminal of the fourth transistor T4 is connected to the second end of the first transistor T1, and the connection relationships of the remaining transistors are the same as Figure 12 the relationships shown.

[0217] In summary, the pixel driving circuit 20 of the present application can accurately control the light emitting time of the LED according to the first data signal Date_PWM, the light emitting control signal EM, and the target reference signal sweep, so as to accurately control the light emitting brightness of the LED, achieve the purpose of realizing different brightness displays, realize precise regulation of gray levels, and the gray level transition is relatively uniform. The present application adjusts the light emitting time of the LED by controlling the on / off of the second transistor T2, realizes the control of the light emitting brightness of the LED, and does not need to adjust the current magnitude of the branch where the LED is located, effectively ensuring the uniformity of the light emitting wavelength of the LED and effectively improving the display image quality of the panel. The pixel driving circuit 20 of the present application includes ten transistors and three capacitors. The driving method is PAM and PWM to drive and control the light emitting time of the LED, which can realize the control of the light emitting of the LED. The working principle and driving principle are relatively simple, reducing the number of transistors, saving the area occupied by the pixel driving circuit 20 in the panel, thereby effectively increasing the pixel density and the panel resolution, and being applicable to glass-based LED high-PPI panel display devices. At the same time, the present application involves fewer control signals, reducing the power consumption of the integrated circuit or the driving circuit for generating control signals, and also saving costs.

[0218] An embodiment of the present application provides a pixel driving circuit 20, including:

[0219] A first transistor T1, the control end is connected to the first end of the first capacitor C1 and the output end of the data input circuit 201, the first end receives the light emitting control signal EM, and the second end is connected to the first end of the light emitting control circuit 202;

[0220] The input end of the data input circuit 201 receives the first data signal Date_PWM, and is used to write the voltage change amount corresponding to the level conversion of the first data signal Date_PWM into the control end of the first transistor T1;

[0221] The second end of the first capacitor C1 receives the target reference signal sweep, and is used to control the voltage at the control end of the first transistor T1 to change when the target reference signal sweep changes;

[0222] The second end of the light emitting control circuit 202 is connected to the LED, and is used to control the LED according to the voltage at the second end of the first transistor T1;

[0223] Wherein, the light emitting control signal EM, the first data signal Date_PWM, and the target reference signal sweep are periodic signals, and there are high and low level conversions of the light emitting control signal EM and the first data signal Date_PWM within the period. When the light emitting control signal EM is at the level for controlling the first transistor T1 to conduct, the target reference signal sweep changes linearly.

[0224] For the specific process of the pixel driving circuit 20, reference may be made to the foregoing embodiments, and details thereof will not be elaborated herein in this application.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0226] For the sake of convenience in explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussions are not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are for the purpose of better explaining the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A display device, characterized in that, The display device includes: a display panel and a pixel driving circuit; The display panel includes a plurality of pixels, and each pixel includes at least one LED; The pixel driving circuit includes: A first transistor, whose control terminal is connected to the first end of a first capacitor and the output terminal of a data input circuit, the first end receives a light emission control signal, and the second end is connected to the first end of the light emission control circuit; The input terminal of the data input circuit receives a first data signal, and is configured to write a voltage change amount corresponding to the level conversion of the first data signal into the control terminal of the first transistor; The second end of the first capacitor receives a target reference signal, and is used to control the voltage at the control terminal of the first transistor to change when the target reference signal changes; The second end of the light emission control circuit is connected to the LED, and is used to control the LED according to the voltage at the second end of the first transistor; Wherein, the light emission control signal, the first data signal, and the target reference signal are periodic signals, and the light emission control signal and the first data signal have high and low level conversions within a period. When the light emission control signal is at a level that controls the first transistor to conduct, the target reference signal changes linearly.

2. The display device according to claim 1, characterized in that, The light emission control circuit includes: A second transistor, whose control terminal is connected to the second end of the first transistor, the first end receives a first voltage signal, and the second end is connected to the first end of a third transistor; the second end of the third transistor is connected to the first end of a fourth transistor; The control terminal of the fourth transistor receives the light emission control signal, and the second end is connected to the LED; The period of the light emission control signal includes at least a light emission stage, and in the light emission stage, the light emission control signal is at a level that controls the first transistor to conduct.

3. The display device according to claim 1, characterized in that, The light emission control circuit includes: A second transistor, whose control terminal receives the light emission control signal, the first end receives a first voltage signal, and the second end is connected to the first end of a third transistor; the second end of the third transistor is connected to the first end of a fourth transistor; The control terminal of the fourth transistor is connected to the second end of the first transistor, and the second end is connected to the LED; The period of the light emission control signal includes at least a light emission stage, and in the light emission stage, the light emission control signal is at a level that controls the first transistor to conduct.

4. The display device according to claim 2 or 3, characterized in that, The data input circuit includes: a fifth transistor and a second capacitor; The control terminal of the fifth transistor receives a first reference signal, the first end receives the first data signal, and the second end is connected to the first end of the second capacitor; The other end of the second capacitor is connected to the control terminal of the first transistor, and is used to write a voltage change amount corresponding to the level conversion into the control terminal of the first transistor when the first data signal has a high and low level conversion; The first reference signal has the same period as the first data signal, and has high and low level conversions within the period. The period includes at least a data voltage writing stage and a light emission stage, and the data voltage writing stage is before the light emission stage; During the data voltage writing stage, the first reference signal is at a level that controls the fifth transistor to conduct, and is different from the level during the light emitting stage; the first data signal has the same level as the first reference signal during the data voltage writing stage and the same level as the first reference signal during the light emitting stage.

5. The display device according to claim 4, characterized in that, The pixel driving circuit further includes: a sixth transistor, a seventh transistor, and an eighth transistor; The control terminal of the sixth transistor receives a second reference signal, the first terminal receives a second data signal, and the second terminal is connected to the first terminal of the third transistor, and is configured to set the voltage at the first terminal of the third transistor to the voltage corresponding to the second data signal; The control terminal of the seventh transistor receives the second reference signal, the first terminal is connected to the control terminal of the third transistor, and the second terminal is connected to the second terminal of the third transistor, and is configured to perform threshold voltage compensation on the third transistor; The control terminal of the eighth transistor receives the second reference signal, the first terminal is connected to the control terminal of the first transistor, and the second terminal is connected to the second terminal of the first transistor, and is configured to perform threshold voltage compensation on the first transistor; Wherein, the second data signal and the second reference signal are periodic signals and have high and low level transitions within a period, the period at least includes a threshold voltage compensation stage, a data voltage writing stage, and a light emitting stage, and the threshold voltage compensation stage is located before the data voltage writing stage; The second data signal has the same level during the data voltage writing stage and the light emitting stage, and is different from the level during the threshold voltage compensation stage; during the threshold voltage compensation stage, the data voltage writing stage, and the light emitting stage, the second reference signal has the same level as the second data signal.

6. The display device according to claim 5, characterized in that, The pixel driving circuit further includes: a ninth transistor, a third capacitor, and a tenth transistor; The control terminal of the ninth transistor receives a third reference signal, the first terminal receives a reset signal, and the second terminal is respectively connected to the first terminal of the third capacitor and the control terminal of the third transistor, and is configured to reset the voltage at the control terminal of the third transistor; The second terminal of the third capacitor receives the first voltage signal and is configured to store voltage; The control terminal of the tenth transistor receives the third reference signal, the first terminal receives a reset signal, and the second terminal is connected to the control terminal of the first transistor, and is configured to reset the voltage at the control terminal of the first transistor; The third reference signal is a periodic signal and has high and low level transitions within a period, the period at least includes a reset stage, a threshold voltage compensation stage, a data voltage writing stage, and a light emitting stage, and the reset stage is located before the threshold voltage compensation stage; During the reset stage, the third reference signal is at a level that controls the ninth transistor and the tenth transistor to conduct, and is different from the levels during the threshold voltage compensation stage, the data voltage writing stage, and the light emitting stage.

7. A display device, characterized in that, Including: A display panel and a pixel driving circuit; The pixel driving circuit is configured to: When the first data signal undergoes a level conversion, the data input circuit writes the voltage change amount corresponding to the level conversion into the control terminal of the first transistor; When the light-emitting control signal is at a level that controls the first transistor to conduct, a target reference signal that linearly changes is received through the first end of the first capacitor. The first end of the first transistor receives the light-emitting control signal to control the first transistor to conduct, and the light-emitting control circuit controls the LED to emit light according to the voltage at the second end of the first transistor; After the level of the light-emitting control signal is level-converted by the level that controls the first transistor to conduct, the first transistor is turned off, and the light-emitting control circuit controls the LED to stop emitting light according to the voltage at the second end of the first transistor; Among them, the light-emitting control signal, the first data signal, and the target reference signal are periodic signals, and there are high and low level conversions within the period of the light-emitting control signal and the first data signal. When the light-emitting control signal is at a level that controls the first transistor to conduct, the target reference signal linearly changes.

8. The display device according to claim 7, characterized in that, The light-emitting control circuit is configured as: In the light-emitting stage, when the light-emitting control signal is at a level that controls the first transistor to conduct, based on the first transistor, the voltage at the control end of the second transistor is set to the voltage corresponding to the light-emitting control signal, and the first end of the second transistor receives the first voltage signal, and the second transistor conducts; Based on the second transistor, the voltage at the first end of the third transistor is set to the voltage corresponding to the first voltage signal to make the third transistor conduct; Based on the third transistor, the voltage at the first end of the fourth transistor is set to the voltage corresponding to the first voltage signal. The control end of the fourth transistor receives the light-emitting control signal, and the fourth transistor conducts to control the LED to emit light; After the level of the light-emitting control signal is level-converted by the level that controls the first transistor to conduct, the first transistor is turned off to make the second transistor, the third transistor, and the fourth transistor turn off, and control the LED to stop emitting light; The period of the light-emitting control signal includes at least the light-emitting stage. In the light-emitting stage, the light-emitting control signal is at a level that controls the first transistor to conduct.

9. The display device according to claim 7, characterized in that, The light-emitting control circuit is configured as: In the light-emitting stage, when the light-emitting control signal is at a level that controls the first transistor to conduct, the control end of the second transistor receives the light-emitting control signal, and the first end receives the first voltage signal, and the second transistor conducts to set the voltage at the first end of the third transistor to the voltage corresponding to the first voltage signal to make the third transistor conduct; Based on the third transistor, the voltage at the first end of the fourth transistor is set to the voltage corresponding to the first voltage signal. Based on the first transistor, the voltage at the control end of the fourth transistor is set to the voltage corresponding to the light-emitting control signal, and the fourth transistor conducts to control the LED to emit light; After the level of the light-emitting control signal is level-converted by the level that controls the first transistor to conduct, the first transistor and the second transistor are turned off; Based on the second transistor, the third transistor is turned off; Based on the third transistor and the first transistor, the fourth transistor is turned off to control the LED to stop emitting light; The period of the light-emitting control signal includes at least a light-emitting stage, and in the light-emitting stage, the light-emitting control signal is at a level for controlling the first transistor to conduct.

10. The display device according to claim 8 or 9, characterized in that, The data input circuit is configured to: In the data voltage writing stage, receive a first reference signal through the control terminal of the fifth transistor, receive a first data signal through the first terminal, turn on the fifth transistor, and based on the coupling effect of the second capacitor, write the voltage change amount corresponding to the high and low level conversion of the first data signal to the control terminal of the first transistor; In the data voltage writing stage, the first reference signal is at a level for controlling the fifth transistor to conduct and is different from the level in the light-emitting stage; the first data signal is at the same level as the first reference signal in the data voltage writing stage and at the same level as the first reference signal in the light-emitting stage.

11. The display device according to claim 10, characterized in that, The pixel driving circuit is further configured to: In the threshold voltage compensation stage, receive a second reference signal through the control terminal of the sixth transistor, receive a second data signal through the first terminal, turn on the sixth transistor, and set the voltage at the first terminal of the third transistor to the voltage corresponding to the second data signal to turn on the third transistor; Receive the second reference signal through the control terminal of the seventh transistor to turn on the seventh transistor, perform threshold voltage compensation on the third transistor, and set the voltage at the control terminal of the third transistor to the sum of the voltage corresponding to the second data signal and the threshold voltage, and the third transistor turns off; Receive the second reference signal through the control terminal of the eighth transistor, turn on the eighth transistor, and perform threshold voltage compensation on the first transistor, and set the voltage at the control terminal of the first transistor to the sum of the voltage corresponding to the light-emitting control signal and the threshold voltage; Wherein, the second data signal and the second reference signal are periodic signals and have high and low level conversions within the period, the period includes at least a threshold voltage compensation stage, a data voltage writing stage, and a light-emitting stage, and the threshold voltage compensation stage is located before the data voltage writing stage; The level of the second data signal is consistent in the data voltage writing stage and the light-emitting stage and is different from the level in the threshold voltage compensation stage; In the threshold voltage compensation stage, the data voltage writing stage, and the light-emitting stage, the level of the second reference signal is the same as that of the second data signal.

12. The display device according to claim 11, characterized in that, The pixel driving circuit is further configured to: In the reset stage, receive a third reference signal through the control terminal of the ninth transistor, receive a reset signal through the first terminal, turn on the ninth transistor, and based on the third capacitor, set the voltage at the control terminal of the third transistor to the voltage corresponding to the reset signal; Receive a third reference signal through the control terminal of the tenth transistor, receive a reset signal through the first terminal, turn on the tenth transistor, and set the voltage at the control terminal of the first transistor to the voltage corresponding to the reset signal; The third reference signal is a periodic signal and has high and low level conversions within the period, the period includes at least a reset stage, a threshold voltage compensation stage, a data voltage writing stage, and a light-emitting stage, and the reset stage is located before the threshold voltage compensation stage; In the reset stage, the third reference signal is a level for controlling the ninth transistor and the tenth transistor to conduct, and is different from the levels in the threshold voltage compensation stage, the data voltage writing stage, and the light emitting stage.

13. A pixel driving circuit, characterized in that, Comprising: A first transistor, the control terminal of which is connected to the first terminal of the first capacitor and the output terminal of the data input circuit, the first terminal receiving a light emitting control signal, and the second terminal being connected to the first terminal of the light emitting control circuit; The input terminal of the data input circuit receives a first data signal, and is configured to write a voltage change amount corresponding to the level conversion of the first data signal into the control terminal of the first transistor; The second terminal of the first capacitor receives a target reference signal, and is configured to control the voltage at the control terminal of the first transistor to change when the target reference signal changes; The second terminal of the light emitting control circuit is connected to the LED, and is configured to control the LED according to the voltage at the second terminal of the first transistor; Wherein, the light emitting control signal, the first data signal, and the target reference signal are periodic signals, and there are high and low level conversions of the light emitting control signal and the first data signal within a period. When the light emitting control signal is a level for controlling the first transistor to conduct, the target reference signal linearly changes.

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