Controller circuit for solving ADC conversion data loss

Abstract

The invention discloses a controller circuit for solving ADC (Analog to Digital Converter) conversion data loss, which comprises an RAM (Random Access Memory), an ADC controller, an ADC, an SRAM (Static Random Access Memory) controller and at least one host, and is characterized in that the ADC controller comprises a group of RAM write interfaces and a group of data registers, and the ADC controller is connected with the ADC and is used for temporarily storing conversion data generated by the ADC into the data registers; the ADC controller is connected with the RAM memory through a group of RAM write interfaces and is used for writing conversion data generated by the ADC and temporarily stored in the data register into the RAM memory, the SRAM controller is connected with the RAM memory and is used for reading the conversion data generated by the ADC in the RAM memory, and the ADC controller and the SRAM controller are connected with at least one host and interact with the host. The data storage period is far smaller than the next data conversion, and the situation that new data are lost or old data are covered can be prevented.

Description

Technical Field

[0001] The invention relates to a controller circuit, in particular to a controller circuit for solving the problem of ADC conversion data loss, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] The data after ADC sampling and conversion is usually stored in a specific data register of the ADC. The specific register may be one or more.

[0003] For the ADC controller, one data register can be used to store the data converted by all channels. This method requires fewer registers, but when the ADC conversion speed is fast and the system reads the ADC register slowly, new data may be lost or old data may be overwritten. It cannot be guaranteed that each read of the ADC data register is the latest data.

[0004] For ADC controllers, multiple data registers can also be used to store conversion data in one-to-one correspondence with channels. However, for ADCs with more channels or higher conversion accuracy, more area will be used in exchange for performance advantages. Even in some designs that do not require strict area requirements, when a single channel is continuously converted or the ADC conversion speed is faster than the system reading the ADC conversion speed, it is still inevitable that the data will always be kept up to date.

[0005] In addition, if the content in the data register of the ADC is processed by the CPU at this time, an interrupt or query method is usually used to read the conversion data of the ADC.

[0006] There are three ways for the system to read ADC conversion data: 1) CPU query: such as Figure 8 As shown in the figure, the CPU keeps querying the flag bit of the ADC data register. Once the flag bit is queried, the ADC data register will be read. This method will continuously occupy CPU resources, which will not only slow down the CPU processing program, but also cause the ADC to continuously convert data, which will lead to untimely data processing, loss of new conversion data or overwriting of old conversion data. The number of clock cycles required for this method is usually dozens of CPU clocks or more.

[0007] 2) CPU interrupt: When interrupts are nested, non-ADC content is processed first, and the ADC data register is read last. Although this method can avoid excessive CPU resource occupation, the CPU takes a long time to process ADC data, and the newly converted data of the ADC will overflow or the original conversion data that has not been read will be overwritten. In addition, this method usually requires dozens of CPU clock cycles or more; like Figure 10As can be seen from the timing diagram of using the CPU to process ADC data shown, when there is no nested interruption and the CPU processes the ADC data immediately upon entering the interruption, although some irrelevant clock cycle overhead before reading the ADC data register is avoided, in some systems with slower frequencies, the time to enter the interruption will be longer. When the conversion speed of the ADC is faster than the processing speed of the CPU, there will still be situations where new data overflows or old data is overwritten, and the number of clock cycles required by this method is usually more than a dozen CPU clock cycles.

[0008] 3) DMA controller: As Figure 9 shown, if the DMA controller and the ADC controller are in different clock domains, cross-clock domain processing will take two DMA clock cycles, and reading the ADC data will take at least two cycles. If the ADC controller and the DMA controller are on two chips, in the case of chip co-packaging, the communication between the two chips will take a relatively long time. Whether it is a single-die chip or a multi-die chip, there will be a problem that the ADC data register does not store the latest conversion data.

[0009] Moreover, the DMA controller will have a relatively large area overhead, and the DMA controller may not be used in some chips.

[0010] Regardless of the design of the ADC controller or the way of reading the ADC data register above, there may be problems of new ADC conversion data overflowing or old ADC conversion data being overwritten. Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a controller circuit for solving the loss of ADC conversion data and preventing the loss of ADC conversion data.

[0012] To solve the above technical problem, the technical solution adopted by the present invention is: A controller circuit for solving the loss of ADC conversion data, comprising a RAM memory, an ADC controller, an ADC, an SRAM controller and at least one host. The ADC controller includes a group of RAM write interfaces and a group of data registers. The ADC controller is connected to the ADC to temporarily store the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a group of RAM write interfaces to write the conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory to read the conversion data generated by the ADC in the RAM memory. The ADC controller and the SRAM controller are connected to at least one host to interact with the host.

[0013] Further, the RAM memory uses a dual-port RAM memory. The dual-port RAM memory includes a first set of interfaces and a second set of interfaces. The dual-port RAM memory is connected to the SRAM controller through the first set of interfaces, and the dual-port RAM memory is connected to the ADC controller through the second set of interfaces.

[0014] Further, the transmission signals of a set of RAM write interfaces of the ADC controller include a read-write clock signal clk, a RAM chip select signal cs for read-write data, a write enable signal we for read-write data, an address addr of the read-write data register, and an input signal data_in for conversion data.

[0015] Further, the timing of the transmission signals of a set of RAM write interfaces of the ADC controller is as follows: Taking the start point of the first clock cycle after the ADC conversion data ends as the counting start point of this timing clock cycle; The first clock cycle: The ADC sends an EOC flag bit and conversion data to the ADC controller; The second clock cycle: The ADC controller sets the write enable signal we and the RAM chip select signal cs in the RAM read-write interface after collecting the EOC flag bit at the rising edge of the second clock cycle; The ADC controller stores the conversion data of the ADC into the data register of the ADC controller through the EOC flag bit; The ADC controller generates an EOC interrupt for the interrupt service program to use; The third clock cycle: The ADC controller writes the conversion data of the ADC in the data register into the RAM memory according to the address addr of the read-write data register and through the input signal data_in of the conversion data.

[0016] Further, the ADC controller further includes an address configuration register. The address addr of the read-write data register is pre-configured by the address configuration register or a part of the RAM memory space is separately allocated for the ADC controller to use. The address addr of the read-write data register is configured to be incremented or non-incremented through the address configuration register.

[0017] Further, when the number of hosts is one, the ADC controller and the SRAM controller are connected to the host and interact with the host. The ADC controller acts as a slave. When the conversion data of the ADC is needed, the SRAM controller reads the conversion data in the RAM memory. At this time, the RAM memory uses a dual-port RAM memory.

[0018] Further, when the number of hosts is multiple, multiple hosts, the ADC controller and the SRAM controller are connected to the host arbitration system for interaction. The ADC controller acts as a slave. When the conversion data of the ADC is needed, the SRAM controller reads the conversion data in the RAM memory.

[0019] Further, when there are multiple hosts, the ADC controller serves as one of the hosts. Multiple hosts, the ADC controller, the SRAM controller, the ADC, and the AHB MUX interface module are connected to the host arbitration system for interaction. The AHB MUX interface module is connected to the RAM memory. When the conversion data of the ADC needs to be used, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.

[0020] Compared with the prior art, the present invention has the following advantages and effects: 1. By adding read and write timing sequences to the ADC controller, the present invention can complete the data storage of the ADC within three clock cycles of the ADC controller. In the first clock cycle, the ADC sends the EOC (end of sequence) flag bit and the converted data to the ADC controller; in the second clock cycle, a write enable is sent to the RAM interface 2; in the third clock cycle, the converted data is written into the SRAM through the RAM interface 2 for storage to prevent the loss of the ADC conversion data. Since at least one sampling cycle + Tresolution is required for one ADC conversion cycle, the data storage cycle in the present invention is much smaller than its next data conversion, which can prevent the loss of new data or the overwrite of old data. 2. The ADC data storage structure of the present invention can reduce the demand for DMA by the ADC, enabling the DMA to release channels to process requests from other slaves. 3. The ADC data storage structure of the present invention can save more area with a smaller area overhead and improve its performance in a system with low demand for DMA. 4. Even in a system with high demand for DMA, the ADC data storage structure of the present invention can reduce the utilization rate of DMA by the ADC, enabling the DMA to release more clock cycles to process requests from other slaves. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of Embodiment 1 of a controller circuit for solving the loss of ADC conversion data according to the present invention.

[0022] Figure 2 is a schematic diagram of Embodiment 2 of a controller circuit for solving the loss of ADC conversion data according to the present invention.

[0023] Figure 3 is a schematic diagram of Embodiment 3 of a controller circuit for solving the loss of ADC conversion data according to the present invention.

[0024] Figure 4Schematic diagram of Embodiment 4 of a controller circuit for solving ADC conversion data loss according to the present invention.

[0025] Figure 5 Timing diagram of the ADC controller according to the present invention.

[0026] Figure 6 Schematic diagram of the dual-port RAM memory according to the present invention.

[0027] Figure 7 Read-write timing diagram of the dual-port RAM memory according to the present invention.

[0028] Figure 8 Schematic diagram of a circuit for using a CPU to process ADC data in the prior art.

[0029] Figure 9 Schematic diagram of a circuit for using DMA to process ADC data in the prior art.

[0030] Figure 10 Timing diagram of using a CPU to process ADC data in the prior art. Detailed implementation manner

[0031] In order to elaborate in detail the technical solutions adopted by the present invention to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. And, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0032] Embodiment 1. As Figure 1 shown, a controller circuit for solving ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller, and a host. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC to temporarily store the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces to write the conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory to read the conversion data generated by the ADC in the RAM memory. The ADC controller and the SRAM controller are connected to the host to interact with the host.

[0033] Among them, the RAM memory multiplexes the system RAM, and the system RAM uses a dual-port RAM memory, as Figure 6As shown in the figure, the dual-port RAM memory includes a first set of interfaces and a second set of interfaces. The dual-port RAM memory is connected to the SRAM controller through the first set of interfaces, and the dual-port RAM memory is connected to the ADC controller through the second set of interfaces. As Figure 7 Shown is the read / write timing diagram of the dual-port RAM.

[0034] The transmission signals of a set of RAM write interfaces of the ADC controller include the read / write clock signal clk, the RAM chip select signal cs for read / write data, the write enable signal we for read / write data, the address addr of the read / write data register, and the input signal data_in of the conversion data.

[0035] As Figure 5 Shown, the timing of the transmission signals of a set of RAM write interfaces of the ADC controller is as follows: Taking the start point of the first clock cycle after the end of the ADC conversion data as the counting start point of this timing clock cycle; The first clock cycle: The ADC sends the EOC flag bit and the conversion data to the ADC controller; The second clock cycle: The ADC controller sets the write enable signal we and the RAM chip select signal cs in the RAM read / write interface after collecting the EOC flag bit at the rising edge of the second clock cycle; The ADC controller stores the conversion data of the ADC into the data register of the ADC controller through the EOC flag bit; The ADC controller generates an EOC interrupt for the interrupt service program to use; The third clock cycle: The ADC controller writes the conversion data of the ADC in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.

[0036] When the ADC controller, as a slave, needs to use the conversion data of the ADC, the SRAM controller reads the conversion data in the RAM memory.

[0037] The ADC controller also includes an address configuration register. The address addr of the read / write data register is pre-configured by the address configuration register or a part of the RAM memory space is separately allocated for the ADC controller to use. The address addr of the read / write data register is configured to be incremented or not incremented through the address configuration register. The addresses addra and addrb of the two sets of interfaces of the dual-port RAM can be determined by the system for the space size of each part.

[0038] Embodiment 2. As Figure 2As shown in the figure, a controller circuit for solving the problem of ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller, multiple hosts, and a host arbitration system. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC to temporarily store the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces to write the conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory to read the conversion data generated by the ADC in the RAM memory. The multiple hosts, the ADC controller, and the SRAM controller are connected to the host arbitration system for interaction.

[0039] Among them, the RAM memory multiplexes the system RAM, and the system RAM uses a dual-port RAM memory. As Figure 6 shown in the figure, the dual-port RAM memory includes a first set of interfaces and a second set of interfaces. The dual-port RAM memory is connected to the SRAM controller through the first set of interfaces, and the dual-port RAM memory is connected to the ADC controller through the second set of interfaces.

[0040] The transmission signals of a set of RAM write interfaces of the ADC controller include a read / write clock signal clk, a RAM chip select signal cs for reading / writing data, a write enable signal we for reading / writing data, an address addr for reading / writing data registers, and an input signal data_in for conversion data.

[0041] As Figure 5 shown in the figure, the timing of the transmission signals of a set of RAM write interfaces of the ADC controller is as follows: Taking the start point of the first clock cycle after the end of the ADC conversion data as the counting start point of this timing clock cycle; The first clock cycle: The ADC sends an EOC flag bit and conversion data to the ADC controller. The second clock cycle: The ADC controller sets the write enable signal we and the RAM chip select signal cs in the RAM read / write interface after collecting the EOC flag bit at the rising edge of the second clock cycle; The ADC controller stores the conversion data of the ADC into the data register of the ADC controller through the EOC flag bit; The ADC controller generates an EOC interrupt for use by the interrupt service program. The third clock cycle: The ADC controller writes the conversion data of the ADC in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.

[0042] When the ADC controller, as a slave, needs to use the conversion data of the ADC, the SRAM controller reads the conversion data in the RAM memory.

[0043] The ADC controller also includes an address configuration register. The address addr of the read / write data register is pre-configured by the address configuration register or a part of the RAM memory space is separately allocated for the ADC controller to use. The address addr of the read / write data register is configured by the address configuration register to be incremented or not incremented.

[0044] Embodiment 3. As Figure 3 shown, a controller circuit for solving the problem of ADC conversion data loss includes a RAM memory, an ADC controller, an ADC, an SRAM controller, and multiple hosts. The ADC controller includes a set of RAM write interfaces and a set of data registers. The ADC controller is connected to the ADC to temporarily store the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory through a set of RAM write interfaces to write the ADC-generated conversion data temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory to read the ADC-generated conversion data in the RAM memory. The multiple hosts, the ADC controller, and the SRAM controller are connected to the host arbitration system for interaction.

[0045] Among them, the RAM memory is separated from the system RAM, that is, a small part of the storage space is specially allocated for the ADC controller. At this time, the SRAM is a single-port SRAM, and the base address of its interface signal addr is a fixed value. There is at least one SRAM in the system for storing ADC private conversion data. The system RAM is connected to the SRAM controller, and the RAM memory is connected to the ADC controller.

[0046] In this embodiment, a set of RAM write interfaces of the ADC controller also needs to have a read function. At this time, the transmission signals of a set of RAM read / write interfaces of the ADC controller include a read / write clock signal clk, a RAM chip select signal cs for read / write data, a write enable signal we for read / write data, an address addr of the read / write data register, an input signal data_in of the conversion data, and a data output signal data_out.

[0047] As Figure 5 shown, the timing of the transmission signals of a set of RAM write interfaces of the ADC controller is as follows: Taking the start point of the first clock cycle after the end of the ADC conversion data as the counting start point of this timing clock cycle; The first clock cycle: The ADC sends an EOC flag bit and conversion data to the ADC controller; The second clock cycle: At the rising edge of the second clock cycle, the ADC controller sets the write enable signal we and the RAM chip select signal cs for reading and writing data in the RAM read-write interface after detecting the EOC flag bit; the ADC controller stores the conversion data of the ADC into the data register of the ADC controller through the EOC flag bit; the ADC controller generates an EOC interrupt for use by the interrupt service routine. The third clock cycle: The ADC controller writes the conversion data of the ADC in the data register into the RAM memory according to the address addr of the read-write data register and through the input signal data_in of the conversion data.

[0048] As a slave, when the ADC controller needs to use the conversion data of the ADC, it reads the conversion data from the RAM memory.

[0049] Embodiment 4. As Figure 4 shown, a controller circuit for solving the loss of ADC conversion data includes a RAM memory, an ADC controller, an ADC, an SRAM controller, multiple hosts, and an AHB MUX interface module. The AHB MUX interface module includes a set of RAM read-write interfaces, and the ADC controller includes a set of data registers. The multiple hosts, the ADC controller, the SRAM controller, the ADC, and the AHB MUX interface module are connected to the host arbitration system for interaction. The SRAM controller is connected to the AHB MUX interface module, and the AHB MUX interface module is connected to the RAM memory through a set of RAM read-write interfaces. The conversion data generated by the ADC is temporarily stored in the data register of the ADC controller through the host arbitration system. The ADC controller is connected to the RAM memory through the host arbitration system and a set of RAM read-write interfaces of the AHB MUX interface module to write the conversion data generated by the ADC temporarily stored in the data register into the RAM memory.

[0050] Among them, the RAM memory multiplexes the system RAM, and at this time the system RAM is a single-port RAM. The interface signals of the SRAM need to process the read-write signals from the ADC controller and the read-write signals from the SRAM controller.

[0051] The transmission signals of a set of RAM read-write interfaces of the AHB MUX interface module include the read-write clock signal clk, the RAM chip select signal cs for reading and writing data, the write enable signal we for reading and writing data, the address addr of the read-write data register, the input signal data_in of the conversion data, and the data output signal data_out.

[0052] As Figure 5 shown, the timing of the transmission signals of a set of RAM write interfaces of the ADC controller is as follows: Take the start point of the first clock cycle after the end of ADC conversion data as the counting start point of this timing clock cycle; The first clock cycle: The ADC sends the EOC flag bit and the conversion data to the ADC controller; The second clock cycle: The ADC controller sets the write enable signal we and the RAM chip select signal cs for reading and writing data in the RAM read-write interface when it samples the EOC flag bit at the rising edge of the second clock cycle; The ADC controller stores the conversion data of the ADC into the data register of the ADC controller through the EOC flag bit; The ADC controller generates an EOC interrupt for the interrupt service program to use; The third clock cycle: The ADC controller writes the conversion data of the ADC in the data register into the RAM memory according to the address addr of the read-write data register and through the input signal data_in of the conversion data.

[0053] The ADC controller is one of the hosts. Multiple hosts, the ADC controller, and the SRAM controller are connected to the host arbitration system for interaction. When the conversion data of the ADC is needed, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.

[0054] By adding the read-write timing of the RAM interface in the ADC controller, the present invention can complete the data storage of the ADC once within three clock cycles of the ADC controller. In the first clock cycle, the ADC sends the EOC (end of sequence) flag bit and the converted data to the ADC controller; In the second clock cycle, the write enable is sent to the RAM interface 2; In the third clock cycle, the conversion data is written into the SRAM through the RAM interface 2 to prevent the loss of the conversion data of the ADC; As Figure 5 shown, since at least one sampling cycle + Tresolution is required for one ADC conversion cycle, the data storage cycle in the present invention is much smaller than its next data conversion, which can prevent the loss of new data or the overwriting of old data; The ADC data storage structure of the present invention can reduce the demand of the ADC for DMA, enabling the DMA to release the channel to process the requests of other slaves; The ADC data storage structure of the present invention can save more area with a smaller area overhead and improve its performance in a system with little demand for DMA; Even in a system with a large demand for DMA, the ADC data storage structure of the present invention can reduce the utilization rate of the ADC for DMA, enabling the DMA to release more clock cycles to process the requests of other slaves.

[0055] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the technical content disclosed above within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent replacement, and improvement made to the above embodiments according to the technical essence of the present invention within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A controller circuit for solving ADC conversion data loss, characterized in that: The invention comprises a RAM memory, an ADC controller, an ADC, an SRAM controller and at least one host. The ADC controller comprises a group of RAM write interfaces and a group of data registers. The ADC controller is connected to the ADC for temporarily storing the conversion data generated by the ADC in the data registers. The ADC controller is connected to the RAM memory via a group of RAM write interfaces for writing the conversion data generated by the ADC temporarily stored in the data registers into the RAM memory. The SRAM controller is connected to the RAM memory for reading the conversion data generated by the ADC in the RAM memory. The ADC controller and the SRAM controller are connected to at least one host for interacting with the host.

2. A controller circuit for solving ADC conversion data loss according to claim 1, characterized in that: The RAM memory adopts a dual-port RAM memory, which includes a first group of interfaces and a second group of interfaces. The dual-port RAM memory is connected to the SRAM controller via the first group of interfaces, and the dual-port RAM memory is connected to the ADC controller via the second group of interfaces.

3. The controller circuit for solving ADC conversion data loss according to claim 1, characterized in that: The transmission signals of a set of RAM write interfaces of the ADC controller include a read / write clock signal clk, a RAM chip select signal cs for read / write data, a write enable signal we for read / write data, an address addr of a read / write data register, and an input signal data_in for conversion data.

4. The controller circuit for solving ADC conversion data loss according to claim 3, characterized in that: The timing sequence of the transmission signal of a set of RAM write interfaces of the ADC controller is: The starting point of the first clock cycle after the ADC converts the data is taken as the counting starting point of this timing clock cycle; First clock cycle: ADC sends the EOC flag and conversion data to the ADC controller; The second clock cycle: the ADC controller collects the EOC flag bit at the rising edge of the second clock cycle and sets the write enable signal we in the RAM read / write interface and the RAM chip select signal cs for reading and writing data; the ADC controller stores the ADC conversion data into the data register of the ADC controller through the EOC flag bit; the ADC controller generates an EOC interrupt for use by the interrupt service program; The third clock cycle: The ADC controller writes the ADC conversion data in the data register into the RAM memory according to the address addr of the read / write data register and through the input signal data_in of the conversion data.

5. The controller circuit for solving ADC conversion data loss according to claim 3, characterized in that: The ADC controller also includes an address configuration register. The address addr of the read / write data register is configured in advance by the address configuration register or a portion of the RAM memory space is separately allocated for use by the ADC controller. The address addr of the read / write data register is configured to be incremented or not incremented by the address configuration register.

6. The controller circuit for solving ADC conversion data loss according to claim 1, characterized in that: When there is only one host, the ADC controller and the SRAM controller are connected to the host and interact with the host. The ADC controller acts as a slave. When the ADC conversion data needs to be used, the SRAM controller reads the conversion data in the RAM memory. At this time, the RAM memory uses a dual-port RAM memory.

7. The controller circuit for solving ADC conversion data loss according to claim 1, characterized in that: When there are multiple hosts, the multiple hosts, ADC controllers and SRAM controllers are connected to the host arbitration system for interaction. The ADC controller acts as a slave and when the ADC conversion data needs to be used, the SRAM controller reads the conversion data in the RAM memory.

8. The controller circuit for solving ADC conversion data loss according to claim 7, characterized in that: When there are multiple hosts, the ADC controller serves as one of the hosts, and the multiple hosts, the ADC controller, the SRAM controller, the ADC and the AHB MUX interface module are connected to the host arbitration system for interaction. The AHB MUX interface module is connected to the RAM memory. When the ADC conversion data is needed, the SRAM controller reads the conversion data in the RAM memory, or other hosts except the ADC controller read the conversion data in the RAM memory.

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