Configuration system and configuration method for storage chip test data

Abstract

The present invention provides a system and method for configuring memory chip test data. The configuration system includes: a control unit for controlling at least one functional module to operate, writing initial test data to a memory chip, and monitoring functional nodes in the operating functional module; the initial test data includes multiple test instructions; the control unit counts the number of times each functional node in each operating functional module executes the test instructions; each time a functional node in a functional module executes a test instruction, the number of times the functional node executes the test instruction increases by one; and the control unit adjusts the number of test instructions in the initial test data based on a preset threshold interval and the number of times each functional node operates. When the number of times each functional node operates falls within the threshold interval, the adjusted initial test data is used to generate target test data. The present invention can reduce memory chip testing time and testing costs.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a configuration system and method for storing chip test data. Background Art

[0002] With the widespread use of memory chips in electronic products such as televisions, set-top boxes, tablets, or mobile phones, the performance and reliability requirements for memory chips are becoming increasingly higher. The most important thing is to ensure that the stored data is stable and reliable. Stress testing of memory chips is a verification test that must be performed before memory chips leave the factory. In the existing technology, storage particles are subjected to black box testing, and the test coverage of memory chips is improved by adding test scripts. However, the method of adding test scripts has the problem of long testing time and low verification efficiency for increasing test coverage. Therefore, how to improve the verification efficiency of memory chips and save verification time has become a problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention provides a configuration system and method for memory chip test data, so as to solve the problems in the prior art of long memory chip test time and low verification efficiency for increasing test coverage.

[0004] The present invention provides a configuration system for storing chip test data, comprising:

[0005] A chip test socket for mounting a memory chip; the memory chip includes a plurality of functional modules, each of which corresponds to a plurality of functional nodes, each of which represents a minimum execution unit for executing a test instruction;

[0006] a control unit, configured to control at least one of the functional modules to operate, write initial test data to the memory chip, and monitor the functional nodes in the operating functional module; the initial test data includes a plurality of test instructions;

[0007] The control unit counts the number of times each functional node in each working functional module executes the test instruction; each time a functional node of the functional module executes a test instruction, the number of times the functional node executes the test instruction is increased by one;

[0008] The control unit adjusts the number of test instructions in the initial test data according to a preset threshold interval and the number of working times corresponding to each functional node, so that when the number of working times corresponding to each functional node is within the threshold interval, the adjusted test data is generated into target test data.

[0009] In one embodiment of the present invention, the control unit is configured to reduce the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is greater than the threshold interval;

[0010] The control unit is configured to increase the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is less than the threshold interval.

[0011] In one embodiment of the present invention, the control unit is used to count the test paths of executing the test instructions, where the test paths are represented as transmission paths between functional nodes of different functional modules corresponding to when executing the test instructions;

[0012] The control unit is used to determine whether the test paths corresponding to all test instructions are repeated on the functional node when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and if repeated, retain a test instruction corresponding to the repeated test path in the initial test data.

[0013] In one embodiment of the present invention, the control unit is used to determine whether the test path of the test instruction corresponding to the functional node intersects with other test paths when the number of working times corresponding to the functional node is not within the threshold range, and if they do not intersect, increase or decrease the number of test instructions corresponding to the functional node in the initial test data.

[0014] In one embodiment of the present invention, the control unit is used to determine whether the test path of the test instruction corresponding to the functional node is repeated with part of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and when repeated, reduce the number of test instructions corresponding to the repeated test path on the functional node in the initial test data.

[0015] In one embodiment of the present invention, the control unit is used to determine whether part of the test path of the test instruction corresponding to the functional node is repeated with part of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and if repeated, retain the test instructions corresponding to the partially repeated test path on the functional node in the initial test data.

[0016] In one embodiment of the present invention, the control unit is used to establish a counting table, and the counting table is used to count the test instructions and working times corresponding to all functional nodes in each working functional module.

[0017] In one embodiment of the present invention, the functional modules include at least a command parsing and scheduling module, a main controller, a firmware logic module, a cache management module, an error correction encoding / decoding module and a flash memory physical layer control module.

[0018] The present invention also provides a system for storing chip test data, comprising:

[0019] A chip test socket for mounting a memory chip; the memory chip includes a plurality of functional modules, each of which corresponds to a plurality of functional nodes, each of which represents a minimum execution unit for executing a test instruction;

[0020] A control unit is used to control at least one of the functional modules to work and write target test data to the storage chip, so that each functional node in each working functional module executes a test instruction; each time a functional node of the functional module executes a test instruction, its working times are increased by one.

[0021] The present invention also provides a configuration method for storage chip test data, comprising:

[0022] Installing a memory chip on a chip test socket; the memory chip includes a plurality of functional modules, each of the functional modules corresponds to a plurality of functional nodes, and the functional nodes represent the minimum execution units for executing test instructions;

[0023] Controlling at least one of the functional modules to operate, writing initial test data to the memory chip, and monitoring the functional nodes in the operating functional module; the initial test data includes a variety of test instructions;

[0024] Counting the number of times each functional node in each working functional module executes the test instruction; each time a functional node of the functional module executes the test instruction, the number of times the functional node executes the test instruction is increased by one;

[0025] According to the preset threshold interval and the number of working times corresponding to each functional node, the number of test instructions in the initial test data is adjusted so that when the number of working times corresponding to each functional node is within the threshold interval, the adjusted initial test data is used to generate target test data.

[0026] Beneficial effects of the present invention: A configuration system and configuration method for storage chip test data of the present invention can reduce the duplication of test data, increase the coverage of test data, and reduce storage chip test time and test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1This is a structural block diagram of a system for configuring storage chip test data provided by one embodiment of the present invention.

[0029] Figure 2 This is a structural block diagram of a memory chip provided by one embodiment of the present invention.

[0030] Figure 3 A schematic diagram of obtaining target test data from initial test data provided by an embodiment of the present invention.

[0031] Figure 4 A schematic diagram of a transmission path between functional nodes of different functional modules corresponding to a test instruction provided in an embodiment of the present invention.

[0032] Figure 5 A schematic diagram illustrating the corresponding working times of functional nodes of a functional module provided in one embodiment of the present invention.

[0033] Figure 6 A schematic diagram of the steps of a method for configuring memory chip test data provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0035] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0036] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0037] See also Figures 1 to 6This invention proposes a system and method for configuring storage chip test data. These methods can be applied to storage devices such as embedded multimedia cards (EMMCs), solid-state drives (SSDs), and universal flash storage (UFS). This invention reduces test data duplication, increases test data coverage, and reduces storage chip testing time and costs. A detailed description of this method is provided below using specific examples.

[0038] See also Figure 1 In one embodiment of the present invention, a configuration system for storing chip test data may include a control unit 101, a chip test socket 102, a power supply unit 103, a serial port unit 104, a hardware trigger unit 105, a storage unit 106, a memory unit 107 and a peripheral interface unit 108.

[0039] Specifically, the power supply unit 103 supplies power to the control unit 101 and the memory chip on the chip test socket 102. The serial port unit 104, hardware trigger unit 105, storage unit 106, memory unit 107 and peripheral interface unit 108 can perform transmission and storage operations of related data.

[0040] Specifically, the chip test socket 102 is used to install a memory chip, such as Figure 2 As shown, the memory chip includes multiple functional modules, each of which corresponds to multiple function nodes. A function node represents the smallest testable functional unit within the module, and can also be understood as the smallest execution unit for executing a test instruction. The function nodes within a functional module execute test instructions and process test sub-data. For example, the function node CMD_M processes read commands, while the function node CMD_N processes write commands.

[0041] Specifically, control unit 101 is the computing and control core of the configuration system for storage chip test data. It controls the operation of the combined functional modules of the storage chips on chip test socket 102. A combined functional module represents the simultaneous operation of any number of functional modules. Control unit 101 can write initial test data to the storage chips while the combined functional modules are operating, thereby testing the functional nodes within the combined functional modules.

[0042] The initial test data may include multiple test instructions and multiple test sub-data. In storage devices, test instructions refer to commands that control storage device operations and may involve operations such as storage device initialization, basic control, single-block / multi-block reads, single-block / multi-block writes, and application-specific commands. Test instructions can transfer test sub-data to different functional modules for testing. In other words, the functional nodes of the functional modules execute the test instructions and process the test sub-data.

[0043] During the testing phase of the memory chip, each functional node in the combined functional module needs to be verified and tested, and in order to ensure that the corresponding test function of each functional node is normal, each functional node needs to be verified and tested multiple times. In this embodiment, the threshold interval is used as the number of verifications required for each functional node.

[0044] The control unit 101 can count the test instructions and operation times corresponding to each functional node in the combined functional module. Each time a functional node in the functional module executes a test instruction, its operation time increments by one. Based on a preset threshold interval and the operation times corresponding to each functional node, the control unit 101 can adjust the number of test instructions in the initial test data to generate adjusted test data.

[0045] Afterwards, the control unit 101 writes the adjusted test data into the memory chip for testing, and generates target test data from the adjusted test data when the number of operations corresponding to each functional node is within a threshold range.

[0046] Once the target test data corresponding to the combined functional module is obtained, the target test data can be written to the memory chip when the memory chip of the same model is in the operating state of the combined functional module, thereby enabling the use of each functional node in the combined functional module. The target test data can ensure that each functional node in the combined functional module is verified and tested, and can also ensure that each functional node undergoes multiple verification tests to ensure the normal use of each functional node.

[0047] See also Figure 1 In one embodiment of the present invention, control unit 101 controls the combined functional module of a memory chip to operate and writes initial test data to the memory chip to test the functional nodes in the combined functional module. Control unit 101 then adjusts the number of test instructions in the initial test data based on a preset threshold interval and the number of operations corresponding to each functional node, thereby generating adjusted test data.

[0048] Specifically, the control unit 101 is configured to reduce the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is greater than the maximum value of the threshold interval.

[0049] The control unit 101 is configured to increase the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is less than a minimum value of the threshold interval.

[0050] like Figure 2 and Figure 3 As shown, the storage chip may include a command parsing and scheduling module 201, a main controller 202, a firmware logic module 203, a cache management module 205, an error correction coding / decoding module 204, a flash memory physical layer control module 206, a power module 207, a serial port module 208, a read-only memory 209, a random access memory 210, a coverage statistics module 211, a direct memory access buffer module 212, a data mapping module 213 and a flash memory 214.

[0051] Specifically, the basic modules of the memory chip may include a serial port module 208 , a power module 207 , a read-only memory 209 , and a random access memory 210 . The power module 207 supplies power to the main controller 202 .

[0052] Specifically, the core modules of the storage chip may include a command parsing and scheduling module 201, a main controller 202, a firmware logic module 203, a cache management module 205, an error correction encoding / decoding module 204, a flash memory physical layer control module 206, a coverage statistics module 211, a direct memory access buffer module 212, a data mapping module 213 and a flash memory 214.

[0053] The command parsing and scheduling module (CMD) 201 is a front-end standard protocol interface. The central processing unit (CPU) 202 is responsible for the logical processing functions of the memory chip hardware. The firmware logic (FW) module 203 is responsible for the computational logic and application functions of the entire memory chip firmware. The low-density parity check (LDPC) error correction / decoding module 204 is used to correct data in the direct memory access buffer (DMA) module 212. The buffer management unit (BMU) 205 manages the usage of each buffer. The NAND flash controller (NFC) 206 is used to control and manage commands for the flash memory 214. The coverage statistics module 211 is used to automatically count the test instructions and operation times corresponding to the functional nodes of each functional module during the verification test of the memory chip when the control unit 101 performs verification testing on the memory chip. The data mapping table is the mapping relationship between the logical block addresses and physical block addresses corresponding to the data in the flash memory 214.

[0054] like Figure 3 As shown, the left side corresponds to the initial test data, which includes test instruction 1, test instruction 2, test instruction 3, ..., test instruction n. The control unit 101 controls the memory chip to be in the operating state of the combined functional module and writes the initial test data to the memory chip to test the functional nodes in the combined functional module.

[0055] Secondly, the control unit 101 counts the test instructions and working times corresponding to each functional node in the combined functional module, and adjusts the number of test instructions that are not in the threshold interval in the initial test data according to the preset threshold interval and the working times corresponding to each functional node to obtain adjusted test data.

[0056] Afterwards, the adjusted test data is written into the memory chip for testing, and when the number of operations corresponding to each functional node is within the threshold range, the adjusted test data is used to generate target test data. Figure 3 The right side data of the target test data includes test instruction 1, test instruction na, test instruction nb, test instruction nc, test instruction nd, test instruction ne, ..., test instruction nx.

[0057] See also Figure 1 、 Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the control unit 101 is used to count the test paths of executing the test instructions, and the test paths are represented as transmission paths between functional nodes of different functional modules corresponding to when executing the test instructions.

[0058] like Figure 4 As shown, the test path may be a transmission path between functional nodes of any functional modules in the combined functional module, and the actual transmission path shall prevail.

[0059] For example, the test path may be CMD Function1-CPU Function1-BMU Function1-FWFunction1-LDPC Function1-NFC Function1.

[0060] For example, the test path may also be CMD Function5-CPU Function5-BMU Function5-FWFunction5-LDPC Function5-NFC Function5.

[0061] For example, the test path may also be CMD Function1-CPU Function2-BMU Function3-FWFunction4-LDPC Function5-NFC Function6.

[0062] Of course, the test path can also be CMD Function1-CPU Function2-BMU Function3, or CMD Function1-CPU Function1-BMU Function1-FW Function1.

[0063] The control unit 101 is used to determine whether the test paths corresponding to all test instructions are repeated on the functional node when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval. If repeated, in the initial test data, one test instruction corresponding to the repeated test path is retained, and other test instructions corresponding to the repeated test path are deleted.

[0064] Specifically, for any functional node in the combined functional module, the control unit 101 is used to delete the other test instructions corresponding to the repeated test path in the initial test data when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, if the test path of one test instruction is repeated (the same) as the test path of another test instruction.

[0065] For example, if the test path of one test instruction is CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function5-NFC Function6, and the test path of another test instruction is also CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function5-NFCFunction6, then the test paths of the two test instructions are repeated (the same).

[0066] That is, both test instructions perform verification tests on the same functional node. If the number of work times corresponding to the functional node is greater than the threshold range, it indicates that the verification times of the functional node are too many, wasting test resources. Therefore, the test instructions corresponding to the repeated test path can be deleted.

[0067] In addition, the control unit 101 is configured to increase the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is less than the minimum value of the threshold interval.

[0068] See also Figure 1 、 Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the control unit 101 is used to determine whether the test path of the test instruction corresponding to the functional node intersects with other test paths when the number of working times corresponding to the functional node is not within the threshold range, and if they do not intersect, increase or decrease the number of test instructions corresponding to the functional node in the initial test data.

[0069] Specifically, such as Figure 4 As shown, for any function node in the combined function module, when the number of operations corresponding to the function node is not within the threshold range, that is, when the number of operations corresponding to the function node is greater than or less than the threshold range. If the test path of the test instruction corresponding to the function node does not intersect with the test paths on other function nodes, the number of test instructions corresponding to the function node in the initial test data is increased or decreased.

[0070] For example, if the test path for the test instruction corresponding to the function node is CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function5-NFC Function6, and the test paths on other function nodes are, for example, CMD Function2-CPU Function3-BMU Function4-FW Function5-LDPCFunction6-NFC Function7, the test path for the test instruction corresponding to the function node does not intersect with the test paths on other function nodes.

[0071] That is, there is no mutual influence between the test instructions corresponding to the functional node and the test instructions corresponding to other functional nodes, so increasing or decreasing the test instructions corresponding to the functional node will not affect the verification test of other functional nodes.

[0072] Therefore, the control unit 101 is configured to increase or decrease the number of test instructions corresponding to the functional node when the number of operations corresponding to the functional node is not within the threshold interval. For example, the control unit 101 is configured to decrease the number of test instructions corresponding to the functional node when the number of operations corresponding to the functional node is greater than the threshold interval. For example, the control unit 101 is configured to increase the number of test instructions corresponding to the functional node when the number of operations corresponding to the functional node is less than the threshold interval.

[0073] See also Figure 1 、 Figure 2 and Figure 4As shown, in one embodiment of the present invention, the control unit 101 is used to determine whether the test path of the test instruction corresponding to the functional node is repeated with part of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and when repeated, reduce the number of test instructions corresponding to the repeated test path on the functional node in the initial test data.

[0074] Specifically, such as Figure 4 As shown, for any functional node in the combined functional module, the control unit 101 is used to reduce the number of test instructions corresponding to the repeated test paths on the functional node in the initial test data when the number of working times corresponding to the functional node is greater than the threshold interval, if the test path of the test instruction corresponding to the functional node is repeated with part of the test paths in other test paths.

[0075] For example, if the test path corresponding to the test instruction of the function node is CMD Function1-CPU Function2-BMU Function3-FW Function4, and other test paths are, for example, CMD Function1-CPU Function2-BMUFunction3-FW Function4-LDPC Function5-NFC Function6, the test path corresponding to the test instruction of the function node is a part of the other test paths.

[0076] That is, the test instructions corresponding to this functional node affect other test instructions. Therefore, increasing or decreasing the test instructions corresponding to this functional node will affect the verification test of other functional nodes. Similarly, increasing or decreasing the test instructions corresponding to other functional nodes will affect the verification test of this functional node.

[0077] Therefore, when the number of operations corresponding to a functional node exceeds a threshold, the control unit 101 is configured to indicate that the functional node has been verified too many times, wasting test resources. The control unit 101 may reduce the number of test instructions corresponding to the repeated test paths on the functional node. Because the test instructions corresponding to the repeated test paths on other functional nodes remain unchanged, the functional node can be verified sufficiently many times without impacting the verification tests of other functional nodes.

[0078] In contrast to the above process, if the number of test instructions corresponding to repeated test paths on other functional nodes is reduced, since the test instructions corresponding to repeated test paths on the functional node have not changed, although it can ensure that the number of verifications of the functional node is sufficient, it will reduce the verification tests of other functional nodes, which is not reasonable.

[0079] See also Figure 1 、 Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the control unit 101 is used to determine whether a portion of the test path corresponding to the test instruction of the functional node is repeated with a portion of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and when repeated, retain the test instructions corresponding to the partially repeated test path on the functional node in the initial test data.

[0080] Specifically, such as Figure 4 As shown, for any functional node in the combined functional module, the control unit 101 is used to maintain the number of test instructions corresponding to the partially repeated test paths on the functional node in the initial test data when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, if part of the test path of the test instruction corresponding to the functional node is repeated with part of the test path in other test paths.

[0081] For example, if the test path for the test instruction corresponding to the function node is CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function9-NFC Function10, and other test paths are, for example, CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function5-NFCFunction6, part of the test path for the test instruction corresponding to the function node, CMD Function1-CPU Function2-BMU Function3-FW Function4, overlaps with part of the test path in other test paths, CMD Function1-CPU Function2-BMU Function3-FW Function4.

[0082] For another example, if the test path for the test instruction corresponding to the function node is CMD Function3-CPU Function2-BMU Function1-FW Function8-LDPC Function9-NFC Function10, and other test paths are, for example, CMD Function1-CPU Function2-BMU Function3-FW Function4-LDPC Function5-NFC Function6, part of the test path CPU Function2 for the test instruction corresponding to the function node overlaps with part of the test path CPU Function2 in other test paths.

[0083] That is, the test instructions corresponding to this functional node affect other test instructions. Therefore, increasing or decreasing the test instructions corresponding to this functional node will affect the verification test of other functional nodes. Similarly, increasing or decreasing the test instructions corresponding to other functional nodes will affect the verification test of this functional node.

[0084] Therefore, when the number of operations corresponding to a functional node exceeds a threshold, the control unit 101 indicates that the functional node has been verified too many times, wasting test resources. However, since part of the test path corresponding to the test instruction of the functional node overlaps with part of the test paths in other test paths, the remaining test path corresponding to the test instruction of the functional node is different from the remaining test paths in other test paths.

[0085] If the number of test instructions corresponding to the partially repeated test paths on the functional node is reduced, or the number of test instructions corresponding to other test paths is reduced, it will affect the verification test of the functional node and the verification test of other functional nodes. Therefore, in order to ensure that the verification times of this functional node and other functional nodes are sufficient, it is necessary to maintain the number of test instructions corresponding to the partially repeated test paths on the functional node.

[0086] See also Figure 1 、 Figure 2 In one embodiment of the present invention, the control unit 101 is used to establish a counting table, which is used to count the test instructions and working times corresponding to all functional nodes in the combined functional module, and when the working times corresponding to the functional node are not within the threshold range, the working times corresponding to the functional node are marked.

[0087] Table 1. Working times corresponding to the function nodes of the combined function module

[0088]

[0089] As can be seen from the above analysis, the core modules of a memory chip may include a command parsing and scheduling module (CMD) 201, a main controller (CPU) 202, a firmware logic module (FW) 203, a cache management module (BMU) 205, an error correction coding / decoding module (LDPC) 204, and a flash physical layer control module (NFC) 206. As shown in Table 1, statistics are collected for the operation times corresponding to the functional nodes in the aforementioned core (functional) modules, i.e., the combined functional modules, to intuitively understand the operation times corresponding to each functional node. When the operation times corresponding to a functional node are outside the threshold range, the operation times corresponding to the functional node are marked. This facilitates adjusting the corresponding number of test instructions in the initial test data to obtain the target test data.

[0090] See also Figure 1 、 Figure 2 、 Figure 4 、 Figure 5 As shown in Table 1, in one embodiment of the present invention, the command parsing and dispatching module (CMD) 201 is taken as an example for analysis. The function nodes of the CMD function module can be subdivided into CMD_Function1 to CMD_Functionx. Assume that there are 28 test instructions for testing. Figure 5 It can be seen that the highest number of verifications is CMD_Function5, with CMD_Count5 corresponding to 28 times, and the least is CMD_Function3, with CMD_Count3 corresponding to 0 times. This distribution of test coverage is unreasonable.

[0091] In the initial test data, it is necessary to adjust the number of corresponding test instructions to increase the coverage of function points with low coverage, such as adding CMD_Function2, Function3, Function6, and other function nodes with less than 10 verification times. It is also necessary to reduce the number of function points with high duplication, such as reducing CMD_Function5, CMD_Function8, CMD_Functionx, and other function nodes with more than 15 verification times. By reducing the total number of 28 test instructions and increasing the test coverage of function nodes with low test coverage, the corresponding working times of each function node are ultimately reduced to 10 to 15 times, thereby improving the overall test efficiency of the memory chip and making the test coverage more average. In combination with the content above, the threshold interval can be set to 10 to 15 times.

[0092] See also Figure 1 In one embodiment of the present invention, a system for using memory chip test data is provided. A chip test socket 102 is used to mount a memory chip. The memory chip includes multiple functional modules, each of which corresponds to multiple functional nodes. A functional node represents the minimum test function unit of the functional module.

[0093] The control unit 101 is used to control at least one functional module to operate and write target test data to the memory chip, so that each functional node in each operating functional module executes the test instruction. Each time a functional node of a functional module executes a test instruction, its operating count increases by one.

[0094] See also Figure 6 In one embodiment of the present invention, a configuration method for storing chip test data is also proposed, which includes the following steps.

[0095] Step S10: Install the memory chip on the chip test socket; the memory chip includes multiple functional modules, each functional module corresponds to multiple functional nodes, and the functional node represents the minimum execution unit for executing the test instruction.

[0096] Step S20: Control at least one functional module to operate, write initial test data to the memory chip, and monitor the functional nodes in the operating functional module; the initial test data includes a variety of test instructions.

[0097] Step S30: Count the number of times each functional node in each working functional module executes the test instruction; each time a functional node of the functional module executes a test instruction, the number of times the functional node executes the test instruction is increased by one.

[0098] Step S40: According to the preset threshold interval and the number of working times corresponding to each functional node, the number of test instructions in the initial test data is adjusted so that when the number of working times corresponding to each functional node is within the threshold interval, the adjusted initial test data is used to generate target test data.

[0099] It can be seen that by adjusting the number of test instructions in the initial test data, such as removing duplicate test instructions, ensuring coverage of the functional nodes of the combined functional module, and different test instructions have minimum correlation, the target test data can be obtained, which has the characteristics of reducing test costs, improving test efficiency, and improving test integrity.

[0100] In summary, the present invention discloses a system and method for configuring memory chip test data, which can reduce test data duplication, increase test data coverage, and reduce memory chip testing time and costs. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial application value.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A configuration system for storing chip test data, characterized in that: include: A chip test socket for mounting a memory chip; the memory chip includes a plurality of functional modules, each of which corresponds to a plurality of functional nodes, each of which represents a minimum execution unit for executing a test instruction; a control unit, configured to control at least one of the functional modules to operate, write initial test data to the memory chip, and monitor the functional nodes in the operating functional module; the initial test data includes a plurality of test instructions; The control unit counts the number of times each functional node in each working functional module executes the test instruction; each time a functional node of the functional module executes a test instruction, the number of times the functional node executes the test instruction is increased by one; The control unit adjusts the number of test instructions in the initial test data according to a preset threshold interval and the number of working times corresponding to each functional node, so that when the number of working times corresponding to each functional node is within the threshold interval, the adjusted test data is generated into target test data.

2. The configuration system for storage chip test data according to claim 1, characterized in that: The control unit is configured to reduce the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is greater than the threshold interval; The control unit is configured to increase the number of test instructions corresponding to the functional node in the initial test data when the number of operations corresponding to the functional node is less than the threshold interval.

3. The configuration system for storage chip test data according to claim 2, characterized in that: The control unit is used to count the test paths of executing the test instructions, where the test paths are represented as transmission paths between functional nodes of different functional modules corresponding to the execution of the test instructions; The control unit is used to determine whether the test paths corresponding to all test instructions are repeated on the functional node when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and if repeated, retain a test instruction corresponding to the repeated test path in the initial test data.

4. The configuration system for storage chip test data according to claim 2, characterized in that: The control unit is used to determine whether the test path of the test instruction corresponding to the functional node intersects with other test paths when the number of working times corresponding to the functional node is not within the threshold range, and if they do not intersect, increase or decrease the number of test instructions corresponding to the functional node in the initial test data.

5. The configuration system for storage chip test data according to claim 2, characterized in that: The control unit is used to determine whether the test path of the test instruction corresponding to the functional node is repeated with part of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and if repeated, reduce the number of test instructions corresponding to the repeated test path on the functional node in the initial test data.

6. The configuration system for storage chip test data according to claim 2, characterized in that: The control unit is used to determine whether a portion of the test path corresponding to the test instruction of the functional node is repeated with a portion of the test path in other test paths when the number of working times corresponding to the functional node is greater than the maximum value of the threshold interval, and if repeated, retain the test instructions corresponding to the partially repeated test path on the functional node in the initial test data.

7. The configuration system for storage chip test data according to claim 1, characterized in that: The control unit is used to establish a counting table, and the counting table is used to count the test instructions and working times corresponding to all functional nodes in each working functional module.

8. The configuration system for storage chip test data according to claim 1, characterized in that: The functional modules at least include a command parsing and scheduling module, a main controller, a firmware logic module, a cache management module, an error correction encoding / decoding module and a flash memory physical layer control module.

9. A configuration method for storing chip test data, characterized in that: include: Installing a memory chip on a chip test socket; the memory chip includes a plurality of functional modules, each of the functional modules corresponds to a plurality of functional nodes, and the functional nodes represent the minimum execution units for executing test instructions; Controlling at least one of the functional modules to operate, writing initial test data to the memory chip, and monitoring the functional nodes in the operating functional module; the initial test data includes a variety of test instructions; Count the number of times each functional node in each working functional module executes the test instruction; Each time a function node of the function module executes a test instruction, its working times increases by one; According to the preset threshold interval and the number of working times corresponding to each functional node, the number of test instructions in the initial test data is adjusted so that when the number of working times corresponding to each functional node is within the threshold interval, the adjusted initial test data is used to generate target test data.

Images