Method and related equipment for suppressing output current of voltage source converter during asymmetric fault

Abstract

The present invention belongs to the field of power electronics and discloses a method and related equipment for suppressing the output current of a voltage source converter during an asymmetric fault. The method collects the grid current and grid voltage during an asymmetric fault; calculates a virtual resistance and virtual inductance; and feeds the virtual resistance and virtual inductance back into a control loop. The virtual resistance adjusts the active power output of the grid-connected inverter, and the virtual inductance adjusts the reactive power output of the grid-connected inverter, thereby suppressing the output current of the voltage source converter. This coordinated control can quickly adjust the equivalent impedance at the initial stage of the fault, dynamically balance the power surge generated by the fault, and achieve millisecond-level current suppression response through real-time power dissipation rather than passive limiting, limiting the output current amplitude to a safe threshold. Compared with traditional methods, this method improves the current suppression capability at the moment of the fault, reduces the risk of equipment damage, and enhances the grid fault ride-through capability and system stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and in particular relates to a method for suppressing output current of a voltage source converter during an asymmetric fault and related equipment. Background Art

[0002] In modern power systems, grid voltage asymmetry is a common and devastating fault. With the widespread integration of distributed energy resources and the increasing complexity of power systems, grid-connected inverters, as key components for efficient energy conversion and transmission, are crucial for operational stability. However, once a grid voltage asymmetry fault occurs, it can easily lead to overcurrent in the grid-connected inverter.

[0003] Traditional control methods typically employ a positive- and negative-sequence separation algorithm to address asymmetric grid voltage faults. This algorithm decomposes the fault voltage into positive and negative-sequence components, then controls each separately. Current limiting measures typically incorporate a limiter into the control loop to suppress overcurrent in the grid-connected inverter. However, the limitations of the limiter become apparent when a large power imbalance occurs at the moment of the fault. Because the limiter is connected in series within the control loop, its operation requires a certain response time. Consequently, it cannot effectively suppress overcurrent in a timely manner at the moment of the fault, limiting its ability to suppress overcurrent in the grid-connected inverter during asymmetric faults. This situation not only impacts the stable operation of the grid-connected inverter but also risks equipment damage. In severe cases, it can even cause large-scale grid disconnections, posing a significant threat to the reliability and security of the entire power system.

[0004] It can be seen that, for grid voltage asymmetry faults, the existing current suppression method cannot effectively and timely suppress overcurrent, affecting the stable operation of the grid-connected inverter. Summary of the Invention

[0005] The present invention provides a method for suppressing the output current of a voltage source converter during an asymmetric fault and related equipment. By adopting the current suppression method, overcurrent can be suppressed in a timely and effective manner, thereby ensuring the stable operation of the grid-connected inverter.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A method for suppressing output current of a voltage source converter during an asymmetric fault, comprising:

[0008] Collect grid current and grid voltage when the grid has asymmetric faults;

[0009] Based on the grid current and grid voltage during an asymmetric fault, a virtual resistance and a virtual inductance are obtained;

[0010] The virtual resistance and virtual inductance are fed back into the control loop, and the active power output by the grid-connected inverter is adjusted by the virtual resistance, and the reactive power output by the grid-connected inverter is adjusted by the virtual inductance, so as to suppress the output current of the voltage source converter.

[0011] Furthermore, before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault in the grid, the method further includes:

[0012] Based on the grid voltage and grid-connected inverter output voltage during asymmetric faults, the active power output of the grid-connected inverter is calculated. p and reactive power q , the specific calculation formula is as follows:

[0013]

[0014] Where, Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter, represents the line impedance, is the power angle difference between the grid-connected inverter and the grid; sin Indicates the sine value of the power angle difference between the grid-connected inverter and the grid; cos Indicates the cosine value of the power angle difference between the grid-connected inverter and the grid.

[0015] Furthermore, obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault in the grid includes:

[0016] Separate the positive and negative sequence of the grid current during an asymmetric fault to obtain the positive sequence d-axis current and the positive sequence q-axis current;

[0017] The grid voltage is subjected to positive and negative sequence separation processing during an asymmetric fault to obtain positive sequence d-axis voltage and positive sequence q-axis voltage;

[0018] Based on the positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, positive-sequence q-axis voltage, and the grid-connected inverter output voltage, the virtual resistance and virtual inductance are calculated respectively.

[0019] Furthermore, the virtual resistance and virtual inductance are calculated based on the positive-sequence d-axis current, the positive-sequence q-axis current, the positive-sequence d-axis voltage, the positive-sequence q-axis voltage, and the grid-connected inverter output voltage. The specific calculation formulas are as follows:

[0020]

[0021] Where, represents a virtual resistor; represents virtual inductance; 、 Represent the positive sequence active power and positive sequence reactive power respectively, 、 They represent the d-axis positive sequence current and the q-axis positive sequence current respectively. 、 They represent the d-axis positive sequence voltage and the q-axis positive sequence voltage respectively; Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter; Indicates the grid angular frequency.

[0022] Furthermore, the grid current is subjected to positive-negative sequence separation processing when the grid has an asymmetric fault, thereby obtaining a positive-sequence d-axis current and a positive-sequence q-axis current, and also obtaining a negative-sequence d-axis current and a negative-sequence q-axis current;

[0023] The grid voltage is subjected to positive and negative sequence separation processing during an asymmetric fault to obtain a positive sequence d-axis voltage and a positive sequence q-axis voltage, and a negative sequence d-axis voltage and a negative sequence q-axis voltage;

[0024] Set the negative sequence current reference to zero.

[0025] Furthermore, the virtual resistance and virtual inductance are fed back into the control loop, the active power output by the grid-connected inverter is adjusted by the virtual resistance, and the reactive power output by the grid-connected inverter is adjusted by the virtual inductance; so as to suppress the output current of the voltage source converter, including:

[0026] The virtual resistor and virtual inductor are fed forward into the control loop to adjust the active power output by the grid-connected inverter through the virtual resistor, and the reactive power output by the grid-connected inverter is adjusted through the virtual inductor, thereby generating a regulated voltage;

[0027] The generated regulation voltage is superimposed on the positive sequence current control output voltage to suppress the output current of the voltage source converter.

[0028] Furthermore, before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault in the grid, the method further includes:

[0029] Based on the grid current and grid voltage during an asymmetric fault, the active power output of the grid-connected inverter is calculated. p and reactive power q , the specific calculation formula is as follows:

[0030]

[0031] Where, 、 Represent the d-axis current and q-axis current respectively, 、 Represent the d-axis voltage and q-axis voltage respectively;

[0032] The d-axis current and the q-axis current are calculated based on the grid current using the dq rotating coordinate system; the d-axis voltage and the q-axis voltage are calculated based on the grid voltage using the dq rotating coordinate system.

[0033] A system for suppressing output current of a voltage source converter during an asymmetric fault, characterized by comprising:

[0034] A power grid data acquisition module is used to collect the grid current and grid voltage when the grid is in an asymmetric fault;

[0035] a calculation module for obtaining a virtual resistance and a virtual inductance based on a grid current and a grid voltage when the grid is subjected to an asymmetric fault;

[0036] The feedback module is used to feed back the virtual resistance and virtual inductance into the control loop, adjust the active power output by the grid-connected inverter through the virtual resistance, and adjust the reactive power output by the grid-connected inverter through the virtual inductance, so as to suppress the output current of the voltage source converter.

[0037] An electronic device, comprising:

[0038] memory for storing computer programs;

[0039] A processor is configured to implement the steps of the above-mentioned method for suppressing the output current of a voltage source converter during an asymmetric fault when executing the computer program.

[0040] A computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, is used to implement the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] The present invention provides a method for suppressing the output current of a voltage source converter during an asymmetric fault. The method introduces a dynamic feedback mechanism of virtual resistance and virtual inductance. When an asymmetric fault occurs in the power grid, the virtual resistance and virtual inductance are calculated by real-time acquisition of the grid current, voltage, and inverter output voltage. The virtual resistance reduces the current amplitude by actively adjusting the active power of the grid, while the virtual inductance suppresses current fluctuations by absorbing reactive power. Both act directly on the control loop, have good dynamic effects, and do not require a series delay of the limiter. This coordinated control can quickly adjust the equivalent impedance at the early stage of the fault, dynamically balance the power mutation caused by the fault, and achieve millisecond-level current suppression response by real-time power dissipation rather than passive limiting, thereby limiting the output current amplitude to a safe threshold. Compared with traditional methods, the present method improves the current suppression capability at the moment of the fault, reduces the risk of equipment damage, and enhances the fault ride-through capability and system stability of the power grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of positive sequence virtual resistance control provided by an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of positive sequence virtual inductance control provided by an embodiment of the present invention;

[0045] Figure 3 A control block diagram of a grid-connected inverter under asymmetric fault conditions provided by an embodiment of the present invention;

[0046] Figure 4 The positive sequence power angle under asymmetric fault provided by the embodiment of the present invention Phase locus diagram;

[0047] Figure 5 The negative sequence power angle under asymmetric fault provided by the embodiment of the present invention Phase locus diagram;

[0048] Figure 6 This is a simulation diagram of an asymmetric fault without using the suppression method provided by an embodiment of the present invention; where (a) is the output current; (b) is the active power; (c) is the reactive power; and (d) is the output voltage frequency.

[0049] Figure 7 This is a simulation diagram of the suppression method used in an asymmetric fault according to an embodiment of the present invention; wherein (a) is the output current; (b) is the active power; (c) is the reactive power; and (d) is the output voltage frequency.

[0050] Figure 8 A flow chart of a method for suppressing output current of a voltage source converter during an asymmetric fault provided by the present invention;

[0051] Figure 9This is a structural diagram of a voltage source converter output current suppression system during an asymmetric fault provided by the present invention. DETAILED DESCRIPTION

[0052] In order to further understand the content of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and are not intended to limit it.

[0053] The following is an explanation of the technical terms involved in the present invention:

[0054] VSC stands for Voltage Source Converter. It is an important power electronic device used in modern power systems to convert and control electrical energy, converting direct current to alternating current and vice versa.

[0055] SVPWM (Space Vector Pulse Width Modulation) is a commonly used pulse width modulation technique that generates a desired AC voltage waveform by controlling the on and off states of the inverter's switching devices.

[0056] The dq rotating coordinate system is a coordinate transformation method commonly used in power system analysis and motor control. "d" represents the direct axis, and "q" represents the quadrature axis. By converting physical quantities (such as voltage and current) in a three-phase stationary coordinate system to the dq rotating coordinate system, the analysis and control of AC motors and power converters can be simplified.

[0057] As described in the background, conventional control methods use a positive- and negative-sequence separation algorithm to decompose the fault voltage into positive and negative-sequence components, and then incorporate a limiter into the control loop to suppress overcurrent. However, because the limiter is connected in series with the control loop, it has a significant response delay, making it difficult to quickly suppress overcurrent, especially when there is a large power imbalance at the moment of a fault. Consequently, the main drawbacks of this existing technology are: first, slow response: the limiter's hysteresis cannot adapt to transient power surges; and second, insufficient stability: under asymmetric faults, the VSC's power angle becomes unstable, leading to oscillations in both active and reactive power.

[0058] In order to solve the above problems, this embodiment provides a method for suppressing the output current of a voltage source converter during an asymmetric fault. This method directly superimposes virtual resistance and virtual inductance on the control loop in a feedforward manner, significantly improving the response speed and suppression capability. Based on the traditional control method, this method accurately calculates the active power and reactive power at the moment of the fault by introducing the grid current and grid voltage, and proposes a positive sequence current virtual impedance control strategy. This strategy can calculate the virtual resistance and virtual inductance, and directly add them to the system control loop in a feedforward manner. It has the characteristics of fast response speed and convenient and quick implementation. It effectively enhances the overcurrent suppression capability of the grid-connected inverter under asymmetric faults. At the same time, it also has a certain suppression capability for the fluctuation of the VSC output voltage frequency during asymmetric faults, ensuring the stable operation of the power system.

[0059] The following is a detailed introduction to the concept and design of this suppression method in conjunction with the accompanying drawings:

[0060] In this embodiment, positive-sequence overcurrents caused by asymmetric faults are suppressed by controlling the positive-sequence current virtual impedance. This virtual impedance specifically includes two components: positive-sequence virtual resistance control and positive-sequence virtual inductance control. This virtual impedance control detects the current rate of change and calculates the changes in active and reactive power during an asymmetric fault. The corresponding virtual resistance and virtual inductance are then calculated from these changes, generating corresponding voltages that are superimposed on the positive-sequence current control output voltage. Regarding negative-sequence current, the negative-sequence current reference value is generally zero during an asymmetric fault, posing a low risk of overcurrent and requiring no specific suppression.

[0061] Positive-sequence current virtual resistance control primarily affects positive-sequence d-axis current control, while positive-sequence current virtual inductance control primarily affects positive-sequence q-axis current control. By suppressing the positive-sequence current, the rapid rise in active and reactive power during an asymmetric fault can be suppressed. The following describes positive-sequence current virtual resistance control in detail.

[0062] According to the analysis, the active power and reactive power output by the grid-connected inverter are expressed as follows:

[0063] (1)

[0064] Where, Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter, represents the line impedance, It is the power angle difference between the grid-connected inverter and the grid.

[0065] In this embodiment, the active power and reactive power output by the grid-connected inverter can also be obtained by calculating using the dq rotating coordinate system:

[0066] (2)

[0067] Where, 、 Represent the d-axis current and q-axis current respectively, 、 Represent the d-axis voltage and q-axis voltage respectively;

[0068] The d-axis current and the q-axis current are calculated based on the grid current using the dq rotating coordinate system; the d-axis voltage and the q-axis voltage are calculated based on the grid voltage using the dq rotating coordinate system.

[0069] By comparing equations (1) and (2), it can be found that under asymmetric faults, the main reason for the overcurrent generated by the grid-connected inverter is power imbalance. Due to the grid voltage failure, the grid-connected inverter is unable to adjust its own output power instantly, causing power imbalance and overcurrent. Combining the inherent characteristics of resistance and inductance, it can be found that active power can be consumed by resistance and reactive power can be consumed by inductance. Therefore, this embodiment proposes positive sequence current virtual impedance control, calculates the virtual resistance for consuming active power and the virtual inductance for consuming reactive power, and uses these two to reduce the power imbalance phenomenon during asymmetric faults and realize the output overcurrent limiting function.

[0070] like Figure 1 As shown, 、 Respectively represent the positive sequence d-axis current reference value and the positive sequence q-axis current reference value, 、 They represent the positive sequence d-axis current and the positive sequence q-axis current respectively, both of which are sampling values. 、 Respectively represent the positive sequence d-axis voltage reference value and the positive sequence q-axis voltage reference value, 、 They represent the positive sequence d-axis voltage and the positive sequence q-axis voltage respectively, both of which are sampled values. The inversion operator is used to take the inverse of the operation result, and the virtual resistance is obtained by positive sequence virtual resistance control. , can automatically adjust the virtual resistance according to the degree of asymmetric fault size.

[0071] like Figure 2 As shown, 、 Respectively represent the positive sequence d-axis current reference value and the positive sequence q-axis current reference value, 、 They represent the positive sequence d-axis current and the positive sequence q-axis current respectively, both of which are sampling values. 、 Respectively represent the positive sequence d-axis voltage and positive sequence q-axis voltage reference values, 、 They represent the positive sequence d-axis voltage and the positive sequence q-axis voltage respectively, both of which are sampled values. The inversion operator is used to take the inverse of the operation result. is the grid angular frequency, and the virtual inductance is obtained by positive sequence virtual inductance control , and can be adjusted automatically according to the degree of asymmetric fault size.

[0072] Combining formula (1) and Figure 1 and Figure 2 The calculation formulas for virtual resistance and virtual inductance are as follows:

[0073] (3)

[0074] Where, represents a virtual resistor; represents virtual inductance; 、 Represent the positive sequence active power and positive sequence reactive power respectively, 、 They represent the d-axis positive sequence current and the q-axis positive sequence current respectively. 、 They represent the d-axis positive sequence voltage and the q-axis positive sequence voltage respectively; Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter; Indicates the grid angular frequency.

[0075] Based on the above suppression method concept and design ideas, this embodiment provides a method for suppressing the output current of a voltage source converter during an asymmetric fault. The specific steps are as follows:

[0076] Collect grid current and grid voltage when the grid has asymmetric faults;

[0077] Based on the grid current and grid voltage during an asymmetric fault, a virtual resistance and a virtual inductance are obtained;

[0078] The grid current and grid voltage are subjected to positive and negative sequence separation processing respectively during an asymmetric fault, and the positive sequence d-axis current, positive sequence q-axis current, positive sequence d-axis voltage and positive sequence q-axis voltage are obtained;

[0079] Based on the positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, positive-sequence q-axis voltage, and the grid-connected inverter output voltage, the virtual resistance and virtual inductance are calculated respectively.

[0080] The grid current and grid voltage under asymmetric fault conditions are subjected to positive and negative sequence separation processing to obtain negative sequence d-axis current, negative sequence q-axis current, negative sequence d-axis voltage and negative sequence q-axis voltage; and the negative sequence current reference value is set to zero.

[0081] The virtual resistance and virtual inductance are fed back into the control loop, the active power output by the grid-connected inverter is adjusted by the virtual resistance, and the reactive power output by the grid-connected inverter is adjusted by the virtual inductance, so as to suppress the output current of the voltage source converter.

[0082] like Figure 3 As shown, Figure 3 Figure 2 is the control block diagram of the grid-connected inverter under asymmetric fault; is the three-phase voltage of the grid (grid voltage), is the three-phase current of the grid (grid current), 、 is the d-axis negative sequence current sampling value, the q-axis negative sequence current sampling value, 、 is the d-axis negative sequence voltage sampling value, the q-axis negative sequence voltage sampling value, 、 is the negative sequence d axis current reference value, the negative sequence q axis current reference value, 、 is the grid voltage d-axis positive sequence voltage sampling value, grid voltage q-axis positive sequence voltage sampling value, 、 is the grid voltage d-axis negative sequence voltage sampling value, grid voltage q-axis negative sequence voltage sampling value, 、 is the positive sequence current d-axis control quantity, the positive sequence current q-axis control quantity, 、 It is the negative sequence current d-axis control quantity and the negative sequence current q-axis control quantity, 、 Coordinate transformation operator, 、 is the input voltage for SVPWM modulation operation, and They are respectively the virtual resistance and virtual inductance output by this suppression method. The voltage, current sampling and positive-negative sequence separation link is responsible for separating the grid voltage and grid current into positive and negative sequences, in preparation for the subsequent positive and negative sequence current control. The reference current calculation is mainly to determine the appropriate dq axis current reference value for positive and negative sequence current control. This suppression method mainly controls the output superimposed on the positive sequence current control. For negative sequence current control, the negative sequence current generated by asymmetric faults is mainly controlled to zero, without additional control; in the figure, grid represents the grid; PI represents the proportional-integral controller; middle, represents the angular frequency, represents inductance; It represents the inductive reactance of an inductor in an AC circuit.

[0083] For the method for suppressing the output current of a voltage source converter during an asymmetric fault provided in this embodiment, a large signal model of a VSC under an asymmetric fault is used to perform the following simulation verification and theoretical analysis:

[0084] When an asymmetric grid voltage fault occurs, the limitations of VSC small-signal analysis methods make it difficult to accurately analyze VSC performance during the fault. Because single-phase and two-phase voltage sag faults have similar mechanisms, both generate negative-sequence components. Therefore, in large-signal analysis, a theoretical analysis is conducted using a single-phase voltage sag fault as an example.

[0085] When the grid is operating normally, the active power of the VSC is:

[0086] (4)

[0087] In formula (4), represents the output voltage of VSC, represents the line impedance, is the power angle of the VSC, which can be expressed as:

[0088] (5)

[0089] In formula (5), Indicates the active power reference value, p Indicates the active power output by the VSC;

[0090] In the case of an asymmetric fault, the active power of the VSC using positive and negative sequence current control is:

[0091] (6)

[0092] In formula (6), is the output voltage of VSC, represents the grid voltage; X represents the line impedance; the power angle of the VSC after adding the positive sequence current virtual impedance control It can be expressed as:

[0093] (7)

[0094] In formula (7), 、 for:

[0095] (8)

[0096] In formula (8), and Denote the sum of the VSC output positive sequence resistance and the line positive sequence inductance respectively. Substituting equation (8) into equation (7), we can obtain the positive sequence power angle It can be expressed as:

[0097] (9)

[0098] In formula (9), and Represents the voltage components of different axes in the dq rotating coordinate system. They participate in the calculation of the final expression of the positive sequence power angle and are used to comprehensively reflect the characteristics of the grid voltage on different axes.

[0099] Since the negative sequence power angle is not subjected to the suppression method provided in this embodiment, the formula (5) can be used directly.

[0100] like Figure 4 As shown, the positive sequence power angle under asymmetric fault using different control methods is Phase trajectory. It can be seen that under the traditional control method, the positive sequence power angle of VSC Divergence, VSC instability. When the suppression method provided in this embodiment is adopted, the oscillation can be significantly reduced and stability can be quickly restored when an asymmetric fault occurs.

[0101] like Figure 5 As shown, it is the negative sequence power angle of current balance control under asymmetric fault Phase trajectory. It can be seen that under the traditional control method, VSC is unstable. When the suppression method provided by this embodiment is adopted, after the fault occurs, the negative sequence power angle It quickly converges to the origin and operates stably, so that the VSC can quickly recover and operate stably when an asymmetric fault occurs. Figure 4 and Figure 5 Δw in represents the angular frequency deviation.

[0102] Based on the above phase trajectory analysis, in order to verify the effectiveness of the method, a simulation of the positive sequence current virtual impedance control of the VSC is performed under an asymmetric fault (single-phase grid voltage drop fault with a drop depth of 50%). The specific simulation parameters are shown in Table 1.

[0103] Table 1 shows the simulation parameters

[0104]

[0105] Combine Figure 6 (a), (b), (c), (d) Figure 6Figure 2 shows the simulation curves for the VSC output current I, active power P, reactive power Q, and output voltage frequency f under the traditional control method. Although the three-phase output current of the VSC remains balanced, the active and reactive powers experience significant oscillations during the fault. Furthermore, the overcurrent is high, causing the output voltage frequency to oscillate.

[0106] contrast Figure 7 (a), (b), (c), (d) Figure 7 The simulation curves corresponding to the VSC output current I, active power P, reactive power Q and output voltage frequency f under the real-time suppression method provided by this invention are shown. It can be seen that this suppression method can significantly reduce output current overcurrent, reduce overshoot of active power and output voltage frequency, and at the same time, control active power oscillation within a certain range. In addition, the three-phase current imbalance is also smaller than that under the traditional control method.

[0107] This method suppresses overcurrents caused by asymmetric faults by controlling the virtual impedance of the positive-sequence current. It also has a certain ability to suppress VSC output voltage frequency fluctuations during asymmetric faults. Analysis using the phase plane method demonstrates that this suppression method improves VSC stability and effectively reduces oscillations under asymmetric faults.

[0108] For example, Figure 8 As shown, this embodiment also provides a method for suppressing the output current of a voltage source converter during an asymmetric fault, comprising the following steps:

[0109] Collect grid current and grid voltage when the grid has asymmetric faults;

[0110] Based on the grid current and grid voltage during an asymmetric fault, a virtual resistance and a virtual inductance are obtained; the virtual resistance is used to adjust the active power output by the grid-connected inverter, and the virtual inductance is used to adjust the reactive power output by the grid-connected inverter;

[0111] The virtual resistance and virtual inductance are fed back into the control loop to ultimately suppress the output current of the voltage source converter.

[0112] In this embodiment, before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault in the grid, the method further includes:

[0113] Based on the grid voltage and grid-connected inverter output voltage during asymmetric faults, the active power output of the grid-connected inverter is calculated. p and reactive power q , the specific calculation formula is as follows:

[0114]

[0115] Where, Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter, represents the line impedance, is the power angle difference between the grid-connected inverter and the grid; sin Indicates the sine value of the power angle difference between the grid-connected inverter and the grid; cos Indicates the cosine value of the power angle difference between the grid-connected inverter and the grid.

[0116] It can be seen that by accurately calculating the active power and reactive power of the power grid and clarifying the degree of power imbalance, a quantitative basis is provided for the dynamic adjustment of the virtual impedance parameters, ensuring the real-time matching of the impedance value and the fault state, and improving the accuracy and adaptability of the control.

[0117] In this embodiment, the grid current and grid voltage during an asymmetric fault are subjected to positive- and negative-sequence separation processing to obtain positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, and positive-sequence q-axis voltage; based on the positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, positive-sequence q-axis voltage, and the output voltage of the grid-connected inverter, the virtual resistance and virtual inductance are calculated respectively.

[0118] The positive and negative sequence separation technology is used to decompose the grid current and grid voltage, focusing on the positive sequence component to establish a virtual impedance model, effectively suppressing the harmonic disturbance caused by asymmetric faults, while simplifying the control complexity and avoiding the interference of the negative sequence component on the system.

[0119] The specific calculation formulas for virtual resistance and virtual inductance are as follows:

[0120]

[0121] Where, represents a virtual resistor; represents virtual inductance; 、 Represent the positive sequence active power and positive sequence reactive power respectively, 、 They represent the d-axis positive sequence current and the q-axis positive sequence current respectively. 、 They represent the d-axis positive sequence voltage and the q-axis positive sequence voltage respectively; Indicates the grid voltage, Indicates the output voltage of the grid-connected inverter; Indicates the grid angular frequency.

[0122] Based on the positive-sequence component, the mathematical expressions of virtual resistance and inductance are derived, and the impedance value is quickly calculated through parameterized formulas, taking into account both power conservation and dynamic response requirements, ensuring the real-time performance and theoretical completeness of current suppression.

[0123] In this embodiment, the positive-sequence separation processing of the grid current and the grid voltage during an asymmetric fault of the grid further includes:

[0124] The grid current and grid voltage are subjected to positive and negative sequence separation processing respectively when the grid is in an asymmetric fault, and negative sequence d-axis current, negative sequence q-axis current, negative sequence d-axis voltage and negative sequence q-axis voltage are obtained;

[0125] Set the negative sequence current reference to zero.

[0126] In this way, by setting the negative-sequence current reference value to zero, the impact of the negative-sequence component on the system is actively eliminated, the current distortion rate under asymmetric faults is reduced, the risk of equipment overheating or oscillation caused by negative-sequence current is avoided, and the symmetry and reliability of system operation are further improved.

[0127] In this embodiment, the method of feeding back the virtual resistance and virtual inductance into the control loop to ultimately suppress the output current of the voltage source converter includes:

[0128] Feeding the virtual resistance and virtual inductance into the control loop to generate the corresponding regulation voltage;

[0129] The generated regulation voltage is superimposed on the positive sequence current control output voltage, and finally the output current of the voltage source converter is suppressed.

[0130] Through feedforward control, the compensation voltage generated by the virtual impedance is superimposed on the positive-sequence current control output to form a dynamic voltage compensation loop, which quickly offsets the impact of sudden changes in fault voltage (grid voltage) on current, achieves multi-variable coordinated suppression, and enhances the robustness of the control loop.

[0131] In this embodiment, before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault in the grid, the method further includes:

[0132] Based on the grid current and grid voltage during an asymmetric fault, the active power output of the grid-connected inverter is calculated. p and reactive power q , the specific calculation formula is as follows:

[0133]

[0134] Where, 、 Represent the d-axis current and q-axis current respectively, 、 Represent the d-axis voltage and q-axis voltage respectively;

[0135] The d-axis current and the q-axis current are calculated based on the grid current using the dq rotating coordinate system; the d-axis voltage and the q-axis voltage are calculated based on the grid voltage using the dq rotating coordinate system.

[0136] The dq rotating coordinate system is used to decouple the grid current and voltage, directly extract the active and reactive power parameters, simplify the traditional power calculation process, improve computing efficiency, and provide real-time data support for the rapid generation of virtual impedance.

[0137] like Figure 9 As shown, this embodiment also provides a system for suppressing the output current of a voltage source converter during an asymmetric fault, including: a grid data acquisition module, used to collect the grid current and grid voltage of the grid during an asymmetric fault; a calculation module, used to obtain a virtual resistance and a virtual inductance based on the grid current and grid voltage of the grid during an asymmetric fault; the virtual resistance is used to adjust the active power output by the grid-connected inverter, and the virtual inductance is used to adjust the reactive power output by the grid-connected inverter; a feedback module, used to feed back the virtual resistance and virtual inductance to the control loop, thereby ultimately suppressing the output current of the voltage source converter.

[0138] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault when executing the computer program.

[0139] When the processor executes the computer program, it implements the steps of suppressing the output current of the voltage source converter during the above-mentioned asymmetric fault, for example: collecting the grid current and grid voltage of the grid during the asymmetric fault; obtaining a virtual resistance and a virtual inductance based on the grid current and grid voltage of the grid during the asymmetric fault; the virtual resistance is used to adjust the active power output by the grid-connected inverter, and the virtual inductance is used to adjust the reactive power output by the grid-connected inverter; the virtual resistance and virtual inductance are fed back to the control loop, and finally the output current of the voltage source converter is suppressed.

[0140] Alternatively, the processor implements the functions of each module in the above system when executing the computer program.

[0141] Exemplarily, the computer program can be divided into one or more modules / units, and the one or more modules / units are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments that can complete preset functions, and the instruction segments are used to describe the execution process of the computer program in the voltage source converter output current suppression device during the asymmetric fault. For example, the computer program can be divided into a power grid data acquisition module, a calculation module, and a feedback module; the specific functions of each module are as follows: the power grid data acquisition module is used to collect the power grid current and power grid voltage during an asymmetric fault; the calculation module is used to obtain a virtual resistance and a virtual inductance based on the power grid current and power grid voltage during an asymmetric fault; the virtual resistance is used to adjust the active power output by the grid-connected inverter, and the virtual inductance is used to adjust the reactive power output by the grid-connected inverter; the feedback module is used to feed back the virtual resistance and virtual inductance to the control loop, ultimately achieving suppression of the voltage source converter output current.

[0142] The device for suppressing the output current of a voltage source converter during an asymmetric fault can be a computing device such as a desktop computer, a laptop, a PDA, or a cloud server. The device for suppressing the output current of a voltage source converter during an asymmetric fault can include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that the above is an example of a device for suppressing the output current of a voltage source converter during an asymmetric fault and does not constitute a limitation on the device for suppressing the output current of a voltage source converter during an asymmetric fault. The device can include more components than those described above, or a combination of certain components, or different components. For example, the device for suppressing the output current of a voltage source converter during an asymmetric fault can also include input and output devices, network access devices, buses, and the like.

[0143] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or any conventional processor. The processor serves as the control center for the output current suppression of the voltage source converter during asymmetric faults, and utilizes various interfaces and lines to connect various parts of the entire voltage source converter output current suppression device during asymmetric faults.

[0144] The memory can be used to store the computer program and / or module, and the processor implements various functions of the voltage source converter output current suppression device during asymmetric fault by running or executing the computer program and / or module stored in the memory, and calling the data stored in the memory.

[0145] The memory may primarily include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function (such as sound playback or image playback); the data storage area may store data generated based on the use of the mobile phone (such as audio data and a phone book). Furthermore, the memory may include high-speed random access memory (RAM) and non-volatile memory, such as a hard disk, internal memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0146] The present invention also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault.

[0147] If the module / unit integrated in the system for suppressing the output current of a voltage source converter during an asymmetric fault is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0148] Based on this understanding, the present invention implements all or part of the process steps of the above-mentioned method for suppressing the output current of a voltage source converter during an asymmetric fault, and can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, it can implement the steps of the above-mentioned method for suppressing the output current of a voltage source converter during an asymmetric fault. The computer program includes computer program code, which can be in source code form, object code form, executable file, or a preset intermediate form.

[0149] The computer-readable storage medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0150] It should be noted that the content contained in the computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practices in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practices, computer-readable storage media do not include electrical carrier signals and telecommunication signals.

[0151] The present invention provides a method for suppressing the output current of a voltage source converter during an asymmetric fault, which has the following advantages:

[0152] First, strong overcurrent suppression capability: This invention utilizes virtual impedance control for positive-sequence current, rapidly calculating and generating virtual resistance and inductance, which directly impact the positive-sequence current control process. Compared to traditional limiter control, this eliminates the need to wait for the control loop's response time and rapidly suppresses positive-sequence overcurrent at the instant of a fault. This effectively reduces the risk of overcurrent in grid-connected inverters under asymmetric faults and ensures safe operation of the equipment.

[0153] Second, significant stability improvements: Phase trajectory analysis of a large-signal VSC model under asymmetric faults demonstrates that the proposed method enables rapid convergence and stable operation for both positive- and negative-sequence power angles during a fault. This demonstrates that the present invention effectively enhances VSC stability under asymmetric faults, enabling grid-connected inverters to better adapt to grid faults, reducing system oscillations and instability caused by faults, and improving the overall reliability of the power system.

[0154] Third, it suppresses frequency fluctuations: Simulation results show that the method of this invention significantly suppresses fluctuations in the VSC output voltage frequency during asymmetric faults. This is crucial for maintaining the power quality of the power system, ensuring that various electrical devices in the system can operate normally at a stable frequency and reducing damage to equipment caused by frequency fluctuations.

[0155] Fourth, it's quick and easy to implement: The proposed positive-sequence current virtual impedance control strategy calculates the virtual resistance and inductance based on existing voltage and current sampling data. This calculation is performed through simple calculations. Furthermore, it is incorporated into the system control loop as a virtual voltage, making it easy to implement without requiring large-scale modifications to existing grid-connected inverter control systems, thus offering excellent engineering application value.

[0156] The above embodiment is only one of the implementation methods that can realize the technical solution of the present invention. The scope of protection claimed by the present invention is not limited only to this embodiment, but also includes changes, replacements and other implementation methods that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for suppressing output current of a voltage source converter during an asymmetric fault, characterized in that: include: Collect grid current and grid voltage when the grid has asymmetric faults; Based on the grid current and grid voltage during an asymmetric fault, a virtual resistance and a virtual inductance are obtained; The virtual resistor and virtual inductor are fed forward into the control loop to adjust the active power output of the grid-connected inverter through the virtual resistor and the reactive power output of the grid-connected inverter through the virtual inductor, thereby generating a regulated voltage; The generated regulation voltage is superimposed on the positive sequence current control output voltage to suppress the output current of the voltage source converter; The method of obtaining a virtual resistance and a virtual inductance based on a grid current and a grid voltage during an asymmetric fault of the grid includes: Separate the positive and negative sequence of the grid current during an asymmetric fault to obtain the positive sequence d-axis current and the positive sequence q-axis current; The grid voltage is subjected to positive and negative sequence separation processing during an asymmetric fault to obtain positive sequence d-axis voltage and positive sequence q-axis voltage; Based on the positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, positive-sequence q-axis voltage, and the grid-connected inverter output voltage, the virtual resistance and virtual inductance are calculated respectively. The specific formulas are as follows: Where R VR Indicates virtual resistance; L VL represents virtual inductance; p + ,q + Represent the positive sequence active power and positive sequence reactive power respectively, They represent the d-axis positive sequence current and the q-axis positive sequence current respectively. They represent the d-axis positive sequence voltage and the q-axis positive sequence voltage respectively; u g Indicates the grid voltage, u o represents the output voltage of the grid-connected inverter; ω represents the grid angular frequency.

2. The method for suppressing output current of a voltage source converter during an asymmetric fault according to claim 1, characterized in that: Before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault, the method further includes: Based on the grid voltage and the grid-connected inverter output voltage during an asymmetric fault, the active power p and reactive power q output by the grid-connected inverter are calculated. The specific calculation formula is as follows: Where u g Indicates the grid voltage, u o represents the output voltage of the grid-connected inverter, X represents the line impedance, δ is the power angle difference between the grid-connected inverter and the grid; sinδ represents the sine value of the power angle difference between the grid-connected inverter and the grid; cosδ represents the cosine value of the power angle difference between the grid-connected inverter and the grid.

3. The method for suppressing output current of a voltage source converter during an asymmetric fault according to claim 1, wherein: The grid current is subjected to positive- and negative-sequence separation processing during an asymmetric fault to obtain a positive-sequence d-axis current and a positive-sequence q-axis current, and a negative-sequence d-axis current and a negative-sequence q-axis current; The grid voltage is subjected to positive and negative sequence separation processing during an asymmetric fault to obtain a positive sequence d-axis voltage and a positive sequence q-axis voltage, and a negative sequence d-axis voltage and a negative sequence q-axis voltage; Set the negative sequence current reference to zero.

4. The method for suppressing output current of a voltage source converter during an asymmetric fault according to claim 1, wherein: Before obtaining the virtual resistance and virtual inductance based on the grid current and grid voltage during an asymmetric fault, the method further includes: Based on the grid current and grid voltage during an asymmetric fault, the active power p and reactive power q output by the grid-connected inverter are calculated. The specific calculation formula is as follows: Where i d 、i q Represents d-axis current, q-axis current, u d 、u q Represent the d-axis voltage and q-axis voltage respectively; The d-axis current and the q-axis current are calculated based on the grid current using the dq rotating coordinate system; the d-axis voltage and the q-axis voltage are calculated based on the grid voltage using the dq rotating coordinate system.

5. A system for suppressing the output current of a voltage source converter during an asymmetric fault, for implementing the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault according to any one of claims 1 to 4, characterized in that: include: A power grid data acquisition module is used to collect the grid current and grid voltage when the grid is in an asymmetric fault; a calculation module for obtaining a virtual resistance and a virtual inductance based on a grid current and a grid voltage when the grid is subjected to an asymmetric fault; A feedback module is used to feed back the virtual resistance and virtual inductance into the control loop, thereby adjusting the active power output by the grid-connected inverter through the virtual resistance and adjusting the reactive power output by the grid-connected inverter through the virtual inductance; In order to suppress the output current of the voltage source converter; The method of obtaining a virtual resistance and a virtual inductance based on a grid current and a grid voltage during an asymmetric fault of the grid includes: Separate the positive and negative sequence of the grid current during an asymmetric fault to obtain the positive sequence d-axis current and the positive sequence q-axis current; The grid voltage is subjected to positive and negative sequence separation processing during an asymmetric fault to obtain positive sequence d-axis voltage and positive sequence q-axis voltage; Based on the positive-sequence d-axis current, positive-sequence q-axis current, positive-sequence d-axis voltage, positive-sequence q-axis voltage, and the grid-connected inverter output voltage, the virtual resistance and virtual inductance are calculated respectively.

6. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault as described in any one of claims 1 to 4 when executing the computer program.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it is used to implement the steps of the method for suppressing the output current of a voltage source converter during an asymmetric fault according to any one of claims 1 to 4.

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