Circuit for improving reliability of power tube in temperature control circuit

Abstract

The invention discloses a circuit for improving the reliability of a power tube in a temperature control circuit. The circuit comprises a two-phase non-overlapping clock generation module and an output-stage power tube module, the input end of the two-phase non-overlapping clock generation module is connected with a PWM control signal, one path of non-intersecting clock generated by the output end of the two-phase non-overlapping clock generation module is connected with a grid electrode of a PMOS power tube in the output-stage power tube module, and the other path of non-intersecting clock generated by the output end of the two-phase non-overlapping clock generation module is connected with a grid electrode of an NMOS power tube in the output-stage power tube module. Under the condition that only capacitance is increased, time of a dead zone is effectively prolonged, so that the condition that output power tubes are conducted at the same time is avoided, and reliability of the power tubes of the temperature control circuit is improved; in addition, in the structure, the dead time can be changed by only adjusting the capacitance value of the capacitor in the delay unit. Compared with the prior art, the invention has the advantages of less area resource consumption and simple structure.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a circuit for improving the reliability of power transistors in a temperature control circuit. Background Art

[0002] With the rapid development of inertial navigation technology, the demand for gyroscopes with higher precision and more stable operation is gradually increasing. The wavelength of the laser has a decisive effect on the accuracy of the gyroscope, and it is greatly affected by temperature changes. To ensure the high-precision performance of the gyroscope, a temperature control module is generally included in the laser.

[0003] In the temperature control circuit, there are power transistors with an output current of about 1 - 3A. In a common implementation of the output stage drive circuit, two power field effect transistors are connected together in a totem pole form, and the common point is used as the output terminal. During normal operation, only one of the field effect transistors is in the on state. In the actual circuit, due to the existence of parasitic capacitance, there is a delay during the switching of the power transistor, and the switching flip action cannot be completed instantaneously. Therefore, the situation where two power transistors are simultaneously turned on may occur occasionally, generating a large current from the power supply to the ground (also known as shoot-through), resulting in the serious consequence of damaging the power transistor. The dead time is the shielding time introduced to avoid this situation. If this time is too short, the shoot-through phenomenon will also occur. Therefore, it is extremely urgent to study a design method for improving the reliability of power transistors.

[0004] In one solution, a PWM (Pulse Width Modulation) signal is used to generate non-overlapping clock signals through a two-phase non-overlapping clock circuit to control the gates of the output power transistors. In this solution, the dead time is determined by the non-overlapping time of the two-phase non-overlapping clock, and this time depends on the delay unit in the two-phase non-overlapping clock generation circuit. Therefore, there is an urgent need for a circuit that can change the delay time through the delay unit and increase the dead time. Summary of the Invention

[0005] The purpose of the present invention is to provide a circuit for improving the reliability of power transistors in a temperature control circuit to solve the problems in the background art.

[0006] To solve the above technical problems, the present invention provides a circuit for improving the reliability of power transistors in a temperature control circuit, including: a two-phase non-overlapping clock generation module and an output stage power transistor module;

[0007] The input end of the two-phase non-overlapping clock generation module is connected to the PWM control signal, and one path of non-overlapping clock generated at the output end is connected to the gate of the PMOS power transistor in the output stage power transistor module, and the other path of non-overlapping clock is connected to the gate of the NMOS power transistor in the output stage power transistor module.

[0008] In one embodiment, the two-phase non-overlapping clock generation module includes NAND gates NAND1 to NAND2, inverter gates INV1 to INV6, buffers BUFFER1 to BUFFER2, and delay cells Delaycell1 and Delaycell2;

[0009] The PWM control signal is simultaneously connected to the input end of the inverter gate INV1 and the second input end of the NAND gate NAND2; the first input end of the NAND gate NAND1 is connected to the output end of the inverter gate INV1, and the output end of the NAND gate NAND1 is connected to the input end of the inverter gate INV2; the input ends of the inverter gates INV3 and INV4 are both connected to the output end of the inverter gate INV2; the input end of the buffer BUFFER1 is connected to the output end of the inverter gate INV3, and the output end of the buffer BUFFER1 is connected to the output stage power transistor module;

[0010] The input end of the delay cell Delay cell1 is connected to the output end of the inverter gate INV4, and the output end of the delay cell Delay cell1 is connected to the first input end of the NAND gate NAND2; the input end of the inverter gate INV6 is connected to the output end of the NAND gate NAND2, and the output end of the inverter gate INV6 is simultaneously connected to the input end of the buffer BUFFER2 and the input end of the inverter gate INV5;

[0011] The input end of the delay cell Delay cell2 is connected to the output end of the inverter gate INV5, and the output end of the delay cell Delay cell2 is connected to the second input end of the NAND gate NAND1; the output end of the buffer BUFFER2 is connected to the output stage power transistor module.

[0012] In one embodiment, the delay cells Delaycell1 and Delaycell2 have the same structure, and each includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN7, a capacitor C, a resistor R, NAND gates NAND3 to NAND5, and an inverter gate INV7;

[0013] The gates of NMOS transistor MN1, NMOS transistor MN2, and NMOS transistor MN3 are commonly connected to the first terminal of capacitor C, and the second terminal of capacitor C is grounded; the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN1; the gate of NMOS transistor MN4 is connected to its own drain to form a diode connection and is connected to the gates of NMOS transistor MN5 and NMOS transistor MN6; resistor R is connected between the power supply and the drain of NMOS transistor MN4; the gate of PMOS transistor MP1 is connected to the gate of NMOS transistor MN2, and the drains of PMOS transistor MP1 and NMOS transistor MN5 are both connected to the gate of MN7; the source of NMOS transistor MN5 is connected to the drain of MN2; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN3; the drain of NMOS transistor MN6 is simultaneously connected to the gate and drain of PMOS transistor MP2 and the gate of PMOS transistor MP3; the drains of PMOS transistor MP3, PMOS transistor MP4, and NMOS transistor MN7 are commonly connected to the first input terminal of NAND gate NAND3; the second input terminal of NAND gate NAND3 is connected to the input signal IN of the delay unit, and the output terminal of NAND gate NAND3 is connected to the gate of PMOS transistor MP4 and the first input terminal of NAND gate NAND4; the second input terminal of NAND gate NAND4 is connected to the output terminal of NAND gate NAND5, and the output terminal of NAND gate NAND4 is connected to the first input terminal of NAND gate NAND5 and the input terminal of inverter INV7; the second input terminal of NAND gate NAND5 is connected to the input signal IN of the delay unit; the output terminal of inverter INV7 outputs the output signal OUT of the delay unit.

[0014] In one embodiment, the output stage power transistor module includes PMOS transistor M1 and NMOS transistor M2; the source of PMOS transistor M1 is connected to the power supply, and the gate is connected to the output terminal of buffer BUFFER1; the source of NMOS transistor M2 is grounded, and the gate is connected to the output terminal of buffer BUFFER2; the drains of PMOS transistor M1 and NMOS transistor M2 are connected.

[0015] In one embodiment, the operating states of the output stage power transistor module include: only PMOS power transistor M1 is turned on, or only NMOS power transistor M2 is turned on, or both PMOS power transistor M1 and NMOS power transistor M2 are turned off simultaneously.

[0016] A circuit for improving the reliability of power transistors in a temperature control circuit provided by the present invention effectively increases the dead time by only adding a capacitor, thereby avoiding the situation where output power transistors conduct simultaneously and improving the reliability of power transistors in the temperature control circuit; in addition, in this structure, the dead time can be changed by only adjusting the capacitance value of the capacitor in the delay unit. Compared with the prior art, the present invention has the advantages of less consumption of area resources and simple structure. Brief Description of the Drawings

[0017] Figure 1 FIG. 1 is a schematic structural diagram of a circuit for improving the reliability of a power transistor in a temperature control circuit provided by the present invention.

[0018] Figure 2 FIG. 2 is a schematic diagram of the generated control signal waveform.

[0019] Figure 3 FIG. 3 is a schematic structural diagram of the implementation of the delay unit in the two-phase non-overlapping clock generation module. Detailed Description of the Preferred Embodiments

[0020] The following further describes in detail a circuit for improving the reliability of a power transistor in a temperature control circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the embodiments of the present invention.

[0021] The present invention provides a circuit for improving the reliability of a power transistor in a temperature control circuit. The overall structure is as shown in Figure 1 FIG. 1, and mainly includes a two-phase non-overlapping clock generation module 1 and an output stage power transistor module 2. The two-phase non-overlapping clock generation module 1 is used to generate a control signal for the output stage power transistor module 2. The input end of the two-phase non-overlapping clock generation module 1 is connected to the PWM control signal, and one output end is connected to the gate of the PMOS power transistor M1 in the output stage power transistor module 2, and the other output end is connected to the gate of the NMOS power transistor M2 in the output stage power transistor module 2. In the present invention, the dead time is extended by increasing the delay time through adding a capacitor structure, so as to ensure the reliability of the power transistor.

[0022] Please continue to refer to Figure 1, the two-phase non-overlapping clock generation module includes NAND gates NAND1 to NAND2, inverter gates INV1 to INV6, buffers BUFFER1 to BUFFER2, and delay cells Delaycell1 and Delaycell2; the PWM control signal is connected to the input end of inverter gate INV1 and the second input end of NAND gate NAND2 at the same time; the first input end of NAND gate NAND1 is connected to the output end of inverter gate INV1, and the output end of NAND gate NAND1 is connected to the input end of inverter gate INV2; the input ends of inverter gates INV3 and INV4 are both connected to the output end of inverter gate INV2; the input end of buffer BUFFER1 is connected to the output end of inverter gate INV3, and the output end of buffer BUFFER1 is connected to the output stage power transistor module; the input end of delay cell Delay cell1 is connected to the output end of inverter gate INV4, and the output end of delay cell Delay cell1 is connected to the first input end of NAND gate NAND2; the input end of inverter gate INV6 is connected to the output end of NAND gate NAND2, and the output end of inverter gate INV6 is connected to the input end of buffer BUFFER2 and the input end of inverter gate INV5 at the same time; the input end of delay cell Delay cell2 is connected to the output end of inverter gate INV5, and the output end of delay cell Delay cell2 is connected to the second input end of NAND gate NAND1; the output end of buffer BUFFER2 is connected to the output stage power transistor module.

[0023] The output stage power transistor module includes PMOS transistor M1 and NMOS transistor M2; the source of PMOS transistor M1 is connected to the power supply, and the gate is connected to the output end of buffer BUFFER1; the source of NMOS transistor M2 is grounded, and the gate is connected to the output end of buffer BUFFER2; the drain of PMOS transistor M1 is connected to the drain of NMOS transistor M2. Under normal working conditions, only the PMOS transistor M1 in the high-side channel or the NMOS transistor M2 in the low-side channel is turned on; if both the PMOS transistor M1 and the NMOS transistor M2 are turned on at the same time, a direct path from the power supply to the ground will be formed, causing damage to the power transistor, and this situation should be avoided. The PMOS transistor M1 and the NMOS transistor M2 can be in the off state at the same time.

[0024] Figure 2Is the generated control signal waveform. Assume that the PWM control signal is at a low level of 0 under the initial conditions. At this time, the voltage at point A is at a high level of 1, the voltage at point B is at a low level of 0. Therefore, the voltage at point C is at a high level of 1, the voltage at point D is at a low level of 0, the voltage at point E is at a high level of 1. Since both point A and point E are at a high level of 1, the voltage at point G is at a high level of 1; when the PWM control signal changes from a low level of 0 to a high level of 1, the voltage at point A changes from a high level of 1 to 0, and the voltage at point G changes to a low level of 0. If the delay of the logic gate is ignored, the rising edge of the PWM control signal and the falling edge of the voltage at point G are aligned (almost no delay, changing simultaneously). The voltage at point B becomes a high level of 1 at this time, and the voltage at point H is still at a low level of 0. So the voltage at point D will not change immediately. The change in the voltage at point G is transmitted to point H after a delay d1, and the voltage at point H changes from a low level of 0 to a high level of 1. At this time, the voltage at point D becomes a high level. In this process, the time interval between the rising edge of the voltage at point D and the rising edge of the PWM control signal is d1; when the PWM control signal changes from a high level of 1 to a low level of 0, the voltage at point B becomes a low level of 0, and the voltage at point D becomes a low level of 0. Ignoring the delay of the logic gate, the falling edge of the PWM control signal and the falling edge of the voltage at point D are aligned (almost no delay, changing simultaneously). The voltage at point A becomes a high level of 1. At this time, the voltage at point E is still at a low level of 0. Therefore, the voltage at point G remains at a low level of 0. The change in the voltage at point D is transmitted to point E after a delay d2, and point E becomes a high level of 1. At this time, point G becomes a high level of 1. In this process, the time interval between the rising edge of the voltage at point G and the falling edge of the PWM control signal is d2. Based on the above analysis, the waveforms of the voltage at point G and the voltage at point D cannot be at a high level simultaneously, and the non-overlapping time is determined by the delay unit. Next, the delay unit will be introduced.

[0025] The structures of delay unit Delaycell1 and delay unit Delaycell2 are the same, and the implementation is as Figure 3As shown, it respectively includes PMOS transistors MP1 to MP4, NMOS transistors MN1 to MN7, capacitor C, resistor R, NAND gates NAND3 to NAND5, and inverter INV7; the gates of NMOS transistor MN1, NMOS transistor MN2, and NMOS transistor MN3 are commonly connected to the first end of capacitor C, and the second end of capacitor C is grounded; the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN1; the gate of NMOS transistor MN4 is connected to its own drain to form a diode connection, and is connected to the gates of NMOS transistor MN5 and NMOS transistor MN6; resistor R is connected between the power supply and the drain of NMOS transistor MN4; the gate of PMOS transistor MP1 is connected to the gate of NMOS transistor MN2, and the drain of PMOS transistor MP1 and the drain of NMOS transistor MN5 are both connected to the gate of MN7; the source of NMOS transistor MN5 is connected to the drain of MN2; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN3; the drain of NMOS transistor MN6 is simultaneously connected to the gate and drain of PMOS transistor MP2 and the gate of PMOS transistor MP3; the drains of PMOS transistor MP3, PMOS transistor MP4, and the drain of NMOS transistor MN7 are commonly connected to the first input terminal of NAND gate NAND3; the second input terminal of NAND gate NAND3 is connected to the input signal IN of the delay unit, and the output terminal of NAND gate NAND3 is connected to the gate of PMOS transistor MP4 and the first input terminal of NAND gate NAND4; the second input terminal of NAND gate NAND4 is connected to the output terminal of NAND gate NAND5, and the output terminal of NAND gate NAND4 is connected to the first input terminal of NAND gate NAND5 and the input terminal of inverter INV7; the second input terminal of NAND gate NAND5 is connected to the input signal IN of the delay unit; the output terminal of inverter INV7 outputs the output signal OUT of the delay unit.

[0026] In the present invention, the delay is increased by adding a capacitor C to the delay unit. According to the above analysis, the delay unit functions in the two-phase non-overlapping clock generation module corresponding to the stage when the input signal IN of the delay unit changes from low level 0 to high level 1. At this time, the input signal IN needs to charge the gate parasitic capacitances of NMOS transistors MN1, MN2, MN3 and the capacitor C; this charging time depends on the driving ability of the input signal IN and the capacitance value of the capacitor C, which is the key to controlling the delay time. When the voltage at point X rises above the threshold voltage of NMOS transistor MN1, there is current flowing through NMOS transistor MN1, and at this time NMOS transistors MN4, MN5, MN6 are turned on. Point X is the input signal of the inverter composed of PMOS transistor MP1, NMOS transistors MN2, and MN5. As the voltage at point X gradually becomes higher, the voltage at point Y gradually becomes lower. In this inverter, the driving ability of the PMOS transistor is stronger than that of the NMOS transistor. When the voltage at point X needs to be greater than a certain high threshold, the voltage at point Y begins to become lower. In the path composed of PMOS transistor MP3 and NMOS transistor MN7, the driving ability of the NMOS transistor is stronger than that of the PMOS transistor. Therefore, when the voltage at point Y is lower than a certain low threshold, the voltage at point Z begins to become higher. When the voltages at point Z and point X are both higher than a certain value, through the logic operation of NAND gate NAND3, the voltage at point M is obtained as low level 0, and PMOS transistor MP4 is turned on, and the voltage at point Z is quickly pulled up. The processed voltage at point M and the voltage at point X are used as the input signals of the RS flip-flop, and the final output voltage OUT is obtained through further pulse shaping. Based on the above analysis, the delay of this delay unit mainly depends on the charging time of the added capacitor structure.

[0027] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A circuit for improving the reliability of a power tube in a temperature control circuit, characterized in that: include: Two-phase non-overlapping clock generation module and output stage power tube module; The input end of the two-phase non-overlapping clock generating module is connected to the PWM control signal, one non-intersecting clock generated at the output end is connected to the gate of the PMOS power tube in the output stage power tube module, and the other non-intersecting clock generated is connected to the gate of the NMOS power tube in the output stage power tube module.

2. The circuit for improving the reliability of a power tube in a temperature control circuit according to claim 1, characterized in that: The two-phase non-overlapping clock generation module includes NAND gates NAND1-NAND2, IN gates INV1-INV6, buffers BUFFER1-BUFFER2 and delay cells Delaycell1 and Delaycell2; The PWM control signal is simultaneously connected to the input end of the NOT gate INV1 and the second input end of the NAND gate NAND2; the first input end of the NAND gate NAND1 is connected to the output end of the NAND gate INV1, and the output end of the NAND gate NAND1 is connected to the input end of the NAND gate INV2; the input end of the NAND gate INV3 and the input end of INV4 are both connected to the output end of the NAND gate INV2; the input end of the buffer BUFFER1 is connected to the output end of the NAND gate INV3, and the output end of the buffer BUFFER1 is connected to the output stage power tube module; The input end of the delay cell Delay cell1 is connected to the output end of the NOT gate INV4, and the output end of the delay cell Delay cell1 is connected to the first input end of the NOT gate NAND2; the input end of the NOT gate INV6 is connected to the output end of the NAND gate NAND2, and the output end of the NOT gate INV6 is connected to the input end of the buffer BUFFER2 and the input end of the NOT gate INV5 at the same time; The input end of the delay cell Delay cell2 is connected to the output end of the NOT gate INV5, and the output end of the delay cell Delay cell2 is connected to the second input end of the NOT gate NAND1; the output end of the buffer BUFFER2 is connected to the output stage power tube module.

3. The circuit for improving the reliability of a power tube in a temperature control circuit according to claim 2, characterized in that: The delay cell Delaycell1 and the delay cell Delaycell2 have the same structure, and respectively include PMOS tubes MP1-MP4, NMOS tubes MN1-MN7, capacitors C, resistors R, NAND gates NAND3-NAND5 and an IN gate INV7; The gates of NMOS tube MN1, MN2 and MN3 are connected to the first end of capacitor C, and the second end of capacitor C is grounded; the source of NMOS tube MN4 is connected to the drain of NMOS tube MN1; the gate of NMOS tube MN4 is connected to its own drain to form a diode connection, and is connected to the gates of NMOS tube MN5 and MN6; the resistor R is connected between the power supply and the drain of NMOS tube MN4; the gate of PMOS tube MP1 is connected to the gate of NMOS tube MN2, and the drain of PMOS tube MP1 and NMOS tube MN5 are connected to the gate of MN7. The source of the NMOS tube MN5 is connected to the drain of MN2; the source of the NMOS tube MN6 is connected to the drain of the NMOS tube MN3; the drain of the NMOS tube MN6 is simultaneously connected to the gate and drain of the PMOS tube MP2 and the gate of the PMOS tube MP3; the drain of the PMOS tube MP3, the drain of the PMOS tube MP4, and the drain of the NMOS tube MN7 are commonly connected to the first input terminal of the NAND gate NAND3; the second input terminal of the NAND gate NAND3 is connected to the input signal IN of the delay unit, and the output terminal of the NAND gate NAND3 is connected to the gate of the PMOS tube MP4 and the first input terminal of the NAND gate NAND4; The second input end of the NAND gate NAND4 is connected to the output end of the NAND gate NAND5, and the output end of the NAND gate NAND4 is connected to the first input end of the NAND gate NAND5 and the input end of the NAND gate INV7; the second input end of the NAND gate NAND5 is connected to the input signal IN of the delay unit; the output end of the NAND gate INV7 outputs the output signal OUT of the delay unit.

4. The circuit for improving the reliability of a power tube in a temperature control circuit according to claim 2, characterized in that: The output stage power tube module includes a PMOS tube M1 and an NMOS tube M2; the source of the PMOS tube M1 is connected to the power supply, and the gate is connected to the output end of the buffer BUFFER1; the source of the NMOS tube M2 is grounded, and the gate is connected to the output end of the buffer BUFFER2; the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2.

5. The circuit for improving the reliability of a power tube in a temperature control circuit as claimed in claim 4, characterized in that: The working state of the output stage power tube module includes: only the PMOS power tube M1 is turned on, or only the NMOS power tube M2 is turned on, or both the PMOS power tube M1 and the NMOS power tube M2 are turned off.

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