Signal detection circuit and signal detection method

Abstract

The invention discloses a signal detection circuit and a signal detection method. The circuit comprises a first logic unit, an edge detection control unit, a counting unit, a shift register unit and an output unit. The first logic unit generates an enabling characterization signal for characterizing a to-be-measured level of the PING signal; the edge detection control unit outputs a clock signal in an effective level of the enabling characterization signal; the counting unit is used for periodically counting the clock signal in the effective level of the enabling characterization signal and outputting a counting signal; the shift register unit generates an indication signal for representing whether the to-be-detected level of the PING signal reaches a target value or not; the output unit outputs a level signal and / or a pulse signal based on the indication signal and the enable signal. According to the signal detection circuit and the signal detection method, each unit is integrated in one circuit module, the pulse and the level marking signal can be output without additional digital processing logic, the modularization degree is improved, and the complexity of a subsequent circuit is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a signal detection circuit and a signal detection method. Background Art

[0002] In a BMS (Battery Management System) system, a chip can work in different operating modes to save power consumption. When the chip needs to enter a high-power operating mode from a low-power shutdown mode, a PING signal with a specific width is required to wake up the chip. As Figure 1 shown, the PING signal is characterized by changing from high to low and then to high. The duration of the signal being low needs to meet the recognition index range. Falling below or above the time boundary cannot trigger recognition.

[0003] Traditional pulse width detection, as Figure 2 shown, when pulse is low, the counter is released from reset and starts to work. After pulse is pulled high, the counter output is held. Subsequently, a large amount of logic circuitry is required to determine whether the counter output is within the range, and the logic circuitry gives a reset signal, reducing the circuit modularity and increasing the complexity of the subsequent circuit.

[0004] In addition, during the power-on stage of the system circuit, there is a circuit situation: Reset has been released, the initial state of pulse is low, CLK_IN is started, and the output of And1 is 1. This situation causes the counter to start working directly, without detecting high-low-high, only detecting low-high, and then outputting a result, thus generating an incorrect flag. This problem is more likely to occur when the PING signal recognition range is relatively large.

[0005] The information disclosed in this background art section is only intended to enhance the overall understanding of the present invention and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present invention is to provide a signal detection circuit and a signal detection method, which improve the circuit modularity and have the ability to recognize the falling edge of the PING signal.

[0007] To achieve the above object, a specific embodiment of the present invention provides a signal detection circuit, including: a first logic unit, an edge detection control unit, a counting unit, a shift register unit, and an output unit.

[0008] The first logic unit is used to receive a PING signal and an enable signal, and generate an enable characterization signal representing the length of the level to be measured of the PING signal based on the PING signal and the enable signal; the edge detection control unit is used to receive the PING signal, the enable characterization signal and a clock signal, perform edge detection on the PING signal based on the enable characterization signal, and output the clock signal within the valid level of the enable characterization signal based on the detection result; the counting unit is used to receive the enable characterization signal and is connected to the edge detection control unit to perform periodic counting on the clock signal output by the edge detection control unit based on its own output signal and a preset counting threshold within the valid level of the enable characterization signal and output a counting signal; the shift register unit is used to receive the enable characterization signal and the counting signal to generate an indication signal representing whether the duration of the level to be measured of the PING signal reaches a target value based on the counting signal within the valid level of the enable characterization signal; the output unit is used to receive the enable characterization signal, the indication signal and the enable signal to output a level signal and / or a pulse signal based on the indication signal and the enable signal outside the valid level of the enable characterization signal.

[0009] In one or more embodiments of the present invention, the signal detection circuit further includes a first delay processing unit, and the first delay processing unit is used to receive the PING signal and is connected to the edge detection control unit to deliver the PING signal after delay processing to the edge detection control unit.

[0010] In one or more embodiments of the present invention, the edge detection control unit includes a first D flip-flop and a selector. The clock input terminal of the first D flip-flop is used to receive the PING signal, the D input terminal of the first D flip-flop is used to receive a first reference level signal, the reset terminal of the first D flip-flop is used to receive the enable characterization signal, the output terminal of the first D flip-flop is connected to the control terminal of the selector, the first input terminal of the selector is used to receive a second reference level signal, the second input terminal of the selector is used to receive the clock signal, and the output terminal of the selector is connected to the counting unit; or

[0011] The edge detection control unit includes a second inverter, a first D flip-flop and a selector. The input terminal of the second inverter is used to receive the PING signal, the output terminal of the second inverter is connected to the clock input terminal of the first D flip-flop, the D input terminal of the first D flip-flop is used to receive a first reference level signal, the reset terminal of the first D flip-flop is used to receive the enable characterization signal, the output terminal of the first D flip-flop is connected to the control terminal of the selector, the first input terminal of the selector is used to receive a second reference level signal, the second input terminal of the selector is used to receive the clock signal, and the output terminal of the selector is connected to the counting unit.

[0012] In one or more embodiments of the present invention, the counting unit includes a plurality of second D flip-flops, a second logic unit, and a first processing unit. The D input terminal, the clock input terminal, and the second output terminal of the second D flip-flop are connected. The second output terminals and the clock input terminals of two adjacent second D flip-flops are connected. The clock input terminal of the first second D flip-flop is connected to the edge detection control unit. The second logic unit is connected to the first output terminal of the second D flip-flop. The second logic unit outputs a counting signal based on the output values of the first output terminals of the second D flip-flops. The first processing unit is configured to generate a first reset signal for resetting the second D flip-flop based on the enable characterization signal and the counting signal.

[0013] In one or more embodiments of the present invention, the counting unit includes three second D flip-flops. The second logic unit includes a second AND gate, a third inverter, and a third AND gate. The first input terminal and the second input terminal of the second AND gate are connected to the first output terminal of the first second D flip-flop and the first output terminal of the third second D flip-flop. The input terminal of the third inverter is connected to the first output terminal of the second second D flip-flop. The first input terminal and the second input terminal of the third AND gate are connected to the output terminal of the second AND gate and the output terminal of the third inverter. The output terminal of the third AND gate is connected to the shift register unit.

[0014] In one or more embodiments of the present invention, the first processing unit includes a fourth AND gate. The first input terminal of the fourth AND gate is configured to receive the counting signal. The second input terminal of the fourth AND gate is configured to receive the enable characterization signal. The output terminal of the fourth AND gate is connected to the reset terminal of the second D flip-flop; or

[0015] The first processing unit includes a fourth AND gate and a first delay module. The input terminal of the first delay module is configured to receive the counting signal. The first input terminal of the fourth AND gate is connected to the output terminal of the first delay module. The second input terminal of the fourth AND gate is configured to receive the enable characterization signal. The output terminal of the fourth AND gate is connected to the reset terminal of the second D flip-flop; or

[0016] The first processing unit includes a fourth AND gate and a fourth inverter. The input terminal of the fourth inverter is configured to receive the counting signal. The first input terminal of the fourth AND gate is connected to the output terminal of the fourth inverter. The second input terminal of the fourth AND gate is configured to receive the enable characterization signal. The output terminal of the fourth AND gate is connected to the reset terminal of the second D flip-flop; or

[0017] The first processing unit includes a fourth AND gate, a first delay module, and a fourth inverter. The input terminal of the fourth inverter is used to receive a counting signal, the output terminal of the fourth inverter is connected to the input terminal of the first delay module, the first input terminal of the fourth AND gate is connected to the output terminal of the first delay module, the second input terminal of the fourth AND gate is used to receive an enable characterization signal, and the output terminal of the fourth AND gate is connected to the reset terminal of the second D flip-flop.

[0018] In one or more embodiments of the present invention, the shift register unit includes a plurality of third D flip-flops and a second processing unit. The clock input terminal of the third D flip-flop is used to receive a counting signal, the reset terminal of the third D flip-flop is used to receive an enable characterization signal, the output terminals of two adjacent third D flip-flops are connected to the D input terminal, the D input terminal of the first third D flip-flop is used to receive a first reference level signal, and the second processing unit generates an indication signal based on the output value of the output terminal of the third D flip-flop; or

[0019] The shift register unit includes a plurality of third D flip-flops, a second processing unit, and a second delay processing unit. The clock input terminal of the third D flip-flop is used to receive a counting signal, the second delay processing unit is used to receive an enable characterization signal and is connected to the reset terminal of the third D flip-flop, the output terminals of two adjacent third D flip-flops are connected to the D input terminal, the D input terminal of the first third D flip-flop is used to receive a first reference level signal, and the second processing unit generates an indication signal based on the output value of the output terminal of the third D flip-flop.

[0020] In one or more embodiments of the present invention, the shift register unit includes three third D flip-flops. The second processing unit includes a fifth inverter and a fifth AND gate. The first input terminal of the fifth AND gate is connected to the output terminal of the first third D flip-flop, the input terminal of the fifth inverter is connected to the output terminal of the third third D flip-flop, the output terminal of the fifth inverter is connected to the second input terminal of the fifth AND gate, and the output terminal of the fifth AND gate is connected to the output unit.

[0021] In one or more embodiments of the present invention, the output unit includes a sixth inverter, a fourth D flip-flop, and a third processing unit. The input terminal of the sixth inverter is used to receive an enable characterization signal, the output terminal of the sixth inverter is connected to the clock input terminal of the fourth D flip-flop, the D input terminal of the fourth D flip-flop is connected to the counting unit, the third processing unit is used to receive an enable signal and is connected to the output terminal and the reset terminal of the fourth D flip-flop to generate a second reset signal for resetting the fourth D flip-flop based on the enable signal and the signal of the output terminal of the fourth D flip-flop, and the output terminal of the fourth D flip-flop is used to output a pulse signal; or

[0022] The output unit includes a sixth inverter, a fourth D flip-flop, a third processing unit, and a fifth D flip-flop. The input terminal of the sixth inverter is used to receive an enable characterization signal. The output terminal of the sixth inverter is connected to the clock input terminal of the fourth D flip-flop. The D input terminal of the fourth D flip-flop is connected to the counting unit. The third processing unit is used to receive an enable signal and is connected to the output terminal and the reset terminal of the fourth D flip-flop to generate a second reset signal for resetting the fourth D flip-flop based on the enable signal and the signal at the output terminal of the fourth D flip-flop. The output terminal of the fourth D flip-flop is used to output a pulse signal. The clock input terminal of the fifth D flip-flop is connected to the output terminal of the fourth D flip-flop. The D input terminal of the fifth D flip-flop is used to receive a first reference level signal. The output terminal of the fifth D flip-flop is used to output a level signal.

[0023] In one or more embodiments of the present invention, the third processing unit includes a sixth AND gate. The first input terminal of the sixth AND gate is connected to the output terminal of the fourth D flip-flop. The second input terminal of the sixth AND gate is used to receive an enable signal. The output terminal of the sixth AND gate is connected to the reset terminal of the fourth D flip-flop; or

[0024] The third processing unit includes a sixth AND gate and a seventh inverter. The input terminal of the seventh inverter is connected to the output terminal of the fourth D flip-flop. The first input terminal of the sixth AND gate is connected to the output terminal of the seventh inverter. The second input terminal of the sixth AND gate is used to receive an enable signal. The output terminal of the sixth AND gate is connected to the reset terminal of the fourth D flip-flop; or

[0025] The third processing unit includes a sixth AND gate and a second delay module. The first input terminal of the sixth AND gate is connected to the output terminal of the fourth D flip-flop. The second input terminal of the sixth AND gate is used to receive an enable signal. The output terminal of the sixth AND gate is connected to the input terminal of the second delay module. The output terminal of the second delay module is connected to the reset terminal of the fourth D flip-flop; or

[0026] The third processing unit includes a sixth AND gate, a seventh inverter, and a second delay module. The input terminal of the seventh inverter is connected to the output terminal of the fourth D flip-flop. The first input terminal of the sixth AND gate is connected to the output terminal of the seventh inverter. The second input terminal of the sixth AND gate is used to receive an enable signal. The output terminal of the sixth AND gate is connected to the input terminal of the second delay module. The output terminal of the second delay module is connected to the reset terminal of the fourth D flip-flop.

[0027] In one or more embodiments of the present invention, the signal detection circuit further includes a shaping unit. The shaping unit is used to perform shaping on the PING signal and output it.

[0028] The present invention also discloses a signal detection method. Based on the signal detection circuit described above, the signal detection method includes:

[0029] Using a first logic unit to generate an enable characterization signal representing the length of the level to be measured of the PING signal based on the PING signal and the enable signal;

[0030] Using an edge detection control unit to perform edge detection on the PING signal based on the enable characterization signal, and output a clock signal within the valid level of the enable characterization signal based on the detection result control;

[0031] Using a counting unit to perform periodic counting on the clock signal output by the edge detection control unit based on its own output signal and a preset counting threshold within the valid level of the enable characterization signal, and output a counting signal;

[0032] Using a shift register unit to generate an indication signal representing whether the duration of the level to be measured of the PING signal reaches a target value based on the counting signal within the valid level of the enable characterization signal;

[0033] Using an output unit to output a level signal and / or a pulse signal based on the indication signal and the enable signal outside the valid level of the enable characterization signal.

[0034] In one or more embodiments of the present invention, the step of using a shift register unit to generate an indication signal representing whether the duration of the level to be measured of the PING signal reaches a target value based on the counting signal within the valid level of the enable characterization signal includes:

[0035] Using a plurality of connected third D flip - flops to perform shift output for each pulse signal in the counting signal within the valid level of the enable characterization signal;

[0036] Using a second processing unit to generate an indication signal based on the output value of the third D flip - flop.

[0037] Compared with the prior art, the signal detection circuit and the signal detection method of the present invention have both falling - edge and rising - edge detections. For PING signals that do not meet the index range, no level signal and / or pulse signal will be triggered. Signals without a falling edge or a rising edge will not trigger a level signal and / or a pulse signal either, thus solving the problem of power - on mis - triggering. The present invention integrates each unit into a module, and can output two types of flag signals, namely pulse and level signals, without additional digital processing logic, improving the modularity of the circuit and reducing the complexity of the subsequent circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0039] Figure 1 It is a waveform diagram of the PING signal in the prior art.

[0040] Figure 2 It is a circuit schematic diagram of the signal detection circuit in the prior art.

[0041] Figure 3 It is a circuit schematic diagram of the signal detection circuit in an embodiment.

[0042] Figure 4 It is a circuit schematic diagram of the shaping unit, the first delay processing unit, and the second delay processing unit in an embodiment.

[0043] Figure 5 It is a circuit schematic diagram of the first logic unit in an embodiment.

[0044] Figure 6 It is a circuit schematic diagram of the edge detection control unit in an embodiment.

[0045] Figure 7 It is a circuit schematic diagram of the counting unit in an embodiment.

[0046] Figure 8 It is a circuit schematic diagram of the second logic unit in an embodiment.

[0047] Figure 9 It is a circuit schematic diagram of the first processing unit in an embodiment.

[0048] Figure 10 It is a circuit schematic diagram of the shift register unit in an embodiment.

[0049] Figure 11 It is a circuit schematic diagram of the second processing unit in an embodiment.

[0050] Figure 12 It is a circuit schematic diagram of the third processing unit in an embodiment.

[0051] Figure 13 It is a waveform diagram of the outputs of each unit in an embodiment. Detailed implementation manners

[0052] To enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0053] In the specification, "coupled" or "connected" or "linked" includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches, follower circuits, etc. Additionally, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0054] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting.

[0055] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations can be performed in an order different from the presented order. The described operations can be performed in an order different from the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0056] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0057] Various components and devices can be mentioned or shown in the singular form herein (e.g., "transistor", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element mentioned in the singular form can include a plurality of such elements according to the teachings herein.

[0058] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. Additionally, the terms "comprising", "including", "having", etc., used with respect to the embodiments of the present disclosure are synonymous.

[0059] As Figure 3 shown, a signal detection circuit in an embodiment of the present invention includes: a shaping unit 10, a first logic unit 20, a first delay processing unit 30, an edge detection control unit 40, a counting unit 50, a shift register unit 60, and an output unit 70.

[0060] Among them, the shaping unit 10 is used to perform initial shaping and output of the PING signal. In other embodiments, the shaping unit 10 may not be provided either.

[0061] The first logic unit 20 is used to receive the shaped PING signal and the enable signal EN, and generate an enable characterization signal ENB representing the length of the level to be measured of the PING signal based on the PING signal and the enable signal EN.

[0062] The first delay processing unit 30 is used to perform delay processing and output of the shaped PING signal. In other embodiments, when signal delay is not required, the first delay processing unit 30 may not be provided either.

[0063] The edge detection control unit 40 is used to receive the shaped and delayed PING signal, the enable characterization signal ENB, and the clock signal CLK, perform edge detection on the PING signal based on the enable characterization signal ENB, and output a clock signal CLK' within the valid level of the enable characterization signal ENB based on the detection result control.

[0064] In one embodiment, when the falling edge of the PING signal arrives, the enable characterization signal ENB also jumps to the valid level after a certain time. At this time, the edge detection control unit 40 transmits the clock signal CLK under the control of the valid level of the enable characterization signal ENB. When the rising edge of the PING signal arrives, the enable characterization signal ENB also jumps to the invalid level after a certain time. The edge detection control unit 40 outputs a fixed level under the control of the invalid level of the enable characterization signal ENB. A section of the clock signal CLK output by the edge detection control unit 40 during the period when the enable characterization signal ENB is at the valid level is the clock signal CLK'. This enables the duration of the clock signal CLK' to represent the duration of the low level of the PING signal, facilitating subsequent circuits to detect whether the duration of the low level of the PING signal meets the requirements through the clock signal CLK'.

[0065] The counting unit 50 is used to receive the enable characterization signal ENB and is connected to the edge detection control unit 40, so as to perform periodic counting on the clock signal CLK output by the edge detection control unit 40 based on its own output signal and a preset counting threshold within the valid level of the enable characterization signal ENB, and output a counting signal E.

[0066] The shift register unit 60 is used to receive the enable characterization signal ENB and the counting signal E, so as to generate an indication signal F for characterizing whether the maintained time of the level to be measured of the PING signal reaches the target value based on the counting signal E within the valid level of the enable characterization signal ENB.

[0067] The output unit 70 is used to receive the enable characterization signal ENB, the indication signal F, and the enable signal EN, so as to output a level signal P and a pulse signal S based on the indication signal F and the enable signal EN outside the valid level of the enable characterization signal ENB.

[0068] Further, as Figure 4 shown, the shaping unit 10 includes a first resistor R1, a first capacitor C1, and a Schmitt trigger T1. The first end of the first resistor R1 is used to receive the PING signal. The first end of the first capacitor C1 is connected to the second end of the first resistor R1 and the input end of the Schmitt trigger T1. The output end of the Schmitt trigger T1 is used to output the shaped PING signal. In other embodiments, the shaping unit 10 may be other circuit structures.

[0069] As Figure 5 shown, the first logic unit 20 includes a first inverter NV1 and a first AND gate AND1. The input end of the first inverter NV1 is used to receive the shaped PING signal. The first input end of the first AND gate AND1 is connected to the output end of the first inverter NV1. The second input end of the first AND gate AND1 is used to receive the enable signal EN. The output end of the first AND gate AND1 is used to output the enable characterization signal ENB. When the shaped PING signal is at a low level and the enable signal EN is at a high level, the first logic unit 20 outputs a high-level enable characterization signal ENB. When the shaped PING signal is at a high level, the first logic unit 20 outputs a low-level enable characterization signal ENB. The length of the level to be measured of the PING signal is the low-level length. When the PING signal is at a low level, the enable characterization signal ENB is at a high level, and this high level is also the valid level of the enable characterization signal ENB. In other embodiments, according to the different high and low levels of the detected PING signal, the first logic unit 20 may also be other circuit structures. For example, the first inverter NV1 may not be provided, such that the low level is the valid level of the enable characterization signal ENB.

[0070] In one embodiment, the structure of the first delay processing unit 30 may be the same as the circuit structure of the shaping unit 10. In other embodiments, the first delay processing unit 30 may also have other circuit structures.

[0071] As Figure 6 shown, the edge detection control unit 40 includes a second inverter NV2, a first D flip-flop D1, and a selector X. The input terminal of the second inverter NV2 is connected to the first delay processing unit 30 to receive the shaped and delay-processed PING signal. The output terminal of the second inverter NV2 is connected to the clock input terminal of the first D flip-flop D1. The D input terminal of the first D flip-flop D1 is used to receive the first reference level signal "1". In one embodiment, the first reference level signal is a high-level signal. The reset terminal RN of the first D flip-flop D1 is used to receive the enable characterization signal ENB. The output terminal Q of the first D flip-flop D1 is connected to the control terminal of the selector X. The first input terminal of the selector X is used to receive the second reference level signal. In one embodiment, the second reference level signal is a low-level signal "0". The second input terminal of the selector X is used to receive the clock signal CLK. The output terminal of the selector X is connected to the counting unit 50. The first D flip-flop D1 performs edge detection on the PING signal. At the falling edge of the PING signal, the first D flip-flop D1 outputs a signal based on the enable characterization signal ENB to control the connection between the second input terminal and the output terminal of the selector X to output the clock signal CLK'.

[0072] In other embodiments, according to the different levels to be measured of the PING signal, the second inverter NV2 may not be provided.

[0073] The counting unit 50 includes a plurality of second D flip-flops, a second logic unit, and a first processing unit 51. The D input terminal, the clock input terminal, and the second output terminal of the second D flip-flop are connected. The second output terminals and the clock input terminals of adjacent two second D flip-flops are connected to achieve the series connection of the plurality of second D flip-flops. The clock input terminal of the first second D flip-flop is connected to the edge detection control unit 40. The second logic unit is connected to the first output terminal of the second D flip-flop. The second logic unit outputs a counting signal E based on the output values of the first output terminals of the respective second D flip-flops. The first processing unit 51 is used to generate a first reset signal O1 for resetting the second D flip-flop based on the enable characterization signal ENB and the counting signal E.

[0074] In one embodiment, as Figure 7As shown, the counting unit 50 includes three second D flip - flops D2. The clock input terminal of the first second D flip - flop D2 is connected to the edge detection control unit 40 to receive the clock signal output by the edge detection control unit 40. The first input terminal D, the clock input terminal, and the second output terminal QN of each second D flip - flop D2 are connected. The clock input terminal of the second second D flip - flop D2 is connected to the second output terminal QN of the first second D flip - flop D2. The clock input terminal of the third second D flip - flop D2 is connected to the second output terminal QN of the second second D flip - flop D2.

[0075] As Figure 8 shown, the second logic unit includes a second AND gate AND2, a third inverter NV3, and a third AND gate AND3. The first input terminal W1 of the second AND gate AND2 is connected to the first output terminal Q of the first second D flip - flop D2. The second input terminal W2 of the second AND gate AND2 is connected to the first output terminal Q of the third second D flip - flop D2. The input terminal W3 of the third inverter NV3 is connected to the first output terminal Q of the second second D flip - flop D2. The first input terminal of the third AND gate AND3 is connected to the output terminal of the second AND gate AND2. The second input terminal of the third AND gate AND3 is connected to the output terminal of the third inverter NV3. The output terminal of the third AND gate AND3 is connected to the shift register unit 60 to output a counting signal E.

[0076] As Figure 9 shown, the first processing unit 51 includes a fourth AND gate AND4, a first delay module dy1, and a fourth inverter NV4. The input terminal of the fourth inverter NV4 is used to receive the counting signal E. The output terminal of the fourth inverter NV4 is connected to the input terminal of the first delay module dy1. The first input terminal of the fourth AND gate AND4 is connected to the output terminal of the first delay module dy1. The second input terminal of the fourth AND gate AND4 is used to receive an enable characterization signal ENB. The output terminal of the fourth AND gate AND4 is connected to the reset terminals RN of the three second D flip - flops D2. The output terminal of the fourth AND gate AND4 outputs a first reset signal O1 to the reset terminals RN of the second D flip - flops D2.

[0077] In other embodiments, according to the different active levels or active transition edges of the reset signal of the second D flip - flop D2, the fourth inverter NV4 may not be provided; in the case where there is no delay requirement, the first delay module dy1 may also not be provided.

[0078] The shift register unit 60 includes a plurality of third D flip - flops D3, a second delay processing unit 61, and a second processing unit 62. The clock input terminal of the third D flip - flop D3 is used to receive a count signal E. The second delay processing unit 61 is used to receive an enable characterization signal and is connected to the reset terminal of the third D flip - flop D3. The output terminals of two adjacent third D flip - flops D3 are connected to the D input terminals. The D input terminal of the first third D flip - flop D3 is used to receive a first reference level signal. The second processing unit 62 generates an indication signal F based on the output value of the output terminal of the third D flip - flop D3. In other embodiments, when there is no delay requirement, the second delay processing unit 61 may not be provided.

[0079] In one embodiment, as Figure 10 shown, the shift register unit 60 includes three third D flip - flops D3. The clock input terminal of each third D flip - flop D3 is used to receive a count signal E. The D input terminal of the first third D flip - flop D3 is used to receive a first reference level signal. In one embodiment, the first reference level signal is a high - level signal "1". The output terminal Q of the first third D flip - flop D3 is connected to the D input terminal of the second third D flip - flop D3. The output terminal Q of the second third D flip - flop D3 is connected to the D input terminal of the third third D flip - flop D3.

[0080] The structure of the second delay processing unit 61 may be the same as the circuit structure of the shaping unit 10. The input terminal of the second delay processing unit 61 is used to receive an enable characterization signal ENB. The output terminal of the second delay processing unit 61 is connected to the reset terminals RN of the third D flip - flops D3 to supply a second reset signal O2 to the third D flip - flops D3. In other embodiments, the second delay processing unit 61 may also be other circuit structures.

[0081] As Figure 11 shown, the second processing unit 62 includes a fifth inverter NV5 and a fifth AND gate AND5. The first input terminal V1 of the fifth AND gate AND5 is connected to the output terminal Q of the first third D flip - flop D3. The input terminal V3 of the fifth inverter NV5 is connected to the output terminal Q of the third third D flip - flop D3. The output terminal of the fifth inverter NV5 is connected to the second input terminal of the fifth AND gate AND5. The output terminal of the fifth AND gate AND5 is connected to the output unit 70 to output an indication signal F.

[0082] As Figure 3As shown, the output unit 70 includes a sixth inverter NV6, a fourth D flip-flop D4, a third processing unit 71, and a fifth D flip-flop D5. The input terminal of the sixth inverter NV6 is used to receive the enable characterization signal ENB. The output terminal of the sixth inverter NV6 is connected to the clock input terminal of the fourth D flip-flop D4. The D input terminal of the fourth D flip-flop D4 is connected to the counting unit 50. The third processing unit 71 is used to receive the enable signal EN and is connected to the output terminal and the reset terminal of the fourth D flip-flop D4 to generate a third reset signal O3 for resetting the fourth D flip-flop D4 based on the enable signal EN and the signal at the output terminal of the fourth D flip-flop D4. The output terminal Q of the fourth D flip-flop D4 is used to output a pulse signal S. The clock input terminal of the fifth D flip-flop D5 is connected to the output terminal RN of the fourth D flip-flop D4. The D input terminal of the fifth D flip-flop D5 is used to receive a first reference level signal. In one embodiment, the first reference level signal is a high-level signal "1". The fourth D flip-flop D4 is a pulse register, and the fifth D flip-flop D5 is a shift register. The reset terminal RN of the fifth D flip-flop D5 is used to receive a reset signal CLR. The output terminal of the fifth D flip-flop D5 is used to output a level signal P.

[0083] In other embodiments, the fifth D flip-flop D5 may not be provided. In this case, only the pulse signal S is output. Of course, when the fifth D flip-flop D5 is provided, the level signal P can also be obtained only as needed.

[0084] As Figure 12 shown, the third processing unit 71 includes a sixth AND gate AND6, a seventh inverter NV7, and a second delay module dy2. The input terminal of the seventh inverter NV7 is connected to the output terminal RN of the fourth D flip-flop D4 to receive the pulse signal S. The first input terminal of the sixth AND gate AND6 is connected to the output terminal of the seventh inverter NV7. The second input terminal of the sixth AND gate AND6 is used to receive the enable signal EN. The output terminal of the sixth AND gate AND6 is connected to the input terminal of the second delay module dy2. The output terminal of the second delay module dy2 is connected to the reset terminal RN of the fourth D flip-flop D4. The second delay module dy2 outputs the third reset signal O3 to the fourth D flip-flop D4.

[0085] In other embodiments, according to the different active levels of the reset signal of the fourth D flip-flop D4, the seventh inverter NV7 may not be provided. If there is no delay requirement, the second delay module dy2 may also not be provided.

[0086] This embodiment also discloses a signal detection method. Based on the above signal detection circuit, the signal detection method includes:

[0087] Generating, by a first logic unit, an enable characterization signal ENB representing the length of the level to be measured of the PING signal based on the PING signal and the enable signal EN.

[0088] The edge detection control unit 40 performs edge detection on the PING signal based on the enable characterization signal ENB, and outputs a clock signal CLK' within the valid level of the enable characterization signal ENB based on the detection result control.

[0089] The counting unit 50 performs periodic counting on the clock signal CLK output by the edge detection control unit 40 based on its own output signal and a preset counting threshold within the valid level of the enable characterization signal ENB, and outputs a counting signal E.

[0090] The shift register unit 60 generates an indication signal F for characterizing whether the duration of the level to be measured of the PING signal reaches a target value within the valid level of the enable characterization signal ENB based on the counting signal E.

[0091] In an embodiment, a plurality of connected third D flip-flops D3 perform shift output for each pulse signal in the counting signal E within the valid level of the enable characterization signal ENB; the second processing unit 62 generates an indication signal F based on the output value of the third D flip-flop D3.

[0092] The output unit 70 outputs a level signal P and a pulse signal S based on the indication signal F and the enable signal EN outside the valid level of the enable characterization signal ENB. Figure 13 And Figures 3 to 12 As shown in Figure 13 , PING' is the signal output by the shaping unit 10 after shaping the PING signal, PING" is the signal output by the first delay processing unit 30 after delaying the PING' signal, CLK' is the signal output by the edge detection control unit 40, and [0:n] corresponds to the output values of three D flip-flops D3.

[0093] Specifically, the PING signal input and the clock signal CLK are asynchronous logics. The PING signal first passes through the shaping unit 10 to remove glitches and interference in the signal input, and a stable PING' signal is obtained. This signal performs a logic operation with the enable signal EN at the first logic unit 20 to obtain the enable characterization signal ENB.

[0094] In the first logic unit 20, when the enable EN is 0, the PING signal cannot be input to the subsequent circuit. When EN is 1, the PING signal can be input to the subsequent circuit. And when the enable signal EN is 0 or the PING signal is 1, the enable characterization signal ENB is 0, and the edge detection control unit 40, the counting unit 50, and the shift register unit 60 are in a reset state, and the output level is fixed.

[0095] When the PING signal is 0 and the enable signal EN is 1, the circuit starts to work, the enable characterization signal ENB is 1, and the edge detection control unit 40, the counting unit 50, and the shift register unit 60 are released from the reset state and enter the working state.

[0096] To prevent mis-triggering when the PING signal jumps from low level to high level, the edge detection control unit 40 is set to perform falling edge detection. When the enable characterization signal ENB jumps to high level, the edge detection control unit 40 is released from reset. The falling edge of the PING' signal is delayed by the first delay processing unit 30 to generate the PING" signal, and the falling edge detection is started. The clock signal CLK can then be output through the edge detection control unit 40 to drive the counting unit 50. By setting the first delay processing unit 30, the release of the reset of the edge detection control unit 40 can be advanced in time before the arrival of the falling edge of the PING" signal.

[0097] The counting unit 50 starts to count after receiving the clock signal CLK'. The counting threshold is determined by the design specifications. When the count reaches the preset counting threshold, the counting unit 50 outputs a high-level counting signal E. In one embodiment, the preset counting threshold is 5. After 5 cycles of the clock signal CLK', the output value of the output terminal Q of the first second D flip-flop D2 is 1, the output value of the output terminal Q of the second second D flip-flop D2 is 0, and the output value of the output terminal Q of the third second D flip-flop D2 is 1. The second logic unit outputs a high-level counting signal E. The high-level counting signal E is output as a low-level first reset signal O1 after passing through the first processing unit 51, which resets each second D flip-flop D2 of the counting unit 50 again. Therefore, the counting signal E will be pulled low again after the delay time of the first processing unit 51 after being pulled high, forming a pulse output. After the counting signal E is pulled low, the counting unit 50 is released from reset again and starts counting again. The counting signal E forms a periodic pulse, that is, when the enable characterization signal ENB is 1 and the PING signal is 0, the counting signal E is a signal that continuously generates pulses.

[0098] Three third D flip-flops D3 form a flip-flop string. The D input terminal of the first third D flip-flop D3 is fixed to logic 1. The clock input terminal of the third D flip-flop D3 receives the counting signal E. Each time a pulse signal of the counting signal E is received, each third D flip-flop D3 increments by 1. For example, after the three third D flip-flops D3 are reset, the logic of each output terminal Q is 000. After receiving one pulse signal, it is 100. After receiving two pulse signals, it is 110. Finally, the output value is directly output to the second processing unit 62.

[0099] The second processing unit 62 determines whether the output value of the flip-flop string is within a specified range. Since the PING signal is a high-low-high signal, the duration of the low level should be within the specified range. Then, when the enabling characterization signal ENB is 1, the number of pulses received by the flip-flop string should also be within a certain range. If it is lower or exceeds the range, 1 cannot be output. In one embodiment, based on the length of the low level of the PING signal, the counting signal E generates two pulses, the output value of the flip-flop string is 110, and the second processing unit 62 outputs a high-level indication signal F, thereby detecting the PING signal that meets the standard (for example, the index of 2 ms to 5 ms).

[0100] The D input terminal of the fourth D flip-flop D4 receives a high-level indication signal F when the low level of the PING signal meets the range. When a rising edge transition occurs in the PING signal, the fourth D flip-flop D4 is triggered to output a high-level signal, and the fourth D flip-flop D4 is reset by the third reset signal O3 generated by the third processing unit 71, and the high-level signal becomes a low level again, thereby generating a pulse signal S whose pulse width is related to the delay time of the third processing unit 71.

[0101] The pulse signal S itself can be used as a pulse output, and at the same time, it can be converted into a stable level signal P through the fifth D flip-flop D5 for output. Both outputs can be used as flag signals indicating whether a PING signal command is received. The fifth D flip-flop D5 has a separate reset signal CLR. Since the duration of the level depends on the actual requirements of the subsequent circuit, the reset signal CLR is given when the subsequent circuit needs to clear the level output, and it is not automatically reset. The fifth D flip-flop D5 can be set in a circuit that does not require a level. The second delay processing unit 61 is to ensure that when the fourth D flip-flop D4 is triggered by the rising edge of the PING signal, the D input terminal of the fourth D flip-flop D4 can maintain a stable value.

[0102] After the PING signal changes from low to high, the edge detection control unit 40, the counting unit 50, and the shift register unit 60 re-enter the reset state. When the next PING signal arrives, the circuit is triggered to detect again. If the effective level width of the PING signal meets the index requirements, the pulse signal S and the level signal P can be sent again to meet the requirements of multiple detections.

[0103] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0104] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A signal detection circuit, characterized in that: include: A first logic unit, configured to receive a PING signal and an enable signal, and generate an enable characterization signal characterizing a length of a level to be measured of the PING signal based on the PING signal and the enable signal; An edge detection control unit, configured to receive a PING signal, an enable characterization signal, and a clock signal, perform edge detection on the PING signal based on the enable characterization signal, and output a clock signal within a valid level of the enable characterization signal based on the control of the detection result; A counting unit, used to receive the enable characterization signal and connected to the edge detection control unit, so as to periodically count the clock signal output by the edge detection control unit based on the signal output by the counting unit and a preset counting threshold within the effective level of the enable characterization signal and output a counting signal; A shift register unit, used for receiving an enable characterization signal and a counting signal, so as to generate an indication signal for indicating whether the level maintenance time to be measured of the PING signal reaches a target value based on the counting signal within the effective level of the enable characterization signal; as well as The output unit is used to receive the enable characterization signal, the indication signal and the enable signal, so as to output a level signal and / or a pulse signal based on the indication signal and the enable signal in addition to the effective level of the enable characterization signal.

2. The signal detection circuit according to claim 1, characterized in that: The signal detection circuit further includes a first delay processing unit, which is used to receive a PING signal and is connected to the edge detection control unit to transmit the delayed PING signal to the edge detection control unit.

3. The signal detection circuit according to claim 1, characterized in that: The edge detection control unit includes a first D flip-flop and a selector, the clock input end of the first D flip-flop is used to receive a PING signal, the D input end of the first D flip-flop is used to receive a first reference level signal, the reset end of the first D flip-flop is used to receive an enable characterization signal, the output end of the first D flip-flop is connected to the control end of the selector, the first input end of the selector is used to receive a second reference level signal, the second input end of the selector is used to receive a clock signal, and the output end of the selector is connected to a counting unit; or The edge detection control unit includes a second inverter, a first D flip-flop and a selector, the input end of the second inverter is used to receive a PING signal, the output end of the second inverter is connected to the clock input end of the first D flip-flop, the D input end of the first D flip-flop is used to receive a first reference level signal, the reset end of the first D flip-flop is used to receive an enable characterization signal, the output end of the first D flip-flop is connected to the control end of the selector, the first input end of the selector is used to receive a second reference level signal, the second input end of the selector is used to receive a clock signal, and the output end of the selector is connected to a counting unit.

4. The signal detection circuit according to claim 1, characterized in that: The counting unit includes a plurality of second D flip-flops, a second logic unit and a first processing unit. The D input terminal, the clock input terminal and the second output terminal of the second D flip-flops are connected. The second output terminals and the clock input terminal of two adjacent second D flip-flops are connected. The clock input terminal of the first second D flip-flop is connected to an edge detection control unit. The second logic unit is connected to the first output terminal of the second D flip-flop. The second logic unit outputs a counting signal based on the output value of the first output terminal of each second D flip-flop. The first processing unit is used to generate a first reset signal for resetting the second D flip-flop based on an enable characterization signal and a counting signal.

5. The signal detection circuit according to claim 4, characterized in that: The counting unit includes three second D flip-flops, the second logic unit includes a second AND gate, a third inverter and a third AND gate, the first input terminal and the second input terminal of the second AND gate are connected to the first output terminal of the first second D flip-flop and the first output terminal of the third second D flip-flop, the input terminal of the third inverter is connected to the first output terminal of the second second D flip-flop, the first input terminal and the second input terminal of the third AND gate are connected to the output terminal of the second AND gate and the output terminal of the third inverter, and the output terminal of the third AND gate is connected to the shift register unit.

6. The signal detection circuit according to claim 4, characterized in that: The first processing unit includes a fourth AND gate, a first input end of the fourth AND gate is used to receive a counting signal, a second input end of the fourth AND gate is used to receive an enable characterization signal, and an output end of the fourth AND gate is connected to a reset end of the second D flip-flop; or The first processing unit includes a fourth AND gate and a first delay module, the input end of the first delay module is used to receive a counting signal, the first input end of the fourth AND gate is connected to the output end of the first delay module, the second input end of the fourth AND gate is used to receive an enable characterization signal, and the output end of the fourth AND gate is connected to the reset end of the second D flip-flop; or The first processing unit includes a fourth AND gate and a fourth inverter, the input end of the fourth inverter is used to receive a counting signal, the first input end of the fourth AND gate is connected to the output end of the fourth inverter, the second input end of the fourth AND gate is used to receive an enable characterization signal, and the output end of the fourth AND gate is connected to the reset end of the second D flip-flop; or The first processing unit includes a fourth AND gate, a first delay module and a fourth inverter, the input end of the fourth inverter is used to receive a counting signal, the output end of the fourth inverter is connected to the input end of the first delay module, the first input end of the fourth AND gate is connected to the output end of the first delay module, the second input end of the fourth AND gate is used to receive an enable characterization signal, and the output end of the fourth AND gate is connected to the reset end of the second D flip-flop.

7. The signal detection circuit according to claim 1, characterized in that: The shift register unit includes a plurality of third D flip-flops and a second processing unit, wherein a clock input terminal of the third D flip-flops is used to receive a counting signal, a reset terminal of the third D flip-flops is used to receive an enable characterization signal, output terminals of two adjacent third D flip-flops are connected to a D input terminal, a D input terminal of the first third D flip-flop is used to receive a first reference level signal, and the second processing unit generates an indication signal based on an output value of an output terminal of the third D flip-flop; or The shift register unit includes a plurality of third D flip-flops, a second processing unit and a second delay processing unit, wherein the clock input terminal of the third D flip-flop is used to receive a counting signal, the second delay processing unit is used to receive an enable characterization signal and is connected to a reset terminal of the third D flip-flop, the output terminals of two adjacent third D flip-flops are connected to a D input terminal, the D input terminal of the first third D flip-flop is used to receive a first reference level signal, and the second processing unit generates an indication signal based on an output value of the output terminal of the third D flip-flop.

8. The signal detection circuit according to claim 7, characterized in that: The shift register unit includes three third D flip-flops, the second processing unit includes a fifth inverter and a fifth AND gate, the first input end of the fifth AND gate is connected to the output end of the first third D flip-flop, the input end of the fifth inverter is connected to the output end of the third third D flip-flop, the output end of the fifth inverter is connected to the second input end of the fifth AND gate, and the output end of the fifth AND gate is connected to the output unit.

9. The signal detection circuit according to claim 1, characterized in that: The output unit includes a sixth inverter, a fourth D flip-flop and a third processing unit, the input end of the sixth inverter is used to receive an enable characterization signal, the output end of the sixth inverter is connected to the clock input end of the fourth D flip-flop, the D input end of the fourth D flip-flop is connected to the counting unit, the third processing unit is used to receive the enable signal, and is connected to the output end and the reset end of the fourth D flip-flop to generate a second reset signal for resetting the fourth D flip-flop based on the enable signal and the signal of the output end of the fourth D flip-flop, and the output end of the fourth D flip-flop is used to output a pulse signal; or The output unit includes a sixth inverter, a fourth D flip-flop, a third processing unit and a fifth D flip-flop, the input end of the sixth inverter is used to receive an enable characterization signal, the output end of the sixth inverter is connected to the clock input end of the fourth D flip-flop, the D input end of the fourth D flip-flop is connected to the counting unit, the third processing unit is used to receive an enable signal, and is connected to the output end and the reset end of the fourth D flip-flop to generate a second reset signal for resetting the fourth D flip-flop based on the enable signal and the signal at the output end of the fourth D flip-flop, the output end of the fourth D flip-flop is used to output a pulse signal, the clock input end of the fifth D flip-flop is connected to the output end of the fourth D flip-flop, the D input end of the fifth D flip-flop is used to receive a first reference level signal, and the output end of the fifth D flip-flop is used to output a level signal.

10. The signal detection circuit according to claim 9, characterized in that: The third processing unit includes a sixth AND gate, a first input terminal of the sixth AND gate is connected to the output terminal of the fourth D flip-flop, a second input terminal of the sixth AND gate is used to receive an enable signal, and an output terminal of the sixth AND gate is connected to a reset terminal of the fourth D flip-flop; or The third processing unit includes a sixth AND gate and a seventh inverter, the input end of the seventh inverter is connected to the output end of the fourth D flip-flop, the first input end of the sixth AND gate is connected to the output end of the seventh inverter, the second input end of the sixth AND gate is used to receive an enable signal, and the output end of the sixth AND gate is connected to the reset end of the fourth D flip-flop; or The third processing unit includes a sixth AND gate and a second delay module, the first input end of the sixth AND gate is connected to the output end of the fourth D flip-flop, the second input end of the sixth AND gate is used to receive an enable signal, the output end of the sixth AND gate is connected to the input end of the second delay module, and the output end of the second delay module is connected to the reset end of the fourth D flip-flop; or The third processing unit includes a sixth AND gate, a seventh inverter and a second delay module, the input end of the seventh inverter is connected to the output end of the fourth D flip-flop, the first input end of the sixth AND gate is connected to the output end of the seventh inverter, the second input end of the sixth AND gate is used to receive an enable signal, the output end of the sixth AND gate is connected to the input end of the second delay module, and the output end of the second delay module is connected to the reset end of the fourth D flip-flop.

11. The signal detection circuit according to claim 1 or 2, characterized in that: The signal detection circuit further comprises a shaping unit, and the shaping unit is used for shaping and outputting the PING signal.

12. A signal detection method, characterized in that: Based on the signal detection circuit according to any one of claims 1 to 11, the signal detection method comprises: Generate an enable characterization signal characterizing the length of the level to be measured of the PING signal based on the PING signal and the enable signal by a first logic unit; Perform edge detection on the PING signal based on the enable characterization signal through the edge detection control unit, and output the clock signal within the effective level of the enable characterization signal based on the control of the detection result; The counting unit periodically counts the clock signal output by the edge detection control unit based on the signal output by the counting unit and a preset counting threshold within the effective level of the enable characterization signal to output a counting signal; Generates, through the shift register unit, an indication signal for indicating whether the level maintenance time to be measured of the PING signal reaches a target value based on the counting signal within the effective level of the enabling characterization signal; In addition to enabling the effective level of the characterization signal, the output unit outputs a level signal and / or a pulse signal based on the indication signal and the enable signal.

13. The signal detection method according to claim 12, characterized in that: The step of generating an indication signal for indicating whether the measured level maintenance time of the PING signal reaches a target value based on the counting signal by the shift register unit within the effective level of the enabling characterization signal comprises: By using a plurality of connected third D flip-flops, within the effective level of the enable characterization signal, each pulse signal in the counting signal is shifted and output; An indication signal is generated by the second processing unit based on the output value of the third D flip-flop.

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