Multi-channel neural signal acquisition circuit and control method thereof

Abstract

The invention discloses a multichannel neural signal acquisition circuit and a control method thereof, the multichannel neural signal acquisition circuit comprises a plurality of sampling channels, the input end of each sampling channel is connected with an analog-to-digital converter, the output end of each sampling channel is provided with a group of shift registers, the analog-to-digital converter stores a conversion result and verification information into the shift registers together, and the analog-to-digital converter stores the conversion result and the verification information into the shift registers. The shift registers in the same row are connected together, and each sampling channel directly forms daisy chain type connection; an output shift register is arranged at the last of each row of daisy chains, and data of each row are converted into serial data from parallel data in a shift mode and then output. According to the multichannel neural signal acquisition circuit and the control method thereof provided by the invention, a group of shift registers are arranged at the output end of each sampling channel, and data in each row are converted from parallel to serial through a shift mode and then are output, so that the number of channels can be conveniently modified, circuit splicing is easy to realize, the realization mode is simple, and data verification is realized.

Description

Technical Field

[0001] The present invention relates to a collection circuit and a control method thereof, and particularly to a multi-channel neural signal collection circuit and a control method thereof. Background Art

[0002] In a multi-channel neural signal collection circuit, there are often situations where up to 256 channels or even higher channel numbers are collected simultaneously. A single neural signal collection circuit, as Figure 1 shown, its function is to convert an input analog signal into a digital signal.

[0003] The increase in the number of channels causes the amount of data to be transmitted to increase in the same proportion after each data collection. For example, a 16-channel, single-channel 12-bit neural signal collection circuit needs to transmit at least 16×12 = 192 bits of data for each conversion, and a 256-channel circuit using the same collector needs to transmit at least 256×12 = 3072 bits of data. The increase in the number of channels will cause the following problems:

[0004] 1. How to determine the start and end positions of the transmitted data? That is, where the data starts and where it ends.

[0005] 2. If an error occurs during the data transmission process, resulting in an increase or decrease in the number of data bits, can the lower computer detect it when receiving?

[0006] 3. Can the number of channels M and the number of bits N of a single channel be increased or decreased through a simple circuit to flexibly set the number of channels?

[0007] The traditional data transmission scheme is implemented by adding an encoding circuit during the data transmission stage, as Figure 2 shown; the data after the sampling channel conversion first enters the digital encoding circuit, and the encoding circuit adds redundancy to the data so that the lower computer can parse the data.

[0008] Such a scheme solves the above two problems, but the digital encoding circuit can only be designed for a specific number of channels and cannot adapt automatically when the number of channels is modified. At the same time, the digital encoding circuit itself consumes a certain amount of power and area. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a multi-channel neural signal collection circuit and a control method thereof, which can conveniently modify the number of channels, are easy to implement circuit splicing, have a simple implementation method and carry data verification.

[0010] The technical solution adopted by the present invention to solve the above technical problems is to provide a multi-channel neural signal acquisition circuit, including multiple sampling channels. Among them, the input end of each sampling channel is connected to an analog-to-digital converter, and a set of shift registers is arranged at the output end of each sampling channel. The analog-to-digital converter stores the conversion result and a check information into the shift register together. The shift registers in the same row are connected together, and each sampling channel forms a daisy-chain connection directly; at the end of each row of the daisy chain, there is an output shift register, which outputs the data of each row from parallel to serial by shifting.

[0011] Further, a low-noise amplifier and a band-pass filter are connected in front of the analog-to-digital converter of each sampling channel.

[0012] Further, the number of sampling channels ≥ 256.

[0013] The present invention also provides a control method for the above multi-channel neural signal acquisition circuit to solve the above technical problems. Among them, it includes the following steps: S1) Connect the output ends of M daisy-chain-connected sampling channels to the shift register, and add a check row above the first row; S2) When data is transmitted, first read the data on the rightmost side of each row. After reading, the numbers in each row are shifted one bit to the right, and then output in turn; S3) After transmitting n×(M + 1) bits of data, transmit M + 1 fixed high levels, where n is the number of bits of the analog-to-digital converter; S4) The lower computer judges the end or start of reading data by judging that more than n×(M + 1) consecutive 0s are read.

[0014] Further, if the high level at the end of the data received by the lower computer becomes low level, it is determined that the transmitted data is in error.

[0015] Further, the value of M ≥ 256.

[0016] The present invention has the following beneficial effects compared with the prior art: The multi-channel neural signal acquisition circuit and its control method provided by the present invention set a set of shift registers at the output end of each sampling channel, and output the data of each row from parallel to serial by shifting, so that the number of channels can be easily modified, the circuit splicing is easy to implement, the implementation method is simple and data verification is carried. Description of the Drawings

[0017] Figure 1 It is a schematic block diagram of an existing single neural signal acquisition circuit;

[0018] Figure 2 It is a schematic diagram of adding an encoding circuit to an existing sampling channel;

[0019] Figure 3 It is a circuit diagram of a traditional multi-channel neural signal acquisition;

[0020] Figure 4 Schematic diagram of the multi-channel neural signal acquisition circuit structure of the present invention;

[0021] Figure 5 Schematic diagram of data transmission of the sampling channel of the present invention using a 6-bit ADC;

[0022] Figure 6 Schematic diagram of judging data transmission loss of the present invention;

[0023] Figure 7 Schematic diagram of the data output format of the multi-channel neural signal acquisition circuit of the present invention. Detailed implementation manners

[0024] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0025] For a neural signal acquisition circuit, there are often situations where there are more than 256 channels. All ADC conversion results must be stored at the position where the conversion channels are located immediately. It can be imagined that if a fully parallel scheme is used, 256 signal lines are required to connect all the data to a digital circuit, and then this digital circuit converts the data from parallel to serial. Such a large number of traces will occupy a large layout area.

[0026] The structure of a traditional multi-channel neural signal acquisition circuit is as Figure 3 shown (taking 32 channels as an example): 32 acquisition channels will be connected to the same ADC through a 32-to-1 analog multiplexer, and the conversion result is output through the digital logic in the ADC (either serially or in parallel). Such a structure is generally applied to neural signal acquisition circuits with less than 64 channels. This is mainly because: 1. When the number of channels increases to hundreds or thousands, the wiring of each channel connected to the multiplexer becomes difficult. 2. On the premise of ensuring the single-channel sampling rate (for example, 32 kSPS), when one ADC corresponds to 32 channels, a 32-fold sampling rate (1.024 MSPS) is required, which will make the design of the ADC difficult when the number of channels is more.

[0027] However, for neural signal acquisition applications, demands for 256 or even more than 1024 channels are not uncommon. Therefore, it is necessary to use the Figure 1 single-channel independent ADC scheme shown. This scheme solves the wiring and ADC design problems caused by the increase in the number of channels, but the subsequent problem is that the conversion results are scattered in the registers of each channel ADC.

[0028] To solve the problem that data is scattered in each register when using a multi-channel, multi-ADC structure neural signal acquisition circuit; please refer to Figure 4, for the original sampling channels of the multi-channel neural signal acquisition circuit provided by the present invention, a group of shift registers are added at their output ends. The analog-to-digital converter will store the conversion result and a check information together in the shift registers. When reading data, the shift registers in the same row will be connected together, and each channel directly forms a daisy-chain connection. There is an output shift register at the end of each daisy-chain connection of each row, and the data of each row is converted from parallel to serial by shifting and then output; thus providing a simple, efficient and flexible data transmission method for such neural signal acquisition circuits.

[0029] As Figure 4 shown in the circuit array, adding or reducing the sampling channels in a certain row or a certain column will not affect the normal output of data, and at the same time, simple data format checking can be achieved by means of the check bits. This data transmission method is particularly suitable for customizing neural signal acquisition chips with different channel numbers based on the already designed and spliceable neural signal acquisition circuits. And for the lower computer, the data format changes very little.

[0030] Figure 5 Taking a 6-bit analog-to-digital converter as an example to illustrate the output data format of each row: When the data starts to be output, the shift registers are connected in series in the order of Figure 5 , and the data output first is located on the right side. Figure 5 In Figure 5 , H represents high level and L represents low level. For applications with the number of channels ≤ 32, using this data output method can already meet most applications. Due to

[0031] the existence of the high-level bits in Figure 6 , when using a 6-bit ADC for the sampling channels, there will be no continuous 7 low levels in the output of the shift registers before the data transmission is completed. When the lower computer reads 7 continuous low levels, it represents the end of the data. Figure 6 At the same time, the high level at the fixed position can also simply check the correctness of the data. As

[0032] shown, due to some errors,

[0033] in Figure 7The method shown above connects the shift registers at the output ends in series and adds parity bits, which can be applied to data transmission with 256 or even 1024 channels. The following still takes the case where the sampling channels use 6-bit ADCs as an example. As Figure 7 shown, connect the output ends of M aforementioned daisy-chain-connected sampling channels to form a shift register (on the right side in the figure), and add a parity row above the first row, with the data in the parity row fixed. When transmitting data, first read the data at the rightmost of each row. After the reading is completed, the numbers in each row will shift one bit to the right, and then be output in sequence.

[0034] When transmitting data in the above data format, M + 1 fixed high levels will be transmitted for every 6×(M + 1) bits of data transmitted. The fixed M + 1 high levels here can help the lower computer verify the correctness of data transmission. At the same time, the lower computer can also judge the end (or start) of the data by judging that more than 6×(M + 1) consecutive 0s are read.

[0035] When transmitting data in the above data format, it is very easy to increase or decrease the number of rows and columns of channels. When the number of bits of the ADC is known, the method for the lower computer to judge the start and end of data can be compatible with different channel situations. In terms of circuit implementation, the entire circuit only needs to use a shift register with a simple structure to achieve.

[0036] The ADCs used in the sampling channels in the above example have 6 bits. In fact, the above data format can support data with higher bit numbers.

[0037] The present invention realizes a serial data output format with data verification, easy circuit splicing, and simple implementation method by reasonably setting the parity bits. When applying this format to a multi-channel neural signal acquisition circuit, it has the following advantages:

[0038] 1. It can be applied to data transmission with a very high number of channels. The more channels there are, the more obvious the advantages are; it is especially suitable for data transmission with the number of channels ≥256, or even 1024 channels.

[0039] 2. There is simple verification at the data output end, which is convenient for the lower computer to judge the validity of the data.

[0040] 3. It is simple to increase or decrease the number of channels. Just reduce the number of rows and columns of the channels. Since the channels are connected in a daisy chain, the output data will automatically adapt to the number of channels. The lower computer can judge the start and end of the data through the parity bits.

[0041] 4. The circuit structure is simple and only a shift register needs to be used.

[0042] Although the present invention has been disclosed above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the claims.

Claims

1. A multi-channel neural signal acquisition circuit, comprising multiple sampling channels, characterized in that: The input end of each sampling channel is connected to an analog-to-digital converter, and a group of shift registers are set at the output end of each sampling channel. The analog-to-digital converter stores the conversion result and a verification information in the shift register. The shift registers in the same row are connected together, and the sampling channels directly form a daisy chain connection; an output shift register is set at the end of each row of daisy chains, and the data of each row is converted from parallel to serial by shifting and then output.

2. The multi-channel neural signal acquisition circuit according to claim 1, characterized in that: A low noise amplifier and a band pass filter are connected before the analog to digital converter of each sampling channel.

3. The multi-channel neural signal acquisition circuit according to claim 1, characterized in that: The number of the sampling channels is ≥256.

4. A control method for a multi-channel neural signal acquisition circuit as claimed in claim 1, characterized in that: The steps include: S1) connecting the output ends of the M sampling channels connected in daisy chain to the shift register, and adding a check row above the first row; S2) When data is transmitted, the rightmost data of each row is read first, and after reading, the data of each row is shifted right by one position, and then output in sequence; S3) After each transmission of n×(M+1) bits of data, M+1 fixed high levels are transmitted, where n is the number of bits of the analog-to-digital converter; S4) The lower computer determines the end or beginning of the read data by judging whether more than n×(M+1) consecutive 0s are read.

5. The control method of the multi-channel neural signal acquisition circuit according to claim 4, characterized in that: If the high level at the end of the data received by the lower computer changes to a low level, it is determined that the transmitted data is wrong.

6. The control method of the multi-channel neural signal acquisition circuit according to claim 4, characterized in that: The value of M is ≥256.

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