Radio frequency receiver front-end circuit
By adopting current multiplexing and quadrature signal generation and transfer technologies in the front-end circuit of the RF receiver, the problems of large chip area, low current utilization rate and large power consumption of the RF receiver are solved, and a low power consumption and high integration RF receiver front-end system is realized.
Patent Information
- Application Number
- CN202510186797.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2025-06-17
AI Technical Summary
The front-end circuit chip area of existing RF receivers is large, the current utilization rate is low and the power consumption is large, making it difficult to extend the battery life of the device while ensuring stable communication.
The current multiplexing method is used to reduce the number of power supply branches, so that the DC current is shared in multiple modules, reduce the chip area, improve the current utilization rate, and transfer the quadrature signal generation to the radio frequency, avoiding the use of a divider circuit or a quadrature oscillator, and reducing the operating frequency and power consumption.
Current multiplexing in the same current path is realized, the number of current branches and overall power consumption is reduced, current utilization is improved, chip area and component redundancy is reduced, and the problem of large power consumption of the front-end circuit of the RF receiver is solved.
Smart Images
Figure CN120165716A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of radio frequency integrated circuit design, in particular to a radio frequency receiver front-end circuit. Background Art
[0002] In many short-range wireless communication application scenarios, the devices are usually very small and can only hold limited battery capacity. How to ensure stable communication while extending the battery life of the device to improve user experience is a key technical issue in this field, and reducing the power consumption of the RF front-end circuit is the key method to solve this technical problem.
[0003] At present, in the traditional low intermediate frequency receiver architecture widely used in the front end of low power RF receiver, circuit modules such as low noise amplifier (LNA), mixer (MIXER), phase-locked loop (PLL) are connected in a step-by-step cascade form. The signal is amplified by the LNA, mixed with the local oscillator signal (LO) generated by the phase-locked loop in the mixer, and the required intermediate frequency signal is generated by frequency conversion. Each circuit designed in this way requires a separate working current so that it can work in the required state according to its own design requirements to meet the requirements of indicators such as gain, bandwidth, noise figure and linearity. In the circuit design of the front end of this RF receiver, the current is limited to the current circuit module, and the utilization efficiency is low. Adding additional functional modules (such as dividing the PLL output by two to generate an orthogonal local oscillator) usually means adding additional current and generating additional consumption. This leads to problems such as large chip area of the front end circuit, low current utilization and high power consumption, which is very unfavorable for power-sensitive systems.
[0004] Based on this, there is an urgent need to design a front-end circuit that can avoid the use of a two-way frequency division circuit or simultaneously use an orthogonal oscillator, reduce the operating frequency, and reduce power consumption, so as to solve the problems of large chip area, low current utilization and high power consumption of the RF receiver front-end circuit in the prior art. Summary of the invention
[0005] The purpose of the present invention is to provide a front-end circuit of a radio frequency receiver, which adopts a current multiplexing method to reduce the number of power supply branches, so that the DC current is shared by multiple modules, reducing the chip area and improving the current utilization rate; and transferring the generation of orthogonal signals to the radio frequency, avoiding the use of a binary frequency division circuit or the use of an orthogonal oscillator at the same time, thereby reducing the operating frequency and power consumption; and solves the problems of large chip area, low current utilization rate and high power consumption of the front-end circuit of the radio frequency receiver in the prior art.
[0006] In order to achieve the above object, the present invention provides the following technical solutions:
[0007] The present invention provides a radio frequency receiver front-end circuit, which may include:
[0008] A first transimpedance amplifier, a second transimpedance amplifier, and a target stacked circuit structure; the target stacked circuit structure is a circuit formed by stacking an orthogonal low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator; the orthogonal low-noise amplifier, the double-balanced mixer, and the voltage-controlled oscillator share a current source;
[0009] The orthogonal low-noise amplifier is connected to the double-balanced mixer; the voltage-controlled oscillator is connected to the double-balanced mixer; the first transimpedance amplifier is connected to the double-balanced mixer, and the second transimpedance amplifier is connected to the double-balanced mixer.
[0010] Preferably, the orthogonal low-noise amplifier may include a first branch and a second branch, and the double-balanced mixer includes a first balanced mixer and a second balanced mixer;
[0011] The signal terminal of the first branch in the orthogonal low-noise amplifier is connected to the first end of the first balanced mixer, and the first transimpedance amplifier is connected to the second end of the first balanced mixer; the signal terminal of the second branch in the orthogonal low-noise amplifier is connected to the first end of the second balanced mixer, and the second transimpedance amplifier is connected to the second end of the second balanced mixer; the first branch is used to output an I-channel low-noise amplified signal, and the second branch is used to output a Q-channel low-noise amplified signal.
[0012] Preferably, the orthogonal low-noise amplifier may include a first NMOS, a second NMOS, a first capacitor, a second capacitor, and a third capacitor, a first voltage transformer, and a second voltage transformer;
[0013] The gate of the first NMOS is connected to the RF signal input terminal of the RF receiver, the drain of the first NMOS is connected to the signal terminal of the first branch, the source of the first NMOS is connected to one end of the first voltage transformer, and the other end of the first voltage transformer is grounded; one end of the first capacitor is connected to the source of the first NMOS, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to the source of the first NMOS, and the other end of the second capacitor is connected to the gate of the second NMOS; the drain of the second NMOS is connected to the signal terminal of the second branch, the source of the second NMOS is connected to one end of the second voltage transformer, and the other end of the second voltage transformer is grounded; one end of the third capacitor is connected to the source of the second NMOS, and the other end of the third capacitor is grounded.
[0014] Preferably, the first balanced mixer may include a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, and a fourth capacitor; the second balanced mixer may include a seventh NMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS, and a fifth capacitor;
[0015] The source of the third NMOS is connected to the signal terminal of the first branch, the drain of the third NMOS is connected to the source of the fifth NMOS, and the gate of the third NMOS is connected to the drain of the fifth NMOS; the gate of the fifth NMOS is connected to the drain of the sixth NMOS; the source of the fourth NMOS is connected to the signal terminal of the first branch, the drain of the fourth NMOS is connected to the source of the sixth NMOS, and the gate of the fourth NMOS is connected to the drain of the sixth NMOS; the gate of the sixth NMOS is connected to the drain of the fifth NMOS; one end of the fourth capacitor is connected to the drain of the third NMOS, and the other end of the fourth capacitor is connected to the drain of the fourth NMOS;
[0016] The source of the seventh NMOS is connected to the signal terminal of the second branch, the drain of the seventh NMOS is connected to the source of the ninth NMOS, and the gate of the seventh NMOS is connected to the drain of the ninth NMOS; the gate of the ninth NMOS is connected to the drain of the tenth NMOS; the source of the eighth NMOS is connected to the signal terminal of the second branch, the drain of the eighth NMOS is connected to the source of the tenth NMOS, and the gate of the eighth NMOS is connected to the drain of the tenth NMOS; the gate of the tenth NMOS is connected to the drain of the ninth NMOS; one end of the fifth capacitor is connected to the drain of the seventh NMOS, and the other end of the fifth capacitor is connected to the drain of the eighth NMOS.
[0017] Preferably, the voltage-controlled oscillator may include an eleventh NMOS, a twelfth NMOS, the fifth NMOS, the sixth NMOS, the ninth NMOS, the tenth NMOS, an inductor, and a variable capacitor; the fifth NMOS, the sixth NMOS, the ninth NMOS, and the tenth NMOS are electrical components shared by the voltage-controlled oscillator and the double-balanced mixer;
[0018] The drain of the eleventh NMOS is connected to the drain of the fifth NMOS, the drain of the eleventh NMOS is connected to the drain of the ninth NMOS, the source of the eleventh NMOS is connected to the power supply terminal, the gate of the eleventh NMOS is connected to the drain of the twelfth NMOS, and the drain of the eleventh NMOS is connected to the phase-locked loop; the drain of the twelfth NMOS is connected to the drain of the sixth NMOS, the drain of the twelfth NMOS is connected to the drain of the tenth NMOS, the source of the twelfth NMOS is connected to the power supply terminal, the gate of the twelfth NMOS is connected to the drain of the eleventh NMOS, and the drain of the twelfth NMOS is connected to the phase-locked loop;
[0019] One end of the inductor is connected to the drain of the eleventh NMOS, and the other end of the inductor is connected to the drain of the twelfth NMOS; one end of the variable capacitor is connected to the drain of the eleventh NMOS, and the other end of the variable capacitor is connected to the drain of the twelfth NMOS.
[0020] Preferably, the first transimpedance amplifier may include a thirteenth NMOS, a fourteenth NMOS, a first resistor, a second resistor, and a third resistor;
[0021] The source of the thirteenth NMOS is connected to the drain of the third NMOS, the gate of the thirteenth NMOS is connected to the gate of the fourteenth NMOS, and the drain of the thirteenth NMOS is connected to the complex filter; the source of the fourteenth NMOS is connected to the drain of the fourth NMOS, and the drain of the fourteenth NMOS is connected to the complex filter;
[0022] One end of the first resistor is connected to the power supply terminal, and the other end of the first resistor is connected to the drain of the thirteenth NMOS; one end of the second resistor is connected to the bias voltage terminal, and the other end of the second resistor is connected to the gate of the fourteenth NMOS; one end of the third resistor is connected to the power supply terminal, and the other end of the third resistor is connected to the drain of the fourteenth NMOS.
[0023] Preferably, the second transimpedance amplifier may include a fifteenth NMOS, a sixteenth NMOS, a fourth resistor, a fifth resistor, and a sixth resistor;
[0024] The source of the fifteenth NMOS is connected to the drain of the seventh NMOS, the gate of the fifteenth NMOS is connected to the gate of the sixteenth NMOS, and the drain of the fifteenth NMOS is connected to the complex filter; the source of the sixteenth NMOS is connected to the drain of the eighth NMOS, and the drain of the sixteenth NMOS is connected to the complex filter;
[0025] One end of the fourth resistor is connected to the power supply terminal, and the other end of the fourth resistor is connected to the drain of the fifteenth NMOS; one end of the fifth resistor is connected to the bias voltage terminal, and the other end of the fifth resistor is connected to the gate of the sixteenth NMOS; one end of the sixth resistor is connected to the power supply terminal, and the other end of the sixth resistor is connected to the drain of the sixteenth NMOS.
[0026] Preferably, the quadrature low-noise amplifier can be used to receive a radio frequency signal, amplify the radio frequency signal, and output an I-channel low-noise amplified signal and a Q-channel low-noise amplified signal; the phase difference between the I-channel low-noise amplified signal and the Q-channel low-noise amplified signal is 90°.
[0027] Preferably, the double-balanced mixer can be used to perform double-balanced mixing processing on the received radio frequency signal and the local oscillator signal, and output a difference frequency signal and a sum frequency signal; the difference frequency signal serves as the intermediate frequency signal of the receiver.
[0028] Preferably, the voltage-controlled oscillator is a complementary voltage-controlled oscillator, and the voltage-controlled oscillator can be used to provide a local oscillator signal to the double-balanced mixer; the operating frequency of the voltage-controlled oscillator is 2.4 GHz; the first transimpedance amplifier is used to amplify the intermediate frequency signal output by the first branch in the target stacked circuit structure and balance the amplitude of the intermediate frequency signal output by the first branch; the second transimpedance amplifier is used to amplify the intermediate frequency signal output by the second branch in the target stacked circuit structure and balance the amplitude of the intermediate frequency signal output by the second branch.
[0029] Compared with the prior art, a front-end circuit of a radio frequency receiver provided by the present invention includes a first transimpedance amplifier, a second transimpedance amplifier, and a target stacked circuit structure arranged in the radio frequency receiver; wherein, the target stacked circuit structure is a circuit formed by stacking a quadrature low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator, and the quadrature low-noise amplifier, the double-balanced mixer, and the voltage-controlled oscillator share a current source; the quadrature low-noise amplifier is connected to the double-balanced mixer, the voltage-controlled oscillator is connected to the double-balanced mixer, the first transimpedance amplifier is connected to the double-balanced mixer, and the second transimpedance amplifier is connected to the double-balanced mixer; based on this, in the present invention, by using the target stacked circuit structure including a quadrature low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator, current reuse in the same current path is achieved, and there is no need to provide current for each module separately, greatly reducing the number of current branches, thereby greatly reducing the overall power consumption and improving the current utilization rate; at the same time, the additional current sources and related bias circuits are also reduced, reducing the redundancy of components and the chip area used; the problems of large chip area, low current utilization rate, and high power consumption in the prior art front-end cascaded circuit of a radio frequency receiver are solved. Description of the Drawings
[0030] The accompanying drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:
[0031] Figure 1 is a schematic structural diagram of a low intermediate frequency receiver circuit of a radio frequency receiver front end in the prior art;
[0032] Figure 2 is a schematic overall architecture diagram of a low intermediate frequency receiver of a radio frequency receiver front end in the prior art;
[0033] Figure 3 is a schematic structural diagram of a radio frequency receiver front end circuit provided by the present invention;
[0034] Figure 4 is a schematic overall architecture diagram of a radio frequency receiver front end circuit provided by the present invention.
[0035] Reference numerals: 310 - first transimpedance amplifier, 320 - second transimpedance amplifier, 330 - target stacked circuit structure, 331 - quadrature low noise amplifier, 332 - double balanced mixer, 3321 - first balanced mixer, 3322 - second balanced mixer, 333 - voltage controlled oscillator, I - first branch, Q - second branch. Detailed Embodiments
[0036] In order to facilitate a clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. For example, the first threshold and the second threshold are only used to distinguish different thresholds and do not limit their chronological order. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and terms such as "first" and "second" do not necessarily limit being different.
[0037] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.
[0038] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the former associated object has an "or" relationship. "At least one (item)" or a similar expression refers to any combination of these items, including any combination of a single item or multiple items. For example, at least one (item) of a, b, or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple.
[0039] First, the following is a table explaining some English abbreviations involved in the present invention:
[0040]
[0041] Currently, in the traditional low-intermediate frequency receiver architecture widely used in the front-end of low-power radio frequency receivers, please refer to Figures 1 to 2 , Figure 1 which is a schematic diagram of the structure of the low-intermediate frequency receiver circuit in the radio frequency receiver front-end in the prior art; Figure 2 which is a schematic diagram of the overall architecture of the low-intermediate frequency receiver in the radio frequency receiver front-end in the prior art; In Figure 1 and Figure 2 , circuit modules such as a low-noise amplifier (LNA), a mixer (MIXER), and a phase-locked loop (PLL) are connected in a cascaded form. The signal is amplified by the LNA and mixed with the local oscillator signal (LO) generated by the phase-locked loop in the mixer to generate the required intermediate frequency signal; for each stage of the circuit of the cascaded architecture of LNA, MIXER, and PLL, a separate operating current is required to meet the requirements of indicators such as gain, bandwidth, noise figure, and linearity; this results in the current of each stage being limited to the current circuit module, with low current utilization efficiency and the problem of increasing additional functional modules; in other words, this circuit in the cascaded manner means the problems of increasing additional current, generating additional consumption, and also increasing the chip area of the circuit, and the power consumption is relatively large.
[0042] Therefore, the present invention proposes a radio frequency receiver front-end circuit, which uses a circuit structure composed of an orthogonal low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator stacked together, realizing current multiplexing in the same current path, reducing the number of power supply branches, reducing the chip area, and improving the current utilization rate; and transferring the generation of orthogonal signals to the radio frequency, avoiding the use of a frequency divider circuit or the simultaneous use of orthogonal oscillators, reducing the operating frequency and power consumption of the circuit.
[0043] Next, the technical solution of the present invention will be described in detail with reference to the accompanying drawings:
[0044] The present invention provides a front-end circuit of a radio frequency receiver, which is particularly suitable for low-power scenarios, such as low-power radio frequency receivers such as ZigBee and low-power Bluetooth sensors.
[0045] The circuit may include: a first transimpedance amplifier, a second transimpedance amplifier, and a target stacked circuit structure; the target stacked circuit structure is a circuit formed by stacking an orthogonal low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator; the orthogonal low-noise amplifier, the double-balanced mixer, and the voltage-controlled oscillator share a current source; the orthogonal low-noise amplifier is connected to the double-balanced mixer; the voltage-controlled oscillator is connected to the double-balanced mixer; the first transimpedance amplifier is connected to the double-balanced mixer, and the second transimpedance amplifier is connected to the double-balanced mixer.
[0046] Based on this, a front-end circuit of a radio frequency receiver provided by the present invention uses a circuit structure formed by stacking an orthogonal low-noise amplifier, a double-balanced mixer, and a voltage-controlled oscillator. Under the same power supply voltage, the LNA, MIXER, and VCO modules are stacked and share the same current source. The upper circuit module uses the output of the lower circuit module as the input, that is, the lower LNA provides amplification of the radio frequency signal, the middle MIXER is responsible for down-converting the radio frequency signal, and the upper VCO provides the local oscillator signal for the MIXER; thus, current reuse is achieved.
[0047] It should be noted that the current reuse technology enables multiple modules to share the same bias source, eliminating the need to provide current separately for each module, thereby greatly reducing the number of current branches and reducing the overall power consumption; at the same time, it can also reduce the additional current sources and related bias circuits, reducing the redundancy of components.
[0048] For example, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of a front-end circuit of a radio frequency receiver provided by the present invention.
[0049] In Figure 3Among them, a radio frequency receiver front-end circuit provided by the present invention may include: a first transimpedance amplifier 310, a second transimpedance amplifier 320, and a target stacked circuit structure 330 (LMV stacked structure); the target stacked circuit structure 330 is a circuit formed by stacking an orthogonal low-noise amplifier 331, a double-balanced mixer 332, and a voltage-controlled oscillator 333; the orthogonal low-noise amplifier 331, the double-balanced mixer 332, and the voltage-controlled oscillator 333 share a current source; the orthogonal low-noise amplifier 331 is connected to the double-balanced mixer 332; the voltage-controlled oscillator 333 is connected to the double-balanced mixer 332; the first transimpedance amplifier 310 is connected to the double-balanced mixer 332, and the second transimpedance amplifier 320 is connected to the double-balanced mixer 332.
[0050] Further, the orthogonal low-noise amplifier 331 may include a first branch and a second branch, and the double-balanced mixer 332 includes a first balanced mixer 3321 and a second balanced mixer 3322.
[0051] Specifically, the signal terminal of the first branch I in the orthogonal low-noise amplifier 331 may be connected to the first end of the first balanced mixer 3321, and the first transimpedance amplifier 310 is connected to the second end of the first balanced mixer 3321. The first branch I is used to output the I-channel low-noise amplified signal, that is, the I-channel low-noise amplified signal generated in the orthogonal low-noise amplifier is output through the first branch I; thereby, the I-channel radio frequency signal is output through the first transimpedance amplifier 310. Further, the signal terminal of the second branch Q in the orthogonal low-noise amplifier 331 may be connected to the first end of the second balanced mixer 3322, and the second transimpedance amplifier 320 is connected to the second end of the second balanced mixer 3322; the second branch Q is used to output the Q-channel low-noise amplified signal, that is, the Q-channel low-noise amplified signal generated in the orthogonal low-noise amplifier is output through the second branch Q; thereby, the Q-channel radio frequency signal is output through the second transimpedance amplifier 320.
[0052] Preferably, the orthogonal low-noise amplifier 331 may include a first NMOS, a second NMOS, a first capacitor, a second capacitor, a third capacitor, a first voltage transformer, and a second voltage transformer.
[0053] Specifically, the gate of the first NMOS can be connected to the RF signal input terminal of the RF receiver, the drain of the first NMOS can be connected to the signal terminal of the first branch, the source of the first NMOS can be connected to one end of the first voltage transformer, and the other end of the first voltage transformer can be grounded; one end of the first capacitor can be connected to the source of the first NMOS, and the other end of the first capacitor can be grounded; one end of the second capacitor can be connected to the source of the first NMOS, and the other end of the second capacitor can be connected to the gate of the second NMOS; the drain of the second NMOS can be connected to the signal terminal of the second branch, the source of the second NMOS can be connected to one end of the second voltage transformer, and the other end of the second voltage transformer can be grounded; one end of the third capacitor can be connected to the source of the second NMOS, and the other end of the third capacitor can be grounded; thereby, the orthogonal low-noise amplifier 331 is used to receive the RF signal, and after the RF signal is amplified and processed, an I-channel low-noise amplified signal and a Q-channel low-noise amplified signal are output, and the phase difference between the I-channel low-noise amplified signal and the Q-channel low-noise amplified signal is 90°.
[0054] In practical applications, the orthogonal low-noise amplifier 331 (orthogonal LNA), located at the very front end of the RF receiver link, mainly functions to amplify the weak signal received by the antenna, and at the same time, tries to introduce extremely low noise to avoid the signal in the subsequent circuit being covered by noise. At the same time, the present invention uses the capacitive degeneration technology to enable the orthogonal signal to be generated in the LNA. The capacitive degeneration orthogonal LNA is as Figure 3 shown. The core of the circuit is two transistors M1 and M2. The RF signal is input to the gate of M1 through the impedance matching network and amplified. The drain current of M1 is output to the I channel (the first branch), and the I-channel low-noise amplified signal is output from the drain of M1; the source of M1 is degenerated by the capacitor C1, the gate of M1 is connected to the source of M2 through the bypass capacitor C2, the drain current of M2 is output to the Q channel (the second branch), and the Q-channel low-noise amplified signal is output from the drain of M2. Due to the introduction of C1, a phase shift is generated between the voltage on the source of M1 and the drain current. This voltage is transmitted to the gate of M2 through C2, so that there is a 90° phase difference between the drain current of M2 and the drain current of M1; thus, the orthogonal transformation of the signal is realized. It should be noted that the I-channel low-noise amplified signal is output through the first branch I, and the Q-channel low-noise amplified signal is output through the second branch Q.
[0055] Based on this, the quadrature generation mechanism in the circuit provided by the present invention maintains a 90° phase shift within a wide frequency range, and by adjusting the values of C1 and C2, the amplitude matching at the target frequency can be optimized. The capacitive degradation quadrature LNA avoids the use of resistors, reduces offset, and has relatively low noise; the common-source circuit also provides a relatively large gain and relatively good stability. In addition, in the traditional cascaded circuit structure, it is necessary to force the VCO to operate at twice the operating frequency of 4.8 GHz, and then a divide-by-two circuit of the PLL is required to generate the quadrature local oscillator signal to ensure that the subsequent stage filters out the image signal through a complex filter. In this design, the generation of the quadrature signal is transferred to the RF LNA, and the VCO oscillates at the operating frequency of 2.4 GHz, avoiding the power consumption required to generate high frequencies compared with the prior art.
[0056] Preferably, the first balanced mixer 3321 may include a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, and a fourth capacitor; the second balanced mixer 3322 may include a seventh NMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS, and a fifth capacitor.
[0057] Specifically, the source of the third NMOS can be connected to the signal terminal of the first branch, the drain of the third NMOS is connected to the source of the fifth NMOS, and the gate of the third NMOS is connected to the drain of the fifth NMOS; the gate of the fifth NMOS is connected to the drain of the sixth NMOS; the source of the fourth NMOS is connected to the signal terminal of the first branch, the drain of the fourth NMOS is connected to the source of the sixth NMOS, and the gate of the fourth NMOS is connected to the drain of the sixth NMOS; the gate of the sixth NMOS is connected to the drain of the fifth NMOS; one end of the fourth capacitor is connected to the drain of the third NMOS, and the other end of the fourth capacitor is connected to the drain of the fourth NMOS.
[0058] Furthermore, the source of the seventh NMOS is connected to the signal terminal of the second branch, the drain of the seventh NMOS is connected to the source of the ninth NMOS, and the gate of the seventh NMOS is connected to the drain of the ninth NMOS; the gate of the ninth NMOS is connected to the drain of the tenth NMOS; the source of the eighth NMOS is connected to the signal terminal of the second branch, the drain of the eighth NMOS is connected to the source of the tenth NMOS, and the gate of the eighth NMOS is connected to the drain of the tenth NMOS; the gate of the tenth NMOS is connected to the drain of the ninth NMOS; one end of the fifth capacitor is connected to the drain of the seventh NMOS, and the other end of the fifth capacitor is connected to the drain of the eighth NMOS. Thus, the first balanced mixer 3321 and the second balanced mixer 3322 in the double balanced mixer are used to perform double balanced mixing processing on the received RF signal and the local oscillator signal, and output the difference frequency signal and the sum frequency signal; the difference frequency signal can be used as the intermediate frequency signal of the receiver.
[0059] In practical applications, after generating and amplifying orthogonal radio frequency signals by the LNA, the low-noise amplified signal of the I path and the low-noise amplified signal of the Q path are respectively connected to the double-balanced mixer through the first branch I and the second branch Q. The double-balanced mixer includes M3, M4, M5, and M6 in the I path and M7, M8, M9, and M10 in the Q path, a total of 8 transistors. The double-balanced mixer passes the input radio frequency signal f RF and the local oscillator signal f LO , and outputs the difference frequency signal and the sum frequency signal. The difference frequency component is usually used as the intermediate frequency signal f IF of the receiver. In order to achieve double-balanced mixing, the traditional structure uses four branches to complete double-balanced mixing, while the circuit structure provided by the invention utilizes the characteristics that both the VCO and the MIXER operate in the large-signal switching state, and only two branches are used to achieve double-balanced mixing, further reducing the power consumption of the circuit.
[0060] Preferably, the voltage-controlled oscillator 333 may include an eleventh NMOS, a twelfth NMOS, a fifth NMOS, a sixth NMOS, a ninth NMOS, a tenth NMOS, an inductor, and a variable capacitor; the fifth NMOS, the sixth NMOS, the ninth NMOS, and the tenth NMOS are electrical components shared by the voltage-controlled oscillator and the double-balanced mixer.
[0061] Specifically, the drain of the eleventh NMOS can be connected to the drain of the fifth NMOS, the drain of the eleventh NMOS can be connected to the drain of the ninth NMOS, the source of the eleventh NMOS can be connected to the power supply terminal, the gate of the eleventh NMOS can be connected to the drain of the twelfth NMOS, and the drain of the eleventh NMOS can be connected to the phase-locked loop; the drain of the twelfth NMOS can be connected to the drain of the sixth NMOS, the drain of the twelfth NMOS can be connected to the drain of the tenth NMOS, the source of the twelfth NMOS can be connected to the power supply terminal, the gate of the twelfth NMOS can be connected to the drain of the eleventh NMOS, and the drain of the twelfth NMOS can be connected to the phase-locked loop;
[0062] Furthermore, one end of the inductor can be connected to the drain of the eleventh NMOS, and the other end of the inductor can be connected to the drain of the twelfth NMOS; one end of the variable capacitor can be connected to the drain of the eleventh NMOS, and the other end of the variable capacitor can be connected to the drain of the twelfth NMOS; based on this, it can be realized to provide the local oscillator signal to the double-balanced mixer by using the voltage-controlled oscillator; wherein, the voltage-controlled oscillator is preferably a complementary voltage-controlled oscillator, and the operating frequency of the voltage-controlled oscillator is preferably 2.4 GHz.
[0063] In practical applications, a differential local oscillator signal can be generated by a complementary voltage-controlled oscillator LC VCO at the topmost of the target stacked circuit structure. Since M5 and M6 on the first branch I and M9 and M10 on the second branch Q serve both as transistors of the MIXER and as transistors of the VCO, and M11 and M12 are shared by the I and Q branches, the complementary LC VCO structure uses a lower bias current compared to a PMOS VCO or an NMOS VCO, saving half of the DC bias current. Also, the I and Q branches share an LC tank, greatly saving the chip area compared to the prior art. It should be noted that the PLL loop is used to fix the local oscillator signal generated by the VCO, making it operate in the required frequency band and preventing the VCO from free oscillation.
[0064] Preferably, the first transimpedance amplifier 310 may include a thirteenth NMOS, a fourteenth NMOS, a first resistor, a second resistor, and a third resistor.
[0065] Specifically, the source of the thirteenth NMOS can be connected to the drain of the third NMOS, the gate of the thirteenth NMOS can be connected to the gate of the fourteenth NMOS, and the drain of the thirteenth NMOS can be connected to the complex filter. The source of the fourteenth NMOS can be connected to the drain of the fourth NMOS, and the drain of the fourteenth NMOS can be connected to the complex filter. One end of the first resistor can be connected to the power supply terminal, and the other end of the first resistor can be connected to the drain of the thirteenth NMOS. One end of the second resistor can be connected to the bias voltage terminal, and the other end of the second resistor can be connected to the gate of the fourteenth NMOS. One end of the third resistor can be connected to the power supply terminal, and the other end of the third resistor can be connected to the drain of the fourteenth NMOS.
[0066] Preferably, the second transimpedance amplifier 320 may include a fifteenth NMOS, a sixteenth NMOS, a fourth resistor, a fifth resistor, and a sixth resistor.
[0067] Specifically, the source of the fifteenth NMOS can be connected to the drain of the seventh NMOS, the gate of the fifteenth NMOS can be connected to the gate of the sixteenth NMOS, and the drain of the fifteenth NMOS can be connected to the complex filter. The source of the sixteenth NMOS can be connected to the drain of the eighth NMOS, and the drain of the sixteenth NMOS can be connected to the complex filter. One end of the fourth resistor can be connected to the power supply terminal, and the other end of the fourth resistor can be connected to the drain of the fifteenth NMOS. One end of the fifth resistor can be connected to the bias voltage terminal, and the other end of the fifth resistor can be connected to the gate of the sixteenth NMOS. One end of the sixth resistor can be connected to the power supply terminal, and the other end of the sixth resistor can be connected to the drain of the sixteenth NMOS.
[0068] Based on this, the first transimpedance amplifier 310 is used to amplify the intermediate-frequency signal output by the first branch I in the target stacked circuit structure, and balance the amplitude of the intermediate-frequency signal output by the first branch I. Also, the second transimpedance amplifier 320 is used to amplify the intermediate-frequency signal output by the second branch Q in the target stacked circuit structure, and balance the amplitude of the intermediate-frequency signal output by the second branch Q. After the TIA circuit amplification, finally, it is connected to a complex filter for filtering, so as to extract the required signal and suppress the image signal before outputting.
[0069] Further, please refer to Figure 4 , Figure 4 which is a schematic diagram of the overall architecture of a radio frequency receiver front-end circuit provided by the present invention. It should be noted that Figure 4 is Figure 3 the schematic diagram corresponding to the circuit structure.
[0070] In Figure 4 , a radio frequency receiver front-end circuit provided by the present invention adopts a low intermediate-frequency architecture, an orthogonal radio frequency signal generation circuit, a current reuse stacking technology, and a double-balanced mixing design. The orthogonal low-noise amplifier 331, the double-balanced mixer 332, and the voltage-controlled oscillator 333 are stacked, and combined with the first transimpedance amplifier 310 and the second transimpedance amplifier 320 to form a low-power, high-integration radio frequency receiver front-end system. This system achieves a significant reduction in power consumption while maintaining high performance, and is particularly suitable for power-sensitive application scenarios such as the Internet of Things and wireless sensor networks, which can effectively extend the battery life of the device and improve the overall energy efficiency.
[0071] Verified by simulation tests, the overall power consumption of a radio frequency receiver front-end circuit provided by the present invention is only 0.48 mW, and other performance indicators such as IIP3 is -20 dB, NF < 6 dB, S11 in the passband < -10 dB, and the conversion gain > 55 dB, all of which meet the industrial standards. Compared with the traditional design, the radio frequency receiver front-end circuit provided by the present invention has extremely low power consumption and is very suitable for applications in scenarios with strict low-power requirements such as the Internet of Things and wearable devices, which promotes the rapid development of low-power products.
[0072] In summary, a front-end circuit of a radio frequency receiver provided by the present invention directly generates quadrature I / Q signals at the radio frequency end by adopting the technology of capacitor-degraded quadrature LNA, MIXER, and VCO stacking, and abandons the frequency divider and quadrature oscillator with relatively high power consumption in the traditional method, thereby significantly reducing power consumption. By achieving a 90-degree phase shift at the radio frequency end and ensuring the phase accuracy of the I / Q signals, and at the same time adopting the current reuse technology, multiple circuit modules (such as LNA, MIXER, VCO) share the current source or bias current, reducing the demand of each module for an independent bias current source, thus significantly reducing the overall power consumption of the front-end of the receiver; using the design architecture of the present invention, the multi-stage circuit modules of the receiver can share the DC current, which not only optimizes the power consumption management, makes the energy efficiency of the entire front-end of the receiver significantly improved, and is applicable to low-power Internet of Things and wireless application scenarios; and also saves the chip area used, further improves the integration degree, and better meets the application requirements in high-density integrated products.
[0073] Although the present invention has been described in connection with various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and realize other changes of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0074] Although the present invention has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present invention. Accordingly, the present specification and the drawings are merely exemplary illustrations of the present invention defined by the appended claims, and are considered to have covered any and all modifications, variations, combinations, or equivalents within the scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.
Claims
1. A radio frequency receiver front-end circuit, characterized in that: include: a first transimpedance amplifier, a second transimpedance amplifier, and a target stacked circuit structure; The target stacked circuit structure is a circuit formed by stacking an orthogonal low noise amplifier, a double balanced mixer and a voltage controlled oscillator; the orthogonal low noise amplifier, the double balanced mixer and the voltage controlled oscillator share a current source; The orthogonal low noise amplifier is connected to the double balanced mixer; the voltage controlled oscillator is connected to the double balanced mixer; the first transimpedance amplifier is connected to the double balanced mixer, and the second transimpedance amplifier is connected to the double balanced mixer.
2. The circuit according to claim 1, characterized in that The orthogonal low noise amplifier comprises a first branch and a second branch, and the double balanced mixer comprises a first balanced mixer and a second balanced mixer; The signal end of the first branch in the orthogonal low noise amplifier is connected to the first end of the first balanced mixer, and the first transimpedance amplifier is connected to the second end of the first balanced mixer; the signal end of the second branch in the orthogonal low noise amplifier is connected to the first end of the second balanced mixer, and the second transimpedance amplifier is connected to the second end of the second balanced mixer; the first branch is used to output an I-channel low noise amplified signal, and the second branch is used to output a Q-channel low noise amplified signal.
3. The circuit according to claim 2, characterized in that The orthogonal low noise amplifier includes a first NMOS, a second NMOS, a first capacitor, a second capacitor, a third capacitor, a first voltage transformer and a second voltage transformer; The gate of the first NMOS is connected to the RF signal input end of the RF receiver, the drain of the first NMOS is connected to the signal end of the first branch, the source of the first NMOS is connected to one end of the first voltage transformer, and the other end of the first voltage transformer is grounded; one end of the first capacitor is connected to the source of the first NMOS, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to the source of the first NMOS, and the other end of the second capacitor is connected to the gate of the second NMOS; the drain of the second NMOS is connected to the signal end of the second branch, the source of the second NMOS is connected to one end of the second voltage transformer, and the other end of the second voltage transformer is grounded; one end of the third capacitor is connected to the source of the second NMOS, and the other end of the third capacitor is grounded.
4. The circuit according to claim 2, characterized in that The first balanced mixer includes a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS, and a fourth capacitor; the second balanced mixer includes a seventh NMOS, an eighth NMOS, a ninth NMOS, a tenth NMOS, and a fifth capacitor; The source of the third NMOS is connected to the signal end of the first branch, the drain of the third NMOS is connected to the source of the fifth NMOS, the gate of the third NMOS is connected to the drain of the fifth NMOS; the gate of the fifth NMOS is connected to the drain of the sixth NMOS; the source of the fourth NMOS is connected to the signal end of the first branch, the drain of the fourth NMOS is connected to the source of the sixth NMOS, the gate of the fourth NMOS is connected to the drain of the sixth NMOS; the gate of the sixth NMOS is connected to the drain of the fifth NMOS; one end of the fourth capacitor is connected to the drain of the third NMOS, and the other end of the fourth capacitor is connected to the drain of the fourth NMOS; The source of the seventh NMOS is connected to the signal end of the second branch, the drain of the seventh NMOS is connected to the source of the ninth NMOS, and the gate of the seventh NMOS is connected to the drain of the ninth NMOS; the gate of the ninth NMOS is connected to the drain of the tenth NMOS; the source of the eighth NMOS is connected to the signal end of the second branch, the drain of the eighth NMOS is connected to the source of the tenth NMOS, and the gate of the eighth NMOS is connected to the drain of the tenth NMOS; the gate of the tenth NMOS is connected to the drain of the ninth NMOS; one end of the fifth capacitor is connected to the drain of the seventh NMOS, and the other end of the fifth capacitor is connected to the drain of the eighth NMOS.
5. The circuit according to claim 4, characterized in that The voltage-controlled oscillator includes an eleventh NMOS, a twelfth NMOS, the fifth NMOS, the sixth NMOS, the ninth NMOS, the tenth NMOS, an inductor, and a variable capacitor; the fifth NMOS, the sixth NMOS, the ninth NMOS, and the tenth NMOS are electrical components shared by the voltage-controlled oscillator and the double-balanced mixer; The drain of the eleventh NMOS is connected to the drain of the fifth NMOS, the drain of the eleventh NMOS is connected to the drain of the ninth NMOS, the source of the eleventh NMOS is connected to the power supply terminal, the gate of the eleventh NMOS is connected to the drain of the twelfth NMOS, and the drain of the eleventh NMOS is connected to a phase-locked loop; the drain of the twelfth NMOS is connected to the drain of the sixth NMOS, the drain of the twelfth NMOS is connected to the drain of the tenth NMOS, the source of the twelfth NMOS is connected to the power supply terminal, the gate of the twelfth NMOS is connected to the drain of the eleventh NMOS, and the drain of the twelfth NMOS is connected to a phase-locked loop; One end of the inductor is connected to the drain of the eleventh NMOS, and the other end of the inductor is connected to the drain of the twelfth NMOS; one end of the variable capacitor is connected to the drain of the eleventh NMOS, and the other end of the variable capacitor is connected to the drain of the twelfth NMOS.
6. The circuit according to claim 4, characterized in that The first transimpedance amplifier includes a thirteenth NMOS, a fourteenth NMOS, a first resistor, a second resistor and a third resistor; The source of the thirteenth NMOS is connected to the drain of the third NMOS, the gate of the thirteenth NMOS is connected to the gate of the fourteenth NMOS, and the drain of the thirteenth NMOS is connected to the complex filter; the source of the fourteenth NMOS is connected to the drain of the fourth NMOS, and the drain of the fourteenth NMOS is connected to the complex filter; One end of the first resistor is connected to the power supply terminal, and the other end of the first resistor is connected to the drain of the thirteenth NMOS; one end of the second resistor is connected to the bias voltage terminal, and the other end of the second resistor is connected to the gate of the fourteenth NMOS; one end of the third resistor is connected to the power supply terminal, and the other end of the third resistor is connected to the drain of the fourteenth NMOS.
7. The circuit according to claim 4, characterized in that The second transimpedance amplifier includes a fifteenth NMOS, a sixteenth NMOS, a fourth resistor, a fifth resistor and a sixth resistor; The source of the fifteenth NMOS is connected to the drain of the seventh NMOS, the gate of the fifteenth NMOS is connected to the gate of the sixteenth NMOS, and the drain of the fifteenth NMOS is connected to the complex filter; the source of the sixteenth NMOS is connected to the drain of the eighth NMOS, and the drain of the sixteenth NMOS is connected to the complex filter; One end of the fourth resistor is connected to the power supply terminal, and the other end of the fourth resistor is connected to the drain of the fifteenth NMOS; one end of the fifth resistor is connected to the bias voltage terminal, and the other end of the fifth resistor is connected to the gate of the sixteenth NMOS; one end of the sixth resistor is connected to the power supply terminal, and the other end of the sixth resistor is connected to the drain of the sixteenth NMOS.
8. The circuit according to claim 1, characterized in that The orthogonal low noise amplifier is used to receive a radio frequency signal, and after amplifying the radio frequency signal, output an I-channel low noise amplified signal and a Q-channel low noise amplified signal; the phase difference between the I-channel low noise amplified signal and the Q-channel low noise amplified signal is 90°.
9. The circuit according to claim 1, characterized in that The double-balanced mixer is used to perform double-balanced mixing processing on the received radio frequency signal and the local oscillator signal, and output a difference frequency signal and a sum frequency signal; the difference frequency signal is used as the intermediate frequency signal of the receiver.
10. The circuit according to claim 1, characterized in that The voltage-controlled oscillator is a complementary voltage-controlled oscillator, and the voltage-controlled oscillator is used to provide a local oscillator signal to the double-balanced mixer; the operating frequency of the voltage-controlled oscillator is 2.4 GHz; the first transimpedance amplifier is used to amplify the intermediate frequency signal output by the first branch in the target stacked circuit structure, and balance the amplitude of the intermediate frequency signal output by the first branch; The second transimpedance amplifier is used to amplify the intermediate frequency signal output by the second branch in the target stacked circuit structure, and balance the amplitude of the intermediate frequency signal output by the second branch.