Storage structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a storage structure and a manufacturing method thereof, the structure comprises storage transistors, bit lines and capacitors, the plurality of storage transistors are arranged at intervals along a first direction, and each storage transistor comprises a first side and a second side which are oppositely arranged along a second direction; each bit line comprises a first part and a second part which are alternately connected in the first direction, the first parts are located on the first sides of the storage transistors, the second parts are located on the second sides of the adjacent storage transistors, and in the first direction, the adjacent storage transistors are connected with the first parts and the second parts respectively; the capacitor is located on the side, away from the bit line in the second direction, of the storage transistor and electrically connected with the semiconductor layer. The storage structure and the manufacturing method thereof provided by the embodiment of the invention are at least beneficial to improving the integration density of the storage structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductors, and particularly to a storage structure and a manufacturing method thereof. Background Art

[0002] A memory is a memory component used to store programs and various data information. The random access memory (RAM) generally used in a computer system can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). The dynamic random access memory is a commonly used semiconductor storage device in a computer and is composed of many repeated memory cells.

[0003] A memory cell generally includes a capacitor and a transistor. One of the source and drain or the drain of the transistor is connected to a bit line structure, and the other of the source and drain or the drain is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitance. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, and further read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.

[0004] Currently, the integration density of the storage structure needs to be improved. Summary of the Invention

[0005] Embodiments of the present disclosure provide a storage structure and a manufacturing method thereof, which are at least beneficial to improving the integration density of the storage structure.

[0006] According to some embodiments of the present disclosure, on the one hand, a storage structure is provided, including: storage transistors, a plurality of storage transistors are arranged at intervals along a first direction. The storage transistor includes a first side and a second side oppositely arranged along a second direction. The storage transistor includes: a word line, a gate dielectric layer, and a semiconductor layer. The word line extends along a third direction; the gate dielectric layer surrounds at least part of the surface of the word line with the third direction as an axis; the semiconductor layer is located on the surface of the gate dielectric layer away from the word line; a bit line, the bit line includes a first part and a second part alternately connected along the first direction. The first part is located on the first side of the storage transistor, and the second part is located on the second side of the adjacent storage transistor. In the first direction, the semiconductor layers of the adjacent storage transistors are respectively connected to the first part and the second part; a plurality of capacitors, the capacitors are located on the side of the storage transistor away from the bit line along the second direction, and the capacitors are electrically connected to the semiconductor layer.

[0007] In some embodiments, the gate dielectric layer surrounds the word line with the third direction as the axis, the semiconductor layer surrounds the gate dielectric layer with the third direction as the axis, the first part of the bit line is in electrical contact with the surface of the semiconductor layer of the memory transistor close to the first side, and the second part of the bit line is in electrical contact with the surface of the semiconductor layer of the memory transistor close to the second side.

[0008] In some embodiments, it further includes: a plurality of filling parts, the filling parts extend along the third direction, the filling parts are located between the memory transistor and the bit line, and in the first direction, the corresponding filling parts of adjacent memory transistors are respectively located on the first side and the second side of the memory transistor.

[0009] In some embodiments, in a plane perpendicular to the third direction, the cross-section of the memory transistor and the cross-section of the filling part are symmetrically arranged along the first direction.

[0010] In some embodiments, the cross-section of the memory transistor and the cross-section of the filling part both include a semicircle, a rectangle or a triangle.

[0011] In some embodiments, a plurality of memory transistors are arranged at intervals along the third direction, and in the third direction, the plurality of memory transistors share the same word line; a plurality of bit lines are arranged at intervals along the third direction.

[0012] In some embodiments, the capacitor includes: a first electrode plate, the first electrode plate extends along the third direction; a first electrode layer, the first electrode layer surrounds the first electrode plate with the third direction as the axis; a dielectric layer, the dielectric layer surrounds the first electrode layer with the third direction as the axis; a second electrode layer, the second electrode layer surrounds the dielectric layer with the third direction as the axis, and the second electrode layer is in electrical contact with the semiconductor layer of the corresponding memory transistor.

[0013] In some embodiments, it further includes: an extended bit line, the extended bit line is arranged along the second direction, one end of the extended bit line is connected to the end of the bit line in the first direction; a selection transistor, the selection transistor is located on the side of the extended bit line far from the bit line in the first direction, and one of the source or drain of the selection transistor is electrically connected to the extended bit line; a common bit line, the common bit line extends along the second direction, the common bit line is located on the side of the selection transistor far from the extended bit line in the first direction, and is electrically connected to the other of the source or drain of the selection transistor.

[0014] In some embodiments, the structure of the selection transistor is the same as that of the memory transistor.

[0015] In some embodiments, the number of selection transistors is multiple, the multiple selection transistors are arranged along the second direction, and in the second direction, the multiple selection transistors share the same extended bit line and the same common bit line.

[0016] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a storage structure, including: providing a substrate; forming storage transistors on the substrate, the plurality of storage transistors are arranged at intervals along a first direction, the storage transistor includes a first side and a second side oppositely arranged along a second direction, and the storage transistor includes: a word line, a gate dielectric layer, and a semiconductor layer, the word line extends along a third direction; the gate dielectric layer surrounds at least a part of the surface of the word line with the third direction as an axis; the semiconductor layer is located on the surface of the gate dielectric layer away from the word line; forming bit lines, the bit lines include a first part and a second part alternately connected along the first direction, the first part is located on the first side of the storage transistor, the second part is located on the second side of the storage transistor, and along the first direction, the semiconductor layers of adjacent storage transistors are respectively connected to the first part and the second part; forming a plurality of capacitors, the capacitors are located on the side of the storage transistor away from the bit line along the second direction, and the capacitors are electrically connected to the semiconductor layer.

[0017] In some embodiments, forming the storage transistors and the bit lines on the substrate includes: forming a stacked structure on the substrate, the stacked structure includes a stacked insulating layer and a sacrificial layer; patterning the stacked structure to form a plurality of active holes arranged at intervals along the first direction, the active holes include sub-active holes located in the sacrificial layer, in the third direction, the orthographic projection size of the sub-active holes is larger than the orthographic projection size of the active holes, and the adjacent sub-active holes along the first direction are interconnected; forming a conductive layer, the conductive layer is located on the inner wall of the sub-active holes; patterning the conductive layer to remove the conductive layer on the opposite inner walls of the adjacent sub-active holes along the second direction, and the remaining conductive layer serves as the bit line; forming a semiconductor layer, the semiconductor layer is at least located on the inner wall of the sub-active hole away from the bit line and is in electrical contact with the bit line; forming a gate dielectric layer, the gate dielectric layer is located on the inner wall of the semiconductor layer; forming a word line, the word line fills the remaining sub-active holes and active holes, and the word line, the gate dielectric layer, and the semiconductor layer constitute the storage transistor.

[0018] In some embodiments, before forming the semiconductor layer, it further includes: forming a filling portion, the filling portion is located on the inner wall of the bit line and fills part of the sub-active holes and part of the active holes.

[0019] In some embodiments, forming the semiconductor layer includes: the semiconductor layer is also located on the inner wall of the bit line.

[0020] In some embodiments, in the step of patterning a stacked structure to form a plurality of active holes spaced apart in a first direction, the method further includes: forming a plurality of capacitor holes in the stacked structure; after forming the storage transistors and bit lines, the method further includes: filling the capacitor holes to form capacitors, where each capacitor includes: a first electrode plate extending in a third direction, the first electrode plate being located on a side of the storage transistor away from the bit line in a second direction; a first electrode layer surrounding the first electrode plate with the third direction as an axis; a dielectric layer surrounding the first electrode layer with the third direction as an axis; and a second electrode layer surrounding the dielectric layer with the third direction as an axis, and the second electrode layer is in electrical contact with the semiconductor layer of the corresponding storage transistor.

[0021] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0022] In the storage structure provided by the embodiments of the present disclosure, a storage transistor and a corresponding capacitor form a storage cell, and a plurality of storage cells are spaced apart in a first direction. The storage or reading of the storage cells can be controlled through word lines and bit lines. Among them, the storage transistor includes a word line, a gate dielectric layer, and a semiconductor layer. The word line extends in a third direction, the gate dielectric layer surrounds at least part of the surface of the word line with the third direction as an axis, and the semiconductor layer is located on the surface of the gate dielectric layer away from the word line. Thus, with the semiconductor layer as the channel, a structure in which the channel wraps the word line is formed, improving the space utilization rate of the storage transistor, being beneficial to improving the integration density of the storage structure. At the same time, the area where the word line covers the channel is increased compared with that of the storage transistor in a planar structure, being beneficial to improving the control force of the word line. In the first direction, the bit line includes alternately connected first and second parts. The first part is located on a first side of the storage transistor, and the second part is located on a second side of an adjacent storage transistor. Then, in the first direction, the bit line is alternately disposed on the first side and the second side of the storage transistor, and the gap between adjacent storage transistors in the first direction is equal to the size of the bit line in the first direction, improving the arrangement density of the storage transistors in the first direction, and further improving the integration density of the storage structure. Capacitors corresponding to adjacent storage cells are respectively located on the first side and the second side of the storage transistors to which they are connected, so that the capacitors corresponding to adjacent storage cells can have a larger volume, being beneficial to improving the storage capacity of the capacitors. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] Figure 1 Schematic diagram of a storage structure provided by an embodiment of the present disclosure;

[0025] Figure 2 Schematic diagram of another storage structure provided by an embodiment of the present disclosure;

[0026] Figure 3 Top view of a storage unit along a third direction provided by an embodiment of the present disclosure;

[0027] Figure 4 Top view of a storage structure along a third direction provided by an embodiment of the present disclosure;

[0028] Figure 5 Top view of another storage unit along a third direction provided by an embodiment of the present disclosure;

[0029] Figure 6 Top view of yet another storage unit along a third direction provided by an embodiment of the present disclosure;

[0030] Figure 7 Top view of another storage structure along a third direction provided by an embodiment of the present disclosure;

[0031] Figures 8 to 16 Schematic diagrams corresponding to the steps of a manufacturing method of a storage structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0032] The embodiments of the present disclosure provide a storage structure, which is at least beneficial to improving the integration density of the storage structure.

[0033] The following will elaborate on the embodiments of the present disclosure in detail with reference to the drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented for the better understanding of the present disclosure by the readers. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented. The following will detail the storage structure provided in this embodiment with reference to the drawings.

[0034] Figure 1 Schematic diagram of a storage structure provided by an embodiment of the present disclosure.

[0035] Reference Figure 1 , the storage structure includes: a storage transistor 100, a bit line 200, and a capacitor 300. A plurality of storage transistors 100 are arranged at intervals along a first direction X. The storage transistor 100 includes a first side and a second side oppositely arranged along a second direction Y. The storage transistor 100 includes: a word line 101, a gate dielectric layer 102, and a semiconductor layer 103. The word line 101 extends along a third direction Z; the gate dielectric layer 102 surrounds at least a part of the surface of the word line 101 with the third direction Z as an axis; the semiconductor layer 103 is located on the surface of the gate dielectric layer 102 away from the word line 101. The bit line 200 includes a first part 201 and a second part 202 alternately connected along the first direction X. The first part 201 is located on the first side of the storage transistor 100, and the second part 202 is located on the second side of the adjacent storage transistor 100. Along the first direction X, the semiconductor layers 103 of the adjacent storage transistors 100 are respectively connected to the first part 201 and the second part 202. The capacitor 300 is located on the side of the storage transistor 100 away from the bit line 200 along the second direction Y, and the capacitor 300 is electrically connected to the semiconductor layer 103.

[0036] Thus, the storage transistor 100 and the corresponding capacitor 300 form a storage cell. Multiple storage cells are arranged at intervals along the first direction X. The storage or reading of the storage cells can be controlled through the word line 101 and the bit line 200. Among them, the storage transistor 100 includes a word line 101, a gate dielectric layer 102, and a semiconductor layer 103. The word line 101 extends along the third direction Z. The gate dielectric layer 102 surrounds at least part of the surface of the word line 101 with the third direction Z as the axis. The semiconductor layer 103 is located on the surface of the gate dielectric layer 102 away from the word line 101. Thus, with the semiconductor layer 103 as the channel, a structure in which the channel wraps the word line 101 is formed, improving the space utilization rate of the storage transistor 100, which is beneficial to improving the integration density of the storage structure. At the same time, the area of the word line 101 covering the channel is increased compared with the storage transistor of the planar structure, which is beneficial to improving the control force of the word line 101. Along the first direction X, the bit line 200 includes alternately connected first part 201 and second part 202. The first part 201 is located on the first side of the storage transistor 100, and the second part 202 is located on the second side of the adjacent storage transistor 100. Then, along the first direction X, the bit line 200 is alternately arranged on the first side and the second side of the storage transistor 100. The gap between adjacent storage transistors 100 along the first direction X is equal to the size of the bit line 200 along the first direction X, improving the arrangement density of the storage transistors 100 along the first direction X, and further improving the integration density of the storage structure. The capacitors 300 corresponding to adjacent storage cells are respectively located on the first side and the second side of the storage transistors 100 to which they are respectively connected. Then, the capacitors 300 corresponding to adjacent storage cells can have a larger volume, which is beneficial to improving the storage capacity of the capacitor 300.

[0037] Figure 2 Schematic diagram of another storage structure provided by an embodiment of the present disclosure.

[0038] Reference Figure 2 In some embodiments, multiple storage transistors 100 can also be arranged at intervals along the third direction Z. Along the third direction Z, multiple storage transistors 100 can share the same word line 101; multiple bit lines 200 can be arranged at intervals along the third direction Z; multiple capacitors 300 can be arranged at intervals along the third direction Z. Thus, the storage cells formed by the storage transistors 100 and the corresponding capacitors 300 can be stacked along the third direction Z to further improve the space utilization rate of the storage cells and the integration density of the storage structure. In addition, multiple storage transistors 100 along the third direction Z share the same word line 101, and the control ability of the word line 101 is further improved.

[0039] It should be noted that in the accompanying drawings provided in this embodiment, the angle between the first direction X and the second direction Y is 90°, and the third direction Z is perpendicular to the plane where the first direction X and the second direction Y are located as an example. In some embodiments, the angle between the first direction and the second direction may be 30°, 45°, or 60°, and the angle between the plane where the first direction and the second direction are located and the third direction may be 30°, 45°, or 60°. This embodiment does not constitute a limitation on the angles between the first direction, the second direction, and the third direction.

[0040] Referring Figure 1 and Figure 2 , in some embodiments, the capacitor 300 may include: a first electrode plate 301, a first electrode layer 302, a dielectric layer 303, and a second electrode layer 304. The first electrode plate 301 extends along the third direction Z; the first electrode layer 302 surrounds the first electrode plate 301 with the third direction Z as the axis; the dielectric layer 303 surrounds the first electrode layer 302 with the third direction Z as the axis; the second electrode layer 304 surrounds the dielectric layer 303 with the third direction Z as the axis, and the second electrode layer 304 is in electrical contact with the semiconductor layer 103 of the corresponding storage transistor 100.

[0041] Referring Figure 2 , when multiple storage transistors 100 are spaced apart along the third direction Z, and multiple capacitors 300 are spaced apart along the third direction Z, the multiple capacitors 300 may share the same first electrode plate 301 along the third direction Z. In this way, the control terminals of the first electrode plates of the capacitors 300 in the storage structure can be reduced, and the control ability of the storage unit can be improved.

[0042] In some embodiments, the material of the first electrode plate 301 may include at least one of platinum nickelide, titanium, tantalum, cobalt, silicon germanide, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0043] In some embodiments, the material of the first electrode layer 302 may include at least one of platinum nickelide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0044] In some embodiments, the material of the dielectric layer 303 may adopt a high-k material to improve the storage capacity of the capacitor 300. For example, high-k materials include but are not limited to: hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), silicon nitride, silicon oxide, zirconium oxide, titanium oxide, aluminum, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, etc.

[0045] In some embodiments, the material of the second electrode layer 304 may include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0046] In some embodiments, the material of the first electrode plate 301 may be the same as that of the first electrode layer 302. Thus, the first electrode plate 301 and the first electrode layer 302 can be formed simultaneously in the same process step to improve the manufacturing efficiency of the storage structure.

[0047] In some embodiments, the material of the first electrode layer 302 may be the same as or different from that of the second electrode layer 304.

[0048] In Figure 1 and Figure 2 For example, taking the shape of the capacitor 300 as a cylinder, it does not limit the shape of the capacitor 300. In some embodiments, the shape of the capacitor may also be a triangular prism, a quadrangular prism, or a polygonal prism.

[0049] In Figure 1 and Figure 2 For example, taking the gate dielectric layer 102 surrounding the word line 101 along the third direction Z and the semiconductor layer 103 surrounding the gate dielectric layer 102 along the third direction Z as an example, the first part 201 of the bit line 200 is in electrical contact with the surface of the semiconductor layer 103 of the memory transistor 100 close to the first side, and the second part 202 of the bit line 200 is in electrical contact with the surface of the semiconductor layer 103 of the memory transistor 100 close to the second side. In this way, a structure in which the entire channel wraps the word line can be formed, improving the contact area between the word line 101 and the channel, and at the same time, it is also beneficial to improve the space utilization rate of the memory transistor.

[0050] Figure 3 This is a top view of a memory cell along the third direction provided by an embodiment of the present disclosure. Among them, Figure 3 The shown memory cell includes a memory transistor, a capacitor, and a part of the bit line.

[0051] Referring to Figure 3 , when the word line 101 and the bit line 200 are turned on, two sub-channels can be respectively formed on both sides of the semiconductor layer 103 along the first direction X (in the direction shown by the arrows in the figure) to facilitate the passage of carriers. It is equivalent to that one memory transistor 100 can form two parallel sub-memory transistors to simultaneously control the storage and reading of a capacitor 300. In this way, it is beneficial to improve the stability of the storage and reading of the storage structure. In Figure 3 , taking the memory transistor 100 and the capacitor 300 corresponding to the first part 201 of the bit line 200 as an example for illustration, the memory transistor 100 and the capacitor 300 corresponding to the second part 202 of the corresponding bit line 200 are the same by analogy.

[0052] Figure 4 A top view of a storage structure along a third direction provided by an embodiment of the present disclosure.

[0053] Referring Figure 4 , in some embodiments, the gate dielectric layer 102 may also cover only a partial surface of the word line 101 with the third direction Z as an axis. Specifically, the storage structure may include: a plurality of filling portions 400, the filling portions 400 extend along the third direction Z, the filling portions 400 are located between the storage transistor 100 and the bit line 200, and in the first direction X, the filling portions 400 corresponding to adjacent storage transistors 100 are respectively located on the first side and the second side of the storage transistor 100, that is, the filling portions 400 may be located between the first portion 201 of the bit line 200 and the corresponding storage transistor 100, and may also be located between the second portion 202 of the bit line 200 and the corresponding storage transistor 100. Thus, the filling portions 400 can serve as a spacer structure between the word line 101 and the bit line 200 to avoid the problem of leakage between the word line 101 and the bit line 200, and the filling portions 400 can also avoid generating parasitic capacitance between the word line 101 and the bit line 200 to improve the stability of the storage structure.

[0054] In some embodiments, the material of the filling portion 400 may be a fluorinated polymer, a low dielectric constant glass fiber, a microporous quality polymer, a fluorinated polyurethane, a porous low dielectric constant fatty acid methyl ester, etc., such as a low dielectric constant material such as a silicon oxynitride compound, a silicon carbonitride compound, a silicon oxycarbide compound or a silicon oxycarbonitride compound.

[0055] Figure 5 Another top view of a storage cell along a third direction provided by an embodiment of the present disclosure, wherein Figure 5 the shown storage cell includes a storage transistor, a capacitor and a partial bit line.

[0056] Referring Figure 5 , the cross-sectional shapes of both the storage transistor 100 and the filling portion 400 are semicircular, and the cross-sectional shapes of the storage transistor 100 and the filling portion 400 are complementary. Thus, both ends of the semiconductor layer 103 in the first direction X are in electrical contact with the second portion 202 of the bit line 200. When the word line 101 and the bit line 200 are turned on, two sub-channel regions (in the directions indicated by the arrows in the figure) can be respectively formed on both sides of the semiconductor layer 103 in the first direction X to facilitate the passage of carriers. It is equivalent that one storage transistor 100 can form two parallel sub-storage transistors to simultaneously control the storage and reading of a capacitor 300. Thus, it is beneficial to improve the stability of storage and reading of the storage structure. In Figure 5In this case, taking the storage transistor 100 and the corresponding capacitor 300 located in the first part 201 of the filling portion 400 away from the bit line 200 as an example for illustration, the storage transistor 100 and the corresponding capacitor 300 located in the second part 202 of the filling portion 400 away from the bit line 200 are the same by analogy.

[0057] It should be noted that in Figure 5 in the plane perpendicular to the third direction Z, the cross-section of the storage transistor 100 and the cross-section of the filling portion 400 are symmetrically arranged along the first direction X, so the cross-sectional shape of the storage transistor 100 is complementary to the cross-sectional shape of the filling portion 400. In this way, the two ends of the semiconductor layer 103 in the first direction X are respectively in electrical contact with only the first part 201 of the bit line 200.

[0058] Figure 6 This is a top view of another storage cell provided by an embodiment of the present disclosure along the third direction, where Figure 6 the shown storage cell includes a storage transistor, a capacitor, and a part of the bit line.

[0059] Referring to Figure 6 , in some embodiments, in the plane perpendicular to the third direction Z, the cross-section of the storage transistor 100 and the cross-section of the filling portion 400 can be relatively arranged along the first direction X, and the cross-sectional area of the storage transistor 100 can be larger than the cross-sectional area of the filling portion 400. In this way, the two ends of the storage transistor 100 in the first direction X can also be in electrical contact with the first part 201 of the corresponding bit line 200 to increase the contact area between the semiconductor layer 103 and the bit line 200, thereby improving the control ability of the bit line 200.

[0060] It should be noted that in Figures 4 to 6 in the plane perpendicular to the third direction Z, taking the cross-sectional shape of the filling portion 400 as a semicircle and the cross-section of the storage transistor 100 as a semicircle (that is, the cross-sectional shape formed by the word line 101, the gate dielectric layer 102, and the semiconductor layer 103 is a semicircle) as an example for illustration, it does not limit the cross-sectional shape of the filling portion 400 and the cross-sectional shape of the storage transistor 100. In some embodiments, the cross-section of the storage transistor and the cross-section of the filling portion can both include a rectangle or a triangle, etc.

[0061] In some embodiments, the material of the word line 101 can include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0062] In some embodiments, the material of the gate dielectric layer 102 can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0063] In some embodiments, the material of the semiconductor layer 103 may include indium gallium zinc oxide or zinc tin oxide. By setting the material of the oxide semiconductor layer to indium gallium zinc oxide or zinc tin oxide, the ion mobility of the semiconductor layer 103 can be improved, thereby improving the performance of the subsequent semiconductor layer 103 as a channel region. The material of the semiconductor layer 103 may also be one or more of other similar materials such as indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, etc.

[0064] In some embodiments, the material of the bit line 200 may be a single metal, a metal compound, or an alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride, or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0065] As Figures 3 to 6 shown, in some embodiments, the surface where the memory transistor 100 contacts the capacitor 300 may adopt an embedded or large-area contact manner, which is beneficial to improving the electrical contact stability between the memory transistor 100 and the capacitor 300, reducing the contact resistance between the memory transistor 100 and the capacitor 300, and improving the efficiency of the semiconductor structure.

[0066] Figure 7 It is a top view of another memory structure provided by an embodiment of the present disclosure along the third direction.

[0067] Referring to Figure 7 , in some embodiments, the memory structure may further include an extended bit line 500, a selection transistor 600, and a common bit line 700. The extended bit line 500 is arranged along the second direction Y, and one end of the extended bit line 500 is connected to the end of the bit line 200 along the first direction X; the selection transistor 600 is located on the side of the extended bit line 500 away from the bit line 200 along the first direction X, and one of the source or drain of the selection transistor 600 is electrically connected to the extended bit line 500; the common bit line 700 extends along the second direction Y, and the common bit line 700 is located on the side of the selection transistor 600 away from the extended bit line 500 along the first direction X, and the common bit line 700 is electrically connected to the other of the source or drain of the selection transistor 600. In this way, when multiple memory structures are arranged along the second direction Y, each bit line 200 can be connected to the common bit line 700 through at least one selection transistor 600, and the conduction of different bit lines 200 is controlled by the selection transistor 600.

[0068] In Figure 7 Taking the number of the selection transistors 600 as two for example, in some embodiments, the number of the selection transistors 600 may also be 1, 3, 5, etc. Thus, when the number of the selection transistors 600 is multiple, the multiple selection transistors 600 may be arranged along the second direction Y. Along the second direction Y, the multiple selection transistors 600 share the same extended bit line 500 and the same common bit line 700. Thus, the bit line 200 may be turned on through any one of the multiple selection transistors 600, or the bit line 200 may be turned on only when at least two of the multiple selection transistors 600 are turned on simultaneously, that is, the connection state of the bit line 200 is controlled through multiple control terminals to improve the control diversity and stability of the storage structure.

[0069] It should be noted that in Figure 7 Taking the example that there is a filling portion 400 between the storage transistor 100 and the bit line 200 for illustration, wherein the structure of the selection transistor 600 is the same as that of the storage transistor 100. Specifically, the selection transistor 600 may also include a word line 601, a gate dielectric layer 602, and a semiconductor layer 603. The word line 601 of the selection transistor 600 extends along the third direction Z. The gate dielectric layer 602 of the selection transistor 600 surrounds at least part of the surface of the word line 601 of the selection transistor 600 with the third direction Z as the axis. The semiconductor layer 603 of the selection transistor 600 surrounds the surface of the gate dielectric layer 602 of the selection transistor 600 with the third direction Z as the axis. The filling portion 400 is also located between the selection transistor 600 and the extended bit line 500 to avoid problems of leakage or parasitic capacitance between the word line 601 of the selection transistor 600 and the extended bit line 500.

[0070] In some embodiments, the structure of the storage transistor may also be different from that of the selection transistor.

[0071] The word line 601, the gate dielectric layer 602, and the semiconductor layer 603 of the selection transistor 600 are the same as or similar to the word line 101, the gate dielectric layer 102, and the semiconductor layer 103 of the storage transistor 100, and will not be elaborated herein.

[0072] In some embodiments, the material of the extended bit line 500 may be a single metal, a metal compound, or an alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride, or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0073] In some embodiments, the material of the extended bit line 500 may be the same as that of the bit line 200, so as to facilitate the formation of the bit line 200 and the extended bit line 500 in the same process step. In some embodiments, the material of the extended bit line 500 may also be different from that of the bit line 200.

[0074] Reference Figure 7 , in some embodiments, the contact surface between the extended bit line 500 and the bit line 200 may adopt an embedded or large-area contact manner, which can help improve the stability of the electrical contact between the extended bit line 500 and the bit line 200, reduce the contact resistance between the extended bit line 500 and the bit line 200, and improve the efficiency of the semiconductor structure.

[0075] In some embodiments, the material of the common bit line 700 may be a single metal, a metal compound or an alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum or platinum.

[0076] In some embodiments, the material of the common bit line 700 may be the same as or different from that of the bit line 200. In some embodiments, the material of the common bit line 700 may be the same as or different from that of the extended bit line 500.

[0077] Reference Figure 7 , in some embodiments, the electrical contact surface between the semiconductor layer 603 of the selection transistor 600 and the common bit line 700 may adopt an embedded or large-area contact manner, which can help improve the stability of the electrical contact between the common bit line 700 and the semiconductor layer 603, reduce the contact resistance between the common bit line 700 and the semiconductor layer 603, and improve the efficiency of the semiconductor structure.

[0078] In Figure 7 , only the extended bit line 500, the selection transistor 600 and the common bit line 700 are provided at one end of the bit line 200 along the first direction X. In some embodiments, the extended bit line, the selection transistor and the common bit line may be provided at both ends of the bit line along the first direction.

[0079] In the storage structure provided by the embodiments of the present disclosure, a storage transistor 100 and a corresponding capacitor 300 form a storage cell. Multiple storage cells are arranged at intervals along a first direction X. The storage or reading of the storage cells can be controlled through a word line 101 and a bit line 200. Among them, the storage transistor 100 includes a word line 101, a gate dielectric layer 102, and a semiconductor layer 103. The word line 101 extends along a third direction Z. The gate dielectric layer 102 surrounds at least part of the surface of the word line 101 with the third direction Z as the axis. The semiconductor layer 103 is located on the surface of the gate dielectric layer 102 away from the word line 101. Thus, with the semiconductor layer 103 as the channel, a structure in which the channel wraps the word line 101 is formed, improving the space utilization rate of the storage transistor 100, being beneficial to improving the integration density of the storage structure. At the same time, the area of the word line 101 covering the channel increases compared with that of a planar-structured storage transistor, being beneficial to improving the control force of the word line 101. Along the first direction X, the bit line 200 includes alternately connected first parts 201 and second parts 202. The first parts 201 are located on a first side of the storage transistor 100, and the second parts 202 are located on a second side of an adjacent storage transistor 100. Then, along the first direction X, the bit line 200 is alternately arranged on the first side and the second side of the storage transistor 100. The gap between adjacent storage transistors 100 along the first direction X is equal to the size of the bit line 200 along the first direction X, improving the arrangement density of the storage transistors 100 along the first direction X, and further improving the integration density of the storage structure. Capacitors 300 corresponding to adjacent storage cells are respectively located on the first side and the second side of the storage transistors 100 to which they are respectively connected. Then, the capacitors 300 corresponding to adjacent storage cells can have a larger volume, being beneficial to improving the storage capacity of the capacitors 300.

[0080] Another embodiment of the present disclosure provides a manufacturing method of a storage structure, which can be used to form the above storage structure to improve the integration density of the storage structure. It should be noted that for the same or corresponding parts as those in the above embodiments, reference can be made to the corresponding descriptions in the foregoing embodiments, and details will not be elaborated hereinafter. The manufacturing method of the storage structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0081] Figures 8 to 16 FIGURES are structural schematic diagrams corresponding to the respective steps of a manufacturing method of a storage structure provided in an embodiment of the present disclosure. Among them, Figures 9 to 16 both include a top view corresponding to the respective steps of the manufacturing method of the storage structure and a cross-sectional structural schematic diagram along the AA1 direction.

[0082] The manufacturing method of the storage structure includes:

[0083] Refer to Figure 8, a substrate 800 is provided, and a memory transistor 100 is formed on the substrate 800. A plurality of memory transistors 100 are arranged at intervals along a first direction X. The memory transistor 100 includes a first side and a second side that are oppositely disposed along a second direction Y. The memory transistor 100 includes: a word line 101, a gate dielectric layer 102, and a semiconductor layer 103. The word line 101 extends along a third direction Z; the gate dielectric layer 102 surrounds at least a part of the surface of the word line 101 with the third direction Z as an axis; the semiconductor layer 103 is located on the surface of the gate dielectric layer 102 away from the word line 101; a bit line 200 is formed. The bit line 200 includes a first part 201 and a second part 202 that are alternately connected along the first direction X. The first part 201 is located on the first side of the memory transistor 100, and the second part 202 is located on the second side of an adjacent memory transistor 100. Along the first direction X, the semiconductor layers 103 of adjacent memory transistors 100 are respectively connected to the first part 201 and the second part 202; a plurality of capacitors 300 are formed. The capacitors 300 are located on a side of the memory transistor 100 away from the bit line 200 along the second direction Y, and the capacitors 300 are electrically connected to the semiconductor layer 103.

[0084] In some embodiments, the substrate 800 may be a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.

[0085] In some embodiments, referring to Figures 9 to 13 , the steps of forming the memory transistor 100 and the bit line 200 on the substrate 800 are as follows:

[0086] Referring to Figure 9 , a stacked structure 801 is formed on the substrate 800. The stacked structure 801 includes a stacked insulating layer 811 and a sacrificial layer 812; the stacked structure 801 is patterned to form a plurality of active holes 821 arranged at intervals along the first direction X. The active holes 821 include sub-active holes 822 located in the sacrificial layer 812. Along the third direction Z, the orthographic projection size of the sub-active holes 822 is larger than the orthographic projection size of the active holes 821, and the adjacent sub-active holes 822 along the first direction X are interconnected.

[0087] In some embodiments, the steps of patterning the stacked structure 801 to form the active holes 821 and the sub-active holes 822 may be: etching the stacked structure 801 along the third direction Z to form a plurality of active holes 821 arranged at intervals along the first direction X in the stacked structure 801; then etching the sacrificial layer 812 along the first direction X and the second direction Y with the active holes 821 to form the sub-active holes 822.

[0088] In some embodiments, the sacrificial layer 812 is made of a different material from the insulating layer 811. In this way, the sacrificial layer 812 and the insulating layer 811 can have different etching selectivity ratios. Thus, when the active hole 821 etches the sacrificial layer 812 along the first direction X and the second direction Y, the size of the active hole 821 in the insulating layer 811 can be unaffected or less affected.

[0089] In some embodiments, the material for forming the sacrificial layer 812 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0090] In some embodiments, the material for forming the insulating layer 811 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0091] Refer to Figure 10 , a conductive layer 211 is formed, and the conductive layer 211 is located on the inner wall of the sub-active hole 822.

[0092] In some embodiments, the material for forming the conductive layer 211 may include a single metal, a metal compound, or an alloy. Among them, the single metal may be cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum, etc.; the metal compound may be tungsten nitride, tantalum nitride, or titanium nitride; the alloy may be an alloy material composed of at least two of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0093] Refer to Figure 11 , the conductive layer 211 is patterned to remove the conductive layer 211 on the opposite inner walls of adjacent sub-active holes 822 along the second direction X, and the remaining conductive layer 211 serves as the bit line 200.

[0094] During the process of patterning the conductive layer 211, in order to make the remaining conductive layer 211 continuous along the first direction X, so as to form a first part 201 and a second part 202 that are alternately connected along the first direction X, a stepped structure is formed on the surface of the remaining conductive layer 211 between adjacent sub-active holes 822. In this way, after the semiconductor layer is formed subsequently, the contact area between the semiconductor layer and the bit line 200 increases, improving the stability of the electrical connection between the semiconductor layer and the bit line 200.

[0095] Refer to Figure 12 , a filling portion 400 is formed. The filling portion 400 is located on the inner wall of the bit line 200 and fills some of the sub-active holes 822 and some of the active holes 821. The filling portion 400 can serve as an isolation structure between the word line formed subsequently and the bit line 200, avoiding problems such as leakage or parasitic capacitance between the word line and the bit line 200.

[0096] Refer to Figure 13, a semiconductor layer 103 is formed. The semiconductor layer 103 is at least located on the inner wall of the sub-active hole 822 away from the bit line 200 and is in electrical contact with the bit line 200; a gate dielectric layer 102 is formed, and the gate dielectric layer 102 is located on the inner wall of the semiconductor layer 103; a word line 101 is formed, and the word line 101 fills the remaining sub-active holes 822 and active holes 821. The word line 101, the gate dielectric layer 102, and the semiconductor layer 103 constitute a memory transistor 100.

[0097] In some embodiments, referring to Figure 14 , a filling portion 400 may not be formed between the formation of the semiconductor layers 103. When the semiconductor layer 103 is formed, the semiconductor layer 103 is also located on the inner wall of the bit line 200. In this way, a structure in which the word line is wrapped by the entire channel can be formed, the contact area between the word line 101 and the channel can be increased, and at the same time, it is beneficial to improve the space utilization rate of the memory transistor.

[0098] In some embodiments, referring to Figure 15 , in the step of patterning the stacked structure 801 to form a plurality of active holes 821 arranged at intervals in the first direction X, it may further include: forming a plurality of capacitor holes 311 in the stacked structure 801.

[0099] In some embodiments, the capacitor hole 311 includes a sub-capacitor hole 312. In the second direction Y, the sub-capacitor hole 312 communicates with the corresponding sub-active hole 822 to facilitate the connection between the semiconductor layer 103 and the capacitor 300.

[0100] Referring to Figure 16 , forming the capacitor 300 includes: forming a second electrode layer 304 that covers the inner wall of the sub-capacitor hole 312, forming a dielectric layer 303 that covers the inner wall of the second electrode layer 304; forming a first electrode layer 302 that covers the inner wall of the dielectric layer 303; forming a first electrode plate 301 that fills the remaining capacitor holes 311 and sub-capacitor holes 312.

[0101] In some embodiments, as Figure 16 shown, before forming the memory transistor 100 and the bit line 200, the active hole 821 may be filled with an insulating material first. After forming the capacitor 300 in the capacitor hole 311, the insulating material in the active hole 821 is then removed to form the memory transistor 100 and the bit line 200. In some embodiments, the capacitor hole may be filled with an insulating material first. After forming the memory transistor and the bit line, the insulating material in the capacitor hole is then removed to form the capacitor. The formation sequence of the capacitor 300, the memory transistor 100, and the bit line 200 is not limited in this embodiment.

[0102] In some embodiments, the insulating material may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc. The insulating material may also be a fluorinated polymer, a low dielectric constant glass fiber, a microporous mass polymer, a fluorinated polyurethane, a porous low dielectric constant fatty acid methyl ester, etc., such as low dielectric constant materials such as silicon oxynitride compounds, silicon carbonitride compounds, silicon oxycarbon compounds or silicon oxycarbonitride compounds.

[0103] In some embodiments, after forming a layer of memory transistors 100, bit lines 200, and capacitors 300, a stacked structure 801 may be further formed on the memory transistors 100, bit lines 200, and capacitors 300 along the third direction Z, and the above-described manufacturing method of the memory structure may be repeated to form a memory structure stacked along the third direction Z as Figure 8 shown. Along the third direction Z, the word lines 101 of the plurality of memory transistors 100 are interconnected, and the first electrode plates 301 of the plurality of capacitors 300 are interconnected. Thus, the plurality of memory transistors 100 along the third direction Z can share the control terminal of the same word line 101, and the plurality of capacitors 300 can share the control terminal of the same first electrode plate 301.

[0104] The manufacturing method of the storage structure provided by the embodiments of the present disclosure forms a storage transistor 100 and a corresponding capacitor 300 to constitute a storage cell. Multiple storage cells are arranged at intervals along the first direction X. The storage or reading of the storage cell can be controlled through the word line 101 and the bit line 200. Among them, the storage transistor 100 includes a word line 101, a gate dielectric layer 102, and a semiconductor layer 103. The word line 101 extends along the third direction Z. The gate dielectric layer 102 surrounds at least part of the surface of the word line 101 with the third direction Z as the axis. The semiconductor layer 103 is located on the surface of the gate dielectric layer 102 away from the word line 101. Thus, with the semiconductor layer 103 as the channel, a structure in which the channel wraps the word line 101 is formed, improving the space utilization rate of the storage transistor 100, being beneficial to improving the integration density of the storage structure. At the same time, the area of the word line 101 covering the channel increases compared with that of the storage transistor in the planar structure, being beneficial to improving the control force of the word line 101. Along the first direction X, the bit line 200 includes an alternately connected first part 201 and a second part 202. The first part 201 is located on the first side of the storage transistor 100, and the second part 202 is located on the second side of the adjacent storage transistor 100. Then, along the first direction X, the bit line 200 is alternately arranged on the first side and the second side of the storage transistor 100. The gap between adjacent storage transistors 100 along the first direction X is equal to the size of the bit line 200 along the first direction X, improving the arrangement density of the storage transistors 100 along the first direction X, and further improving the integration density of the storage structure. The capacitors 300 corresponding to adjacent storage cells are respectively located on the first side and the second side of the storage transistors 100 to which they are respectively connected. Then, the capacitors 300 corresponding to adjacent storage cells can have a larger volume, being beneficial to improving the storage capacity of the capacitors 300.

[0105] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure. In practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A storage structure, characterized in that, Comprising: Storage transistors, a plurality of the storage transistors are arranged at intervals along a first direction, the storage transistors include a first side and a second side oppositely arranged along a second direction, the storage transistors include: a word line, a gate dielectric layer and a semiconductor layer, the word line extends along a third direction; the gate dielectric layer surrounds at least a part of the surface of the word line with the third direction as an axis; the semiconductor layer is located on the surface of the gate dielectric layer away from the word line; Bit lines, the bit lines include a first part and a second part alternately connected along the first direction, the first part is located on the first side of the storage transistors, the second part is located on the second side of the adjacent storage transistors, in the first direction, the semiconductor layers of the adjacent storage transistors are respectively connected to the first part and the second part; A plurality of capacitors, the capacitors are located on a side of the storage transistors away from the bit lines along the second direction, and the capacitors are electrically connected to the semiconductor layers.

2. The storage structure according to claim 1, characterized in that, The gate dielectric layer surrounds the word line with the third direction as an axis, the semiconductor layer surrounds the gate dielectric layer with the third direction as an axis, the first part of the bit line is in electrical contact with the surface of the semiconductor layer of the storage transistor close to the first side, and the second part of the bit line is in electrical contact with the surface of the semiconductor layer of the storage transistor close to the second side.

3. The storage structure according to claim 1, characterized in that, Further comprising: A plurality of filling portions, the filling portions extend along the third direction, the filling portions are located between the storage transistors and the bit lines, in the first direction, the corresponding filling portions of the adjacent storage transistors are respectively located on the first side and the second side of the storage transistors.

4. The storage structure according to claim 3, characterized in that, In a plane perpendicular to the plane where the third direction is located, the cross-sections of the storage transistors and the filling portions are symmetrically arranged along the first direction.

5. The storage structure according to claim 4, characterized in that, The cross-sections of the storage transistors and the filling portions both include a semicircle, a rectangle or a triangle.

6. The storage structure according to claim 1, characterized in that, A plurality of the storage transistors are arranged at intervals along the third direction, in the third direction, a plurality of the storage transistors share the same word line; a plurality of the bit lines are arranged at intervals along the third direction.

7. The storage structure according to claim 1, characterized in that, The capacitor includes: A first electrode plate, the first electrode plate extends along the third direction; A first electrode layer, the first electrode layer surrounds the first electrode plate with the third direction as an axis; A dielectric layer, the dielectric layer surrounds the first electrode layer with the third direction as an axis; A second electrode layer, the second electrode layer surrounds the dielectric layer with the third direction as an axis, and the second electrode layer is electrically connected to the semiconductor layer of the corresponding storage transistor.

8. The storage structure according to claim 1, characterized in that, Further comprising: An extended bit line, the extended bit line is arranged along the second direction, and one end of the extended bit line is connected to the end of the bit line along the first direction; A selection transistor, the selection transistor is located on a side of the extended bit line away from the bit line along the first direction, One of the source or drain of the selection transistor is electrically connected to the extended bit line; A common bit line, the common bit line extending along the second direction, the common bit line being located on a side of the selection transistor away from the extended bit line in the first direction and being electrically connected to the other of the source or drain of the selection transistor.

9. The storage structure according to claim 8, characterized in that, The structure of the selection transistor is the same as that of the storage transistor.

10. The storage structure according to claim 8 or 9, characterized in that, The number of the selection transistors is plural, the plural selection transistors are arranged along the second direction, and in the second direction, the plural selection transistors share the same extended bit line and the same common bit line.

11. A manufacturing method of a storage structure, characterized in that, Comprising: Providing a substrate; Forming storage transistors on the substrate, the plural storage transistors being arranged at intervals in the first direction, the storage transistor including a first side and a second side oppositely arranged in the second direction, the storage transistor including: a word line, a gate dielectric layer, and a semiconductor layer, the word line extending along a third direction; the gate dielectric layer surrounding at least a part of the surface of the word line with the third direction as an axis; the semiconductor layer being located on a surface of the gate dielectric layer away from the word line; Forming a bit line, the bit line including a first part and a second part alternately connected in the first direction, the first part being located on the first side of the storage transistor, the second part being located on the second side of the storage transistor, and in the first direction, the semiconductor layers of adjacent storage transistors are respectively connected to the first part and the second part; Forming plural capacitors, the capacitors being located on a side of the storage transistor away from the bit line in the second direction, the capacitors being electrically connected to the semiconductor layer.

12. The manufacturing method of the storage structure according to claim 11, characterized in that, Forming the storage transistor and the bit line on the substrate includes: Forming a stacked structure on the substrate, the stacked structure including a stacked insulating layer and a sacrificial layer; Patterning the stacked structure to form plural active holes arranged at intervals in the first direction, the active holes including sub-active holes located in the sacrificial layer, in the third direction, a projected size of the sub-active holes being larger than a projected size of the active holes, and the sub-active holes adjacent to each other in the first direction being communicated with each other; Forming a conductive layer, the conductive layer being located on an inner wall of the sub-active holes; Patterning the conductive layer to remove the conductive layer on opposite inner walls of adjacent sub-active holes in the second direction, and the remaining conductive layer serving as the bit line; Forming the semiconductor layer, the semiconductor layer being at least located on an inner wall of the sub-active holes on a side away from the bit line and being in electrical contact with the bit line; Forming the gate dielectric layer, the gate dielectric layer being located on an inner wall of the semiconductor layer; Forming the word line, the word line filling the remaining sub-active holes and the active holes, and the word line, the gate dielectric layer, and the semiconductor layer constituting the storage transistor.

13. The manufacturing method of the storage structure according to claim 12, wherein, Before forming the semiconductor layer, further comprising: Forming a filling portion, the filling portion being located on an inner wall of the bit line and filling part of the sub-active holes and part of the active holes.

14. The manufacturing method of the storage structure according to claim 12, wherein, Forming the semiconductor layer includes: the semiconductor layer is also located on an inner wall of the bit line.

15. The manufacturing method of the storage structure according to claim 12, wherein, In the step of graphically representing the stacked structure to form a plurality of active holes spaced apart in the first direction, it further includes: forming a plurality of capacitor holes in the stacked structure; After forming the storage transistor and the bit line, it further includes: filling the capacitor holes to form the capacitor, the capacitor including: a first electrode plate extending in the third direction, the first electrode plate being located on a side of the storage transistor away from the bit line in the second direction; a first electrode layer surrounding the first electrode plate with the third direction as an axis; a dielectric layer surrounding the first electrode layer with the third direction as an axis; a second electrode layer surrounding the dielectric layer with the third direction as an axis, and the second electrode layer being in electrical contact with the semiconductor layer of the corresponding storage transistor.

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