Semiconductor structure and method of making the same, three-dimensional memory

Abstract

The embodiment of the present disclosure relates to a semiconductor structure and a preparation method thereof, and a three-dimensional memory, the semiconductor structure comprising: a first word line extending along a first direction; a semiconductor layer surrounding part of a side surface of the first word line, the semiconductor layer comprising: a channel region and source-drain regions located on both sides of the channel region, the channel region and the source-drain regions being arranged in a circumferential direction around the side surface of the first word line; a second word line extending along the first direction, the second word line being located on a side of the semiconductor layer opposite to the first word line; a bit line located on the side of the semiconductor layer away from the first word line and extending along a second direction; and a capacitor located on the side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction and are respectively in electrical contact with the source-drain regions. The semiconductor structure provided by the embodiment of the present disclosure can at least improve the stability of the channel region while reducing the overall size of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a preparation method thereof, and a three-dimensional memory. BACKGROUND

[0002] With the increasing integration of semiconductor devices, the size of memory, such as dynamic random access memory (DRAM), is becoming smaller and smaller, and the structure of three-dimensional memory is attracting more and more attention.

[0003] In the structure of three-dimensional memory, transistors are usually horizontally stacked to try to improve the integration of the memory. However, as the integration density of dynamic memory develops in the direction of higher and higher, higher requirements are put forward for the size of the transistor in the structure of the dynamic memory array. With the further reduction of the size of the transistor, it inevitably leads to the degradation of the performance of the memory device. For example, with the reduction of the size of the channel of the transistor, the stability of the channel is low, which damages the performance of the transistor, and further causes the reduction of the electrical performance of the memory.

[0004] Therefore, how to reduce the size of the transistor while ensuring the stability of the channel region has become a problem to be solved at present. SUMMARY

[0005] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, and a three-dimensional memory, which can at least solve the above problems.

[0006] Embodiments of the present disclosure provide a semiconductor structure, comprising: a first word line, the first word line extending along a first direction; a semiconductor layer, the semiconductor layer surrounding part of the side surface of the first word line, the semiconductor layer comprising: a channel region and source-drain regions located on both sides of the channel region, the channel region and the source-drain regions being arranged circumferentially around the side surface of the first word line; a second word line, the second word line extending along the first direction, the second word line being located on the side of the semiconductor layer away from the first word line and being oppositely arranged with the first word line; a bit line, the bit line being located on the side of the semiconductor layer away from the first word line and extending along a second direction; and a capacitor, the capacitor being located on the side of the semiconductor layer away from the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction and respectively electrically contact the source-drain regions, and the second direction intersects the third direction.

[0007] In some embodiments, the semiconductor structure further comprises: a first gate dielectric layer located between the semiconductor layer and the first word line; and a second gate dielectric layer located between the second word line and the semiconductor layer, the second gate dielectric layer covering the channel region and exposing the source-drain regions.

[0008] In some embodiments, the material of the semiconductor layer comprises IGZO.

[0009] In some embodiments, a first word line side opposite to the source / drain region of the semiconductor layer is arc-shaped, the first gate dielectric layer covers the first word line side in a shape-following manner, and the source / drain region of the semiconductor layer covers the first gate dielectric layer side in a shape-following manner.

[0010] In some embodiments, the semiconductor structure further comprises: a support layer extending along a third direction, the support layer having a first side opposite to a second side along a second direction, and two third sides opposite to each other along the third direction, the semiconductor layer and the first word line being embedded in the first side, and the second word line being embedded in the second side, wherein the third sides of the support layer expose the source / drain region of the semiconductor layer.

[0011] In some embodiments, a maximum width dimension of the first word line along the third direction is greater than a maximum width dimension of the second word line along the third direction.

[0012] Correspondingly, the embodiments of the present disclosure further provide a three-dimensional memory comprising a plurality of semiconductor structures as any one of the above, a plurality of semiconductor structures arranged along the second direction share a bit line, and a plurality of semiconductor structures arranged along the first direction share the first word line and the second word line.

[0013] Correspondingly, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: forming a first word line extending along a first direction; forming a semiconductor layer surrounding part of a side of the first word line, the semiconductor layer comprising: a channel region and source / drain regions located on both sides of the channel region, the channel region and the source / drain regions being arranged in a circumferential direction around the side of the first word line; forming a second word line extending along the first direction, the second word line being located on a side of the semiconductor layer opposite to the first word line; forming a bit line located on the side of the semiconductor layer opposite to the first word line and extending along a second direction; and forming a capacitor located on the side of the semiconductor layer opposite to the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line along a third direction, and respectively electrically contact the source / drain regions, and the second direction intersects the third direction.

[0014] In some embodiments, before the step of forming the first word line, the method further comprises: forming a first gate dielectric layer covering part of a side of the first word line, the semiconductor layer covering a surface of the first gate dielectric layer; and forming a second gate dielectric layer located on a side of the semiconductor layer away from the first gate dielectric layer and covering the channel region.

[0015] In some embodiments, the method for forming the semiconductor layer, the first gate dielectric layer and the second gate dielectric layer comprises: forming a support layer, the support layer extending along a third direction, the support layer having a first side and a second side opposite to each other along a second direction, and two third sides opposite to each other along the third direction; etching part of the support layer from the first side of the support layer to form a first groove extending from the first side to the second side; forming an initial second gate dielectric layer conforming to the first groove; forming a semiconductor layer conforming to the initial second gate dielectric layer in the first groove; forming a first gate dielectric layer conforming to a surface of the semiconductor layer in the first groove; etching part of the support layer and part of the initial second gate dielectric layer from the third side of the support layer until part of a surface of the semiconductor layer facing away from the first word line is exposed, and the remaining part of the initial second gate dielectric layer serving as the second gate dielectric layer.

[0016] In some embodiments, the method for forming the first word line comprises: forming the first word line in the remaining first groove, the first word line filling the first groove.

[0017] In some embodiments, the method for forming the second word line comprises: etching part of the support layer from the second side of the support layer to form a second groove extending from the second side to the first side; and forming the second word line filling the second groove.

[0018] In some embodiments, after the step of forming the second word line, the first groove is formed, the first groove exposing a side surface of the second word line facing the first groove.

[0019] In some embodiments, in the third direction, an opening size of the first groove is greater than an opening size of the second groove.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] In the semiconductor structure provided by the embodiments of the present disclosure, the semiconductor layer is arranged to surround part of the side surface of the first word line, and the channel region and the source / drain region of the semiconductor layer are arranged in a circumferential direction around the side surface of the first word line, that is, the channel region and the source / drain region are both located on the side surface of the word line. Compared with the semiconductor layer extending in the same direction, the entire semiconductor layer surrounds part of the side surface of the word line, which can reasonably utilize the space on the circumferential side of the word line, greatly reduces the space occupied by the semiconductor layer in the same horizontal direction, reduces the overall size of the transistor formed by the semiconductor layer, and further enables more transistors to be arranged in the memory, thereby improving the integration density of the memory. In addition, the second word line is arranged on the side of the semiconductor layer away from the first word line to form a double-gate structure, which increases the gate control capability and improves the stability of the channel region. In this way, the stability of the channel region is ensured while the size of the transistor is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the embodiments described, but the subject matter of embodiments encompasses any and all implementations of one or more embodiments. For the avoidance of doubt, the subject matter of embodiments encompasses a combination of one or more embodiments with any and all features that are described herein. The subject matter of embodiments encompasses implementations in software, hardware, firmware, middleware, microcode, or any combination thereof. Although the subject matter of embodiments is described in connection with various embodiments, one or more embodiments are not limited to any embodiment or implementation in this summary. The terms "comprises", "comprising", "includes", "including", "has", "having" and the like are used synonymously to denote a non- restrictive inclusion (in other words, a quantity is comprised of one or more members) unless otherwise indicated through use of alternative terminology (such as "consisting" or "consisting essentially of"). The term "plurality" indicates a quantity of two or more, unless otherwise indicated. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration," unless otherwise indicated. The term "or" is used herein in a distributive sense, i.e., the term "or" is used to indicate a disjunctive term (i.e., the term "or" shall be interpreted as meaning one, some, or all of the listed terms, but not necessarily excluding additional terms). The term "about" is used herein to mean approximately, roughly, around, or in the immediate vicinity of, unless otherwise indicated. The phrase "connected to" is used herein to indicate a direct electrical connection which can contain intervening wired or wireless components.

[0023] Figure 1 A perspective view of a semiconductor structure according to an embodiment of the present disclosure;

[0024] Figure 2 A top view of a semiconductor structure according to an embodiment of the present disclosure;

[0025] Figure 3 A perspective view of another semiconductor structure according to an embodiment of the present disclosure;

[0026] Figure 4 A top view of another semiconductor structure according to an embodiment of the present disclosure;

[0027] Figure 5 A perspective view of yet another semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 6 A top view of yet another semiconductor structure according to an embodiment of the present disclosure;

[0029] Figure 7 A perspective view of a three-dimensional memory according to another embodiment of the present disclosure;

[0030] Figure 8 A perspective view of a step of forming an initial support layer and an isolation layer in a method of manufacturing a semiconductor structure according to another embodiment of the present disclosure;

[0031] Figure 9 A top view of a step of forming a first trench in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0032] Figure 10 A perspective view of a step of forming a first trench in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0033] Figure 11 A perspective view of a step of forming an isolation structure in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0034] Figure 12 A corresponding perspective view of the step of forming the second trench in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0035] Figure 13 A corresponding partial view of the step of forming the first recess in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0036] Figure 14 A corresponding partial view of the step of forming the first word line in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0037] Figure 15 A corresponding perspective view of the step of forming the third trench in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0038] Figure 16 A corresponding partial view of the step of forming the second recess in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0039] Figure 17 A corresponding plan view of the step of forming the second word line in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0040] Figure 18 A corresponding perspective view of the step of forming the second word line in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure is shown in the figure below;

[0041] Figure 19 A corresponding perspective view of the step of forming the third trench in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is shown in the figure below;

[0042] Figure 20 A corresponding partial view of the step of forming the second recess in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is shown in the figure below;

[0043] Figure 21 A corresponding partial view of the step of forming the second word line in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is shown in the figure below;

[0044] Figure 22 A corresponding perspective view of the step of forming the second word line in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is shown in the figure below;

[0045] Figure 23 A corresponding partial view of the step of forming the first recess in the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is shown in the figure below;

[0046] Figure 24 A corresponding perspective view of a step of forming a first opening in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 1A;

[0047] Figure 25 A corresponding partial view of a step of etching an initial second gate dielectric layer in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 2A;

[0048] Figure 26 A corresponding perspective view of a step of forming a bit line in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 3A;

[0049] Figure 27 A corresponding partial view of a step of forming a bit line in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 4A;

[0050] Figure 28 A corresponding perspective view of a step of forming a second opening in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 5A;

[0051] Figure 29 A corresponding partial view of a step of forming a second gate dielectric layer in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 6A;

[0052] Figure 30 A corresponding perspective view of a step of forming a capacitor in a method of manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. 7A. DETAILED DESCRIPTION

[0053] As can be seen from the background, how to reduce the size of the transistor while ensuring the stability of the channel region has become a problem to be solved at present. One of the reasons for the above problem is that the 3D stacked DRAM structure is widely studied in the current semiconductor structure. In the current 3D stacked semiconductor structure, a plurality of semiconductor layers are located on a substrate and extend along a direction parallel to the surface of the substrate, and the plurality of semiconductor layers are arranged in a stacked manner away from the substrate. The semiconductor layer includes a source-drain region and a channel region arranged adjacent to each other. The word line extends perpendicular to the surface of the substrate and is in electrical contact with the side surface of the channel region of the semiconductor layer. That is, the word line and the semiconductor layer are arranged adjacent to each other, the word line only contacts part of the side surface of the semiconductor layer, and the source-drain region in the semiconductor layer extends away from the channel region and occupies the space in the extension direction of the semiconductor layer. This results in that the transistor formed by each semiconductor layer occupies more space in the extension direction of the semiconductor layer, and as the size of the semiconductor structure decreases, the arrangement density of the transistor in the semiconductor structure cannot be further increased, and the gate control ability of the channel in the semiconductor layer is poor.

[0054] The embodiment of the present disclosure provides a semiconductor structure, and the channel region and the source-drain region are located on the side of the word line. Compared with the semiconductor layer extending in the same direction, the whole semiconductor layer surrounds the side of the word line part, which can reasonably use the space of the side of the word line, greatly reduces the space occupied by the semiconductor layer in the same horizontal direction, so that the overall size of the transistor formed by the semiconductor layer is reduced, and more transistors can be arranged in the memory, and the integration density of the memory is improved. In addition, the second word line is arranged on the side of the semiconductor layer away from the first word line, a double-gate structure is formed, the gate control ability is increased, and the stability of the channel region is improved. In this way, the size of the transistor is reduced while the stability of the channel region is ensured.

[0055] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to enable the readers to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0056] Figure 1 A three-dimensional structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 2 A top view structural schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 3 A three-dimensional structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 4 A top view structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided.

[0057] Figure 5 A three-dimensional structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided. Figure 6 A top view structural schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure is provided.

[0058] Reference Figures 1-2The semiconductor structure comprises a first word line 101 extending along a first direction X. The semiconductor structure further comprises a semiconductor layer 102 surrounding a part of a side surface of the first word line 101, the semiconductor layer 102 comprising a channel region 10 and source / drain regions 11 located on two sides of the channel region 10, the channel region 10 and the source / drain regions 11 being arranged in a circumferential direction around the side surface of the first word line 101. The semiconductor structure further comprises a second word line 103 extending along the first direction X, the second word line 103 being located on a side of the semiconductor layer 102 opposite to the first word line 101. The semiconductor structure further comprises a bit line 104 located on the side of the semiconductor layer 102 opposite to the first word line 101 and extending along a second direction Y. The semiconductor structure further comprises a capacitor 105 located on the side of the semiconductor layer 102 opposite to the first word line 101, wherein the bit line 104 and the capacitor 105 are located on opposite sides of the first word line 101 in a third direction W and are electrically connected to the source / drain regions 11 respectively, and the second direction Y intersects the third direction W.

[0059] Each semiconductor layer 102 can be used to form a transistor. The channel region 10 can be used to form a channel of the transistor, and the two source / drain regions 11 can be used to form a source and a drain of the transistor respectively. The bit line 104 can be electrically connected to the source, and the capacitor 105 can be electrically connected to the drain.

[0060] The first word line 101 and the second word line 103 are located on opposite sides of the semiconductor layer 102 respectively, and the second word line 103 is located opposite to the channel region 10. The first word line 101 and the second word line 103 are used to form two gates of the transistor respectively, forming a double-gate structure, increasing the gate control ability, and improving the stability of the channel region 10.

[0061] The channel region 10 and the source / drain regions 11 are arranged around the side surface of the word line, which can utilize the circumferential space of the word line to arrange the source / drain regions 11. Compared with the case that the source / drain regions 11 and the channel region 10 extend in the same horizontal direction, the space occupied by the source / drain regions 11 in the same horizontal direction can be greatly reduced, and thus the overall size of the transistor formed by the semiconductor layer 102 can be reduced. If multiple transistors need to be integrated in the same memory, the arrangement density of the transistors can be increased, and the integration density of the memory can be improved.

[0062] Specifically, in some embodiments, the semiconductor layer 102, the first word line 101 and the second word line 103 can be located on the same substrate. The first word line 101 and the second word line 103 extend along a direction perpendicular to the surface of the substrate, i.e., the first direction X is perpendicular to the surface of the substrate.

[0063] The bit line 104 and the capacitor 105 are located on the substrate, and the bit line 104 extends along a direction parallel to the surface of the substrate, i.e., a second direction Y is parallel to the surface of the substrate. In one specific example, the first direction X can be perpendicular to the second direction Y.

[0064] The bit line 104 and the capacitor 105 are located on the substrate, and the bit line 104 extends along a direction parallel to the surface of the substrate, i.e., a second direction Y is parallel to the surface of the substrate. In one specific example, the first direction X can be perpendicular to the second direction Y. In the related art, the semiconductor layer 102 is arranged to extend along the third direction W, and the source-drain region 11 is located on both sides of the channel region 10 along the third direction W, thereby being electrically connected to the bit line 104 and the capacitor 105, respectively. However, this will make the semiconductor layer 102 occupy a larger space along the third direction W, and the number of semiconductor layers 102 arranged at intervals along the third direction W is limited. In the embodiments of the present disclosure, the semiconductor layer 102 is arranged to surround the side surface of the first word line 101, and the source-drain region 11 is located on the side surface of the word line, thereby reducing the space occupied by the source-drain region 11 along the third direction W, and further reducing the size of the transistor formed by the semiconductor layer 102 along the third direction W. In this way, the number of transistors arranged at intervals along the third direction W can be increased, and the arrangement density of the transistors can be greatly increased.

[0065] In some embodiments, the material of the semiconductor layer 102 includes IGZO (indium gallium zinc oxide). IGZO is a new type of semiconductor material, which has a high electron mobility and good stability, and can improve the response rate of the transistor. In addition, using IGZO as the material of the semiconductor layer 102 can make the thickness of the semiconductor layer 102 smaller. In one specific example, the thickness of the semiconductor layer 102 can be close to the thickness of the first gate dielectric layer or the second gate dielectric layer, thereby further reducing the size of the semiconductor structure.

[0066] In some embodiments, the material of the semiconductor layer 102 can also be other semiconductor materials, for example, the material of the semiconductor layer 102 can also be germanium, germanium-silicon, or silicon-on-insulator.

[0067] In some embodiments, the material of the first word line 101 can be a metal-based material, for example, can include metal, metal nitride, metal silicide, or a combination thereof. The material of the second word line 103 can be a metal-based material, for example, can include metal, metal nitride, metal silicide, or a combination thereof. The metal can be at least one of aluminum, tungsten, silver, copper, gold, cobalt, nickel, or titanium, for example.

[0068] In some embodiments, the doping ion type of the source-drain region 11 can be different from the doping ion type of the channel region 10. For example, the doping ion type of the source-drain region 11 can be N-type doping ions, and the doping ion type of the channel region 10 can be P-type doping ions, so that the conductivity type of the transistor is N-type.

[0069] In some embodiments, the doping ion type of the source-drain region 11 can also be the same as the doping ion type of the channel region 10.

[0070] Reference is made to Figure 3 and Figure 4 In some embodiments, the semiconductor structure further comprises: a first gate dielectric layer 111 located between the semiconductor layer 102 and the first word line 101; and a second gate dielectric layer 112 located between the semiconductor layer 102 and the second word line 103, the second gate dielectric layer 112 covering the channel region 10 and exposing the source-drain region 11.

[0071] The first gate dielectric layer 111 is used to isolate the electric charge between the first word line 101 and the channel region 10 after the transistor is turned on, and the second gate dielectric layer 112 is used to isolate the electric charge between the second word line 103 and the channel region 10 after the transistor is turned on, so as to ensure the stability of the transistor.

[0072] The first gate dielectric layer 111 surrounds part of the side surface of the first word line 101 and directly contacts the side surface of the first word line 101. The semiconductor layer 102 covers the surface of the first gate dielectric layer 111 away from the first word line 101.

[0073] The second gate dielectric layer 112 is located on the side of the semiconductor layer 102 away from the first gate dielectric layer 111 and contacts part of the semiconductor layer 102. The second gate dielectric layer 112 at least covers the channel region 10 of the semiconductor layer 102, so as to isolate the electric charge between the second word line 103 and the channel region 10 after the transistor is turned on. The source-drain region 11 of the semiconductor layer 102 is not covered by the second gate dielectric layer 112, so that the surface of the source-drain region 11 can be exposed, so that the bit line 104 and the capacitor can be in electrical contact with the exposed source-drain region 11.

[0074] It can be found that the first gate dielectric layer 111 and the second gate dielectric layer 112 both surround the side surface of the first word line 101, so that the first gate dielectric layer 111 and the second gate dielectric layer 112 also do not occupy too much space in the third direction W, so that the size of the transistor in the third direction W can be small.

[0075] In some embodiments, the material of the first gate dielectric layer 111 can be silicon oxide or high-k dielectric material. The material of the second gate dielectric layer 112 can be silicon oxide or high-k dielectric material.

[0076] In some embodiments, the first word line 101 opposite to the source-drain region 11 is arc-shaped, the first gate dielectric layer 111 is conformal to the side surface of the first word line 101, and the semiconductor layer 102 is conformal to the side surface of the first gate dielectric layer 111.

[0077] Conformal refers to that the surface topography of the first gate dielectric layer 111 is consistent with the surface topography of the first word line 101 to be covered, and the surface topography of the semiconductor layer 102 is consistent with the surface topography of the first gate dielectric layer 111 to be covered. That is, the surface topography of the first gate dielectric layer 111 opposite to the source-drain region 11 is arc-shaped, and the surface topography of the semiconductor layer 102 of the source-drain region 11 is arc-shaped.

[0078] The arc-shaped surface has a large surface area. The surface topography of the semiconductor layer 102 of the source-drain region 11 is arc-shaped, so that the exposed area of the source-drain region 11 is large, and the contact area between the source-drain region 11 and the bit line 104 and the capacitor 105 is large, which ensures good electrical contact performance between the source-drain region 11 and the bit line 104 and the capacitor 105, and improves the signal transmission rate between the bit line 104 and the capacitor 105 and the source-drain region 11. It is not difficult to find that although the semiconductor layer 102 occupies a small area in the embodiment of the present disclosure, the contact area between the semiconductor layer 102 and the first word line 101, the bit line 104 and the capacitor 105 is not reduced. That is, the overall size of the semiconductor structure can be ensured to be small, while the electrical contact performance of the bit line 104, the capacitor 105 and the semiconductor layer 102 is taken into account, and the electrical performance of the semiconductor structure is ensured to be good.

[0079] Reference Figure 5 And Figure 6 In some embodiments, the semiconductor structure further comprises: a support layer 106 extending along the third direction W, the support layer 106 having a first side 1 and a second side 2 opposite along the second direction Y, and two third sides 3 opposite along the third direction W, the semiconductor layer 102 and the first word line 101 are embedded in the first side 1, and the second word line 103 is embedded in the second side 2, wherein the third side 3 of the support layer 106 exposes the source-drain region 11 of the semiconductor layer 102.

[0080] The support layer 106 can support the semiconductor layer 102. The semiconductor layer 102 and the first word line 101 are embedded in the support layer 106 from the first side 1 of the support layer 106, and the second word line 103 is embedded in the support layer 106 from the second side 2 of the support layer 106.

[0081] The third side 3 of the support layer 106 exposes the source-drain region 11 of the semiconductor layer 102, i.e. the source-drain region 11 is exposed outside the support layer 106. The bit line 104 contacts the source-drain region 11 and the third side 3 of the support layer 106, and can be electrically connected to the source-drain region 11 and can be supported by the support layer 106. The capacitor 105 contacts the source-drain region 11 and another third side 3 of the support layer 106, and can be electrically connected to the source-drain region 11 and can be supported by the support layer 106.

[0082] In some embodiments, the material of the support layer 106 is an insulating material, such as silicon nitride or the like.

[0083] In some embodiments, the first gate dielectric layer 111 and the second gate dielectric layer 112 are embedded in the support layer 106 from the first side 1.

[0084] That is, the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111 and the second gate dielectric layer 112 are all located in the support layer 106, and in the second direction Y, the overall size of the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111 and the second gate dielectric layer 112 is close to or the same as the width size of the support layer 106. Thus, only the width size of the support layer 106 in the second direction Y needs to be adjusted, and the overall size of the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111 and the second gate dielectric layer 112 in the second direction Y can be adjusted, so that the first word line 101, the second word line 103, the semiconductor layer 102, the first gate dielectric layer 111 and the second gate dielectric layer 112 occupy less space in the second direction Y, and more semiconductor structures can be arranged in the second direction Y.

[0085] In some embodiments, the side of the first word line 101 away from the second word line 103 can protrude out of the first side 1.

[0086] In some embodiments, the side of the first word line 101 away from the second word line 103 can be flush with the first side 1.

[0087] In some embodiments, the side of the second word line 103 away from the first word line 101 can protrude out of the first side 1.

[0088] In some embodiments, the side of the second word line 103 away from the first word line 101 can be flush with the first side 1.

[0089] In some embodiments, if the number of semiconductor layers 102 is multiple, the number of support layers 106 is also multiple, and the multiple support layers 106 are stacked in the first direction X. Each support layer 106 corresponds to a semiconductor layer 102. The word lines extend in the first direction X and correspond to each of the multiple semiconductor layers 102 stacked in the first direction X. The number of bit lines 104 can be multiple, the multiple bit lines 104 are stacked in the first direction X, and the bit lines 104 are electrically connected to the semiconductor layers 102 stacked in the first direction X one by one. The number of capacitors 105 can be multiple, the multiple capacitors 105 are stacked in the first direction X, and the capacitors 105 are electrically connected to the semiconductor layers 102 stacked in the first direction X one by one.

[0090] In some embodiments, the maximum width dimension of the first word line 101 in the third direction W is greater than the maximum width dimension of the second word line 103 in the third direction W.

[0091] Since the first gate dielectric layer 111, the semiconductor layer 102, and the second gate dielectric layer 112 all surround the side surface of the first word line 101, the maximum width dimension of the first word line 101 in the third direction W is set to be greater than the maximum width dimension of the second word line 103 in the third direction W, so that the side area of the first word line 101 is greater than that of the second word line 103, and the first gate dielectric layer 111, the semiconductor layer 102, and the second gate dielectric layer 112 surrounding the side surface of the first word line 101 are longer. In this way, the length and area of the source-drain region 11 of the semiconductor layer 102 are increased, and the contact area between the bit line 104 and the capacitor 105 and the source-drain region 11 is increased, so that the contact performance between the bit line 104 and the capacitor 105 and the source-drain region 11 is better.

[0092] In some embodiments, the maximum width dimension of the first word line 101 in the third direction W can also be equal to the maximum width dimension of the second word line 103 in the third direction W.

[0093] In the semiconductor structure provided by the above embodiments, the channel region 10 and the source-drain region 11 are both located on the side surface of the word line. Compared with the semiconductor layer 102 extending in the same direction, the entire semiconductor layer 102 surrounds part of the side surface of the word line, which reasonably utilizes the space on the side surface of the word line, greatly reduces the space occupied by the semiconductor layer 102 in the same horizontal direction, reduces the overall size of the transistor formed by the semiconductor layer 102, and further arranges more transistors in the memory to improve the integration density of the memory. In addition, the second word line 103 is arranged on the side of the semiconductor layer 102 away from the first word line 101 to form a double-gate structure, increase the gate control ability, and improve the stability of the channel region 10. In this way, the stability of the channel region 10 is ensured while the size of the transistor is reduced.

[0094] Correspondingly, the disclosure also provides a three-dimensional memory including a plurality of semiconductor structures as provided in the above embodiments. As shown in Figure 7 The plurality of semiconductor structures arranged along the second direction Y share one bit line 104, and the plurality of semiconductor structures arranged along the first direction X share the first word line 101 and the second word line 103. Each semiconductor structure corresponds to one capacitor 105.

[0095] Reference Figure 7 In particular, the plurality of semiconductor structures includes a plurality of semiconductor layers 102, which can be stacked along a direction perpendicular to the surface of the substrate. Each column of semiconductor layers 102 stacked along the direction perpendicular to the surface of the substrate is referred to as a stack structure. There can be a plurality of stack structures, and the plurality of stack structures can be arranged along the second direction Y and the third direction W. Each stack structure can share the same first word line 101 and the same second word line 103. Among them, the second direction Y and the third direction W are both parallel to the surface of the substrate, and the second direction Y and the third direction W are perpendicular to each other.

[0096] Since the semiconductor layer 102 is arranged around the side surface of the first word line 101, the source-drain region 11 is located on the side surface of the word line, which can reduce the space occupied by the source-drain region 11 in the third direction W, and further make the transistor formed by the semiconductor layer 102 smaller in size in the third direction W. That is, each semiconductor structure is smaller in size in the third direction W, and further more stack structures can be arranged in the third direction W, thereby increasing the integration of the three-dimensional memory.

[0097] The type of the three-dimensional memory can be DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0098] Correspondingly, the disclosure also provides a semiconductor structure preparation method, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of the disclosure will be described in detail below with reference to the accompanying drawings.

[0099] Reference Figures 8-18 The semiconductor structure preparation method includes:

[0100] The first word line 101 is formed, and the first word line 101 extends along the first direction X. The second word line 103 is formed, and the second word line 103 extends along the first direction X. The second word line 103 is located on the side of the semiconductor layer 102 away from the first word line 101, and is arranged opposite to the first word line 101. The semiconductor layer 102 is formed, and the semiconductor layer 102 surrounds part of the side surface of the first word line 101. The semiconductor layer 102 includes: a channel region 10 and source-drain regions 11 located on both sides of the channel region 10. The channel region 10 and the source-drain regions 11 are arranged in a circumferential direction around the side surface of the first word line 101.

[0101] The channel region 10 and the source-drain regions 11 are located on the side surface of the word line, which can reasonably utilize the circumferential space of the word line, so that the overall size of the transistor formed by the semiconductor layer 102 is reduced, and thus more transistors can be arranged in the memory, thereby improving the integration density of the memory. In addition, the second word line 103 is arranged on the side of the semiconductor layer 102 away from the first word line 101 to form a double-gate structure, increase the gate control ability, and improve the stability of the channel region 10, so that the size of the transistor is reduced while the stability of the channel region 10 is ensured.

[0102] In some embodiments, the first word line 101, the second word line 103, and the semiconductor layer 102 are formed on the substrate 100.

[0103] In some embodiments, the material of the substrate 100 can be a semiconductor material. In some embodiments, the material of the substrate 100 can be silicon. In some embodiments, the substrate 100 can also be germanium, germanium-silicon, or silicon-on-insulator.

[0104] In some embodiments, before the step of forming the first word line 101, the method further includes: forming a first gate dielectric layer 111 covering part of the side surface of the first word line 101, and the semiconductor layer 102 covers the surface of the first gate dielectric layer 111; and forming a second gate dielectric layer 112, which is located on the side of the semiconductor layer 102 away from the first gate dielectric layer 111 and covers the channel region 10.

[0105] The method of forming the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 will be described below.

[0106] In some embodiments, the method of forming the semiconductor layer 102, the first gate dielectric layer 111, and the second gate dielectric layer 112 includes:

[0107] Reference Figures 8-10 First, a support layer 106 is formed, and the support layer 106 extends along the third direction W. The support layer 106 has a first side 1 and a second side 2 opposite along the second direction Y, and two third sides 3 opposite along the third direction W.

[0108] In some embodiments, the method of forming the support layer 106 comprises:

[0109] Referring to Figure 8 forming a plurality of initial support layers 20 and a plurality of isolation layers 21 on the substrate 100, which are alternately stacked in a direction away from the substrate 100, i.e., the plurality of initial support layers 20 and the plurality of isolation layers 21 are alternately stacked in the first direction X. The material of the initial support layer 20 can be silicon nitride, and the material of the isolation layer 21 can be silicon oxide.

[0110] Referring to Figure 9 and Figure 10 performing etching on the plurality of initial support layers 20 and the plurality of isolation layers 21 to form a plurality of first trenches 30 spaced apart in the second direction Y, each of the first trenches 30 penetrating the plurality of initial support layers 20 and the plurality of isolation layers 21, and the bottom of the first trench 30 exposing the surface of the substrate 100. The initial support layers 20 spaced apart by the first trenches 30 form the support layers 106, each of the support layers 106 extending in the third direction W. That is, the support layers 106 are stacked between adjacent first trenches 30, and the support layers 106 are spaced apart by the isolation layers 21.

[0111] Referring to Figure 9 and Figure 10 In some embodiments, the substrate 100 comprises a first region 23 and a second region 24 adjacent to each other in the third direction W, and only the plurality of initial support layers 20 and the plurality of isolation layers 21 on the second region 24 are etched to form a plurality of first trenches 30 spaced apart in the second direction Y on the second region 24. The initial support layers 20 and the isolation layers 21 on the first region 23 are reserved and in contact with the third side 3 of the support layers 106. The initial support layers 20 and the isolation layers 21 on the first region 23 can be referred to as a sub-stack structure 40.

[0112] In some embodiments, the method of forming the first trenches 30 can comprise: performing a patterning process on the top surface of the isolation layer 21 on the first region 23 to define the position of the first trenches 30. In some embodiments, the patterning process can adopt any one of a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process.

[0113] Then, performing an etching process on the patterned isolation layer 21 to etch the isolation layer 21 and the initial support layer 20 to form the first trenches 30.

[0114] Referring to Figure 11After the support layer 106 is formed, the isolation structure 107 filling the first trench 30 is formed. The isolation structure 107 covers the support layer 106 and the sidewall of the isolation layer 21.

[0115] In some embodiments, the deposition process can be used to form the isolation structure 107.

[0116] In some embodiments, the material of the isolation structure 107 is different from the material of the support layer 106. Specifically, the material of the isolation structure 107 can be silicon oxide, and the material of the support layer 106 can be silicon nitride.

[0117] Referring to Figure 13 After the isolation structure 107 is formed, the support layer 106 can be etched from the first side 1 to form the first recess 51 extending from the first side 1 to the second side 2. The first recess 51 provides space for forming the first gate dielectric layer 111, the second gate dielectric layer 112, the semiconductor layer 102, and the first word line 101.

[0118] In some embodiments, the method of forming the first recess 51 can include:

[0119] Referring to Figure 12 The second trench 61 is formed in the isolation structure 107. The second trench 61 extends through the isolation structure 107, and the bottom of the second trench 61 exposes the surface of the substrate 100. The sidewall of the second trench 61 exposes the support layer 106 and the sacrificial layer. The second trench 61 only exposes part of the sidewall of each support layer 106 and each sacrificial layer. The support layer 106 exposed by the second trench 61 is etched later to form the first recess 51. That is, the second trench 61 formed actually positions the first recess 51 formed later.

[0120] In some embodiments, the method of forming the second trench 61 can include performing a patterning process on the top surface of the isolation structure 107, for example, using the SADP process or the SAQP process to define the position of the second trench 61.

[0121] Then, the patterned isolation structure 107 is etched until the surface of the substrate 100 is exposed to form the second trench 61.

[0122] Referring to Figure 13 After the second trench 61 is formed, the support layer 106 exposed by the second trench 61 is etched along the second trench 61 to form the first recess 51 by etching part of the width of the support layer 106.

[0123] Since the material of the isolation structure 107 is different from that of the support layer 106, and the material of the isolation layer 21 is different from that of the support layer 106, the support layer 106 can be etched only by using the etching selectivity ratio between the isolation structure 107 and the support layer 106, and the etching selectivity ratio between the isolation layer 21 and the support layer 106 to form the first recess 51.

[0124] In some embodiments, a wet etching process can be used to etch the support layer 106 to form the first recess 51.

[0125] Referring to Figure 14 After the first recess 51 is formed, an initial second gate dielectric layer 22 is formed along the second trench 61 to conformally cover the first recess 51. That is, the initial second gate dielectric layer 22 covers the sidewall of the first recess 51 and contacts the support layer 106 exposed by the sidewall of the first recess 51, so that the profile shape of the initial second gate dielectric layer 22 is the same as that of the first recess 51.

[0126] Referring to Figure 14 The semiconductor layer 102 is formed along the second trench 61 to conformally cover the initial second gate dielectric layer 22 within the first recess 51. That is, the semiconductor layer 102 covers the surface of the initial second gate dielectric layer 22, and the profile shape of the semiconductor layer 102 is the same as that of the initial second gate dielectric layer 22.

[0127] Referring to Figure 14 The first gate dielectric layer 111 is formed along the second trench 61 to conformally cover the surface of the semiconductor layer 102 within the first recess 51. That is, the first gate dielectric layer 111 covers the surface of the semiconductor layer 102, and the profile shape of the first gate dielectric layer 111 is the same as that of the semiconductor layer 102.

[0128] In some embodiments, a deposition process can be used to form the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111, respectively.

[0129] It can be understood that since the second trench 61 exposes not only the support layer 106 but also the isolation layer 21. In the step of depositing the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 into the first recess 51 along the second trench 61, the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 are also formed on the sidewall of the isolation layer 21. In order to separate the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 located in different first recesses 51, the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 covering the sidewall of the isolation layer 21 need to be removed.

[0130] In some embodiments, a dry etching process can be employed to remove the initial second gate dielectric layer 22, the semiconductor layer 102 and the first gate dielectric layer 111 on the sidewall of the isolation layer 21 in the second trench 61. Since the isolation layer 21 protrudes out of the first recess 51, when a dry etching process is employed and the etching gas is directed to the second trench 61, the etching gas in the second trench 61 first contacts the initial second gate dielectric layer 22, the semiconductor layer 102 and the first gate dielectric layer 111 on the sidewall of the isolation layer 21. By controlling the etching time, the initial second gate dielectric layer 22, the semiconductor layer 102 and the first gate dielectric layer 111 on the sidewall of the isolation layer 21 can be removed.

[0131] Reference is made to Figure 14 and Figure 15 After the first gate dielectric layer 111 is formed, the first word line 101 is formed. In some embodiments, the method of forming the first word line 101 includes forming the first word line 101 in the remaining first recess 51, and the first word line 101 fills the first recess 51. In this way, the side surface of the first word line 101 located in the first recess 51 is in contact with the semiconductor layer 102, and the semiconductor layer 102 can surround part of the side surface of the first word line 101.

[0132] The first word line 101 not only fills the first recess 51, but also fills the second trench 61. In this way, the first word line 101 formed extends along the first direction X, and the first word line 101 is opposite to each semiconductor layer 102 stacked along the first direction X.

[0133] In some embodiments, a deposition process, such as an atomic layer deposition process, can be employed to form the first word line 101.

[0134] In some embodiments, the method of forming the second word line 103 includes:

[0135] Reference is made to Figure 16 The self-supporting layer 106 is etched from the second side 2 to the first side 1 to form a second recess 52 extending from the second side 2 to the first side 1, and the second recess 52 exposes the surface of the initial second gate dielectric layer 22.

[0136] In some embodiments, the method of forming the second recess 52 can include:

[0137] Reference is made to Figure 15 A third trench 62 is formed in the isolation structure 107, the third trench 62 penetrates through the isolation structure 107, and the bottom of the third trench 62 exposes the surface of the substrate 100. The second trench 61 and the third trench 62 can be located on opposite sides of the support layer 106 along the second direction Y, respectively, so that the second trench 61 and the third trench 62 respectively expose the first side 1 and the second side 2 of the support layer 106.

[0138] The third trench 62 exposes the support layers 106 and the sacrificial layers in an alternating stack. The third trench 62 exposes only a portion of the side surface of each support layer 106 and each sacrificial layer. Etching the support layers 106 exposed by the third trench 62 forms the second recesses 52 at the locations.

[0139] In some embodiments, the method of forming the third trench 62 can include a patterning process on the top surface of the isolation structures 107, such as a SADP process or a SAQP process, to define the locations of the third trench 62.

[0140] The patterned isolation structures 107 are then etched until the surface of the substrate 100 is exposed, forming the third trench 62.

[0141] Reference is made to Figure 16 After the third trench 62 is formed, the support layers 106 exposed by the third trench 62 are etched along the third trench 62 to form the second recesses 52 by etching a portion of the width of the support layers 106.

[0142] Reference is made to Figure 13 And Figure 16 In some embodiments, the opening size d1 of the first recesses 51 is larger than the opening size d2 of the second recesses 52 along the third direction W.

[0143] It can be understood that the first recesses 51 need to have a larger size because the first recesses 51 need to be filled with the first gate dielectric layer 111, the second gate dielectric layer 112, the semiconductor layer 102, and the first word line 101, while the second recesses 52 only need to be filled with the second word line 103.

[0144] In some embodiments, a wet etching process can be used to etch the support layers 106 to form the second recesses 52. The first recesses 51 can be formed to have a larger opening size by controlling the etching time of the first recesses 51 to be longer than the etching time of the second recesses 52.

[0145] Reference is made to Figure 17 And Figure 18 After the second recesses 52 are formed, the second word lines 103 are formed to fill the second recesses 52.

[0146] The second word lines 103 not only fill the second recesses 52, but also fill the third trench 62, such that the second word lines 103 extend along the first direction X and are opposite to each of the semiconductor layers 102 stacked along the first direction X.

[0147] In some embodiments, a deposition process, such as an atomic layer deposition process, can be used to form the second word lines 103.

[0148] The above step is performed after the step of forming the first word line 101.

[0149] Reference is made to Figures 19-23 In some embodiments, the first recess 51 can also be formed after the step of forming the second word line 103, and the first recess 51 exposes the side surface of the second word line 103 facing the first recess 51. That is, the step of forming the second recess 52 can be performed first, and the second word line 103 is formed in the second recess 52. Then, the first recess 51 is formed, and the first recess 51 exposes the surface of the second word line 103. In this way, the second gate dielectric layer 112 formed later can be in contact with the second word line 103.

[0150] Reference is made to Figure 19 The third trench 62 is formed in the isolation structure 107, the third trench 62 penetrates the isolation structure 107, and the bottom of the third trench 62 exposes the surface of the substrate 100.

[0151] Reference is made to Figure 20 After the third trench 62 is formed, the support layer 106 exposed by the third trench 62 is etched along the third trench 62, and a portion of the width of the support layer 106 is etched to form the second recess 52.

[0152] Reference is made to Figure 21 After the second recess 52 is formed, the second word line 103 is formed in the second recess 52.

[0153] Reference is made to Figure 22 After the second word line 103 is formed, the second trench 61 is formed in the isolation structure 107, the second trench 61 penetrates the isolation structure 107, and the bottom of the second trench 61 exposes the surface of the substrate 100. The sidewall of the second trench 61 exposes the support layer 106 and the sacrificial layer in the alternating stack.

[0154] Reference is made to Figure 23 After the second trench 61 is formed, the support layer 106 exposed by the second trench 61 is etched along the second trench 61, and a portion of the width of the support layer 106 is etched to form the first recess 51, and the first recess 51 exposes the surface of the second word line 103.

[0155] Then, the initial second gate dielectric layer 22, the semiconductor layer 102, and the first gate dielectric layer 111 are sequentially formed in the first recess.

[0156] Reference is made to Figures 24-26 After the first word line 101 and the second word line 103 are formed, the bit line 104 is formed on the side of the semiconductor layer 102 away from the first word line 101 and extends along the second direction Y.

[0157] The bit line 104 can be located on the third side 3 of the support layer 106, in contact with the semiconductor layer 102 exposed by the third side 3 of the support layer 106.

[0158] It can be understood that, since the initial second gate dielectric layer 22 covers the entire surface of the semiconductor layer 102, in order to form electrical connection between the subsequently formed bit line 104 and capacitor 105 and the semiconductor layer 102, part of the surface of the semiconductor layer 102 needs to be exposed to form the source / drain region 11.

[0159] Therefore, referring to Figure 24 and Figure 25 , part of the support layer 106 and part of the initial second gate dielectric layer 22 are etched from the third side 3 of the support layer 106 until part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed.

[0160] Specifically, in some embodiments, the initial support layer 20 in the sub-stack structure 40 is etched to form a first opening 71 between adjacent isolation layers 21 in the sub-stack structure 40, the first opening 71 exposing the third side 3 of the support layer 106. Then, the exposed third side 3 of the support layer 106 can be etched until the initial second gate dielectric layer 22 is exposed, and the initial second gate dielectric layer 22 can be etched until part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed.

[0161] In some embodiments, a wet etching process can be used to etch the exposed third side 3 and the initial second gate dielectric layer 22.

[0162] After part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, a doping process can be performed on the exposed semiconductor layer 102 to form the source / drain region.

[0163] Referring to Figures 26-27 , after the source / drain region is formed, part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, the bit line 104 is formed to fill the first opening 71, so that the bit line 104 can be in contact with the surface of the semiconductor layer 102. In some embodiments, a deposition process can be used to form the bit line 104.

[0164] Referring to Figures 28-30 , after the bit line 104 is formed, the capacitor 105 is formed on the side of the semiconductor layer 102 facing away from the first word line 101, wherein the bit line 104 and the capacitor 105 are respectively located on opposite sides of the first word line 101 in the third direction W and are respectively in electrical contact with the source / drain region 11, and the second direction Y intersects the third direction W.

[0165] In some embodiments, the isolation structure 107 is not only located between the adjacent support layers 106, covering the first side 1 and the second side 2 of the support layer 106, but also covering the third side 3 of the support layer 106 away from the bit line 104. Based on this, it is necessary to first etch the isolation structure 107 covering the third side 3 of the support layer 106 away from the bit line 104, for example, a dry etching process can be used to etch the isolation structure 107 covering the third side 3 of the support layer 106 away from the bit line 104 until the third side 3 of the support layer 106 away from the bit line 104 is exposed.

[0166] After that, referring to Figure 28 , a wet etching process is used to etch the third side 3 of the support layer 106 away from the bit line 104 until the initial second gate dielectric layer 22 is exposed, forming a second opening 72.

[0167] Referring to Figure 28 and Figure 29 , the etching of the initial second gate dielectric layer 22 continues along the second opening 72 until the part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, and the remaining part of the initial second gate dielectric layer 22 serves as the second gate dielectric layer 112. After the part of the surface of the semiconductor layer 102 facing away from the first word line 101 is exposed, a doping process can be performed on the exposed semiconductor layer 102 to form a source-drain region. In this way, two source-drain regions can be formed on the semiconductor layer 102 exposed by the second gate dielectric layer 112, and the remaining part of the semiconductor layer 102 covered by the second gate dielectric layer 112 forms a channel region.

[0168] Referring to Figure 30 , a capacitor 105 is formed to fill the second opening 72, and the capacitor 105 is in electrical contact with the other source-drain region 11 of the semiconductor layer 102.

[0169] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and detail without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a first word line extending along a first direction; a semiconductor layer surrounding a part of a side surface of the first word line, the semiconductor layer comprising a channel region and source-drain regions located on two sides of the channel region, the channel region and the source-drain regions being arranged in a circumferential direction around the side surface of the first word line; a second word line extending along the first direction, the second word line being located on a side of the semiconductor layer opposite to the first word line; a bit line located on the side of the semiconductor layer opposite to the first word line and extending along a second direction; a capacitor located on the side of the semiconductor layer opposite to the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction, and are respectively in electrical contact with the source-drain regions, the second direction intersecting the third direction. The semiconductor structure further comprises a support layer extending along the third direction, the support layer having a first side and a second side opposite to each other along the second direction, and two third sides opposite to each other along the third direction, the semiconductor layer and the first word line being embedded in the first side, and the second word line being embedded in the second side, wherein the third sides of the support layer expose the source-drain regions of the semiconductor layer. A maximum width dimension of the first word line in the third direction is greater than a maximum width dimension of the second word line in the third direction.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a first gate dielectric layer located between the semiconductor layer and the first word line; a second gate dielectric layer located between the second word line and the semiconductor layer, the second gate dielectric layer covering the channel region and exposing the source-drain regions.

3. The semiconductor structure of claim 2, wherein, A material of the semiconductor layer comprises IGZO.

4. The semiconductor structure of claim 2, wherein, A side surface of the first word line opposite to the source-drain regions is a curved surface, the first gate dielectric layer covers the side surface of the first word line in a conformal manner, and the source-drain regions of the semiconductor layer cover the side surface of the first gate dielectric layer in a conformal manner.

5. A three-dimensional memory, comprising: The semiconductor structure comprises: a plurality of semiconductor structures as claimed in any one of claims 1-4, a plurality of the semiconductor structures arranged along the second direction share one bit line, and a plurality of the semiconductor structures arranged along the first direction share the first word line and the second word line.

6. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises: forming a first word line extending along a first direction; forming a semiconductor layer surrounding a part of a side surface of the first word line, the semiconductor layer comprising a channel region and source-drain regions located on two sides of the channel region, the channel region and the source-drain regions being arranged in a circumferential direction around the side surface of the first word line; forming a second word line extending along the first direction, the second word line being located on a side of the semiconductor layer opposite to the first word line; forming a bit line located on the side of the semiconductor layer opposite to the first word line and extending along a second direction; forming a capacitor located on the side of the semiconductor layer opposite to the first word line, wherein the bit line and the capacitor are respectively located on opposite sides of the first word line in a third direction, and are respectively in electrical contact with the source-drain regions, the second direction intersecting the third direction.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: Before the step of forming the first word line, further comprising: forming a first gate dielectric layer covering part of the side surface of the first word line, the semiconductor layer covering the surface of the first gate dielectric layer; and forming a second gate dielectric layer, the second gate dielectric layer being located at the side of the semiconductor layer away from the first gate dielectric layer, covering the channel region.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The method of forming the semiconductor layer, the first gate dielectric layer and the second gate dielectric layer comprises: forming a support layer, the support layer extending along a third direction, the support layer having a first side and a second side opposite to each other along a second direction, and two third sides opposite to each other along the third direction; etching part of the support layer from the first side of the support layer to form a first recess extending from the first side to the second side; forming an initial second gate dielectric layer conforming to the first recess; forming a semiconductor layer conforming to the initial second gate dielectric layer within the first recess; forming a first gate dielectric layer conforming to the surface of the semiconductor layer within the first recess; etching part of the support layer and part of the initial second gate dielectric layer from the third side of the support layer until part of the surface of the semiconductor layer facing away from the first word line is exposed, the remaining part of the initial second gate dielectric layer serving as the second gate dielectric layer.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The method of forming the first word line comprises: forming a first word line within the remaining first recess, the first word line filling the first recess.

10. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The method of forming the second word line comprises: etching part of the support layer from the second side of the support layer to form a second recess extending from the second side to the first side; forming the second word line filling the second recess.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: After the step of forming the second word line, the first recess is formed, the first recess exposing the side surface of the second word line facing the first recess.

12. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: In the third direction, the opening size of the first recess is greater than the opening size of the second recess.

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