IGBT cellular structure and manufacturing method

Abstract

The invention relates to the technical field of semiconductor devices, in particular to an IGBT cellular structure and a manufacturing method. The IGBT cellular structure comprises a drift layer, a grid electrode, a body region, a hole low-resistance channel, an emitter region, a heavily doped ohmic contact region, an emitter electrode, grid metal and a collector electrode. Wherein the drift layer is provided with a first groove filled with a grid electrode; a hole low-resistance channel is arranged in the body region and is not connected with the grid electrode, the depth of the hole low-resistance channel is equal to the junction depth of the body region, and a plurality of transversely-spaced emitter regions are arranged; the upper surface of the body region is provided with a recessed contact hole, and the bottom of the hole is provided with a heavily doped ohmic contact region which forms ohmic contact with the hole low-resistance channel. By optimizing the structural design, under the condition of ensuring that the on-state voltage drop is not increased, the short-circuit time is prolonged, the power consumption is reduced, meanwhile, the manufacturing process is simplified, and the production efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor power devices, and in particular, to an IGBT cell structure and a manufacturing method thereof. Background Art

[0002] Insulated gate bipolar transistors (IGBTs) have been widely used in power electronic systems and are core devices for power conversion; the short-circuit time of an insulated gate bipolar transistor (IGBT) refers to the time during which the IGBT can continuously conduct under short-circuit conditions without failure, and is also referred to as the "short-circuit withstand time".

[0003] The on-state voltage drop of an insulated gate bipolar transistor is positively correlated with the short-circuit time. When the short-circuit time increases, the on-state voltage drop will increase; when the short-circuit time increases significantly, the on-state voltage drop increases significantly, which is not conducive to the application of the circuit, and the coordination between the two is poor.

[0004] To solve the above problems, in the related art, the patent with publication number CN118943174A discloses a quickly turn-off IGBT device and a manufacturing method thereof. The device includes: an N-type substrate, a P-type CHP hole low-resistance channel is arranged on the front surface of the N-type substrate, and the front surface of the P-type CHP hole low-resistance channel is a front emitter metal region; at least one trench region penetrates the P-type CHP hole low-resistance channel; a hole extraction region is located on the other side of the trench region relative to the front emitter metal region; an SG region is arranged in the trench region, one end of the SG region is in ohmic contact with the front emitter metal region, the other end is in ohmic contact with the hole extraction region, and a thick oxide layer, a polysilicon gate, and a gate oxide layer are sequentially arranged on both sides of the SG region on the sidewall of the trench region. This solution can quickly cut off the current generated by the hole carriers injected from the back when the IGBT device is turned off, avoid the generation of tail current, and thus reduce the turn-off loss of the IGBT device.

[0005] In view of the above related art, when forming the hole circulation path, it is necessary to first form the hole extraction region and then form the SG region. The cell structure is complex, the manufacturing process steps are numerous, and the formed structure is not easy to control. Summary of the Invention

[0006] This application provides an IGBT cell structure and a manufacturing method thereof, which can increase the short-circuit time without increasing the on-state voltage drop, and can simplify the cell structure and the manufacturing process.

[0007] In a first aspect, an IGBT cell structure provided by this application adopts the following technical solution: An IGBT cell structure includes: A drift layer is provided with a first trench, a gate is arranged in the first trench, and a body region is connected to opposite sides of the gate. A hole low-resistance channel is provided in the body region. The hole low-resistance channel is not connected to the gate. The depth of the hole low-resistance channel is equal to the junction depth of the body region. An emitter region adjacent to the gate is also provided in the body region. A concave contact hole is formed on the upper surface of the body region. A heavily doped ohmic contact region is provided at the bottom of the concave contact hole. The heavily doped ohmic contact region forms an ohmic contact with the hole low-resistance channel. An emitter, a gate metal, and a collector. The emitter is disposed on the upper surfaces of the concave contact hole and the drift layer. The gate metal is separated from the emitter and connected to the gate. The collector is disposed on the lower surface of the drift layer.

[0008] By adopting the above technical solution, compared with the related technologies in the background art, the structure of the solution of the present application is more simplified, the process is simpler, the manufacturing difficulty is lower, and without increasing the on-state voltage drop, it can effectively reduce the base region voltage drop of the parasitic npn triode, increase the latching current density, and improve the short-circuit time capability.

[0009] Optionally, the width of the hole low-resistance channel is 1 / 3 - 2 / 3 of the width of the body region.

[0010] By adopting the above technical solution, the width of the hole low-resistance channel is accurately controlled within the range of 1 / 3 to 2 / 3 of the width of the body region, thereby significantly reducing the base region voltage drop of the parasitic NPN triode and further increasing the latching current density. This design not only optimizes the flow path of holes in the p-body region but also enhances the short-circuit tolerance of the IGBT transistor and improves the overall performance stability.

[0011] Optionally, the gate and the hole low-resistance channel extend laterally, and a plurality of emitter regions are arranged at intervals laterally.

[0012] By adopting the above technical solution, the gate and the hole low-resistance channel extend laterally, enabling holes to flow smoothly in the horizontal direction, reducing the base region voltage drop of the parasitic NPN triode, and thus improving the short-circuit time capability. At the same time, a plurality of emitter regions are arranged at intervals laterally and are respectively in contact with the first trench and the emitter on both sides. This design optimizes the current distribution and further enhances the reliability and performance stability of the device.

[0013] Optionally, the heavily doped ohmic contact region is disposed around the peripheral side of the hole low-resistance channel.

[0014] By adopting the above technical solution, it ensures that the flow of hole current in the cell is smoother, reduces the local thermal effect, and improves the overall performance and reliability of the device.

[0015] Optionally, the first trench includes a main trench and a dummy trench. The hole low-resistance channel is disposed between adjacent main trenches, and the dummy trench is disposed on a side of the main trench away from the hole low-resistance channel.

[0016] By adopting the above technical solution, the dummy trench gate structure can be used to reduce the saturation current density, thereby improving the short-circuit resistance of the device. Without changing the gate density, this design optimizes the device performance by using some gates only for maintaining the breakdown voltage.

[0017] Optionally, the drift layer and the emitter region are of a first conductivity type, the body region, the hole low-resistance channel, and the heavily doped ohmic contact region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

[0018] By adopting the above technical solution, a reasonable distribution of regions of different conductivity types in the IGBT cell structure can be achieved, thereby optimizing the carrier transport path and reducing the influence of parasitic effects. Specifically, the drift layer and the emitter region of the first conductivity type contribute to improving the breakdown voltage performance of the device, while the body region, the hole low-resistance channel, and the heavily doped ohmic contact region of the second conductivity type reduce the resistance of holes in the p-body region, thereby improving the overall performance of the device, especially showing better coordination in terms of the short-circuit time and the on-state voltage drop.

[0019] In a second aspect, a manufacturing method of an IGBT cell structure provided by the present application adopts the following technical solution: A manufacturing method of an IGBT cell structure includes the following steps: S10: Provide a drift layer, etch the drift layer to form a first trench, and fill polysilicon into the first trench to form a gate; S20: Form a body region in the drift layer by ion implantation and diffusion, and the body region is adjacent to opposite side edges of the first trench; S30: Etch the body region to form a filling trench, and form a heavily doped hole low-resistance channel in the filling trench. The depth of the hole low-resistance channel is equal to the junction depth of the body region, and the hole low-resistance channel is not connected to the gate; S40: Inject ions onto the upper surface of the body region to form an emitter region. The emitter region is adjacent to the first trench and is located on both sides of the hole low-resistance channel; S50: Etch the upper surface of the body region to form a concave contact hole, inject ions into the concave contact hole to form a heavily doped ohmic contact region. The heavily doped ohmic contact region forms an ohmic contact with the hole low-resistance channel, and the upper surfaces of the emitter region, the heavily doped ohmic contact region, and the hole low-resistance channel are exposed on the inner wall of the concave contact hole; S60. The deposited metal forms an emitter on the upper surface of the drift layer within the recessed contact hole. The deposited metal forms a gate metal that is separated from the emitter and connected to the gate. The deposited metal forms a collector on the lower surface of the drift layer.

[0020] By adopting the above technical solution, the manufacturing method of the IGBT cell structure can significantly improve the hole transport efficiency in the body region, thereby effectively reducing the base region voltage drop of the parasitic NPN triode. This not only increases the latch current density and enhances the short-circuit withstand ability, but also extends the short-circuit time while maintaining a low on-state voltage drop, optimizing the overall performance and reliability of the device.

[0021] Optionally, in step S30, the width of the hole low-resistance channel is 1 / 3 - 2 / 3 of the width of the body region.

[0022] Optionally, in step S40, the gate and the hole low-resistance channel extend laterally, and a plurality of emitter regions are arranged at intervals laterally.

[0023] Optionally, in step S10, the first trench includes a main trench and a virtual trench. The hole low-resistance channel is arranged between adjacent main trenches, and the virtual trench is arranged on the side of the main trench away from the hole low-resistance channel.

[0024] By adopting the above technical solution, the design of the main trench and the virtual trench can optimize the spatial layout of the IGBT cell structure and reduce the influence of parasitic effects. Specifically, the hole low-resistance channel is arranged between adjacent main trenches, which helps to form a more uniform electric field distribution, thereby improving the breakdown voltage performance of the device. At the same time, the presence of the virtual trench can effectively shield external interference, enhance the stability and reliability of the device, and further improve the short-circuit withstand ability and switching speed.

[0025] In summary, the present application includes at least one of the following beneficial technical effects: 1. Compared with the related technologies in the background art, the solution of the present application has a simpler structure, a simpler process, lower manufacturing difficulty, and can effectively reduce the base region voltage drop of the parasitic npn triode without increasing the on-state voltage drop, increase the latch current density, and improve the short-circuit time ability; 2. The gate and the hole low-resistance channel extend laterally, enabling the holes to flow smoothly in the horizontal direction, reducing the base region voltage drop of the parasitic NPN triode, and thus improving the short-circuit time ability. At the same time, a plurality of emitter regions are arranged at intervals laterally, and are respectively in contact with the first trench and the emitter on both sides. This design optimizes the current distribution and further enhances the reliability and performance stability of the device; 3. The design of the main trench and the virtual trench can optimize the spatial layout of the IGBT cell structure and reduce the influence of parasitic effects. Specifically, the hole low-resistance channel is arranged between adjacent main trenches, which helps to form a more uniform electric field distribution, thereby improving the breakdown voltage performance of the device. At the same time, the existence of the virtual trench can effectively shield external interference, enhance the stability and reliability of the device, and further improve the short-circuit withstand ability and switching speed. Description of the Drawings

[0026] Figure 1 is a schematic diagram of the overall structure of some preferred embodiments of the present application.

[0027] Figure 2 is a top view of some preferred embodiments of the present application mainly showing the structure around the concave contact hole.

[0028] Figure 3 is a schematic diagram of providing a drift layer and opening a first trench in the process of fabricating the IGBT cell structure of some preferred embodiments of the present application.

[0029] Figure 4 is a schematic diagram of forming a gate and a body region in the process of fabricating the IGBT cell structure of some preferred embodiments of the present application.

[0030] Figure 5 is a schematic diagram of forming a hole low-resistance channel in the process of fabricating the IGBT cell structure of some preferred embodiments of the present application.

[0031] Figure 6 is a schematic diagram of forming an emitter region in the process of fabricating the IGBT cell structure of some preferred embodiments of the present application.

[0032] Figure 7 is a schematic diagram of opening a concave contact hole in the body region and forming a heavily doped ohmic contact region in the process of fabricating the IGBT cell structure of some preferred embodiments of the present application.

[0033] Description of the Reference Numerals: 10. Drift layer; 11. First trench; 12. Main trench; 13. Virtual trench; 14. Hard mask oxide layer; 20. Gate; 21. Gate oxide layer; 30. Body region; 31. Emitter region; 32. Concave contact hole; 33. Heavily doped ohmic contact region; 34. Filled trench; 40. Hole low-resistance channel; 50. Isolation layer; 61. Emitter; 62. Gate metal; 63. Collector; 64. FS buffer layer. Detailed Embodiments

[0034] Next, the accompanying drawings in the embodiments of the present invention will be combined Figures 1-7, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only a part of the embodiments for understanding the inventive concept of the present invention and cannot represent all the embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art under the premise of understanding the inventive concept of the present invention fall within the scope of protection of the present invention.

[0035] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present invention, the directional indications are only used to explain the relative positional relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly. For a better understanding of the technical solutions of the present invention, the manufacturing method of the semiconductor device of the present invention will be further described and explained in detail below, but it does not constitute the scope of protection defined by the present invention.

[0036] What is shown in the drawings is only the part common to multiple embodiments. The parts with differences or distinctions are described in words or presented in a way of comparing with the drawings. Based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the following described individual technical features or any combination of them can be characterized in the same embodiment, or whether the technical features with mutually exclusive technical essences can only be characterized in different variant embodiments respectively.

[0037] The inventors of the present application have found that insulated gate bipolar transistors have been widely used in power electronic systems and are the core devices for power conversion. However, in the existing IGBTs, the on-state voltage drop is positively correlated with the short-circuit time. When the short-circuit time needs to be increased, the on-state voltage drop will increase, which is not conducive to the application of the circuit. The improvement of the short-circuit time is related to the current path of holes in the p-body region and is more related to the base voltage drop of the parasitic NPN transistor. When the hole voltage drop formed by the hole current in the p-body region and the base length of the parasitic NPN transistor is higher than 0.6V, latch-up will occur. Therefore, the present application mainly adopts an IGBT cell structure to solve the above technical problems.

[0038] An IGBT cell structure provided by an embodiment of the present application, referring to Figure 1 and Figure 2, including a drift layer 10, a hole low-resistance channel 40, an emitter 61, a gate metal 62, and a collector 63. Among them, the drift layer 10 is provided with a first trench 11, and a gate electrode 20 is arranged in the first trench 11. Body regions 30 are connected to opposite sides of the gate electrode 20; the hole low-resistance channel 40 is arranged in the body region 30 and is not connected to the gate electrode 20, and the depth of the hole low-resistance channel 40 is equal to the junction depth of the body region 30; an emitter region 31 adjacent to the gate electrode 20 is further arranged in the body region 30, a concave contact hole 32 is formed on the upper surface of the body region 30, and a heavily doped ohmic contact region 33 is arranged at the bottom of the concave contact hole 32. The heavily doped ohmic contact region 33 forms an ohmic contact with the hole low-resistance channel 40; the emitter 61 is arranged on the upper surfaces of the concave contact hole 32 and the drift layer 10, the gate metal 62 is separated from the emitter 61 and connected to the gate electrode 20, and the collector 63 is arranged on the lower surface of the drift layer 10.

[0039] Among them, the drift layer 10 and the emitter region 31 are of a first conduction type, and the body region 30, the hole low-resistance channel 40, and the heavily doped ohmic contact region 33 are of a second conduction type, and the first conduction type is opposite to the second conduction type. In this embodiment, the first conduction type is N-type and the second conduction type is P-type for illustration.

[0040] Specifically, the drift layer 10 is made of an N-type semiconductor material, and the material of the drift layer 10 can be Si material, SiC material, etc., which is used to carry current transmission under high voltage. A gate oxide layer 21 is formed on the side walls and the bottom of the first trench 11, and the gate electrode 20 is filled with polysilicon material, which plays a role in controlling current.

[0041] Preferably, the first trench 11 includes a main trench 12 and a virtual trench 13. The hole low-resistance channel 40 is arranged between adjacent main trenches 12, and the virtual trench 13 is arranged on the side of the main trench 12 away from the hole low-resistance channel 40. The gate electrode 20 in the main trench 12 is powered on, and the gate electrode 20 in the virtual trench 13 is not powered on to optimize the spatial layout of the IGBT cell structure and reduce the influence of parasitic effects. Specifically, the hole low-resistance channel 40 is arranged between adjacent main trenches 12, which helps to form a more uniform electric field distribution, thereby improving the breakdown voltage performance of the device. At the same time, the existence of the virtual trench 13 can effectively shield external interference, enhance the stability and reliability of the device, and further improve the short-circuit withstand ability and switching speed.

[0042] Among them, the body region 30 is made of P-type semiconductor material, the body region 30 is formed by ion implantation and diffusion, the junction depth of the body region 30 is less than the depth of the gate electrode 20, the hole low-resistance channel 40 is arranged in the middle of the body region 30, and the depth of the hole low-resistance channel 40 is equal to the junction depth of the body region 30, so that holes in the drift layer 10 can directly flow to the emitter 61 through the hole low-resistance channel 40, the hole transmission path is shorter, and it is more conducive to the rapid extraction of holes.

[0043] Optionally, the hole low-resistance channel 40 can be formed by wet etching technology to form a filling trench 34 with the same depth as the junction depth of the body region 30 in the body region 30. Then, a heavily doped P-type epitaxial layer is filled in the filling trench 34 by epitaxial growth. Next, the P-type epitaxial layer is etched back, and only the P-type epitaxial layer in the filling trench 34 is retained to form the hole low-resistance channel 40. For example, an appropriate amount of boron element can be added during the epitaxial growth process by chemical vapor deposition (CVD) method, so that the finally formed P-type epitaxial layer has a high hole concentration. In this way, holes can flow smoothly in the low-resistance channel, reducing the influence of the parasitic NPN transistor.

[0044] In a preferred embodiment, the width of the hole low-resistance channel 40 is set to be 1 / 3 to 2 / 3 of the width of the body region 30 to balance the relationship between the on-state voltage drop and the short-circuit time. Specifically, through experimental tests on hole low-resistance channels 40 with different widths, it is found that when the proportion of the width of the hole low-resistance channel 40 in the total width of the body region 30 is between 1 / 3 and 2 / 3, the best comprehensive performance can be obtained. If the width is too narrow, although it is beneficial to reduce the on-state voltage drop, it may increase the base voltage drop of the parasitic NPN transistor and affect the short-circuit time; conversely, if the width is too wide, it will increase the area of the body region 30 and increase the on-state voltage drop. Therefore, choosing an appropriate proportion range can ensure both a low on-state voltage drop and effectively extend the short-circuit time.

[0045] The emitter region 31 is a small region made of N+-type semiconductor material and is formed by ion implantation and high-temperature annealing processes. In a preferred embodiment, the gate 20 and the hole low-resistance channel 40 extend laterally, and a plurality of emitter regions 31 are arranged at intervals laterally. Both sides of each emitter region 31 are in contact with the gate oxide layer 21 and the emitter 61 respectively, so that holes can flow smoothly in the horizontal direction, reducing the base voltage drop of the parasitic NPN transistor, thereby improving the short-circuit time ability. At the same time, a plurality of emitter regions 31 are arranged at intervals laterally, and both sides are in contact with the first trench 11 and the emitter 61 respectively. This design optimizes the current distribution and further enhances the reliability and performance stability of the device. In other embodiments, the emitter region 31 can also be arranged to extend laterally.

[0046] The heavily doped ohmic contact region 33 is made of P+-type semiconductor material. An isolation layer 50 is deposited on the upper surface of the drift layer 10, and a concave contact hole 32 is formed by photolithography, exposure, and etching. P+-type dopants are implanted into the concave contact hole 32 to form the heavily doped ohmic contact region 33. Commonly used dopants include aluminum and gallium. In a preferred embodiment, the heavily doped ohmic contact region 33 is arranged to surround the peripheral side of the hole low-resistance channel 40, and its purpose is to enhance the reliability of the ohmic contact.

[0047] The emitter 61 covers the inside of the recessed contact hole 32 and the upper surface of the isolation layer 50, and is mainly made of a metal material such as aluminum or copper, and is used to collect current. The gate metal 62 is separated from the emitter 61 and connected to the gate 20, and is used to transmit a control signal. The gate 20 can be connected to the gate metal 62 through the recessed contact hole 32 provided at another position to improve the current transmission stability. An FS buffer layer 64 is further provided on the lower surface of the drift layer 10, and the collector 63 is provided on the lower surface of the FS buffer layer 64 for receiving current output.

[0048] Optionally, after the back surface of the drift layer 10 is ground to the required thickness, the FS buffer layer 64 is formed by high-energy ion implantation, and the impurities are activated by laser annealing. Next, P+ collector 63 ions are implanted on the back surface, and the impurities are activated by laser annealing, and finally metallization is formed on the back surface. In this way, efficient and reliable packaging can be achieved, and the overall performance of the device can be improved.

[0049] The implementation principle of this embodiment is as follows: by adding a hole low-resistance channel 40 in the body region 30, the base region voltage drop of the parasitic NPN transistor is reduced, the latching current density is increased, and the short-circuit time capability of the IGBT is improved. This design not only maintains a low on-state voltage drop, but also enhances the reliability and stability of the device to a certain extent, and is suitable for high-voltage and high-current application scenarios.

[0050] The embodiment of the present application also discloses a manufacturing method of an IGBT cell structure, which includes the following steps: S10. Refer to Figure 3 and Figure 4 , provide a drift layer 10, etch the drift layer 10 to form a first trench 11, and fill polysilicon into the first trench 11 to form a gate 20.

[0051] Optionally, the drift layer 10 is an N-drift layer 10. First, a hard mask oxide layer 14 with a certain thickness is deposited on the upper surface of the drift layer 10, and a trench window of the hard mask oxide layer 14 is opened by photolithography and etching; the hard mask oxide layer 14 is used as a mask to etch a first trench 11 with a certain depth and width. Preferably, the first trench 11 extends horizontally; after the first trench 11 is formed, a sacrificial oxide layer grows on the sidewall of the first trench 11, and then the sacrificial oxide layer is removed to improve the roughness of the sidewall of the first trench 11; a gate oxide layer 21 is formed on the sidewall and bottom of the first trench 11, and in-situ doped polysilicon is filled into the first trench 11; the filled in-situ polysilicon is etched back, and the in-situ polysilicon in the first trench 11 is retained to form a gate 20.

[0052] S20. Refer to Figure 4 , form a body region 30 in the drift layer 10 by ion implantation and diffusion, and the body region 30 abuts against the opposite sides of the first trench 11.

[0053] Optionally, the body region 30 is made of P-type semiconductor material. The relative side of the body region 30 adjacent to the gate oxide layer 21 has a depth less than that of the gate 20.

[0054] S30. Refer to Figure 5 , etch the body region 30 to form a filling trench 34, and form a heavily doped hole low-resistance channel 40 in the filling trench 34. The depth of the hole low-resistance channel 40 is equal to the junction depth of the body region 30, and the hole low-resistance channel 40 is not in contact with the gate 20.

[0055] Optionally, a hard mask oxide layer 14 can be formed on the body region 30 by wet etching technology, and a hard mask window is opened. Then, the body region 30 is etched to form a filling trench 34. Preferably, the filling trench 34 extends horizontally. After the sacrifice oxide layer is grown in the filling trench 34, it is removed, and then the filling trench 34 is filled with a heavily doped P-type epitaxial layer by epitaxial growth. Then, the P-type epitaxial layer is etched back, and only the P-type epitaxial layer in the filling trench 34 is retained to form the hole low-resistance channel 40, so that the holes in the drift layer 10 can directly flow to the emitter 61 through the hole low-resistance channel 40. The hole transmission path is shorter, which is more conducive to the rapid extraction of holes.

[0056] In a preferred embodiment, the width of the hole low-resistance channel 40 is set to 1 / 3 to 2 / 3 of the width of the body region 30 to balance the relationship between the on-state voltage drop and the short-circuit time.

[0057] In a preferred embodiment, the first trench 11 includes a main trench 12 and a virtual trench 13. The hole low-resistance channel 40 is disposed between adjacent main trenches 12, and the virtual trench 13 is disposed on the side of the main trench 12 away from the hole low-resistance channel 40. The gate 20 in the main trench 12 is electrically connected, and the gate 20 in the virtual trench 13 is not electrically connected to optimize the spatial layout of the IGBT cell structure and reduce the influence of parasitic effects.

[0058] S40. Refer to Figure 6 , ions are implanted on the upper surface of the body region 30 to form an emitter region 31. The emitter region 31 is adjacent to the first trench 11 and the emitter region 31 is located on both sides of the hole low-resistance channel 40.

[0059] Optionally, an N+ emitter region 31 is formed by photolithography, masking implantation, and high-temperature annealing. At this time, one side of the N+ emitter region 31 should extend as much as possible towards the center line of the hole low-resistance channel 40 so that it can be exposed after subsequent etching, and the other side of the N+ emitter region 31 is in contact with the gate oxide layer 21.

[0060] In a preferred embodiment, a plurality of emitter regions 31 are arranged at intervals in the horizontal direction to optimize the current distribution.

[0061] S50. Refer toFigure 7 , an upper surface of the body region 30 is etched to form a concave contact hole 32, ions are injected into the concave contact hole 32 to form a heavily doped ohmic contact region 33, the heavily doped ohmic contact region 33 forms an ohmic contact with the hole low-resistance channel 40, and upper surfaces of the emitter region 31, the heavily doped ohmic contact region 33, and the hole low-resistance channel 40 are exposed on an inner wall of the concave contact hole 32.

[0062] Specifically, an isolation layer 50 is deposited on an upper surface of the drift layer 10, and the concave contact hole 32 is formed by photolithography exposure development and etching. P+ dopants are injected into the concave contact hole 32 to form the heavily doped ohmic contact region 33, and the injected P+ dopants are annealed to activate the impurities. Commonly used dopants include aluminum and gallium. In a preferred embodiment, the heavily doped ohmic contact region 33 is disposed around a peripheral side of the hole low-resistance channel 40, and the purpose is to enhance the reliability of the ohmic contact.

[0063] S60. Refer to Figure 1 and Figure 2 , metal is deposited in the concave contact hole 32 to form an emitter 61 on an upper surface of the drift layer 10, metal is deposited to form a gate metal 62, the gate metal 62 is separated from the emitter 61 and connected to the gate 20, and metal is deposited on a lower surface of the drift layer 10 to form a collector 63.

[0064] Specifically, barrier metals such as Ti / TiN are deposited, an AL layer lead metal is deposited, and the emitter 61 metal and the gate metal 62 are formed by photolithography etching. Preferably, the gate 20 is connected to the gate metal 62 through the concave contact hole 32; the emitter 61 is connected to the hole low-resistance channel 40 through the concave contact hole 32.

[0065] During the packaging process, first, a back surface of the drift layer 10 is ground to a required thickness, then an FS buffer layer 64 is formed by high-energy ion implantation, and the impurities are activated by laser annealing; next, P+ collector 63 ions are implanted into the back surface, and the impurities are activated by laser annealing, and finally, metallization is formed on the back surface. In this way, efficient and reliable packaging can be achieved, and the overall performance of the device can be improved.

[0066] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.

Claims

1. An IGBT cell structure, characterized in that: include: A drift layer (10) is provided with a first trench (11), a gate (20) is provided in the first trench (11), and a body region (30) is connected to opposite sides of the gate (20); A hole low-resistance channel (40) is provided in the body region (30), the hole low-resistance channel (40) is not connected to the gate (20), the depth of the hole low-resistance channel (40) is equal to the junction depth of the body region (30), an emitter region (31) adjacent to the gate (20) is also provided in the body region (30), a recessed contact hole (32) is provided on the upper surface of the body region (30), a heavily doped ohmic contact region (33) is provided at the bottom of the recessed contact hole (32), and the heavily doped ohmic contact region (33) forms an ohmic contact with the hole low-resistance channel (40); An emitter (61), a gate metal (62) and a collector (63), wherein the emitter (61) is arranged on the recessed contact hole (32) and the upper surface of the drift layer (10), the gate metal (62) is separated from the emitter (61) and connected to the gate (20), and the collector (63) is arranged on the lower surface of the drift layer (10).

2. The IGBT cell structure according to claim 1, characterized in that: The width of the hole low-resistance channel (40) is 1 / 3-2 / 3 of the width of the body region (30).

3. The IGBT cell structure according to claim 1, characterized in that: The gate (20) and the hole low-resistance channel (40) extend in a transverse direction, a plurality of emitter regions (31) are arranged at intervals in a transverse direction, and two sides of the emitter region (31) are respectively in contact with the first groove (11) and the emitter (61).

4. The IGBT cell structure according to claim 3, characterized in that: The heavily doped ohmic contact region (33) is arranged around the peripheral side of the hole low-resistance channel (40).

5. The IGBT cell structure according to claim 1, characterized in that: The first groove (11) comprises a main groove (12) and a dummy groove (13), the hole low-resistance channel (40) is arranged between adjacent main grooves (12), and the dummy groove (13) is arranged on a side of the main groove (12) away from the hole low-resistance channel (40).

6. The IGBT cell structure according to claim 1, characterized in that: The drift layer (10) and the emission region (31) are of a first conductivity type, the body region (30), the hole low-resistance channel (40) and the heavily doped ohmic contact region (33) are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

7. A method for manufacturing an IGBT cell structure, characterized in that: The following steps are involved: S10, providing a drift layer (10), etching the drift layer (10) to form a first trench (11), and filling the first trench (11) with polysilicon to form a gate (20); S20, forming a body region (30) in the drift layer (10) by ion implantation and diffusion, wherein the body region (30) is connected to opposite sides of the first trench (11); S30, etching the body region (30) to form a filling groove (34), forming a heavily doped hole low-resistance channel (40) in the filling groove (34), the depth of the hole low-resistance channel (40) being equal to the junction depth of the body region (30), and the hole low-resistance channel (40) not being in contact with the gate (20); S40, injecting ions into the upper surface of the body region (30) to form an emission region (31), wherein the emission region (31) is adjacent to the first groove (11) and the emission region (31) is located on both sides of the hole low-resistance channel (40); S50, etching the upper surface of the body region (30) to form a recessed contact hole (32), injecting ions into the recessed contact hole (32) to form a heavily doped ohmic contact region (33), wherein the heavily doped ohmic contact region (33) forms an ohmic contact with the hole low-resistance channel (40), and the upper surfaces of the emitter region (31), the heavily doped ohmic contact region (33) and the hole low-resistance channel (40) are exposed on the inner wall of the recessed contact hole (32); S60, depositing metal in the recessed contact hole (32) and on the upper surface of the drift layer (10) to form an emitter (61), depositing metal to form a gate metal (62), the gate metal (62) being separated from the emitter (61) and connected to the gate (20), and depositing metal to form a collector (63) on the lower surface of the drift layer (10).

8. The method for manufacturing an IGBT cell structure according to claim 7, characterized in that: In the step S30, the width of the hole low-resistance channel (40) is 1 / 3-2 / 3 of the width of the body region (30).

9. The method for manufacturing an IGBT cell structure according to claim 7, characterized in that: In the step S40, the gate (20) and the hole low-resistance channel (40) extend in a lateral direction, and a plurality of the emission regions (31) are arranged at intervals in a lateral direction.

10. The method for manufacturing an IGBT cell structure according to claim 7, characterized in that: In the step S10, the first groove (11) comprises a main groove (12) and a dummy groove (13), the hole low-resistance channel (40) is arranged between adjacent main grooves (12), and the dummy groove (13) is arranged on a side of the main groove (12) away from the hole low-resistance channel (40).

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