Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the channel structure is located on the substrate, the channel structure comprises a channel layer and a barrier layer which are sequentially formed on the substrate, and the channel structure comprises a gate region, and a source region and a drain region which are located on the two sides of the gate region; the first groove is located in the source electrode region and the drain electrode region, and the first groove at least penetrates through the barrier layer; the insertion layer is arranged in the barrier layer; the side wall of the insertion layer located at the ends of the source electrode region and the drain electrode region shrinks inwards by a preset distance relative to the side wall of the barrier layer to form a sunken groove, and the sunken groove is communicated with the first groove; and the heavily doped material layer is used for filling the first groove and the sunken groove. According to the technical scheme provided by the invention, the contact resistance between the heavily doped material layer and the side wall of the channel structure is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the manufacturing process of GaN-based HEMT devices, the source-drain ohmic contact process is one of the key technologies, directly affecting the frequency and power performance of the devices. In recent years, secondary epitaxial growth of N-type heavily doped GaN in the ohmic contact region to reduce the ohmic contact resistivity and improve the surface morphology has become a new process internationally.

[0003] Currently, most of the secondary epitaxial growth of N-type heavily doped GaN is achieved by molecular beam epitaxy (MBE), but some people also use metal-organic chemical vapor deposition (MOCVD). The ohmic contact resistance achieved by this method mainly includes the contact resistance between the metal and N-type heavily doped GaN, the bulk resistance of N-type heavily doped GaN, and the contact resistance between N-type heavily doped GaN and the sidewall of the channel structure. Among them, the quality of the contact between N-type heavily doped GaN and the sidewall of the channel structure directly affects the contact resistance between N-type heavily doped GaN and the sidewall of the channel structure, and this contact resistance has the greatest impact on the overall ohmic contact. Figure 1 is a structural cross-sectional view after secondary epitaxial growth of heavily doped GaN material in the prior art. Figure 1 As shown, a buffer layer 2, a GaN channel layer 3, and a barrier layer 4 are stacked on a substrate 1; the GaN channel layer 3 and the barrier layer 4 form a channel structure. Using a patterned SiO2 layer 5 as a mask, the exposed barrier layer 4 and GaN channel layer 3 are etched in sequence, and the etching depth reaches below the GaN heterojunction interface. In the actual operation process, due to the problem of etching accuracy, it is easy to over-etch the channel structure. The side position of the channel structure is retracted by a certain distance relative to the mask layer SiO2 layer 5 above it. When secondary epitaxial growth of heavily doped GaN material 6 is carried out, due to the existence of over-etching, the side of the heavily doped GaN material 6 is in poor contact with the channel structure, resulting in a significant increase in the contact resistance between the N-type heavily doped GaN material 6 and the sidewall of the channel structure. Therefore, effectively reducing the contact resistance between the N-type heavily doped GaN material 6 and the sidewall of the channel structure is of great significance for reducing the overall ohmic contact. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same to reduce the contact resistance between the heavily doped material layer and the sidewall of the channel structure.

[0005] According to one aspect of the present invention, a semiconductor structure is provided, including:

[0006] A substrate;

[0007] A channel structure located on the substrate, the channel structure including a channel layer and a barrier layer formed on the substrate in sequence, the channel structure including a gate region, and a source region and a drain region located on both sides of the gate region;

[0008] A first groove located in the source region and the drain region, the first groove penetrating at least the barrier layer;

[0009] An insertion layer disposed in the barrier layer; the side walls of the insertion layer at the ends of the source region and the drain region are recessed a preset distance relative to the side walls of the barrier layer to form an indented trench, and the indented trench communicates with the first groove;

[0010] A heavily doped material layer, the heavily doped material layer filling the first groove and the indented trench.

[0011] Optionally, the semiconductor structure further includes:

[0012] A gate located in the gate region, the gate being located on the side of the barrier layer away from the substrate;

[0013] A source and a drain respectively located in the source region and the drain region, the source and the drain being formed on the side of the heavily doped material layer away from the substrate.

[0014] Optionally, the heavily doped material layer is a single-layer material layer or a stacked material layer, and the stacked material layer includes a superlattice structure.

[0015] Optionally, the materials of the barrier layer and the insertion layer are group III nitride materials, the material of the barrier layer is AlGaN, and the material of the insertion layer is AlN or GaN.

[0016] Optionally, the side wall of the heavily doped material layer close to the insertion layer includes at least one protrusion; the indented trench includes at least one finger-shaped trench, and the at least one finger-shaped trench is arranged at intervals along the direction of the channel width; the protrusions are embedded in the finger-shaped trenches one by one.

[0017] Optionally, the vertical projection of the side wall of the heavily doped material layer close to the insertion layer on the substrate is serrated or comb-shaped.

[0018] Optionally, the distance between the at least one finger-shaped trench and the side of the indented trench close to the first groove is ≥0.

[0019] Optionally, a plurality of the insertion layers are disposed in the barrier layer; in the direction perpendicular to the substrate, the plurality of insertion layers are sequentially arranged at intervals.

[0020] Optionally, the semiconductor structure includes a plurality of the channel structures, and the plurality of channel structures are sequentially stacked on one side of the substrate. Each layer of the plurality of insertion layers corresponding to the plurality of channel structures includes the recessed trench.

[0021] Optionally, the first groove penetrates at least to the barrier layer of the channel structure near one side of the substrate.

[0022] Optionally, along the direction from the substrate to the channel layer, the lengths of the plurality of channel structures gradually decrease.

[0023] Optionally, along the direction from the substrate to the channel layer, the lengths of the plurality of insertion layers remain unchanged, gradually decrease, or gradually increase.

[0024] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, including:

[0025] Providing a substrate;

[0026] Forming a channel structure on one side of the substrate, where forming the channel structure includes sequentially forming a channel layer and a barrier layer on the substrate. The channel structure includes a gate region, and a source region and a drain region located on both sides of the gate region; wherein forming the barrier layer includes forming the barrier layer

[0027] Etching the channel structure to form a first groove, and the first groove penetrates at least the barrier layer;

[0028] Laterally etching the sidewalls of the insertion layer so that the sidewalls of the insertion layer at the ends of the source region and the drain region are retracted by a preset distance relative to the sidewalls of the barrier layer to form a recessed trench, and the recessed trench communicates with the first groove;

[0029] Forming a heavily doped material layer in the first groove; the heavily doped material layer fills the first groove and the recessed trench.

[0030] Optionally, after forming the heavily doped material layer in the first groove, it further includes:

[0031] Forming a gate on the barrier layer;

[0032] Forming a source and a drain on the heavily doped material layer; the source and the drain are located on opposite sides of the gate.

[0033] Optionally, forming a barrier layer on the surface of the channel layer away from the substrate and forming an insertion layer in the barrier layer includes:

[0034] Forming a first barrier sub-layer on the surface of the channel layer away from the substrate;

[0035] An insertion layer is formed on the surface of the first barrier sub-layer away from the substrate side;

[0036] A second barrier sub-layer is formed on the surface of the insertion layer away from the substrate side; the barrier layer includes the first barrier sub-layer and the second barrier sub-layer.

[0037] Optionally, the lateral etching of the sidewalls of the insertion layer to form the recessed trench includes:

[0038] Selectively laterally etching the sidewalls of the insertion layer along the direction of the channel width to form at least one finger-shaped trench, and the at least one finger-shaped trench is arranged at intervals along the direction of the channel width;

[0039] When forming the heavily doped material layer in the first groove, it further includes:

[0040] Laterally growing the heavily doped material layer so that the heavily doped material layer fills the at least one first sub-trench to form a protrusion.

[0041] Optionally, forming the heavily doped material layer in the first groove includes:

[0042] Forming a heavily doped material layer of a single-layer material layer or a stacked-layer material layer in the first groove.

[0043] Optionally, forming the insertion layer in the barrier layer includes:

[0044] Forming a plurality of the insertion layers in the barrier layer; in the direction perpendicular to the substrate, the plurality of insertion layers are arranged at intervals in sequence.

[0045] Optionally, forming a channel structure on one side of the substrate includes:

[0046] Forming a plurality of the channel structures on one side of the substrate; the plurality of channel structures are stacked on one side of the substrate in sequence.

[0047] Optionally, etching the channel structure to form a first groove includes:

[0048] Etching the plurality of channel structures such that along the direction from the substrate to the channel layer, the lengths of the plurality of channel structures gradually decrease.

[0049] In the technical solution provided by the embodiment of the present invention, by arranging an insertion layer in the barrier layer, after etching a channel structure to form a first groove penetrating at least the barrier layer, the sidewalls of the insertion layer are etched laterally, so that the sidewalls of the insertion layer at the source region and the drain region ends are recessed by a preset distance relative to the sidewalls of the barrier layer to form a recessed trench, and the recessed trench is arranged to communicate with the first groove; when forming a heavily doped material layer in the first groove, the heavily doped material layer can fill the first groove and also fill the recessed trench, thereby increasing the contact area between the heavily doped material layer and the channel structure and reducing the contact resistance between the heavily doped material layer and the sidewalls of the heterojunction.

[0050] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0052] Figure 1 is a cross-sectional structure diagram of the structure after secondary epitaxial growth of heavily doped GaN material in the prior art;

[0053] Figure 2 is a cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention;

[0054] Figure 3 is a cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0055] Figure 4 is a top view of an insertion layer, a barrier layer, and a channel layer provided by an embodiment of the present invention;

[0056] Figure 5 is Figure 2 a cross-sectional structure diagram of the structure shown along the section line AA1;

[0057] Figure 6 is a top view of an insertion layer, a barrier layer, and a channel layer provided by an embodiment of the present invention;

[0058] Figure 7 is Figure 2 another cross-sectional structure diagram of the structure shown along the section line AA1;

[0059] Figure 8It is a top view of another insertion layer, barrier layer, and channel layer provided by an embodiment of the present invention;

[0060] Figure 9 is Figure 2 Another schematic cross-sectional structure diagram along the section line AA1 in the shown structure;

[0061] Figure 10 It is a top view of another insertion layer, barrier layer, and channel layer provided by an embodiment of the present invention;

[0062] Figure 11 It is a top view of another insertion layer, barrier layer, and channel layer provided by an embodiment of the present invention;

[0063] Figure 12a It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0064] Figure 12b It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0065] Figure 12c It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0066] Figure 13 It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0067] Figure 14 It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0068] Figures 15 to 18 It is a schematic cross-sectional structure diagram of steps S110 - S150 in a method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0069] Figures 19 to 22 It is a schematic cross-sectional structure diagram of steps S210 - S250 in a method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0070] Figures 23 to 24 is for preparing Figure 14 A schematic cross-sectional structure diagram of some steps in the method for preparing the shown semiconductor structure. Detailed implementation manners

[0071] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0072] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0073] An embodiment of the present invention provides a semiconductor structure. Figure 2 It is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention. Refer to Figure 2 , including:

[0074] Substrate 10;

[0075] A channel structure 302 located on the substrate 10. The channel structure 302 includes a channel layer 20 and a barrier layer 30 formed in sequence on the substrate 10. The channel structure 302 includes a gate region Q1, and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1;

[0076] A first groove 70 located in the source region Q2 and the drain region Q3, and the first groove 70 penetrates at least the barrier layer 30;

[0077] An insertion layer 40 is disposed in the barrier layer 30; the side walls of the insertion layer 40 at the ends of the source region Q2 and the drain region Q3 are retracted by a preset distance relative to the side walls of the barrier layer 30 to form an indented trench 60, and the indented trench 60 communicates with the first groove 70;

[0078] A heavily doped material layer 50 fills the first groove 70 and the indented trench 60.

[0079] Specifically, the substrate 10 can be a semiconductor substrate 10. The material of the substrate 10 can include but is not limited to Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (such as silicon-on-insulator (SOI)) or other suitable substrate 10 materials. In some embodiments, the substrate 10 can include, for example but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the material of the substrate 10 can include a silicon substrate 10 having a <111> orientation. In some embodiments, the substrate 10 can include a buffer layer, which can be in contact with the channel structure 302 and is used to reduce the lattice and thermal mismatch between the substrate 10 and the channel structure 302, thereby solving defects attributed to the mismatch / difference. The buffer layer can include III-V compounds. The III-V compounds can include but are not limited to aluminum, gallium, indium, nitrogen, or combinations thereof. Therefore, the exemplary materials of the buffer layer can further include, for example but not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

[0080] The channel structure 302 includes a channel layer 20 and a barrier layer 30 formed successively on the substrate 10. The material of the channel layer 20 can include but is not limited to nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-x-y)N (where x + y ≤ 1), AlyGa(1-y)N (where y ≤ 1). The material of the barrier layer 30 can include but is not limited to group III-V nitride semiconductor materials, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof. The bandgap (i.e., the forbidden band width) of the material of the channel layer 20 is different from that of the material of the barrier layer 30, such that their electron affinities are different from each other and a heterojunction is formed therebetween. A triangular well potential is generated at the bonding interface between the channel layer 20 and the barrier layer 30, such that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

[0081] Etching is performed in the source region Q2 and the drain region Q3 of the channel structure 302, so as to form a first groove 70 in the source region Q2 and the drain region Q3. The first groove 70 at least penetrates the barrier layer 30, such that the bottom surface height of the first groove 70 is less than or equal to the interface height of the heterojunction, that is, the first groove 70 may partially penetrate the trench layer 20 or may completely penetrate the channel layer 20; the bottom surface height of the first groove 70 may be the height of the bottom surface of the first groove (etching tabletop 01) relative to the substrate 10, and the interface height of the heterojunction may be the height of the interface of the heterojunction relative to the substrate 10. Thus, it is ensured that the heavily doped material layer 50 located in the first groove 70 can be in contact with the heterojunction. Among them, the heavily doped material layer 50 includes, but is not limited to, an N-type heavily doped nitride semiconductor material layer. The N-type doping concentration of the heavily doped material layer 50 is greater than 1E18 / cm 3 , thereby ensuring that the heavily doped material layer 50 has a low resistance and improving the conductivity of the heavily doped material layer 50.

[0082] In order to reduce the contact resistance between the heavily doped material layer 50 and the channel structure 302, an insertion layer 40 is provided in the barrier layer 30 in the embodiments of the present invention. The barrier layer 30 may include a first barrier sub-layer 31 and a second barrier sub-layer 32, and the insertion layer 40 is located between the first barrier sub-layer 31 and the second barrier sub-layer 32. The material of the insertion layer 40 is different from that of the barrier layer 30, and there is an etching selectivity ratio between the barrier layer 30 and the insertion layer 40. Therefore, by means of lateral etching of the insertion layer 40, the side wall of the insertion layer 40 is retracted by a preset distance relative to the side wall of the barrier layer 30 to form an indented trench 60. The indented trench 60 communicates with the first groove 70. When a heavily doped nitride semiconductor material is epitaxially grown for the second time in the first groove 70 to form the heavily doped material layer 50, the nitride semiconductor material can be epitaxially grown laterally in the indented trench 60, so that the contact area between the heavily doped material layer 50 and the channel structure 302 can be increased, and the laterally epitaxially grown heavily doped material layer 50 has better crystal quality, effectively reducing the contact resistance between the heavily doped material layer 50 and the side wall of the heterojunction. Among them, the material of the insertion layer 40 is a group III nitride material. The materials of the barrier layer 30 and the insertion layer 40 are group III nitride materials. The material of the barrier layer 30 is AlGaN, and the material of the insertion layer 40 is AlN or GaN. Optionally, when the material of the barrier layer 30 is AlGaN, for example, the material of the insertion layer 40 can be GaN or AlN. The structures of the barrier layer 30 and the insertion layer 40 form a sandwich barrier layer structure. The material of the insertion layer 40 is composed of some chemical elements in the barrier layer 30, which can meet the requirements of selective etching and make the lattice constant of the material of the insertion layer 40 relatively close to the lattice constant of the material of the barrier layer 30, thereby improving the growth quality of the semiconductor structure. Optionally, the projection of the indented groove 60 on the substrate 10 is located in the source region Q2 and the drain region Q3. The side wall of the insertion layer 40 is retracted by a preset distance relative to the side wall of the barrier layer 30 to form the indented groove 60, and the preset distance is less than one-third of the length of the channel structure 302.

[0083] The semiconductor structure provided by the embodiment of the present invention includes: a substrate; a channel structure 302 located on the substrate 10, the channel structure 302 includes a channel layer 20 and a barrier layer 30 formed in sequence on the substrate 10, the channel structure 302 includes a gate region Q1, and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1; a first groove 70 located in the source region Q2 and the drain region Q3, the first groove 70 at least penetrates the barrier layer 30; an insertion layer 40 disposed in the barrier layer 30; the side walls of the insertion layer 40 at the ends of the source region Q2 and the drain region Q3 are retracted by a preset distance relative to the side walls of the barrier layer 30 to form a recessed trench 60, and the recessed trench 60 communicates with the first groove 70; a heavily doped material layer 50, and the heavily doped material layer 50 fills the first groove 70 and the recessed trench 60. It can increase the contact area between the heavily doped material layer 50 and the channel structure 302, and reduce the contact resistance between the heavily doped material layer 50 and the side walls of the heterojunction.

[0084] Based on the above embodiments, in an embodiment of the present invention, please continue to refer to Figure 2 , the semiconductor structure further includes: a gate G located in the gate region Q1, and the gate G is located on the side of the barrier layer 30 away from the substrate 10; a source S and a drain D respectively located in the source region Q2 and the drain region Q3, and the source S and the drain D are formed on the side of the heavily doped material layer 50 away from the substrate 10.

[0085] Specifically, the material of the gate G can be a metal or a metal compound, including but not limited to tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys or combinations thereof. There may be a layer of p-doped III-V nitride semiconductor material, such as p-type GaN, between the gate G and the barrier layer 30. The p-doped material can be obtained by using p-type impurities such as Be, Zn, Cd, and Mg. The materials of the source S and the drain D can include but are not limited to metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials or combinations thereof. The source S and the drain D can be a single layer, or multiple layers with the same or different compositions. In some embodiments, the source S and the drain D form an ohmic contact with the heavily doped material layer 50. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the source S and the drain D.

[0086] Based on the above embodiments, in an embodiment of the present invention, please continue to refer to Figure 2, the heavily doped material layer 50 is a single-layer material layer. The heavily doped material layer 50 is an N-type heavily doped nitride semiconductor material layer, and the N-type doping concentration of the heavily doped material layer 50 is greater than 1E18 / cm 3 .

[0087] Based on the above embodiments, in an embodiment of the present invention, Figure 3 is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention. Refer to Figure 3 , the heavily doped material layer 50 is a laminated material layer. The laminated material layer includes a superlattice structure. Adjacent two material layers (such as the film layer 51 and the film layer 52) have different N-type heavily doped nitride semiconductor materials, and the N-type doping concentration is greater than 1E18 / cm 3 . Exemplarily, the heavily doped material layer 50 is a superlattice structure in which InGaN layers and GaN layers are alternately stacked in sequence. Alternatively, the heavily doped material layer 50 is a superlattice structure in which AlGaN layers and GaN layers are alternately stacked in sequence. The superlattice structure has a high crystal quality, thereby further improving the growth quality of the semiconductor structure.

[0088] Based on the above embodiments, in an embodiment of the present invention, Figure 4 is a top view of an insertion layer, a barrier layer, and a channel layer provided by an embodiment of the present invention, Figure 5 is Figure 2 a schematic cross-sectional structure diagram along the section line AA1 in the structure shown. Refer to Figure 4 , Figure 5 and Figure 2 , the recessed trench 60 is a trench that penetrates in the channel width direction X. It can be understood that the entire side wall of the insertion layer 40 is etched along the channel width direction X to form the recessed trench 60. The side wall of the heavily doped material layer 50 close to the insertion layer 40 is a plane, so that the bottom surface of the recessed trench 60 is a flat surface, and the vertical projection of the side wall of the heavily doped material layer 50 close to the insertion layer 40 on the substrate 10 is linear.

[0089] Based on the above embodiments, in an embodiment of the present invention, Figure 6 is another top view of an insertion layer, a barrier layer, and a channel layer provided by an embodiment of the present invention, Figure 7 is Figure 2 another schematic cross-sectional structure diagram along the section line AA1 in the structure shown. Refer to Figure 6 and Figure 7 , and in combination with Figure 2, the recessed groove 60 includes at least one finger-shaped groove 601, and the at least one finger-shaped groove 601 is arranged at intervals along the channel width direction X; the side wall of the heavily doped material layer 50 close to the insertion layer 40 includes at least one protrusion 501; the protrusions 501 are embedded in the finger-shaped grooves 601 in one-to-one correspondence. It can be understood that when etching the side wall of the insertion layer 40, the side walls at some positions are selectively etched to form the first sub-groove 601. Setting the recessed groove 60 as a plurality of finger-shaped grooves 601 can further increase the contact area between the heavily doped material layer 50 and the channel structure 302, and reduce the contact resistance between the heavily doped material layer 50 and the side wall of the heterojunction. Among them, the recessed groove 60 may include a plurality of rectangular finger-shaped grooves 601, and the vertical projection of the side wall of the heavily doped material layer 50 close to the insertion layer 40 on the substrate 10 is comb-shaped. In this embodiment, the distance between the finger-shaped groove 601 and the side of the recessed groove 60 close to the first groove 70 is equal to 0.

[0090] Based on the above embodiments, Figure 8 is another top view of the insertion layer, barrier layer and channel layer provided by the embodiment of the present invention, Figure 9 is Figure 2 another schematic cross-sectional structure along the section line AA1 in the shown structure, refer to Figure 8 and Figure 9 , the difference between the recessed groove 60 provided by the embodiment of the present invention and the recessed groove 60 shown in Figure 6 and Figure 7 is that the recessed groove 60 provided by the embodiment of the present invention includes a plurality of triangular finger-shaped grooves 601, and the vertical projection of the side wall of the heavily doped material layer 50 close to the insertion layer 40 on the substrate 10 is serrated.

[0091] Based on the above embodiments, in an embodiment of the present invention, Figure 10 is another top view of the insertion layer, barrier layer and channel layer provided by the embodiment of the present invention, Figure 11 is another top view of the insertion layer, barrier layer and channel layer provided by the embodiment of the present invention, refer to Figure 10 and Figure 11 , the distance between the finger-shaped groove 601 and the side of the recessed groove 60 close to the first groove 70 is greater than 0; at least one finger-shaped groove 401 is arranged at intervals along the channel width direction X; the side wall of the heavily doped material layer 50 close to the insertion layer 40 includes at least one protrusion 501, and the protrusions 501 are embedded in the finger-shaped grooves 401 in one-to-one correspondence.

[0092] It can be understood that after etching the entire sidewall of the insertion layer 40 to form the recessed trench 60, the position at the bottom of the recessed trench 60 is selectively etched in the channel width direction X to form the finger-like trench 401; alternatively, when etching the sidewall of the insertion layer 40 to form the recessed trench 60, by adjusting the etching speed and / or etching duration at different positions, the recessed trench 60 and the finger-like trench 401 are formed simultaneously. Exemplarily, when etching the sidewall of the insertion layer 40, at the position where the finger-like trench 401 is located, the etching time at this position can be extended, and at the position where the finger-like trench 401 is not located, the etching time at this position can be shortened. Forming at least one finger-like trench 401 communicating with the recessed trench 60 on the sidewall of the insertion layer 40 close to the heavily doped material layer 50 can further increase the contact area between the heavily doped material layer 50 and the channel structure 302, and reduce the contact resistance between the heavily doped material layer 50 and the sidewall of the heterojunction. Optionally, when the finger-like trench 401 is rectangular as shown in Figure 10 , the vertical projection of the sidewall of the heavily doped material layer 50 close to the insertion layer 40 on the substrate 10 is comb-shaped (refer to Figure 7 ); when the finger-like trench 401 is triangular as shown in Figure 11 , the vertical projection of the sidewall of the heavily doped material layer 50 close to the insertion layer 40 on the substrate 10 is serrated (refer to Figure 9 ).

[0093] In summary, the distance between at least one finger-like trench 601 and the side of the recessed trench 60 close to the first groove 70 is ≥0.

[0094] Based on the above embodiments, in an embodiment of the present invention, Figure 12a is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention. Referring to Figure 12a , a plurality of insertion layers 40 are provided in the barrier layer 30; in the direction perpendicular to the substrate 10, the plurality of insertion layers 40 are arranged at intervals in sequence.

[0095] Specifically, the sidewalls of each insertion layer 40 close to the sidewall of the source region and the sidewall of the drain region are each recessed by a preset distance relative to the sidewall of the barrier layer 30, thereby forming a plurality of recessed grooves 60, and each recessed groove 60 communicates with the first groove 70. In the figure, it is exemplarily shown that there are two insertion layers 40 provided in the barrier layer 30, and each insertion layer 40 forms a recessed groove 60 at the position close to the source region and the position close to the drain region respectively, so that four recessed grooves 60 can be formed. By providing a plurality of insertion layers 40 in the barrier layer 30, the contact area between the heavily doped material layer 50 and the channel structure 302 can be further increased, and the contact resistance between the heavily doped material layer 50 and the sidewall of the heterojunction is reduced. In an alternative embodiment, along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of insertion layers 40 remain unchanged, gradually decrease, or gradually increase, wherein the length direction of the insertion layer 40 is parallel to the channel length direction of the channel structure 302. Specifically, referring to Figure 12b , Figure 12b is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention. Along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of insertion layers 40 gradually decrease; referring to Figure 12c , Figure 12c is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention. Along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of insertion layers 40 gradually increase.

[0096] Based on the above embodiments, in an embodiment of the present invention, Figure 13 is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention. Referring to Figure 13 , the channel structure 302 includes a plurality of channel structures 302, and the plurality of channel structures 302 are sequentially stacked on one side of the substrate 10. Each layer of the plurality of insertion layers 40 corresponding to the plurality of channel structures 302 includes a recessed groove 60. The first groove 70 penetrates at least to the barrier layer 30 adjacent to the substrate 10 side. Specifically, the present invention adopts a multi-channel AlGaN / GaN heterojunction stacked structure, which can form a plurality of parallel two-dimensional electron gas paths between the source and the drain, improve the total density of the two-dimensional electron gas, and greatly increase the saturation current of the device.

[0097] Optionally, referring to Figure 14 , along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of channel structures 302 gradually decrease.

[0098] Specifically, if in accordance with Figure 13In the shown structure, the lengths of multiple channel structures 302 are comparable. The bottom surface of the first groove 70 formed by etching the multiple channel structures 302 includes an etching mesa 01. In an embodiment of the present invention, along the direction from the substrate 10 to the channel layer 20, the lengths of the multiple channel structures 302 gradually decrease and may have multiple mesas. When the multi-channel stacked heterojunction is k layers, there may be corresponding etching mesas on the upper surface of each barrier layer 30 except the top barrier layer 30. Adding the 01 arranged inside the first channel layer 20, that is, k etching mesas; or corresponding mesas may be arranged on the upper surfaces of m - 1 barrier layers 30 (excluding the top barrier layer 30) among the k barrier layers 30. That is, the total number of etching mesas is m, where 2 ≤ m ≤ k. In this way, there are multiple steps on the sidewalls of the multi-layer heterojunction stacked structure. The N-type heavily doped GaN material is formed on the m mesas and wraps the sidewalls of the k-layer GaN layer and the heterojunction of the barrier layer 30. Due to the multiple stepped mesas existing on the sidewalls, the n-type heavily doped GaN material is in closer contact with the sidewalls of the heterojunction, thus reducing the contact resistance between the N-type heavily doped GaN material and the sidewalls of the multi-layer GaN heterojunction. Figure 14 Two channel structures are exemplarily drawn therein, that is, the multi-channel stacked heterojunction is 2 layers, and the etching mesas include two etching mesas, namely etching mesa 01 and etching mesa 02.

[0099] An embodiment of the present invention further provides a method for preparing a semiconductor structure. Figures 15 to 18 It is a schematic cross-sectional structure diagram of steps S110 - S150 in a method for preparing a semiconductor structure provided by an embodiment of the present invention. Refer to Figures 15 to 18 , the method for preparing a semiconductor structure includes:

[0100] S110. Provide a substrate 10.

[0101] S120. Form a channel structure 302 on one side of the substrate 10. Forming the channel structure 302 includes sequentially forming a channel layer 20 and a barrier layer 30 on the substrate 10. The channel structure 302 includes a gate region Q1 and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1; wherein forming the barrier layer 30 includes forming an insertion layer 40 in the barrier layer 30. Specifically, refer to Figure 15 .

[0102] Optionally, forming the barrier layer 30 on the surface of the channel layer 20 away from the substrate 10 and forming the insertion layer 40 in the barrier layer 30 includes: forming a first barrier sub-layer 31 on the surface of the channel layer 20 away from the substrate 10; forming the insertion layer 40 on the surface of the first barrier sub-layer 31 away from the substrate 10; forming a second barrier sub-layer 32 on the surface of the insertion layer 40 away from the substrate 10; the barrier layer 30 includes the first barrier sub-layer 31 and the second barrier sub-layer 32.

[0103] S130. Etch the channel structure 302 to form a first groove 70, and the first groove 70 penetrates at least the barrier layer 30.

[0104] Specifically, referring to Figure 16 , by etching the channel structure 302 to the barrier layer 30 or to a partial thickness of the barrier layer 30, the first groove 70 is formed such that the bottom surface height of the first groove 70 is less than or equal to the interface height of the heterojunction, that is, the first groove 70 can partially penetrate the trench layer 20 or can completely penetrate the channel layer 20; the bottom surface height of the first groove 70 can be the height of the bottom surface of the first groove 70 relative to the substrate 10, and the interface height of the heterojunction can be the height of the interface of the heterojunction relative to the substrate 10. Thus, it is ensured that the heavily doped material layer 50 located in the first groove 70 can contact the heterojunction.

[0105] S140. Laterally etch the sidewalls of the insertion layer 40 so that the sidewalls of the insertion layer 40 at the source region Q2 and the drain region Q3 ends are retracted by a preset distance relative to the sidewalls of the barrier layer 30 to form an indented trench 60, and the indented trench 60 communicates with the first groove 70.

[0106] Specifically, referring to Figure 17 , in order to reduce the contact resistance between the heavily doped material layer 50 and the channel structure 302, an insertion layer 40 is provided in the barrier layer 30 in the embodiments of the present invention, and the material of the insertion layer 40 is different from that of the barrier layer 30. Therefore, by laterally etching the insertion layer 40, the sidewalls of the insertion layer 40 are retracted by a preset distance relative to the sidewalls of the barrier layer 30, and an indented trench 60 is formed at the insertion layer 40 of the channel structure 302, and the indented trench 60 communicates with the first groove 70.

[0107] S150. Form a heavily doped material layer 50 in the first groove 70; the heavily doped material layer 50 fills the first groove 70 and the indented trench 60.

[0108] Specifically, referring to Figure 18 , when depositing an N-type heavily doped nitride semiconductor material in the first groove 70 to form the heavily doped material layer 50, the nitride semiconductor material can be filled in the indented trench 60, thereby increasing the contact area between the heavily doped material layer 50 and the channel structure 302 and reducing the contact resistance between the heavily doped material layer 50 and the sidewalls of the heterojunction.

[0109] Optionally, after forming the heavily doped material layer 50 in the first groove 70, it further includes:

[0110] S160. Form a gate G on the barrier layer 30, and form a source S and a drain D on the heavily doped material layer 50; the source S and the drain D are located on opposite sides of the gate G. Specifically, refer to Figure 2 .

[0111] In the technical solution provided by the embodiment of the present invention, by providing an insertion layer 40 within the barrier layer 30, after etching the channel structure 302 to form a first groove 70 that at least penetrates the barrier layer 30, the sidewalls of the insertion layer 40 are etched laterally, so that the sidewalls of the insertion layer 40 at the source region Q2 and the drain region Q3 ends are recessed by a preset distance relative to the sidewalls of the barrier layer 30 to form a recessed trench 60, and the recessed trench 60 is provided to communicate with the first groove 70; when forming the heavily doped material layer 50 in the first groove 70, the heavily doped material layer 50 can fill the first groove 70 and can also fill the recessed trench 60, thereby increasing the contact area between the heavily doped material layer 50 and the channel structure 302 and reducing the contact resistance between the heavily doped material layer 50 and the sidewalls of the heterojunction.

[0112] Optionally, etching the sidewalls of the insertion layer 40 laterally to form the recessed trench 60 includes: selectively etching the sidewalls of the insertion layer 40 laterally to form at least one finger-shaped trench 601 at the source region Q2 and the drain region Q3 ends of the insertion layer 40, and at least one finger-shaped trench 601 is arranged at intervals along the channel width direction; the recessed trench 60 includes at least one finger-shaped trench 601. Through the above preparation method of the recessed trench 60, the recessed trench 60 can be formed to include multiple finger-shaped trenches 601 as shown in Figure 6 or 8. Referring to Figure 7 or Figure 9 , when forming the heavily doped material layer 50 in the first groove 70, it further includes: laterally growing the heavily doped material layer 50 so that the heavily doped material layer 50 fills at least one finger-shaped trench 601 to form a protrusion 501.

[0113] Optionally, after selectively etching the sidewalls of the insertion layer 40 laterally to form the recessed trench 60 as shown in Figure 4 , it further includes: continuing to etch the sidewalls of the insertion layer 40 laterally to form at least one finger-shaped trench 401. Referring to Figure 10 and Figure 11 , at least one finger-shaped trench 401 is arranged at intervals along the channel width direction. When forming the heavily doped material layer 50 in the first groove 70, it further includes: laterally growing the heavily doped material layer 50 so that the heavily doped material layer 50 fills the recessed trench 60 and at least one finger-shaped trench 401 to form a protrusion 501 in at least one finger-shaped trench 401.

[0114] Optionally, forming the heavily doped material layer 50 in the first groove 70 includes:

[0115] A heavily doped material layer 50 of a single-layer material layer or a heavily doped material layer 50 of a laminated material layer is formed in the first groove 70, and the heavily doped material layer 50 is N-type doped when the heavily doped material layer 50 is formed; wherein, the doping concentration is greater than 1E18 / cm 3 .

[0116] Optionally, an insertion layer 40 is formed in the barrier layer 30, including: forming a plurality of insertion layers 40 in the barrier layer 30; in a direction perpendicular to the substrate 10, the plurality of insertion layers 40 are sequentially arranged at intervals. Thus, a semiconductor structure as shown in, for example Figure 12a can be formed.

[0117] The embodiment of the present invention also provides a preparation method of another semiconductor structure, Figures 19 to 22 is a schematic cross-sectional structure diagram of steps S210 to S250 in a preparation method of a semiconductor structure provided by an embodiment of the present invention. Refer to Figures 19 to 22 , the preparation method of the semiconductor structure includes:

[0118] S210. Provide a substrate 10.

[0119] S220. Form a plurality of channel structures 302 on one side of the substrate 10, and the plurality of channel structures 302 are sequentially stacked on one side of the substrate 10. Specifically, refer to Figure 19 , a plurality of channel structures 302 are formed on one side of the substrate 10. Forming the channel structure 302 includes sequentially forming a channel layer 20 and a barrier layer 30 on the substrate 10. The channel structure 302 includes a gate region Q1, and a source region Q2 and a drain region Q3 located on both sides of the gate region Q1; wherein forming the barrier layer 30 includes forming an insertion layer 40 in the barrier layer 30.

[0120] S230. Etch the plurality of channel structures 302 to form a first groove 70 that at least penetrates the barrier layer 30 adjacent to one side of the substrate 10. Specifically, refer to Figure 20 .

[0121] S240. Selectively laterally etch the sidewalls of the insertion layer 40 so that the sidewalls of the insertion layer 40 at the ends of the source region Q2 and the drain region Q3 are retracted by a preset distance relative to the sidewalls of the barrier layer 30 to form an indented trench 60, and the indented trench 60 communicates with the first groove 70. Specifically, refer to Figure 21 , the sidewalls of the insertion layer 40 located in different layers can be etched simultaneously, or the sidewalls of the insertion layer 40 located in different layers can be etched at different times.

[0122] S250. Form a heavily doped material layer 50 in the first groove 70; the heavily doped material layer 50 fills the first groove 70 and the indented trench 60. Specifically, refer to Figure 22 .

[0123] S260. Form a gate G on the barrier layer 30 that is farthest from the substrate 10, and form a source S and a drain D on the heavily doped material layer 50; the source S and the drain D are located on opposite sides of the gate G. For details, refer to Figure 13 .

[0124] The manufacturing method of the semiconductor structure provided by the embodiment of the present invention forms a plurality of channel structures 302 on one side of the substrate 10, and the plurality of channel structures 302 are stacked on one side of the substrate 10 in sequence. Etch the plurality of channel structures 302 to form a first groove 70 that at least penetrates the barrier layer 30 adjacent to one side of the substrate 10. The present invention adopts a multi-channel AlGaN / GaN heterojunction stack structure, which can form a plurality of parallel two-dimensional electron gas paths between the source and the drain, increase the total density of the two-dimensional electron gas, and greatly increase the saturation current of the device.

[0125] Optionally, refer to Figure 14 , along the direction from the substrate 10 to the channel layer 20, the lengths of the plurality of channel structures 302 gradually decrease. Figures 23 to 24 is a schematic cross-sectional structure of some steps in the manufacturing method of the semiconductor structure provided by the embodiment of the present invention. Refer to Figure 14 , in the process of etching the plurality of channel structures 302, along the direction from the gate to the substrate 10, etch the barrier layer 30, the insertion layer 40, and the channel layer 20 from deep to shallow multiple times to form a plurality of etched platforms at different heights (such as etched platform 01 and etched platform 02); among them, different etched platforms are respectively located below the interfaces of the heterojunctions formed by the channel layer 20 and the barrier layer 30 at different layers. Figure 23 and Figure 24 , in this way, there are a plurality of steps on the side walls of the multi-layer heterojunction stack structure, and the N-type heavily doped GaN material is formed on the plurality of platforms and wraps the side walls of the multi-layer channel layer 20 and the barrier layer 30 heterojunction. Due to the plurality of stepped platforms existing on the side walls, the N-type heavily doped GaN material is in closer contact with the side walls of the heterojunction, thus reducing the contact resistance between the N-type heavily doped GaN material and the side walls of the multi-layer GaN heterojunction.

[0126] In this way, there are a plurality of steps on the side walls of the multi-layer heterojunction stack structure, and the N-type heavily doped GaN material is formed on the plurality of platforms and wraps the side walls of the multi-layer channel layer 20 and the barrier layer 30 heterojunction. Due to the plurality of stepped platforms existing on the side walls, the N-type heavily doped GaN material is in closer contact with the side walls of the heterojunction, thus reducing the contact resistance between the N-type heavily doped GaN material and the side walls of the multi-layer GaN heterojunction.

[0127] Refer to Figure 14 , optionally, along the direction from the substrate 10 to the trench layer 20, the lengths of the plurality of recessed trenches 60 of the plurality of insertion layers 40 corresponding to the plurality of channel structures 302 gradually decrease. Optionally, along the direction from the substrate 10 to the trench layer 20, the projections of the plurality of recessed trenches 60 of the plurality of insertion layers 40 corresponding to the plurality of channel structures 302 on the substrate 10 do not overlap each other.

[0128] In this embodiment, refer to Figure 13, the side wall of the first groove 70 adjacent to the plurality of channel structures 302 is a vertical surface; refer to Figure 14 , the side wall of the first groove 70 adjacent to the plurality of channel structures 302 is stepped; in other embodiments, the lengths of the plurality of channel structures 302 gradually decrease, and the side wall of the first groove 70 adjacent to the plurality of channel structures 302 is an inclined surface.

[0129] Note that the above is only the preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate (10); A channel structure (302) located on the substrate (10), the channel structure (302) comprising a channel layer (20) and a barrier layer (30) sequentially formed on the substrate (10), the channel structure (2) comprising a gate region (Q1), and a source region (Q2) and a drain region (Q3) located on both sides of the gate region (Q1); A first groove (70) located in the source region (Q2) and the drain region (Q3), the first groove (70) penetrating at least the barrier layer (30); An insertion layer (40) disposed within the barrier layer (30); the sidewalls of the insertion layer (40) at the ends of the source region (Q2) and the drain region (Q3) are recessed a preset distance relative to the sidewalls of the barrier layer (30) to form a recessed trench (60), and the recessed trench (60) communicates with the first groove (70); A heavily doped material layer (50), the heavily doped material layer (50) filling the first groove (70) and the recessed trench (60).

2. The semiconductor structure according to claim 1, characterized in that, Further comprising: A gate (G) located within the gate region (Q1), the gate (G) being located on a side of the barrier layer (30) away from the substrate (10); A source (S) and a drain (D) respectively located within the source region (Q2) and the drain region (Q3), the source (S) and the drain (D) being formed on a side of the heavily doped material layer (50) away from the substrate (10).

3. The semiconductor structure according to claim 1, characterized in that, The heavily doped material layer (50) is a single-layer material layer or a stacked material layer, and the stacked material layer includes a superlattice structure.

4. The semiconductor structure according to claim 1, characterized in that, The materials of the barrier layer (30) and the insertion layer (40) are group III nitride materials, the material of the barrier layer (30) is AlGaN, and the material of the insertion layer (40) is AlN or GaN.

5. The semiconductor structure according to claim 1, characterized in that, The sidewall of the heavily doped material layer (50) adjacent to the insertion layer (40) includes at least one protrusion (501); the recessed trench (60) includes at least one finger-like trench (601), and the at least one finger-like trench (601) is arranged at intervals along the channel width direction; the protrusions are embedded in the finger-like trenches (601) in one-to-one correspondence.

6. The semiconductor structure according to claim 5, characterized in that, The vertical projection of the sidewall of the heavily doped material layer (50) adjacent to the insertion layer (40) on the substrate (10) is serrated or comb-shaped.

7. The semiconductor structure according to claim 5, characterized in that, The distance between the at least one finger-like trench (601) and the side of the recessed trench (60) adjacent to the first groove (70) ≥ 0.

8. The semiconductor structure according to claim 1, characterized in that, A plurality of the insertion layers (40) are disposed within the barrier layer (30); in a direction perpendicular to the substrate (10), the plurality of the insertion layers (40) are sequentially arranged at intervals.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The semiconductor structure includes a plurality of the channel structures (2), and the plurality of the channel structures (302) are sequentially stacked on one side of the substrate (10), and each layer of the plurality of the insertion layers (40) corresponding to the plurality of the channel structures (302) includes the recessed trench (60).

10. The semiconductor structure according to claim 9, characterized in that, The first groove (70) penetrates at least up to the barrier layer (30) of the channel structure (2) adjacent to the side of the substrate (10).

11. The semiconductor structure according to claim 9, characterized in that, Along the direction from the substrate (10) towards the channel layer (20), the lengths of multiple channel structures (302) gradually decrease.

12. The semiconductor structure according to claim 9, characterized in that, Along the direction from the substrate (10) towards the channel layer (20), the lengths of multiple insertion layers (40) remain unchanged, gradually decrease, or gradually increase.

13. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate (10); Forming a channel structure (302) on one side of the substrate (10), wherein forming the channel structure (302) includes sequentially forming a channel layer (20) and a barrier layer (30) on the substrate (10), the channel structure (302) includes a gate region (Q1), and a source region (Q2) and a drain region (Q3) located on both sides of the gate region (Q1); wherein forming the barrier layer (30) includes forming an insertion layer (40) within the barrier layer (30); Etching the channel structure (302) to form a first groove (70), the first groove (70) penetrating at least the barrier layer (30); Transversely etching the sidewalls of the insertion layer (40) such that the sidewalls of the insertion layer (40) at the ends of the source region (Q2) and the drain region (Q3) are recessed by a preset distance relative to the sidewalls of the barrier layer (30) to form a recessed trench (60), the recessed trench (60) communicating with the first groove (70); Forming a heavily doped material layer (50) within the first groove (70); the heavily doped material layer (50) fills the first groove (70) and the recessed trench (60).

14. The method for preparing a semiconductor structure according to claim 13, wherein, After forming the heavily doped material layer (50) within the first groove (60), further comprising: Forming a gate (G) on the barrier layer (30); Forming a source (S) and a drain (D) on the heavily doped material layer (50); the source (S) and the drain (D) are located on opposite sides of the gate (G).

15. The method for preparing a semiconductor structure according to claim 13, wherein, Forming a barrier layer (30) on the surface of the channel layer (20) away from the substrate (10) and forming an insertion layer (40) within the barrier layer (30) includes: Forming a first barrier sub-layer (31) on the surface of the channel layer (20) away from the substrate (10); Forming an insertion layer (40) on the surface of the first barrier sub-layer (31) away from the substrate (10); Forming a second barrier sub-layer (32) on the surface of the insertion layer (40) away from the substrate (10); the barrier layer (30) includes the first barrier sub-layer (32) and the second barrier sub-layer (32).

16. The method for preparing a semiconductor structure according to claim 13, wherein, The transversely etching the sidewalls of the insertion layer (40) to form the recessed trench (60) includes: selectively transversely etching the sidewalls of the insertion layer (40) along the direction of the channel width to form at least one finger-like trench (601), the at least one finger-like trench (601) being arranged at intervals along the direction of the channel width; When forming the heavily doped material layer (50) in the first groove (70), it further includes: Laterally growing the heavily doped material layer (50) so that the heavily doped material layer (50) fills the at least one first sub-groove (601) to form a protrusion (501).

17. The method for preparing a semiconductor structure according to claim 13, wherein, Forming the heavily doped material layer (50) in the first groove (70) includes: Forming a heavily doped material layer (50) of a single-layer material layer or a stacked-layer material layer in the first groove (70).

18. The method for preparing a semiconductor structure according to claim 13, wherein, Forming the insertion layer (40) in the barrier layer (30) includes: Forming a plurality of the insertion layers (40) in the barrier layer (30); in a direction perpendicular to the substrate (10), the plurality of the insertion layers (40) are sequentially arranged at intervals.

19. The method for preparing a semiconductor structure according to claim 13, wherein, Forming the channel structure (302) on one side of the substrate (10) includes: Forming a plurality of the channel structures (302) on one side of the substrate (10); the plurality of the channel structures (302) are sequentially stacked on one side of the substrate (10).

20. The method for preparing a semiconductor structure according to claim 19, wherein, Etching the channel structure (302) to form the first groove (70) includes: Etching the plurality of the channel structures (302) such that along the direction from the substrate (10) to the channel layer (20), the lengths of the plurality of the channel structures (302) gradually decrease.

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