Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a first well which comprises a first main well region and a plurality of first interdigital regions extending outwards from the first main well region, and ions in the first well are uniformly distributed; the second well comprises a second main well region and a plurality of second interdigital regions extending outwards from the second main well region, ions in the second well are uniformly distributed and are opposite to ions in the first well in conduction type, the second interdigital regions extend towards the first main body region, and the first interdigital regions extend towards the second main body region; the first interdigital areas and the second interdigital areas are arranged in a mutually interpenetrating manner; the drain region is located in the first well; the source region is positioned in the second well and is electrically contacted with the first interdigital region; and the gate region is positioned above the first well and the second well. According to the semiconductor structure and the preparation method thereof, the ion concentration of each region of the device is more uniform, the HCI effect of the device is not obvious, and the reliability of the device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Power MOSFETs are most commonly used in switches. In applications such as startup circuits, surge protection, solid-state relays, and constant current sources, power MOSFETs need to operate as normally "on" switches, that is, when the gate voltage is zero, the power MOSFET is turned on and current flows through it, and when the gate voltage is negative, the power MOSFET is turned off and no current flows through it. Such power MOSFETs are generally referred to as depletion-mode MOSFETs.

[0003] The most common structure of a depletion-mode MOSFET is to additionally implant an extra N-type implantation region on the surface of the P-well where the source region is located and make electrical contact with the N-well where the drain region is located, so that inversion is formed on the surface of the P-well and in the gap between the P-well and the N-well. In this way, conduction can occur between the drain region and the source region without applying pressure to the gate region, and the surface inversion can be achieved by applying a negative voltage to the gate to turn off the current channel.

[0004] The disadvantage of this structure is that the additionally implanted N-type implantation region will also increase the N-type ion concentration on the surface of the N-well where the drain region is located, and a relatively concentrated N-type ion doping region will appear at the bottom of the gate region, making the HCI effect (Hot Carrier Injection effect) of the MOSFET device relatively significant, resulting in reduced reliability and reduced lifespan; moreover, it will also reduce the breakdown voltage of the MOSFET device, and only by increasing the device size can the breakdown voltage requirement be met, which in turn increases the cost to a certain extent. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor structure and a method for manufacturing the same, in which the ion concentration in each region of the device is more uniform, the HCI effect of the device is not significant, and the reliability of the device is improved.

[0006] To achieve the above object, this application provides the following technical solutions:

[0007] This application provides a semiconductor structure, which includes:

[0008] A first well, including a first main well region and a plurality of first finger regions extending outward from the first main well region, and the ions in the first well are uniformly distributed;

[0009] A second well, including a second main well region and a plurality of second finger regions extending outward from the second main well region, wherein ions in the second well are uniformly distributed and have a conductivity type opposite to that of the ions in the first well, the second finger regions extend toward the first body region, the first finger regions extend toward the second body region, and the first finger regions and the second finger regions are interspersed with each other;

[0010] A drain region, located in the first well;

[0011] A source region, located in the second well and in electrical contact with the first finger region;

[0012] A gate region, located above the first well and the second well.

[0013] In one embodiment, there is a gap between each of the first finger regions and each of the second finger regions.

[0014] In one embodiment, there is an overlapping region between each of the first finger regions and each of the second finger regions.

[0015] In one embodiment, there is a gap between the first finger region and the second main well region.

[0016] In one embodiment, there is a gap between the second finger region and the first main well region.

[0017] In one embodiment, the semiconductor structure further includes a field plate, the field plate is located above the gate region and a part of the first well, and extends above a part of the drain region.

[0018] In one embodiment, the semiconductor structure further includes an active region, and the first well and the second well are both located in the active region.

[0019] In one embodiment, the source region is also located in a part of the first finger region.

[0020] The present application also provides a method for manufacturing a semiconductor structure for manufacturing the semiconductor structure as described above, the manufacturing method including:

[0021] Performing a first well ion implantation and a second well ion implantation on a semiconductor substrate respectively, the conductivity type of the ions in the second well ion implantation is opposite to that of the ions in the first well ion implantation, to form a first well and a second well, the first well includes a first main well region and a plurality of first finger regions extending outward from the first main well region, the second well includes a second main well region and a plurality of second finger regions extending outward from the second main well region, and the second finger regions extend toward the first body region, the first finger regions extend toward the second body region, and the first finger regions and the second finger regions are interspersed with each other;

[0022] A gate region is formed above the first well and the second well;

[0023] Drain ion implantation is performed in the first well to form a drain region, and source ion implantation is performed in the second well to form a source region, and the source region is in electrical contact with the first finger region.

[0024] In one embodiment, the manufacturing method further includes:

[0025] A field plate is formed above the gate region and a part of the first well, and the field plate extends above a part of the drain region.

[0026] Compared with the prior art, the technical solution of the present application has the following beneficial effects:

[0027] For the semiconductor structure and its manufacturing method of the present application, in the above embodiments, by forming a first well including a first finger region and a second well including a second finger region, the conductivity types of the ions in the second well and the ions in the first well are opposite, the second finger region extends toward the first main region, the first finger region extends toward the second main region, and the first finger regions and the second finger regions are interspersed with each other, and the source region is in electrical contact with the first finger region, so that the drain region in the first well and the source region in the second well are in a normally open state. Therefore, compared with the traditional depletion-type MOSFET, the semiconductor structure of the present application reduces the locally separate ion implantation regions for forming the normally open state current channel, the ion concentration in each region of the device is more uniform, and the HCI effect of the device is not significant, which can improve the reliability of the device. Moreover, the ion concentration in each region of the device is uniform, and the breakdown voltage of the device will not be affected, which can ensure the high breakdown voltage of the device. There is no need to increase the size of the device to improve the breakdown voltage of the device. Compared with the existing devices, the size of the device is smaller, which can increase the integration degree of the device and can reduce the cost. The current channel required for the semiconductor structure is realized in the step of manufacturing the well (subsequently used for manufacturing the drain region), without additional ion implantation steps or additional photomasks, and only the photomask originally used for manufacturing the well needs to be adjusted accordingly, which can be compatible with the manufacturing method of ordinary MOS devices, further reducing the process cost of the product. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0029] Figure 1A plan view schematic diagram of a semiconductor structure provided by the first embodiment of the present application;

[0030] Figure 1A is Figure 1 A cross-sectional view along the A-A direction;

[0031] Figure 1B is Figure 1 A cross-sectional view along the B-B direction;

[0032] Figure 2 Another plan view schematic diagram of a semiconductor structure provided by the first embodiment of the present application;

[0033] Figure 3 A flow schematic diagram of a preparation method of a semiconductor structure provided by the second embodiment of the present application;

[0034] Figures 4 - 8 respectively are Figure 3 Cross-sectional schematic diagrams of the semiconductor structure at each step in the shown process. Specific embodiments

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application. And in the following embodiments, each embodiment is described with emphasis. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0036] Figure 1 A top view of the semiconductor structure provided by the first embodiment of the present application, Figure 1A is Figure 1 A cross-sectional view along the A-A direction, Figure 1B is Figure 1 A cross-sectional view along the B-B direction. Among them, in order to more clearly show the relationship between each structure, Figure 1 the drain region 30 and the source region 40 are not shown, Figure 1 and Figure 1B show the drain region 30 and the source region 40, and the boundaries between the first main well region 11 and the first finger region 12, and between the second main well region 21 and the second finger region 22 are shown by dotted lines. Please refer to Figure 1 , Figure 1A and Figure 1B as shown, the semiconductor structure of the present application may include:

[0037] A semiconductor substrate (not shown). Among them, the semiconductor substrate can be a silicon substrate.

[0038] The first well 10 is located within the substrate. The first well 10 may include a first main well region 11 and a plurality of first finger regions 12 extending outward from the first main well region 11. Ions within the first well 10 are uniformly distributed.

[0039] The second well 20 is located within the substrate. The second well 20 may include a second main well region 21 and a plurality of second finger regions 22 extending outward from the second main well region 21. Ions within the second well 20 are uniformly distributed and have a conductivity type opposite to that of the ions within the first well 10. The second finger regions 22 extend toward the first body region, and the first finger regions 12 extend toward the second body region. Each of the first finger regions 12 and each of the second finger regions 22 are interspersed with each other.

[0040] The drain region 30 is located within the first well 10.

[0041] The source region 40 is located within the second well 20 and is in electrical contact with the first finger regions 12.

[0042] The gate region 50 is located above the first well 10 and the second well 20.

[0043] More specifically, the gate region 50 is located above the first finger regions 12 (and the second finger regions 22). The first finger regions 12 are located below the gate region 50 and cross the gate region 50. The first finger regions 12 serve as the current channel between the source region 40 and the drain region 30.

[0044] In one embodiment, the first main well region 11 and the second main well region 21 are respectively located on both sides of the gate region 50, and the gate region 50 is also located above a part of the first main well region 11.

[0045] In one embodiment, the size of the first finger regions 12 crossing the gate region 50 is greater than 0, that is, a part of the first finger regions 12 extends to the side of the gate region 50 closer to the second well 20.

[0046] In one embodiment, the source region 40 is located within the second well 20 and within a part of the first finger regions 12, that is, within the first finger regions 12 on the side of the gate region 50 closer to the second well 20, so that the source region 40 is in electrical contact with the first finger regions 12.

[0047] In a specific embodiment, the semiconductor structure is a depletion-type MOSFET. The first well 10 is an N well, and N-type ions are implanted, with light doping. The second well 20 is a P well, and P-type ions are implanted, with light doping. The drain region 30 and the source region 40 are both implanted with N-type ions, with heavy doping. The source region 40 is in electrical contact with the first finger region 12, and then is in electrical contact with the drain region 30 via the first finger region 12 and the first main well region 11, so that the semiconductor structure is in a normally-on (conducting) state. When a negative voltage is applied to the gate region 50, the first finger region 12 is inverted and depleted, which can pinch off the current channel, causing the device (semiconductor structure) to turn off.

[0048] In the above embodiment, by forming a first well including a first finger region and a second well including a second finger region, the conductivity types of the ions in the second well and the ions in the first well are opposite. The second finger region extends toward the first main body region, the first finger region extends toward the second main body region, and the first finger regions and the second finger regions are interspersed with each other. The source region is in electrical contact with the first finger region, so that the drain region located in the first well and the source region located in the second well are in a normally-on state. Thus, compared with the traditional depletion-type MOSFET, the semiconductor structure of the present application reduces the local and separate ion implantation regions for forming the current channel in the normally-on state, the ion concentrations in each region of the device are more uniform, and the HCI effect of the device is not significant, which can improve the reliability of the device.

[0049] In the embodiment of the present application, there are no special limitations on the sizes and numbers of the first finger region 12 and the second finger region 22, and they can be set according to the requirements of actual product applications.

[0050] Among them, in Figure 1 the shown specific embodiment, there is a gap between each of the first finger regions 12 and each of the second finger regions 22.

[0051] In another specific embodiment, please refer to Figure 2 as shown, there is an overlapping region between each of the first finger regions 12 and each of the second finger regions 22.

[0052] In another specific embodiment, there is a gap between the first finger region 12 and the second main well region 21.

[0053] In yet another specific embodiment, there is a gap between the second finger region 22 and the first main well region 11.

[0054] In the above embodiments, by adjusting the size of the gap or the overlapping area between the first finger region, the second finger region, the first main well region, and the second main well region, the turn-on voltage of the device can be adjusted, thereby improving the adaptability of the device. Through testing by the applicant, the semiconductor structure of the present application can achieve a turn-on voltage between 0 V and -2 V, meeting the requirements of practical applications.

[0055] Moreover, compared with the traditional depletion-type MOSFET, since there is no separately implanted ion implantation region in the semiconductor structure of the present application, the ion concentration in each region of the device is uniform, and the breakdown voltage of the device will not be affected, ensuring a relatively high breakdown voltage of the device. There is no need to increase the size of the device to improve its breakdown voltage. Compared with existing devices, the size of the device is relatively small, which can increase the integration density of the device and reduce costs.

[0056] In one embodiment, the number of the first finger regions 12 and the second finger regions 22 can be equal. For example, there are 3 first finger regions 12 and 3 second finger regions 22.

[0057] In another embodiment, the number of the first finger regions 12 and the second finger regions 22 can be unequal, with a difference of 1 between the number of the second finger regions 22 and the first finger regions 12. As Figure 1 shown, the number of the first finger regions 12 can be 3, and the number of the second finger regions 22 can be 4. Any one of the first finger regions 12 can be located between two adjacent second finger regions 22. Or the number of the first finger regions 12 can be 4, and the number of the second finger regions 22 can be 3. Any one of the second finger regions 22 can be located between two adjacent first finger regions 12.

[0058] Those skilled in the art can understand that the present application does not specifically limit the number of the first finger regions 12 and the second finger regions 22. In other embodiments, the number of the first finger regions 12 and the second finger regions 22 can also be other values.

[0059] In this embodiment, the breakdown voltage of the semiconductor structure is achieved by the field plate 60.

[0060] In one implementation manner, the semiconductor structure may further include a field plate 60, which is located above the gate region 50 and a part of the first well 10 and extends above a part of the drain region 30.

[0061] In this embodiment, by adjusting the length of the field plate 60, it is easy to achieve a breakdown voltage of the device between 10 V and 40 V, meeting the application requirements.

[0062] In one embodiment, the semiconductor structure may further include an active region 70, and both the first well 10 and the second well 20 are located within the active region 70. Thus, in a specific embodiment, a complete depletion-type MOSFET is formed. In an actual product, the edges of the first well 10 and the second well 20 extend beyond the edge of the active region 70 to ensure that the entire active region 70 is located in a region with uniform ion concentration, thereby ensuring the performance of the device.

[0063] Please refer to Figure 3 shown. A method for fabricating a semiconductor structure according to a second embodiment of the present application is used to fabricate the semiconductor structure as described above, and please also refer to Figures 4 - 7 shown. The fabrication method may include:

[0064] Step 1: Fabricate a plurality of isolation structures 80 on a semiconductor substrate, and an active region 70 is formed between the isolation structures 80 (please refer to Figure 4 shown).

[0065] In this embodiment, the isolation structure 80 may adopt a shallow trench isolation structure (STI).

[0066] Step 2: Perform a first well ion implantation and a second well ion implantation on the semiconductor substrate respectively. The conductivity type of the ions in the second well ion implantation is opposite to that of the ions in the first well ion implantation, to form the first well 10 and the second well 20. The first well 10 includes a first main well region 11 and a plurality of first finger regions 12 extending outward from the first main well region 11. The second well 20 includes a second main well region 21 and a plurality of second finger regions 22 extending outward from the second main well region 21. And the second finger regions 22 extend towards the first body region, and the first finger regions 12 extend towards the second body region. The first finger regions 12 and the second finger regions 22 are interspersed with each other (please refer to Figure 1 and Figure 5 shown).

[0067] In this embodiment, no specific limitation is made on the sequence of the first well ion implantation and the second well ion implantation.

[0068] Step 3: Fabricate a gate region 50 above the first well 10 and the second well 20 (please refer to Figure 6 shown).

[0069] In this embodiment, the first main well region 11 and the second main well region 21 are respectively located on both sides of the gate region 50, and the gate region 50 is also located above a part of the first main well region 11. A part of the first finger regions 12 extends to the side of the gate region 50 biased towards the second well 20.

[0070] Step Four: Perform drain ion implantation in the first well 10 to form a drain region 30, and perform source ion implantation in the second well 20 to form a source region 40. The source region 40 is in electrical contact with the first finger region 12 (please refer to Figure 1 and Figure 7 as shown).

[0071] In this embodiment, the sequence of drain ion implantation and source ion implantation is not specifically limited. During source ion implantation, it is implanted not only in the second well 20 but also in a part of the first finger region 12, that is, in the first finger region 12 on the side of the gate region 50 closer to the second well 20. In this way, a part of the first finger region 12 on the side of the gate region 50 closer to the second well 20 actually becomes a part of the source region 40 because source ions are also implanted therein, and the part of the first finger region 12 where source ions are not implanted forms electrical contact with the source region 40.

[0072] When preparing the first well 10 in the preparation method of the present application, the first finger region 12 formed simultaneously with the first main well region 11 (subsequently used to prepare the drain region 30) realizes the current channel required by the semiconductor structure. No additional ion implantation steps are required, nor are additional photomasks required. Only the photomask originally used for preparing the well needs to be adaptively adjusted, which can be compatible with the preparation method of ordinary MOS devices, further reducing the process cost of the product. Moreover, the first finger region 12 and the first main well region 11 are formed simultaneously in the same ion implantation step, and the ion concentration in each region is uniform. Therefore, the above-mentioned advantages of insignificant HCI effect, good reliability, and no impact on the breakdown voltage of the device are achieved. In an actual product, the edges of the first well 10 and the second well 20 extend beyond the edge of the active region 70 to ensure that the entire active region 70 is located in a region with uniform ion concentration, thereby ensuring the performance of the device and improving the yield of the process.

[0073] Please also refer to Figure 3 and Figure 8 as shown. In an embodiment, the preparation method may further include:

[0074] Step Five: Form a field plate 60 above the gate region 50 and a part of the first well 10. The field plate 60 extends above a part of the drain region 30. In this way, the field plate 60 required for the device breakdown voltage is realized, meeting the requirements of the device for breakdown voltage.

[0075] For the specific description of the semiconductor structure in the preparation method of the present application, reference can be made to the corresponding description in the foregoing semiconductor structure embodiment, which will not be elaborated here.

[0076] Compared with the prior art, the technical solution of the present application has the following beneficial effects:

[0077] The semiconductor structure and its manufacturing method of the present application form a first well including a first finger region and a second well including a second finger region. The conductivity types of the ions in the second well and the ions in the first well are opposite. The second finger region extends towards the first main region, and the first finger region extends towards the second main region. Each first finger region and each second finger region are arranged in an interdigitated manner. The source region is in electrical contact with the first finger region, so that the drain region in the first well and the source region in the second well are in a normally-on state. Therefore, compared with the traditional depletion-type MOSFET, the semiconductor structure of the present application reduces the local and separate ion implantation regions for forming the current channel in the normally-on state, the ion concentration in each region of the device is more uniform, and the HCI effect of the device is not significant, which can improve the reliability of the device. Moreover, the ion concentration in each region of the device is uniform, and the breakdown voltage of the device will not be affected, which can ensure the high breakdown voltage of the device. There is no need to increase the size of the device to improve the breakdown voltage. Compared with the existing devices, the size is smaller, which can increase the integration degree of the device and reduce the cost. The current channel required for the semiconductor structure is realized in the step of preparing the well (subsequently used to prepare the drain region), without additional ion implantation steps or additional photomasks, and only the photomask originally used for preparing the well needs to be adjusted appropriately, which can be compatible with the manufacturing method of ordinary MOS devices and further reduce the process cost of the product.

[0078] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights. In addition, specific examples are used in the specification to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application, and the content of this specification should not be construed as a limitation to the present application.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: A first trap, comprising a first main trap region and a plurality of first interdigitated regions extending outward from the first main trap region, wherein ions in the first trap are uniformly distributed; A second well comprises a second main well region and a plurality of second interdigital regions extending outward from the second main well region, wherein ions in the second well are evenly distributed and have a conductivity type opposite to that of ions in the first well, the second interdigital regions extend toward the first main region, the first interdigital regions extend toward the second main region, and the first interdigital regions and the second interdigital regions are interlaced with each other; a drain region located in the first well; a source region, located in the second well and electrically contacting the first interdigital region; The gate region is located above the first well and the second well.

2. The semiconductor structure according to claim 1, characterized in that: There is a gap between each of the first interdigital regions and each of the second interdigital regions.

3. The semiconductor structure according to claim 1, characterized in that: Each of the first interdigital regions and each of the second interdigital regions have an overlapping area.

4. The semiconductor structure according to claim 1, characterized in that: A gap is provided between the first interdigital region and the second main well region.

5. The semiconductor structure according to claim 1, characterized in that: A gap is provided between the second interdigital region and the first main well region.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further includes a field plate, which is located above the gate region and a portion of the first well and extends above a portion of the drain region.

7. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes an active region, and the first well and the second well are both located in the active region.

8. The semiconductor structure according to claim 1, characterized in that: The source region is also located in a portion of the first interdigital region.

9. A method for preparing a semiconductor structure, used for preparing the semiconductor structure according to any one of claims 1 to 8, characterized in that: The preparation method comprises: Performing a first well ion implantation and a second well ion implantation on a semiconductor substrate respectively, wherein the conductivity type of the ions implanted in the second well ion implantation is opposite to that of the ions implanted in the first well ion implantation, so as to form a first well and a second well, wherein the first well comprises a first main well region and a plurality of first interdigitated regions extending outward from the first main well region, and the second well comprises a second main well region and a plurality of second interdigitated regions extending outward from the second main well region, and the second interdigitated regions extend toward the first main region, and the first interdigitated regions extend toward the second main region, and the first interdigitated regions and the second interdigitated regions are interlaced with each other; Forming a gate region above the first well and the second well; Drain ion implantation is performed in the first well to form a drain region, and source ion implantation is performed in the second well to form a source region, and the source region is in electrical contact with the first interdigital region.

10. The preparation method according to claim 9, characterized in that: The preparation method further comprises: A field plate is formed above the gate region and a portion of the first well, and the field plate extends to a portion of the drain region.

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