Array substrate and display panel

Abstract

The embodiment of the invention discloses an array substrate and a display panel, the array substrate comprises a substrate, an active layer and a plurality of conducting layers, the active layer and the conducting layers are stacked on one side of the substrate, the conducting layers are located on one side, away from the substrate, of the active layer, and the active layer and the conducting layers form at least one pixel circuit. The pixel circuit comprises a driving transistor, a first leakage suppression transistor, a first capacitor and a second capacitor. The multi-layer conducting layer comprises a first connecting line and a second connecting line, a first pole plate of the second capacitor is connected with a first pole of the first electric leakage suppression transistor through the first connecting line, and a second pole of the first electric leakage suppression transistor is connected with a grid electrode of the driving transistor through the second connecting line; wherein the orthographic projection of the first pole plate of the second capacitor on the substrate is at least partially overlapped with the orthographic projection of the second pole plate of the first capacitor on the substrate. The scheme is beneficial to improving the layout space utilization rate.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular, to an array substrate and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements for the performance of display panels.

[0003] Currently, the layout space utilization rate of display panels is low, which cannot meet the display requirements and is not conducive to improving the display effect. Summary of the Invention

[0004] Embodiments of the present invention provide an array substrate and a display panel to improve the layout space utilization rate and improve the display effect.

[0005] According to an aspect of the present invention, there is provided an array substrate, including:

[0006] A substrate;

[0007] An active layer and a multi-layer conductive layer stacked on one side of the substrate, the multi-layer conductive layer is located on the side of the active layer away from the substrate, and at least one pixel circuit is formed by the active layer and the multi-layer conductive layer. The pixel circuit includes a driving transistor, a first leakage suppression transistor, a first capacitor, and a second capacitor;

[0008] The multi-layer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence. The gate of the driving transistor and the first electrode plate of the first capacitor connected to the gate of the driving transistor are located on the first conductive layer. The second electrode plate of the first capacitor is located on the second conductive layer. The first electrode plate of the second capacitor is located on the third conductive layer. The second electrode plate of the second capacitor is located on the fourth conductive layer;

[0009] The multi-layer conductive layer further includes a first connection line and a second connection line. The first electrode plate of the second capacitor is connected to the first pole of the first leakage suppression transistor through the first connection line. The second pole of the first leakage suppression transistor is connected to the gate of the driving transistor through the second connection line;

[0010] Wherein, the orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate.

[0011] Optionally, the first connection line sequentially connects the first electrode plate of the second capacitor and the first pole of the first leakage suppression transistor through a first type of via. The second pole of the first leakage suppression transistor is connected to one end of the second connection line through a first type of via. The gate of the driving transistor is connected to the other end of the second connection line through a first type of via;

[0012] Optionally, the positive projection of the first electrode plate of the second capacitor on the substrate overlaps with the active layer of the first leakage suppression transistor, and the positive projection of the first type of via on the substrate overlaps with the positive projection of the first electrode plate of the second capacitor on the substrate and the positive projection of the active layer corresponding to the first leakage suppression transistor on the substrate at the same time;

[0013] Optionally, the first connection line is disposed on the same layer as the second electrode plate of the second capacitor;

[0014] Optionally, the second connection line is disposed on the same layer as the second electrode plate of the second capacitor.

[0015] Optionally, the first connection line is located in the fourth conductive layer, and the fourth conductive layer is located on the side of the third conductive layer away from the substrate;

[0016] The first type of via extends from the fourth conductive layer to the active layer;

[0017] Optionally, the material of the third conductive layer is molybdenum;

[0018] Optionally, the multi-layer conductive layer further includes a power line, the second electrode plate of the second capacitor is connected to the power line, the second electrode plate of the first capacitor is connected to the power line, and the first electrode plate of the first capacitor is connected to the gate of the driving transistor;

[0019] Optionally, the power line is disposed on the same layer as the second electrode plate of the second capacitor;

[0020] Optionally, the gate of the driving transistor is multiplexed as the first electrode plate of the first capacitor.

[0021] Optionally, the array substrate further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, and the fourth insulating layer is located between the third conductive layer and the fourth conductive layer. The first type of via penetrates through the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer, or the first type of via penetrates through the fourth insulating layer, the third insulating layer, and the second insulating layer;

[0022] Optionally, the thickness of the third insulating layer is less than the thickness of the second insulating layer, and the thickness of the fourth insulating layer is less than the thickness of the second insulating layer;

[0023] Optionally, the sum of the thicknesses of the third insulating layer and the fourth insulating layer is equal to the thickness of the second insulating layer;

[0024] Optionally, the positive projection of the first connection line on the substrate is separated from the positive projection of the second electrode plate of the second capacitor on the substrate;

[0025] Optionally, the thickness of the fourth insulating layer is greater than the thickness of the third insulating layer;

[0026] Optionally, the thickness of the fourth insulating layer is between 500 Å and 3000 Å;

[0027] Optionally, the thickness of the fourth insulating layer is 1000 Å.

[0028] Optionally, the first conductive layer further includes a first scanning line extending along a first direction. The first scanning line overlaps with the active layer to form a first leakage suppression transistor. The orthographic projection of the first scanning line on the substrate is separated from the orthographic projection of the first connection line on the substrate;

[0029] Optionally, both the first connection line and the second connection line extend along a second direction, wherein the first direction intersects the second direction, and the orthographic projection of the first scanning line on the substrate overlaps with the orthographic projection of the second connection line on the substrate;

[0030] Optionally, the orthographic projection of the first scanning line on the substrate and the orthographic projection of the second connection line on the substrate are arranged in a cross manner.

[0031] Optionally, the pixel circuit further includes a second leakage suppression transistor, a first compensation transistor, and a second compensation transistor. The first conductive layer further includes a second scanning line. The orthographic projection of the second scanning line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first scanning line on the substrate. The overlap of the first scanning line with the active layer further forms a second leakage suppression transistor and a first compensation transistor. The overlap of the second scanning line with the active layer forms a second compensation transistor. The first connection line is sequentially connected to the second pole of the driving transistor through the second leakage suppression transistor, the first compensation transistor, and the second compensation transistor;

[0032] Optionally, the orthographic projection of the second scanning line on the substrate and the orthographic projection of the second connection line on the substrate are arranged in a cross manner;

[0033] Optionally, the overlap of the second scanning line with the active layer further forms a data writing transistor. The first pole of the data writing transistor is connected to the data line through a first-type via, and the second pole of the data writing transistor is connected to the first pole of the driving transistor through the active layer;

[0034] Optionally, the data line and the second scanning line are arranged on different layers;

[0035] Optionally, the data line is located in the fourth conductive layer.

[0036] Optionally, the pixel circuit further includes a first initialization transistor and a second initialization transistor, and the array substrate further includes a third scan line, a fourth scan line, and an initialization signal line. The third scan line overlaps with the active layer to form the first initialization transistor, and the fourth scan line overlaps with the active layer to form the second initialization transistor. The first initialization transistor is connected to the initialization signal line and is configured to sequentially transmit the initialization voltage on the initialization signal line to the gate of the driving transistor via the second leakage suppression transistor and the first leakage suppression transistor. The second initialization transistor is connected between the initialization signal line and the light-emitting element and is configured to transmit the initialization voltage to the light-emitting element.

[0037] Optionally, the third scan line and the fourth scan line are disposed on the same layer and are disposed on a different layer from the initialization signal line.

[0038] Optionally, the third scan line and the fourth scan line are located in the first conductive layer, and the initialization signal line is located in the second conductive layer.

[0039] Optionally, the positive projection of the third scan line on the substrate is located on a side of the positive projection of the first scan line on the substrate away from the positive projection of the gate of the driving transistor on the substrate, and the positive projection of the fourth scan line on the substrate is located on a side of the positive projection of the third scan line on the substrate away from the positive projection of the gate of the driving transistor on the substrate.

[0040] Optionally, the multi-layer conductive layer further includes a third connection line. The initialization signal line is connected to the first end of the third connection line through a first type of via, and the first pole of the first initialization transistor is connected to the other end of the third connection line through a first type of via.

[0041] Optionally, the third connection line is located in the fourth conductive layer.

[0042] Optionally, the pixel circuit further includes a bias transistor, and the multi-layer conductive layer further includes a bias voltage signal line. The fourth scan line overlaps with the active layer to form the bias transistor. The bias transistor is connected between the bias voltage signal line and the first pole or the second pole of the driving transistor and is configured to transmit the bias voltage on the bias voltage signal line to the first pole or the second pole of the driving transistor.

[0043] Optionally, the multi-layer conductive layer further includes a fourth connection line. The fourth connection line is sequentially connected to the bias voltage signal line and the first pole of the bias transistor through a first type of via.

[0044] Optionally, the positive projection of the fourth connection line on the substrate overlaps with the positive projection of the bias voltage signal line on the substrate, and the positive projection of the fourth connection line on the substrate overlaps with the active layer corresponding to the bias transistor.

[0045] Optionally, the positive projection of the first type of via on the substrate overlaps with the positive projection of the bias voltage signal line on the substrate and the active layer corresponding to the bias transistor at the same time.

[0046] Optionally, the positive projection of the bias voltage signal line on the substrate is located between the positive projection of the third scanning line on the substrate and the positive projection of the fourth scanning line on the substrate;

[0047] Optionally, the bias voltage signal line is located in the second conductive layer, and the fourth connection line is located in the fourth conductive layer;

[0048] Optionally, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, the multi-layer conductive layer further includes a light-emitting control signal line and a power supply line, the light-emitting control signal line overlaps with the active layer to form the first light-emitting control transistor and the second light-emitting control transistor, the first pole of the first light-emitting control transistor is connected to the power supply line through a first-type via, the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor through the active layer, the first pole of the second light-emitting control transistor is connected to the second pole of the driving transistor through the active layer, and the second pole of the second light-emitting control transistor is connected to the light-emitting element through a first-type via;

[0049] Optionally, the positive projection of the light-emitting control signal line on the substrate is located on the side of the positive projection of the gate of the driving transistor on the substrate away from the positive projection of the second scanning line on the substrate.

[0050] Optionally, the first electrode plate of the second capacitor is connected to one end of the first connection line through a second-type via, and the first pole of the first leakage suppression transistor is connected to the other end of the first connection line through a first-type via; the second pole of the first leakage suppression transistor is connected to one end of the second connection line through a first-type via, and the gate of the driving transistor is connected to the other end of the second connection line through a first-type via;

[0051] Optionally, the first-type via extends from the first connection line and / or the second connection line to the active layer, and the second-type via is located between the first connection line and the first electrode plate of the second capacitor;

[0052] Optionally, the array substrate further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, and the fourth insulating layer is located between the third conductive layer and the fourth conductive layer;

[0053] The first-type via penetrates through the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer, and the second-type via penetrates through the fourth insulating layer.

[0054] According to another aspect of the present invention, a display panel is provided, and the display panel includes the array substrate provided by any embodiment of the present invention.

[0055] The technical solution provided by the embodiment of the present invention is to add the first electrode plate of the second capacitor above the second electrode plate of the first capacitor, and make the positive projection of the second electrode plate of the first capacitor on the substrate at least partially overlap with the positive projection of the first electrode plate of the second capacitor on the substrate, so that the first capacitor and the second capacitor are arranged in a stacked manner, which is beneficial to increasing the capacitance value of the second capacitor, can keep the voltage at both ends of the first leakage suppression transistor stable, and further can keep the gate potential of the driving transistor better, which is beneficial to improving the display effect. In addition, it can also reduce the layout occupation space of the two capacitors, which is beneficial to improving the layout space utilization rate.

[0056] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0058] Figure 1 It is a top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0059] Figure 2 It is a cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0060] Figure 3 It is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0061] Figure 4 It is another cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0062] Figure 5 It is another cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0063] Figure 6 It is another top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0064] Figure 7 It is another top view structural schematic diagram of an array substrate provided by an embodiment of the present invention;

[0065] Figure 8 It is another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0066] Figure 9 Another cross-sectional structure schematic diagram of an array substrate provided by an embodiment of the present invention;

[0067] Figure 10 Another top-view structure schematic diagram of an array substrate provided by an embodiment of the present invention;

[0068] Figure 11 Another cross-sectional structure schematic diagram of an array substrate provided by an embodiment of the present invention;

[0069] Figure 12 A driving timing schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0070] Figure 13 A structure schematic diagram of a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0071] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0072] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0073] As described in the background art, there is a problem of poor display effect in the existing display panel. After research by the inventor, the reasons for the above problems are as follows: The display panel includes a pixel circuit, the pixel circuit includes a plurality of thin film transistors, the thin film transistors include a driving transistor and a switching transistor. Due to various reasons such as the self-characteristics of the thin film transistors, the thin film transistors cannot be completely turned off, resulting in a leakage path formed between the gate of the driving transistor and the connected switching transistor, causing the gate voltage of the driving transistor to be unstable and the display brightness to decay. In the related art, usually a voltage stabilizing capacitor is added to the node of the gate leakage path of the driving transistor to reduce the gate leakage, so that there are two relatively large capacitors in the pixel circuit, increasing the complexity of the pixel circuit layout, and affecting the layout space of the original storage capacitor, resulting in a decrease in the storage capacitor, which is not conducive to the stability of the gate voltage of the driving transistor, thus affecting the display effect.

[0074] In view of the above problems, an embodiment of the present invention provides an array substrate, which improves the display effect by optimizing the layout of the pixel circuit. Figure 1 FIG. is a top view structural schematic diagram of an array substrate provided by an embodiment of the present invention. Figure 2 FIG. is a cross-sectional structural schematic diagram of an array substrate provided by an embodiment of the present invention, specifically Figure 1 the cross-sectional structure obtained by cutting the shown array substrate along the cutting line aa'. Figure 3 FIG. is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention. Referring to Figure 1 、 Figure 2 and Figure 3 an array substrate provided by an embodiment of the present invention includes:

[0075] Substrate 11;

[0076] An active layer 101 and a multi-layer conductive layer stacked on one side of the substrate 11, the multi-layer conductive layer is located on the side of the active layer 101 away from the substrate 11, and the active layer 101 and the multi-layer conductive layer form at least one pixel circuit, and the pixel circuit includes a driving transistor Q1, a first leakage suppression transistor Q2, a first capacitor C1 and a second capacitor C2;

[0077] The multi-layer conductive layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3 and a fourth conductive layer M4 stacked in sequence. The gate of the driving transistor Q1 and the first electrode plate 21 of the first capacitor C1 connected to the gate of the driving transistor Q1 are located in the first conductive layer M1, the second electrode plate 22 of the first capacitor C1 is located in the second conductive layer M2, the first electrode plate 31 of the second capacitor C2 is located in the third conductive layer M3, and the second electrode plate 32 of the second capacitor C2 is located in the fourth conductive layer M4;

[0078] The multi-layer conductive layer further includes a first connection line 41 and a second connection line 42. The first electrode plate 31 of the second capacitor C2 is connected to the first pole of the first leakage suppression transistor Q2 through the first connection line 41, and the second pole of the first leakage suppression transistor Q2 is connected to the gate of the driving transistor Q1 through the second connection line 42;

[0079] Among them, the positive projection of the first electrode plate 31 of the second capacitor C2 on the substrate 11 at least partially overlaps with the positive projection of the second electrode plate 22 of the first capacitor C1 on the substrate 11.

[0080] Specifically, the substrate 11 can be used to provide protection and support for the array substrate. Among them, the substrate 11 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or can also be a rigid substrate formed of materials such as glass. A multi-layer conductive layer is stacked on one side of the substrate 11, and the multi-layer conductive layers are isolated from each other by an insulating layer. For example, the multi-layer conductive layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, and a fourth conductive layer M4. A first insulating layer 12 is provided between the active layer 101 and the first conductive layer M1, a second insulating layer 13 is provided between the first conductive layer M1 and the second conductive layer M2, a third insulating layer 14 is provided between the second conductive layer M2 and the third conductive layer M3, and a fourth insulating layer 15 is provided between the third conductive layer M3 and the fourth conductive layer M4.

[0081] A plurality of pixel circuits are formed on the array substrate, which are used to generate a driving current to drive the light-emitting element D1 connected to the pixel circuit to emit light. The pixel circuit is at least formed by a thin-film transistor and a capacitor. The thin-film transistor at least includes a driving transistor Q1 and a first leakage suppression transistor Q2, and the capacitor includes a first capacitor C1 and a second capacitor C2. Among them, the first capacitor C1 is used to store the gate voltage of the driving transistor Q1, the first leakage suppression transistor Q2 is used to suppress the leakage of the gate of the driving transistor Q1, and the second capacitor C2 is used to stabilize the voltage of the second pole of the first leakage suppression transistor Q2 to reduce the voltage difference across the first leakage suppression transistor Q2, thereby reducing the leakage current of the gate of the driving transistor Q1.

[0082] In this embodiment, the first electrode plate 31 of the second capacitor C2 is disposed above the second electrode plate 22 of the first capacitor C1, and the orthographic projection of the first electrode plate 31 of the second capacitor C2 on the substrate 11 overlaps with the orthographic projection of the second electrode plate 22 of the first capacitor C1 on the substrate 11. The first electrode plate 21 and the second electrode plate 22 of the first capacitor C1 overlap to form the first capacitor C1, and the first electrode plate 31 and the second electrode plate 32 of the second capacitor C2 overlap to form the second capacitor C2. Since the first electrode plate 31 of the second capacitor C2 and the second electrode plate 22 of the first capacitor C1 are located in different conductive layers, a capacitor can also be formed at the overlapping portion of the first electrode plate 31 of the second capacitor C2 and the second electrode plate 22 of the first capacitor C1. In this embodiment, the second electrode plate 32 of the second capacitor C2 is connected to the second electrode plate 22 of the first capacitor C1 (both are connected to the first power supply voltage VDD). Therefore, the capacitor formed at the overlapping portion of the first electrode plate 31 of the second capacitor C2 and the second electrode plate 22 of the first capacitor C1 can be used as an additional capacitor of the second capacitor C2 and connected in parallel with the second capacitor C2 to increase the overall capacitance value of the second capacitor C2.

[0083] The technical solution provided by the embodiment of the present invention adds the first electrode plate 31 of the second capacitor C2 above the second electrode plate 22 of the first capacitor C1, and makes the orthographic projection of the second electrode plate 22 of the first capacitor C1 on the substrate 11 overlap at least partially with the orthographic projection of the first electrode plate 31 of the second capacitor C1 on the substrate 11, so that the first capacitor C1 and the second capacitor C2 are arranged in a stacked manner, which is beneficial to increasing the capacitance value of the second capacitor C2, can keep the voltage at both ends of the first leakage suppression transistor Q2 stable, and further can keep the gate potential of the driving transistor Q1 better, which is beneficial to improving the display effect. In addition, it can also reduce the layout occupation space of the two capacitors, which is beneficial to improving the layout space utilization rate.

[0084] Optionally, in this embodiment, the capacitance value of the second capacitor C2 can be adjusted by adjusting the overlapping area between the first electrode plate 31 of the second capacitor C2 and the second electrode plate C2 of the second capacitor C2 and / or the second electrode plate 22 of the first capacitor C1.

[0085] Figure 4 It is a schematic cross-sectional structure diagram of another array substrate provided by the embodiment of the present invention. Figure 5 It is a schematic cross-sectional structure diagram of another array substrate provided by the embodiment of the present invention, where Figure 4 Specifically Figure 1 It is the cross-sectional structure obtained by cutting the array substrate along the cutting line bb'. Figure 5 Specifically Figure 1 It is the cross-sectional structure obtained by cutting the array substrate along the cutting line cc'. Refer to Figure 1 、 Figure 4 And Figure 5, on the basis of the above embodiments, optionally, the first connection line 41 is sequentially connected to the first electrode plate 31 of the second capacitor C2 and the first pole of the first leakage suppression transistor Q2 through the first type of via K1. The second pole of the first leakage suppression transistor Q2 is connected to one end of the second connection line 42 through the first type of via K1. The gate of the driving transistor Q1 is connected to the other end of the second connection line 42 through the first type of via K1.

[0086] Wherein, the positive projection of the first electrode plate 31 of the second capacitor C2 on the substrate 11 overlaps with the active layer 101 of the first leakage suppression transistor Q1, and the positive projection of the first type of via K1 on the substrate 11 intersects with the positive projection of the first electrode plate 31 of the second capacitor C2 on the substrate 11 and the positive projection of the active layer 101 corresponding to the first leakage suppression transistor Q1 on the substrate 11 at the same time. That is to say, the first electrode plate 31 of the second capacitor C2 and the first pole of the first leakage suppression transistor Q1 are connected through one first type of via K1. The purpose of such a design is to ensure that most of the transistor or wiring areas are the same as those of the process without the third metal layer M3, reduce the process difficulty, and at the same time, using a single via mask can reduce the number of masks and effectively save the process cost. Here, the material of the third conductive layer M3 is molybdenum, and the third conductive layer M3 is only used as the node electrode plate (i.e., the first electrode plate 31) of the second capacitor C2 and is no longer used as the wiring of other structures.

[0087] Optionally, in this embodiment, the first connection line 41 and the second electrode plate 32 of the second capacitor C2 are arranged on the same layer, and the second connection line 42 and the second electrode plate 32 of the second capacitor C2 are arranged on the same layer.

[0088] Specifically, the first connection line 41, the second connection line 42, and the second electrode plate 32 of the second capacitor C2 are all located in the fourth conductive layer M4. Among them, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4 are stacked in sequence, and the fourth conductive layer M4 is located on the side of the third conductive layer M3 away from the substrate 11. The first type of via K1 extends from the first connection line 41 to the active layer 101 for connection with the first electrode plate 31 of the second capacitor C2 and the first leakage suppression transistor Q2.

[0089] It should be noted that, in this embodiment, the first type of via K1 is an interlayer via, specifically a deep via. The first type of via K1 can penetrate the first insulating layer 12, the second insulating layer 13, the third insulating layer 14, and the fourth insulating layer 15, or can penetrate the first insulating layer 12, the second insulating layer 13, and the third insulating layer 14.

[0090] Optionally, the array substrate further includes a planarization layer 16, and the planarization layer 16 is located on the side of the fourth conductive layer M4 away from the substrate 11 and can be used for planarizing the wiring structure.

[0091] In this embodiment, along the thickness direction Z of the array substrate, the thickness of the third insulating layer 14 is less than that of the second insulating layer 13, and the thickness of the fourth insulating layer 15 is less than that of the second insulating layer 13. Optionally, the sum of the thicknesses of the third insulating layer 14 and the fourth insulating layer 15 is equal to the thickness of the second insulating layer 13, so that when etching the first type of vias K1, the original etching rate can be used for etching, which is convenient for etching the first type of vias K1.

[0092] Continuing to refer to Figure 1 and Figure 4 , optionally, the orthographic projection of the first connection line 41 on the substrate 11 is separated from the orthographic projection of the second electrode plate 32 of the second capacitor C2 on the substrate 11, that is, in the Y direction or the X direction, the first connection line 41 does not overlap with the second electrode plate 32 of the second capacitor C2. Since the first connection line 41 and the second electrode plate 32 of the second capacitor C2 are arranged in the same layer, when etching the fourth conductive layer M4 to form the first connection line 41 and the second electrode plate 32 of the second capacitor C2, in order to avoid damaging the third conductive layer M3, the thickness of the fourth insulating layer 15 can be appropriately increased to protect the third conductive layer M3. For example, the thickness of the fourth insulating layer 15 is greater than that of the third insulating layer 14.

[0093] In an alternative embodiment provided in this embodiment, the thickness of the fourth insulating layer 15 is between 500 Å and 3000 Å. For example, the thickness of the fourth insulating layer 15 can be 1000 Å.

[0094] Figure 6 FIG. is a top view structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 7 FIG. is a top view structural schematic diagram of another array substrate provided by an embodiment of the present invention, where Figure 7 only the active layer 101 and the scanning line are shown. Referring to Figure 6 and Figure 7 , on the basis of the above embodiments, optionally, the first conductive layer M1 further includes a first scanning line 111 extending along the first direction, the first scanning line 111 overlaps with the active layer 101 to form a first leakage suppression transistor Q2, and the orthographic projection of the first scanning line 111 on the substrate 11 is separated from the orthographic projection of the first connection line 41 on the substrate 11.

[0095] Both the first connection line 41 and the second connection line 42 extend along the second direction, the first direction intersects with the second direction, and the orthographic projection of the first scanning line 111 on the substrate 11 overlaps with the orthographic projection of the second connection line 42 on the substrate 11. Among them, the first direction can be the X direction, and the second direction can be the Y direction. For example, the orthographic projection of the first scanning line 111 on the substrate 11 and the orthographic projection of the second connection line 42 on the substrate 11 are cross-arranged.

[0096] Specifically, the overlapping position of the first scan line 111 and the active layer 101 serves as the gate of the first leakage suppression transistor Q2. The active layer 101 includes the channel region of the first leakage suppression transistor Q1, and the two sides of the channel region are respectively the first pole and the second pole of the first leakage suppression transistor Q1. The first pole of the first leakage suppression transistor Q1 is connected to the first electrode plate 31 of the second capacitor C2 through the first connection line 41, and the second pole of the first leakage suppression transistor Q1 is connected to the gate of the driving transistor Q1 through the second connection line 42.

[0097] Continue to refer to Figure 6 , the multi-layer conductive layer further includes a power supply line 50. The second electrode plate 32 of the second capacitor C2 is connected to the power supply line 50, the second electrode plate 22 of the first capacitor C1 is connected to the power supply line 50, and the first electrode plate 21 of the first capacitor C1 is connected to the gate of the driving transistor Q1. Among them, the power supply line 50 and the second electrode plate 32 of the second capacitor C2 are arranged on the same layer, both located in the fourth conductive layer M4.

[0098] In this embodiment, the first electrode plate 21 of the first capacitor C1 and the first electrode plate 31 of the second capacitor C2 are connected together through the active layer 101. When the first leakage suppression transistor Q2 is turned on, the first electrode plate 31 of the second capacitor C2 and the first electrode plate 21 of the first capacitor C1 have the same potential. When the first leakage suppression transistor Q2 changes from on to off, the parasitic capacitance between the gate of the first leakage suppression transistor Q2 and the gate of the driving transistor Q1 has a coupling effect, coupling the gate voltage of the driving transistor Q1, so that the gate potential of the driving transistor Q1 is close to the potential of the first pole of the first leakage transistor Q2, thereby reducing the voltage difference between the first pole and the second pole of the first leakage transistor Q2, which is beneficial to reducing the leakage current of the first leakage transistor Q2, and further maintaining the stability of the gate potential of the driving transistor Q1. Here, the gate of the driving transistor Q1 is multiplexed as the first electrode plate 21 of the first capacitor C1.

[0099] Optionally, the pixel circuit further includes a second leakage suppression transistor Q3, a first compensation transistor Q5, and a second compensation transistor Q4. The first conductive layer M1 further includes a second scan line 112. The orthographic projection of the second scan line 112 on the substrate 11 is located between the orthographic projection of the gate of the driving transistor Q1 on the substrate 11 and the orthographic projection of the first scan line 111 on the substrate 11. The overlapping of the first scan line 111 and the active layer 101 also forms the second leakage suppression transistor Q3 and the first compensation transistor Q5. The overlapping of the second scan line 112 and the active layer 101 forms the second compensation transistor Q4. The first connection line 41 is sequentially connected to the second pole of the driving transistor Q1 through the second leakage suppression transistor Q3, the first compensation transistor Q5, and the second compensation transistor Q4.

[0100] Among them, the positive projection of the second scan line 112 on the substrate 11 and the positive projection of the second connection line 42 on the substrate 11 are arranged in a crossed manner.

[0101] Continue to refer to Figure 6 and Figure 7 The pixel circuit further includes a data writing transistor Q6. The second scan line 112 overlaps with the active layer 101 to form the data writing transistor Q6. The first pole of the data writing transistor Q6 is connected to the data line 201 through a first type via, and the second pole of the data writing transistor Q6 is connected to the first pole of the driving transistor Q1 through the active layer 101. Among them, the data line 201 and the second scan line 112 are arranged on different layers to avoid mutual interference between them. For example, the data line 201 is located in the fourth conductive layer M4.

[0102] Optionally, the pixel circuit further includes a first initialization transistor Q7 and a second initialization transistor Q8. The array substrate further includes a third scan line 113, a fourth scan line 114, and an initialization signal line 116. The third scan line 113 overlaps with the active layer 101 to form the first initialization transistor Q7, and the fourth scan line 114 overlaps with the active layer 101 to form the second initialization transistor Q8; the first initialization transistor Q7 is connected to the initialization signal line 116, and is configured to sequentially transmit the initialization voltage Vref on the initialization signal line 116 to the gate of the driving transistor Q1 through the second leakage suppression transistor Q3 and the first leakage suppression transistor Q2; the second initialization transistor Q8 is connected between the initialization signal line 116 and the light emitting element D1, and is configured to transmit the initialization voltage Vref to the light emitting element D1.

[0103] Among them, the third scan line 113 and the fourth scan line 114 are arranged on the same layer, and are arranged on different layers from the initialization signal line 116. For example, the third scan line 113 and the fourth scan line 114 are located in the first conductive layer M1, and the initialization signal line 116 is located in the second conductive layer M2. The vertical projection of the third scan line 113 on the substrate 11 is located on one side of the vertical projection of the first scan line 111 on the substrate 11 away from the vertical projection of the gate of the driving transistor Q1 on the substrate 11; the vertical projection of the fourth scan line 114 on the substrate 11 is located on one side of the vertical projection of the third scan line 113 on the substrate 11 away from the vertical projection of the gate of the driving transistor Q1 on the substrate 11, so as to optimize the layout.

[0104] Optionally, the multi-layer conductive layer further includes a third connection line 43. The initialization signal line 116 is connected to the first end of the third connection line 43 through a first type via, and the first pole of the first initialization transistor Q7 is connected to the other end of the third connection line 43 through a first type via. Among them, the third connection line 43 is located in the fourth conductive layer M4, and the positive projection of the third connection line 43 on the substrate 11 and the positive projection of the fourth scan line 114 on the substrate 11 are arranged in a crossed manner.

[0105] Optionally, the pixel circuit further includes a first light emission control transistor Q10 and a second light emission control transistor Q11, and the multi-layer conductive layer further includes a light emission control signal line 115 and a power supply line 50, the light emission control signal line 115 overlaps with the active layer 101 to form the first light emission control transistor Q10 and the second light emission control transistor Q11, the first electrode of the first light emission control transistor Q10 is connected to the power supply line 50 through a first type via hole, the second electrode of the first light emission control transistor Q10 is connected to the first electrode of the driving transistor Q1 through the active layer 101, the first electrode of the second light emission control transistor Q11 is connected to the second electrode of the driving transistor Q1 through the active layer 101, and the second electrode of the second light emission control transistor Q11 is connected to the light emitting element D1 through the first type via hole. The positive projection of the light emission control signal line 115 on the substrate 11 is located on the side of the positive projection of the gate of the driving transistor Q1 on the substrate 11 away from the positive projection of the second scanning line 112 on the substrate 11.

[0106] The power line 50 and the second electrode plate 32 of the second capacitor C2 are an integrated structure.

[0107] Figure 8 Another schematic diagram of a pixel circuit is provided for reference. Figure 6 and Figure 8 On the basis of the above embodiments, optionally, the pixel circuit further includes a bias transistor Q9, the multi-layer conductive layer further includes a bias voltage signal line 117, the fourth scan line 114 overlaps with the active layer 101 to form a bias transistor Q9, and the bias transistor Q9 is connected between the bias voltage signal line 117 and the first electrode or the second electrode of the driving transistor Q1, and is used to transmit the bias voltage Vcom on the bias voltage signal line 117 to the first electrode or the second electrode of the driving transistor Q1. Among them, the bias transistor Q9 in the current level pixel circuit can be connected to the bias voltage signal line 117 in the previous level pixel circuit. The bias voltage signal line 117 can be located in the second conductive layer M2. Here, the second initialization transistor Q8 and the initialization signal line 116 can be connected by a connecting line in the third conductive layer M3 or the fourth conductive layer M4, and the bias voltage signal line 117 and the bias transistor Q9 can be connected by a connecting line in the third conductive layer M3 or the fourth conductive layer M4, so as to optimize the layout and reduce signal interference.

[0108] Figure 9 A schematic cross-sectional structure diagram of another array substrate provided in an embodiment of the present invention, specifically: Figure 6 The cross-sectional structure of the array substrate along the cutting line dd' is shown in FIG. Figure 6 and Figure 9, the multi-layer conductive layer further includes a fourth connection line 44, and the fourth connection line 44 is sequentially connected to the bias voltage signal line 117 and the first pole of the bias transistor Q9 through the first type of via K1.

[0109] Among them, the fourth connection line 44 is located in the fourth conductive layer M4. The orthographic projection of the fourth connection line 44 on the substrate 11 overlaps with the orthographic projection of the bias voltage signal line 117 on the substrate 11, and the orthographic projection of the fourth connection line 44 on the substrate 11 overlaps with the active layer 101 corresponding to the bias transistor Q9. The orthographic projection of the first type of via K1 on the substrate 11 overlaps with the orthographic projection of the bias voltage signal line 117 on the substrate 11 and the active layer 101 corresponding to the bias transistor Q9 at the same time.

[0110] Optionally, the orthographic projection of the third scan line 113 on the substrate 11 is located on the side of the orthographic projection of the first scan line 111 away from the gate of the driving transistor Q1 on the substrate 11, and the orthographic projection of the bias voltage signal line 117 on the substrate 11 is located between the orthographic projection of the third scan line 113 on the substrate 11 and the orthographic projection of the fourth scan line 114 on the substrate 11, which is beneficial to the connection of the bias transistor Q9.

[0111] In the above embodiments, there is only one type of via (i.e., the first type of via K1) in the layout structure of the array substrate, which is beneficial to optimizing the layout space, improving the utilization rate of the layout space, thereby achieving a high PPI, and by reducing the types of vias, it is beneficial to simplify the manufacturing process and reduce the manufacturing cost.

[0112] Of course, in the layout design with a low PPI, multiple types of vias can also be used. Figure 10 FIG. [X] is a top view structural schematic diagram of another array substrate provided by an embodiment of the present invention. Figure 11 FIG. [Y] is a cross-sectional structural schematic diagram of another array substrate provided by an embodiment of the present invention. Refer to Figure 10 and Figure 11 , the first electrode plate 31 of the second capacitor C2 is connected to one end of the first connection line 41 through the second type of via K2, and the first pole of the first leakage suppression transistor Q2 is connected to the other end of the first connection line 41 through the first type of via K1. That is, the first electrode plate 31 of the second capacitor C2 and the first leakage suppression transistor Q2 are connected together across the first connection line 41. Among them, the first type of via K1 extends from the first connection line 41 and / or the second connection line 42 to the active layer 101, and the second type of via K2 is located between the first connection line 41 and the first electrode plate 31 of the second capacitor C2. The first type of via K1 penetrates the fourth insulating layer 15, the third insulating layer 14, the second insulating layer 13, and the first insulating layer 12, and the second type of via K2 penetrates the fourth insulating layer 15.

[0113] The second pole of the first leakage suppression transistor Q2 is connected to one end of the second connection line 42 through a first type via K1, and the gate of the driving transistor Q1 is connected to the other end of the second connection line 42 through the first type via K1, which is the same as the connection method of the second pole of the first leakage suppression transistor Q2 in Figure 1 .

[0114] Figure 12 It is a schematic diagram of the driving timing of a pixel circuit provided by an embodiment of the present invention, which is applicable to the pixel circuit shown in Figure 8 . Referring to Figure 8 and Figure 12 , taking each transistor as a P-type transistor as an example, within a display period, it includes a writing frame and a holding frame. Among them, the writing frame includes a first initialization stage T1, a data writing and compensation stage T2, a second initialization stage T3, and a light emitting stage T4.

[0115] In the first initialization stage T1, the first scan signal S1 is at a low level, the second scan signal S2 is at a high level, the third scan signal S3 is at a low level, the fourth scan signal S4 is at a high level, and the light emission control signal EM is at a high level. Therefore, the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first compensation transistor Q5, and the first initialization transistor Q7 are turned on, and the second compensation transistor Q4, the data writing transistor Q6, the second initialization transistor Q8, the bias transistor Q9, the first light emission control transistor Q10, and the second light emission control transistor Q11 are turned off. The initialization voltage Vref on the initialization signal line is transmitted to the gate of the driving transistor Q1 through the first initialization transistor Q7, the second leakage suppression transistor Q3, and the first leakage suppression transistor Q2, initializing the gate of the driving transistor Q1 and turning on the driving transistor Q1 at the same time.

[0116] During the data writing and compensation stage T2, the first scan signal S1 is at a low level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a high level, and the emission control signal EM is at a high level. Therefore, the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first compensation transistor Q5, the second compensation transistor Q4, and the data writing transistor Q6 are turned on, the first initialization transistor Q7 is turned on, and the second initialization transistor Q8, the bias transistor Q9, the first emission control transistor Q10, and the second emission control transistor Q11 are turned off. The data voltage Vdata on the data line is written to the gate of the driving transistor Q1 through the data writing transistor Q6, the driving transistor Q1, the second compensation transistor Q4, the first compensation transistor Q5, the second leakage suppression transistor Q3, and the first leakage suppression transistor Q2. When the gate voltage of the driving transistor Q1 reaches Vdata + Vth1, the driving transistor Q1 is turned off, realizing data writing and threshold voltage compensation. The gate voltage is stored on the storage capacitor C1 and the voltage stabilizing capacitor C2 respectively. Wherein, Vth1 is the threshold voltage of the driving transistor Q1.

[0117] When the first scan signal S1 jumps from a low level to a high level, the first leakage suppression transistor Q2 changes from on to off. Under the coupling action of the parasitic capacitance at the gate of the driving transistor Q1, the gate voltage of the driving transistor Q1 is pulled up to be close to the voltage stored on the voltage stabilizing capacitor C2. Therefore, the voltage difference between the first pole and the second pole of the first leakage suppression transistor Q3 is small, making the leakage current of the first leakage suppression transistor Q3 small, so as to maintain the stability of the gate voltage of the driving transistor Q1.

[0118] In the second initialization stage T3, the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a low level, and the light emission control signal EM is at a high level. Therefore, the second initialization transistor Q8 and the bias transistor Q9 are turned on, and the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first compensation transistor Q5, the first initialization transistor Q7, the second compensation transistor Q4, the data writing transistor Q6, the first light emission control transistor Q10, and the second light emission control transistor Q11 are turned off. The initialization voltage Vref is transmitted to the first pole (anode) of the light emitting element D1 through the first initialization transistor Q7 to initialize the first pole of the light emitting element D1, so as to reduce the influence of the residual charge of the first pole of the light emitting element D1 on the display effect. At the same time, the bias transistor Q9 transmits the bias voltage Vcom to the first pole of the driving transistor Q1 to perform voltage biasing on the driving transistor Q1, so as to reduce the difference in the bias states of the driving transistor Q1 in the writing frame and the holding frame, so that the first pole of the driving transistor Q1 has the same voltage value under the same gray scale condition, so as to ensure that the first pole and the second pole of the driving transistor Q1 maintain the same potential respectively in the writing frame and the holding frame. Among them, the bias voltage Vcom can be set according to the actual screen adjustment effect.

[0119] Of course, in other embodiments, the bias transistor Q9 can also transmit the bias voltage Vcom to the second pole of the driving transistor Q1, which can also play a role in changing the bias state of the driving transistor Q1 and has the same beneficial effect.

[0120] In the light emission stage T4, the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a high level, and the light emission control signal EM is at a low level. Therefore, the first light emission control transistor Q10 and the second light emission control transistor Q11 are turned on, and the first leakage suppression transistor Q2, the second leakage suppression transistor Q3, the first compensation transistor Q5, the first initialization transistor Q7, the second compensation transistor Q4, the data writing transistor Q6, the second initialization transistor Q8, and the bias transistor Q9 are turned off. The driving transistor Q1 generates a driving current to drive the light emitting element D1 to emit light. Since the gate voltage of the driving transistor Q1 can be kept stable for a long time, the uniformity of the driving current can be ensured, and the afterimage problem of the display screen can be improved.

[0121] The working process in the holding frame is as follows:

[0122] The T5 stage is the initialization and voltage biasing stage, and the specific working process is the same as that of the second initialization stage T2, and the relevant description above can be referred to.

[0123] The T6 stage is the light-emitting stage, and its specific working process is the same as that of the light-emitting stage T4. For the relevant description, please refer to the above content.

[0124] The technical solution provided in this embodiment is to set a holding frame and set the T5 stage and the T6 stage within the holding frame. This is equivalent to increasing the number of times the light-emitting element D1 emits light within one display cycle, and can convert the low-frequency luminance components that are easily perceived by the human eye into high-frequency luminance components that are not easily perceived, thereby improving the flicker phenomenon of the display screen. Moreover, the storage capacitor C1 in the pixel circuit can have a relatively large capacitance value, which is beneficial to improving the stability of the gate potential of the driving transistor Q1, thereby further improving the flicker phenomenon of the display screen. And through the corresponding via design, it is possible to ensure that the second connection line 42 has a relatively wide line width to improve the display effect while meeting the high-brightness display requirements.

[0125] Optionally, an embodiment of the present invention further provides a display panel, which includes the array substrate provided in any embodiment of the present invention. Therefore, this display panel also has the beneficial effects described in any of the above embodiments. Among them, the display panel can be a flexible display panel or a rigid display panel. The display panel formed by using the array substrate provided in any of the above embodiments can effectively improve the display effect of AOD (Always On Display). Figure 13 FIG. is a schematic structural diagram of a display panel provided in an embodiment of the present invention. In this embodiment, the display panel 200 can be a mobile phone panel or can be applied to any electronic product with a display function, including but not limited to the following categories: display panels in products such as televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, vehicle-mounted displays, medical devices, industrial control devices, and touch interaction terminals. The embodiments of the present invention do not make special limitations in this regard.

[0126] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0127] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer and a multi-layer conductive layer stacked on one side of the substrate, the multi-layer conductive layer is located on a side of the active layer away from the substrate, the active layer and the multi-layer conductive layer constitute at least one pixel circuit, and the pixel circuit includes a driving transistor, a first leakage suppression transistor, a first capacitor and a second capacitor; The multi-layer conductive layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence, the gate of the driving transistor and the first electrode plate of the first capacitor connected to the gate of the driving transistor are located in the first conductive layer, the second electrode plate of the first capacitor is located in the second conductive layer, the first electrode plate of the second capacitor is located in the third conductive layer, and the second electrode plate of the second capacitor is located in the fourth conductive layer; The multi-layer conductive layer further includes a first connecting line and a second connecting line, the first electrode of the second capacitor is connected to the first electrode of the first leakage suppression transistor through the first connecting line, and the second electrode of the first leakage suppression transistor is connected to the gate of the driving transistor through the second connecting line; The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the substrate.

2. The array substrate according to claim 1, characterized in that: The first connecting line sequentially connects the first electrode plate of the second capacitor and the first electrode of the first leakage suppression transistor through a first type via hole, the second electrode of the first leakage suppression transistor is connected to one end of the second connecting line through the first type via hole, and the gate of the driving transistor is connected to the other end of the second connecting line through the first type via hole; Preferably, the orthographic projection of the first electrode plate of the second capacitor on the substrate overlaps with the active layer of the first leakage suppression transistor, and the orthographic projection of the first type of via on the substrate overlaps with the orthographic projection of the first electrode plate of the second capacitor on the substrate and the orthographic projection of the active layer corresponding to the first leakage suppression transistor on the substrate; Preferably, the first connecting line is arranged in the same layer as the second electrode plate of the second capacitor; Preferably, the second connecting line is arranged in the same layer as the second electrode plate of the second capacitor.

3. The array substrate according to claim 2, characterized in that: The first connecting line is located in the fourth conductive layer, and the fourth conductive layer is located on a side of the third conductive layer away from the substrate; The first type via extends from the fourth conductive layer to the active layer; Preferably, the material of the third conductive layer is molybdenum; Preferably, the multi-layer conductive layer further comprises a power line, the second electrode plate of the second capacitor is connected to the power line, the second electrode plate of the first capacitor is connected to the power line, and the first electrode plate of the first capacitor is connected to the gate of the driving transistor; Preferably, the power line is arranged in the same layer as the second electrode plate of the second capacitor; Preferably, the gate of the driving transistor is reused as the first plate of the first capacitor.

4. The array substrate according to claim 2, characterized in that: The array substrate further includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the first type via hole penetrates the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer, or the first type via hole penetrates the fourth insulating layer, the third insulating layer and the second insulating layer; Preferably, the thickness of the third insulating layer is smaller than the thickness of the second insulating layer, and the thickness of the fourth insulating layer is smaller than the thickness of the second insulating layer; Preferably, the sum of the thickness of the third insulating layer and the fourth insulating layer is equal to the thickness of the second insulating layer; Preferably, the orthographic projection of the first connecting line on the substrate is separated from the orthographic projection of the second electrode plate of the second capacitor on the substrate; Preferably, the thickness of the fourth insulating layer is greater than the thickness of the third insulating layer; Preferably, the thickness of the fourth insulating layer is between 500A and 3000A; Preferably, the thickness of the fourth insulating layer is 1000A.

5. The array substrate according to claim 1, characterized in that: The first conductive layer further includes a first scan line extending along a first direction, the first scan line overlaps with the active layer to form the first leakage suppression transistor, and an orthographic projection of the first scan line on the substrate is separated from an orthographic projection of the first connecting line on the substrate; Preferably, the first connection line and the second connection line both extend along a second direction, wherein the first direction intersects the second direction, and an orthographic projection of the first scanning line on the substrate overlaps with an orthographic projection of the second connection line on the substrate; Preferably, the orthographic projection of the first scanning line on the substrate and the orthographic projection of the second connecting line on the substrate are arranged to intersect.

6. The array substrate according to claim 5, characterized in that: The pixel circuit further includes a second leakage suppression transistor, a first compensation transistor and a second compensation transistor, the first conductive layer further includes a second scan line, the orthographic projection of the second scan line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first scan line on the substrate, the first scan line overlaps with the active layer to form the second leakage suppression transistor and the first compensation transistor, the second scan line overlaps with the active layer to form the second compensation transistor, and the first connecting line is connected to the second electrode of the driving transistor through the second leakage suppression transistor, the first compensation transistor and the second compensation transistor in sequence; Preferably, the orthographic projection of the second scanning line on the substrate is arranged to intersect with the orthographic projection of the second connecting line on the substrate; Preferably, the second scan line overlaps the active layer to form a data writing transistor, a first electrode of the data writing transistor is connected to the data line through a first type via hole, and a second electrode of the data writing transistor is connected to the first electrode of the driving transistor through the active layer; Preferably, the data line and the second scanning line are arranged in different layers; Preferably, the data line is located in the fourth conductive layer.

7. The array substrate according to claim 6, characterized in that: The pixel circuit further includes a first initialization transistor and a second initialization transistor, the array substrate further includes a third scan line, a fourth scan line and an initialization signal line, the third scan line overlaps with the active layer to form the first initialization transistor, and the fourth scan line overlaps with the active layer to form the second initialization transistor; The first initialization transistor is connected to the initialization signal line, and is used to transmit the initialization voltage on the initialization signal line to the gate of the driving transistor via the second leakage suppression transistor and the first leakage suppression transistor in sequence; The second initialization transistor is connected between the initialization signal line and the light emitting element, and is used to transmit the initialization voltage to the light emitting element; Preferably, the third scan line and the fourth scan line are arranged in the same layer, and are arranged in a different layer from the initialization signal line; Preferably, the third scan line and the fourth scan line are located in the first conductive layer, and the initialization signal line is located in the second conductive layer; Preferably, the orthographic projection of the third scan line on the substrate is located on a side where the orthographic projection of the first scan line on the substrate is away from the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the fourth scan line on the substrate is located on a side where the orthographic projection of the third scan line on the substrate is away from the orthographic projection of the gate of the driving transistor on the substrate; Preferably, the multi-layer conductive layer further comprises a third connecting line, the initialization signal line is connected to a first end of the third connecting line through a first type via hole, and the first electrode of the first initialization transistor is connected to the other end of the third connecting line through the first type via hole; Preferably, the third connecting line is located in the fourth conductive layer.

8. The array substrate according to claim 7, characterized in that: The pixel circuit further includes a bias transistor, the multi-layer conductive layer further includes a bias voltage signal line, the fourth scan line overlaps with the active layer to form the bias transistor, the bias transistor is connected between the bias voltage signal line and the first electrode or the second electrode of the driving transistor, and is used to transmit the bias voltage on the bias voltage signal line to the first electrode or the second electrode of the driving transistor; Preferably, the multi-layer conductive layer further comprises a fourth connecting line, and the fourth connecting line sequentially connects the bias voltage signal line and the first electrode of the bias transistor through the first type of via hole; Preferably, the orthographic projection of the fourth connecting line on the substrate overlaps with the orthographic projection of the bias voltage signal line on the substrate, and the orthographic projection of the fourth connecting line on the substrate overlaps with the active layer corresponding to the bias transistor; Preferably, the orthographic projection of the first type via on the substrate overlaps with the orthographic projection of the bias voltage signal line on the substrate and the active layer corresponding to the bias transistor; Preferably, the orthographic projection of the bias voltage signal line on the substrate is located between the orthographic projection of the third scanning line on the substrate and the orthographic projection of the fourth scanning line on the substrate; Preferably, the bias voltage signal line is located in the second conductive layer, and the fourth connecting line is located in the fourth conductive layer; Preferably, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, the multi-layer conductive layer further includes a light emission control signal line and a power supply line, the light emission control signal line overlaps the active layer to form the first light emission control transistor and the second light emission control transistor, the first electrode of the first light emission control transistor is connected to the power supply line through the first type of via hole, the second electrode of the first light emission control transistor is connected to the first electrode of the driving transistor through the active layer, the first electrode of the second light emission control transistor is connected to the second electrode of the driving transistor through the active layer, and the second electrode of the second light emission control transistor is connected to the light emitting element through the first type of via hole; Preferably, the orthographic projection of the light emitting control signal line on the substrate is located on a side of the orthographic projection of the gate of the driving transistor on the substrate away from the orthographic projection of the second scanning line on the substrate.

9. The array substrate according to claim 1, characterized in that: The first electrode plate of the second capacitor is connected to one end of the first connection line through a second type via hole, and the first electrode of the first leakage suppression transistor is connected to the other end of the first connection line through a first type via hole; The second electrode of the first leakage suppression transistor is connected to one end of the second connection line through the first type via hole, and the gate of the driving transistor is connected to the other end of the second connection line through the first type via hole; Preferably, the first type via extends from the first connection line and / or the second connection line to the active layer, and the second type via is located between the first connection line and the first plate of the second capacitor; Preferably, the array substrate further comprises a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, and the fourth insulating layer is located between the third conductive layer and the fourth conductive layer; The first type via penetrates the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer, and the second type via penetrates the fourth insulating layer.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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