Photoelectric system packaging structure and preparation method thereof

Abstract

According to the photoelectric system packaging structure and the preparation method thereof provided by the invention, in the packaging process, the first through hole is formed in the back surface of the image sensor chip, and the metal wiring layer and the solder mask layer are sequentially formed in the first through hole and the back surface of the image sensor chip, so that an electric signal of the image sensor chip is led to the back surface from the front surface; in this way, the distance between the image sensor chip and the grating coupling-out surface of the optical chip can be controlled within 10 [mu] m, so that the optical signal of the optical chip can be received in a close-range fit manner; in addition, electric signals of the image sensor chip can be led to the substrate through the metal wiring layer on the back face of the image sensor chip in the formed solder resist window, the signal transmission difficulty between the optical chip and the image sensor chip and between the optical chip and other devices is effectively reduced, in addition, the photoelectric system packaging structure is simple, the manufacturing cost is low, and the photoelectric system packaging structure is suitable for large-scale popularization and application. And the yield and the service life of a finished product of the photoelectric system packaging structure can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and particularly to an optoelectronic system packaging structure and a preparation method thereof. Background Art

[0002] As the core component of optoelectronic conversion, the image sensor chip plays an important role in the fields of machine vision, communication, medical treatment, etc. And the optical chip, as the key component for light source or optical signal processing, the integration with the image sensor chip becomes the key to improving the system performance. However, during the integration process of the image sensor chip and the optical chip, the problem of electrical signal extraction becomes increasingly prominent.

[0003] Currently, the design of image sensor chips on the market generally adopts a layout method with a relatively high degree of integration, that is, the image area and the electrical signal window are set on the same plane. This design is relatively simple in manufacturing and has a relatively low cost, so it has been widely used in many application fields. However, with the continuous progress of technology and the increasing diversification of application requirements, some limitations of this design have gradually emerged. Especially when it is necessary to bond the image sensor chip and the optical chip to receive the optical signal emitted by the optical chip at a short distance, the problem is particularly prominent. Since the image area and the electrical signal window are on the same plane, when the two are closely bonded, the extraction path of the electrical signal will be severely restricted, thus seriously affecting the performance and stability of the image sensor chip.

[0004] Therefore, it is necessary to improve the existing bonding and packaging process of the image sensor chip and the optical chip.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an optoelectronic system packaging structure and a preparation method thereof, which are used to solve the problem that when the image sensor chip and the optical chip are bonded and packaged in the prior art, the extraction path of the electrical signal is severely restricted when receiving the optical signal emitted by the optical chip at a short distance, resulting in the inability to extract the electrical signal.

[0007] To achieve the above purpose and other related purposes, the present invention provides a preparation method for an optoelectronic system packaging structure, and the preparation method includes the following steps:

[0008] Provide an optical chip, and the surface of the optical chip has a grating coupling-in region and a grating coupling-out region;

[0009] Provide a temporary carrier and a second wafer, where the second wafer includes a plurality of image sensor chips, each image sensor chip is provided with an image area and a pad area, and the second wafer and the temporary carrier are bonded through a release layer;

[0010] Perform a first etching process to etch the second wafer to form a first through hole, and the first through hole exposes part of the pad area;

[0011] Form a metal wiring layer and a solder mask layer in the first through hole in sequence. One end of the metal wiring layer is connected to the pad area, the other end of the metal wiring layer covers the back surface of the second wafer, and the solder mask layer completely covers the second wafer and the metal wiring layer;

[0012] Lithograph the solder mask layer to form a solder mask opening window, and the solder mask opening window exposes the metal wiring layer covering the back surface of the second wafer;

[0013] Provide a substrate, bond the optical chip to the substrate, and bond the image sensor chip to the optical chip. Wherein, a first curing glue is filled between the optical chip and the substrate, and a second curing glue is filled between the image sensor chip and the optical chip to realize the connection and fixation of the image sensor chip, the optical chip and the substrate;

[0014] Provide a cover plate, the cover plate is provided with an optical window, and the cover plate covers the substrate to complete the encapsulation of the optical chip and the image sensor chip.

[0015] Optionally, the optical window is arranged opposite to the grating coupling-in area of the optical chip, and the image sensor chip is arranged opposite to the grating coupling-out area of the optical chip.

[0016] Optionally, the second curing glue is an epoxy resin glue that is non-conductive and has high light transmittance.

[0017] Optionally, the image area is located at the center position of the image sensor chip, and the pad area is circumferentially distributed along the edge of the image sensor chip.

[0018] Optionally, before bonding the optical chip to the substrate, it further includes the step of forming a groove in the substrate to accommodate the optical chip and the image sensor chip through the groove. The method of forming the groove includes a laser drilling process.

[0019] Optionally, before bonding the image sensor chip to the optical chip, it further includes steps of cutting the wafer according to a preset scribing groove on the second wafer, cutting the second wafer into individual image sensor chips, and performing a debonding process on the image sensor chips to remove the temporary carrier and the release layer.

[0020] Optionally, a first lead insensitive to material thermal mismatch is provided between the substrate and the metal wiring layer exposed by the solder mask opening, so as to realize electrical connection between the image sensor chip and the substrate by welding.

[0021] Optionally, the substrate includes one of a metal substrate, a glass substrate, a semiconductor substrate, a polymer substrate, or a ceramic substrate that is thermally adapted to the optical chip.

[0022] The present invention also provides an optoelectronic system packaging structure, which includes:

[0023] A substrate, located at the bottom layer of the optoelectronic system packaging structure, for providing mechanical strength support;

[0024] A cover plate, on which a light window is provided, and the cover plate is connected to the substrate and encloses an accommodation space with the groove of the substrate;

[0025] An optical chip, located in the accommodation space and filled with a first curing adhesive between the optical chip and the substrate, and the surface of the optical chip has a grating coupling-in region and a grating coupling-out region;

[0026] An image sensor chip, located above the optical chip and filled with a second curing adhesive between the image sensor chip and the optical chip, the image sensor chip has an image region at the central position and a pad region circumferentially distributed along the edge of the image sensor chip, and a first through hole is formed in the image sensor chip to expose the pad region;

[0027] A metal wiring layer, located in the first through hole and on the back surface of the image sensor chip, to electrically lead out the pad region to the back surface of the image sensor chip;

[0028] A solder mask layer, located on the back surface of the image sensor chip, the solder mask layer has a solder mask opening to expose the metal wiring layer, and a first lead is provided in the solder mask opening, and both ends of the first lead are electrically connected to the metal wiring layer exposed by the solder mask opening and the substrate respectively.

[0029] Optionally, the light window is disposed opposite to the grating coupling-in region of the optical chip, and the image sensor chip is disposed opposite to the grating coupling-out region of the optical chip.

[0030] As described above, the optoelectronic system packaging structure and its manufacturing method of the present invention have the following beneficial effects compared with the prior art: By forming a first through hole on the back surface of the image sensor chip, and forming a metal wiring layer and a solder mask layer on the first through hole and the back surface of the image sensor chip, the electrical signal of the image sensor chip is led from the front surface to the back surface, so that the distance between the image sensor chip and the grating coupling surface of the optical chip can be controlled within 10 μm. Thus, while realizing close proximity to receive the optical signal of the optical chip, the electrical signal of the image sensor chip can also lead the metal wiring layer on the back surface of the image sensor chip to the substrate through the formed solder mask opening window, effectively reducing the signal transmission difficulty between the optical chip, the image sensor chip and other devices. In addition, the optoelectronic system packaging structure is relatively simple, with low manufacturing cost, and can improve the yield and service life of the optoelectronic system packaging structure finished product. Description of the Drawings

[0031] Figure 1 It shows a process flow chart of the manufacturing method of the optoelectronic system packaging structure of the present invention.

[0032] Figure 2 It shows a top view structural schematic diagram of the optical chip provided in the optoelectronic system packaging structure of the present invention.

[0033] Figure 3 It shows a cross-sectional structural schematic diagram of the temporary carrier and the second wafer provided in the optoelectronic system packaging structure of the present invention.

[0034] Figure 4 It shows a cross-sectional structural schematic diagram after grinding the second wafer in the optoelectronic system packaging structure of the present invention.

[0035] Figure 5 It shows a cross-sectional structural schematic diagram after forming the first through hole in the optoelectronic system packaging structure of the present invention.

[0036] Figure 6 It shows a cross-sectional structural schematic diagram after forming the metal wiring layer and the solder mask layer in the optoelectronic system packaging structure of the present invention.

[0037] Figure 7 It shows a cross-sectional structural schematic diagram after forming the solder mask opening window in the optoelectronic system packaging structure of the present invention.

[0038] Figure 8 It shows a top view structural schematic diagram of the image sensor chip formed after cutting the second wafer in the optoelectronic system packaging structure of the present invention.

[0039] Figure 9 It shows a structural schematic diagram after coupling the optical chip and the substrate in the optoelectronic system packaging structure of the present invention.

[0040] Figure 10 It shows a schematic cross-sectional structure diagram after the image sensor chip and the optical chip are coupled in the optoelectronic system packaging structure of the present invention.

[0041] Figure 11 It shows a schematic cross-sectional structure diagram of the optoelectronic system packaging structure formed by the present invention.

[0042] Description of component numbers

[0043] 10. Optical chip; 101. Grating coupling-in area; 102. Grating coupling-out area; 11. Second wafer; 12. Image sensor chip; 121. Image area; 122. Pad area; 13. Temporary carrier; 14. Release layer; 151. First through hole; 152. Solder mask opening; 16. Metal wiring layer; 17. Solder mask layer; 18. Substrate; 181. Accommodation space; 191. First curing adhesive; 192. Second curing adhesive; 20. First lead; 21. Cover plate; 211. Optical window; S1-S7. Steps. Detailed implementation manners

[0044] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0045] It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0046] Please refer to Figures 1 to 11 . It should be noted that the structures, ratios, sizes, etc. shown in the diagrams of this specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the implementation conditions of the present invention. Therefore, they do not have technical essence. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle", "first", "second", etc. cited in this specification are only for the convenience of clear narration, rather than used to limit the implementation scope of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope where the present invention can be implemented.

[0047] Embodiment 1

[0048] This embodiment provides a preparation method for an optoelectronic system packaging structure, asFigure 1 As shown, it shows the process flow chart of the preparation method, including the following steps:

[0049] S1: Provide an optical chip 10, and the surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102;

[0050] S2: Provide a temporary carrier 13 and a second wafer 11. The second wafer 11 includes a plurality of image sensor chips 12. Each image sensor chip 12 is provided with an image region 121 and a pad region 122, and the second wafer 11 is bonded to the temporary carrier 13 through a release layer 14;

[0051] S3: Perform a first etching process to etch the second wafer 11 to form a first through hole 151, and the first through hole 151 exposes a part of the pad region 122;

[0052] S4: Sequentially form a metal wiring layer 16 and a solder mask layer 17 in the first through hole 151. One end of the metal wiring layer 16 is connected to the pad region 122, the other end of the metal wiring layer 16 covers the back surface of the second wafer 11, and the solder mask layer 17 completely covers the second wafer 11 and the metal wiring layer 16;

[0053] S5: Lithograph the solder mask layer 17 to form a solder mask opening 152. The solder mask opening 152 exposes the metal wiring layer 16 covering the back surface of the second wafer 11;

[0054] S6: Provide a substrate 18, bond the optical chip 10 to the substrate 18, and bond the image sensor chip 12 to the optical chip 10. Among them, a first curing adhesive 191 is filled between the optical chip 10 and the substrate 18, and a second curing adhesive 192 is filled between the image sensor chip 12 and the optical chip 10 to realize the connection and fixation of the image sensor chip 12, the optical chip 10 and the substrate 18;

[0055] S7: Provide a cover plate 21. The cover plate 21 is provided with an optical window 211, and the cover plate 21 covers the substrate 18 to complete the encapsulation of the optical chip 10 and the image sensor chip 12.

[0056] The following further introduces the preparation method of the optoelectronic system packaging structure in conjunction with the accompanying drawings, specifically as follows:

[0057] In step S1, please refer to Figure 1 and Figure 2 , provide an optical chip 10, and the surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102.

[0058] In this embodiment, a first semiconductor wafer is provided. The first semiconductor wafer includes a plurality of optical chip 10 regions. The first semiconductor wafer is cut along the scribing groove region on the first semiconductor wafer, so as to separate the plurality of optical chip 10 regions to form a plurality of individual optical chips 10. In the above process, the individual separation of the optical chips 10 is realized, and it can be ensured that the optical chips 10 will not be contaminated by the pollutants generated during the cutting process, and the integrity and reliability of the circuit functions of the optical chips 10 can also be ensured.

[0059] Specifically, as Figure 2 shown, it is a top view structural schematic diagram of the optical chip 10 in this embodiment. The surface of the optical chip 10 has a grating coupling-in region 101 and a grating coupling-out region 102. The grating coupling-in region 101 is used to couple light into the optical chip 10, and the grating coupling-out region 102 is used to couple the image light conducted in the optical chip 10 out to the image sensor chip 12. An optical waveguide formed by optical wire bonding technology is arranged between the grating coupling-in region 101 and the grating coupling-out region 102, so that the signal transmission path between the adjacent grating coupling-in region 101 and the grating coupling-out region 102 is no longer metal, but an optical waveguide. Optionally, the shape of the optical waveguide can be linear, arc-shaped or other shapes.

[0060] In step S2, please refer to Figure 1 and Figure 3 , a temporary carrier 13 and a second wafer 11 are provided. The second wafer 11 includes a plurality of image sensor chips 12. Each image sensor chip 12 is provided with an image region 121 and a pad region 122, and the second wafer 11 is bonded to the temporary carrier 13 through a release layer 14.

[0061] Optionally, the temporary carrier 13 includes one of non-metallic materials such as a silicon oxide carrier, a glass carrier, a ceramic carrier, a polymer carrier, etc. Its shape can be circular, square or any other desired shape, which is not particularly limited here and is specifically selected according to needs.

[0062] Specifically, in this embodiment, a release layer 14 is coated on the temporary carrier 13. The release layer 14 has the characteristic of being able to adhere to other components and solidify after high-temperature heating, so as to realize the fixation of the second wafer 11.

[0063] Specifically, in this embodiment, the temporary carrier 13 selects a glass carrier with a low coefficient of thermal expansion. On the one hand, the glass carrier substrate 18 has a low coefficient of thermal expansion, which can reduce the warping generated during the cutting of the second wafer 11. On the other hand, the glass carrier has a low cost, and it is easy to form a release layer 14 on its surface and reduce the difficulty of the subsequent removal process.

[0064] Optionally, the release layer 14 may include a polymer layer or a tape adhesion layer.

[0065] Specifically, the material of the release layer 14 may be selected from tapes with adhesiveness on both sides (such as chip attachment films or non-conductive films, etc.) or adhesives made by spin coating processes; preferably, in this embodiment, the release layer 14 is preferably a UV glue, which has the characteristic of being easily denatured and peeled off after being irradiated by UV light (ultraviolet light); of course, in other examples, the release layer 14 may also be other material layers formed by physical vapor deposition or chemical vapor deposition methods, such as epoxy resin, silicone rubber, polyimide, etc. When separating the temporary carrier 13 later, methods such as wet etching and chemical mechanical polishing can be used to remove the release layer 14.

[0066] In this embodiment, a second wafer 11 is provided. The second wafer 11 includes a plurality of image sensor chips 12, and each image sensor chip 12 is provided with an image area 121 and a pad area 122. Specifically, as Figure 3 shown, after bonding the second wafer 11 and the temporary carrier 13 through the release layer 14, the back surface of the second wafer 11 is exposed.

[0067] In step S3, please refer to Figure 1 , Figure 4 and Figure 5 , perform a first etching process to etch the second wafer 11 to form a first through hole 151, and the first through hole 151 exposes part of the pad area 122.

[0068] As an example, as Figure 4 shown, after bonding the second wafer 11 and the temporary carrier 13, there is also a step of grinding and planarizing the second wafer 11, so that the second wafer 11 maintains an appropriate thickness, which is beneficial to reducing the volume of the subsequent formed optoelectronic system packaging structure and improving the packaging quality of the optoelectronic system packaging structure.

[0069] Specifically, in this embodiment, as Figure 5 shown, perform a first etching process to form a photoresist masking layer on the back surface of the second wafer 11, expose and develop the photoresist masking layer to form a patterned photoresist masking layer. Etch the second wafer 11 based on the patterned photoresist masking layer to form a first through hole 151 on the back surface of the second wafer 11, and the first through hole 151 exposes the pad area 122 in the image sensor chip 12. Then remove the photoresist masking layer. The composition, flow rate, and process conditions of the etching gas used in the first etching process are all well-known in the art, and those skilled in the art can select and adjust them according to actual needs, and will not be further described in detail here.

[0070] In step S4, refer to Figure 1 and Figure 6 , a metal wiring layer 16 and a solder mask layer 17 are sequentially formed in the first through hole 151. One end of the metal wiring layer 16 is connected to the pad region 122, and the other end of the metal wiring layer 16 covers the back surface of the second wafer 11. The solder mask layer 17 completely covers the second wafer 11 and the metal wiring layer 16.

[0071] As Figure 6 shown, a metal is deposited in the first through hole 151 by physical vapor deposition to form the metal wiring layer 16, and the metal wiring layer 16 extends to the back surface of the second wafer 11, so as to lead the electrical signal of the image sensor chip 12 from the front side to the back side. Optionally, the material of the metal wiring layer 16 is one or a combination of copper, aluminum, nickel, gold, silver, and titanium. Specifically, in this embodiment, the material of the metal wiring layer 16 is preferably copper because copper not only has good electrical conductivity but also has very good ductility. Setting copper between the pad region 122 and the solder mask layer 17 helps to improve the electrical conduction performance of the optoelectronic system packaging structure. After the metal wiring layer 16 is formed, chemical mechanical polishing is used for planarization to make the top surface of the metal wiring layer 16 flat, and the metal wiring layer 16 forms good contact with the pad region 122 on the front surface of the second wafer 11 to achieve better electrical connection.

[0072] Optionally, the process for forming the solder mask layer 17 includes one of a liquid sealant curing process, a vacuum lamination process, and a spin coating process. The solder mask layer 17 includes one of an epoxy resin layer, a polyimide layer, and a silica gel layer. The solder mask layer 17 completely covers the back surface of the second wafer 11 and the metal wiring layer 16. After the solder mask layer 17 is formed, a planarization process for the solder mask layer 17 is also included. The planarization process can make the optoelectronic system packaging structure maintain an appropriate thickness, further reduce the volume of the packaging structure, and improve the packaging quality.

[0073] Specifically, in this embodiment, the process for forming the solder mask layer 17 is as follows: After screen printing the solder mask ink on the surface of the image sensor chip 12, it is sequentially subjected to pre-curing, exposure, development, and thermal curing treatments to cure the solder mask ink into the solder mask layer 17. Further, a windowing process is performed on the solder mask layer 17 to expose the pad region 122 on the image sensor chip 12. The solder mask layer 17 can provide a permanent electrical environment and a chemical corrosion-resistant protective layer for the image sensor chip 12, and at the same time play a role in beautifying the appearance.

[0074] In step S5, refer to Figure 1 and Figure 7, lithographically pattern the solder mask layer 17 to form a solder mask opening 152, which exposes the metal wiring layer 16 covering the back surface of the second wafer 11.

[0075] In this embodiment, as Figure 7 shown, lithographically pattern the solder mask layer 17 to form a solder mask opening. Specifically, form a photoresist mask layer on the solder mask layer 17, expose and develop the photoresist mask layer to form a patterned photoresist mask layer. Etch the solder mask layer 17 based on the patterned photoresist mask layer to form a solder mask opening 152 in the solder mask layer 17, which exposes the metal wiring layer 16 on the back surface of the second wafer 11. Then remove the photoresist mask layer. The process conditions for lithographically patterning the solder mask layer 17 are well known in the art and those skilled in the art can adjust them according to actual needs, and will not be further elaborated here.

[0076] In step S6, please refer to Figure 1 , Figure 9 and Figure 10 , provide a substrate 18, bond the optical chip 10 to the substrate 18, and bond the image sensor chip 12 to the optical chip 10. Among them, a first curing adhesive 191 is filled between the optical chip 10 and the substrate 18, and a second curing adhesive 192 is filled between the image sensor chip 12 and the optical chip 10 to realize the connection and fixation of the image sensor chip 12, the optical chip 10 and the substrate 18.

[0077] As an example, before bonding the image sensor chip 12 to the optical chip 10, it further includes steps of cutting the wafer along the preset scribe grooves on the second wafer 11, cutting the second wafer 11 into individual image sensor chips 12 and performing a debonding process on the image sensor chips 12 to remove the temporary carrier 13 and the release layer 14.

[0078] Specifically, the second wafer 11 contains several image sensor chips 12. Cut the second wafer 11 along the preset scribe groove area on the second wafer 11 to separate the several image sensor chips 12 to form several individual image sensor chips 12. This not only realizes the separate separation of the image sensor chips 12, but also ensures the integrity and reliability of the circuit functions of the image sensor chips 12.

[0079] Optionally, use a grinding process, a thinning process or a tearing process to remove the temporary carrier 13 and the release layer 14. Preferably, in this embodiment, use a thinning process to remove the temporary carrier 13 and the release layer 14, as Figure 8As shown in the figure, it is a top view structural schematic diagram of the image sensor chip 12. The surface of the image sensor chip 12 has an image area 121 and a pad area 122. The image area 121 is located at the center position of the image sensor chip 12, and the pad area 122 is circumferentially distributed along the edge of the image sensor chip 12. After packaging, the image area 121 is disposed opposite to the grating coupling output area 102, so that the image sensor chip 12 can receive the image light that is received from the grating coupling input area 101 and conducted to the grating coupling output area 102.

[0080] As an example, the substrate 18 includes a metal substrate, a glass substrate, a semiconductor substrate, a polymer substrate or a ceramic substrate that is thermally adapted to the optical chip 10. The present invention does not make special limitations on its material, properties or internal structure. Preferably, as Figure 9 shown, in this embodiment, the substrate 18 is selected as a ceramic substrate that is thermally adapted to the optical chip 10. Among them, before bonding the optical chip 10 to the substrate 18, a receiving space 181 needs to be formed at the corresponding contact position of the substrate 18. The height of this receiving space 181 is greater than the sum of the heights of the optical chip 10 and the image sensor chip 12. The receiving space 181 can protect the packaging structure, prevent the packaging structure from being affected by the external environment during use, prevent the packaging structure from being damaged, and improve the service life of the packaging structure.

[0081] Specifically, before bonding the optical chip 10 to the substrate 18, it further includes the step of forming a groove in the substrate 18 to accommodate the optical chip 10 and the image sensor chip 12 through the groove. Among them, the method of forming the groove includes a laser drilling process. The laser grooving process has good precision and high controllability, and can accurately form the groove without affecting other structures.

[0082] As Figure 9 shown, during the bonding process of the optical chip 10 and the substrate 18, a first gap will be formed between the optical chip 10 and the substrate 18. In order to improve the strength of the packaging structure, it is necessary to fill the first gap with a first curing glue 191, and perform high-temperature curing heating on the first curing glue 191. The technical principle of high-temperature curing heating is to heat the first curing glue 191 with high-temperature hot air, so that the first curing glue 191 in the first gap is fused under the action of the high-temperature hot air, so as to form a larger contact area to realize the connection and fixation between the optical chip 10 and the substrate 18.

[0083] As Figure 10As shown, during the bonding process of the image sensor chip 12 and the optical chip 10, a second gap will be formed between the image sensor chip 12 and the optical chip 10. In order to improve the strength of the packaging structure, it is necessary to fill the second gap with a second curing adhesive 192 and perform high-temperature curing heating on the second curing adhesive 192, so that the second curing adhesive 192 in the second gap is fused under the action of high-temperature hot air, thereby forming a larger contact area to achieve the connection and fixation between the image sensor chip 12 and the optical chip 10. Preferably, the second curing adhesive 192 is an epoxy resin glue that is non-conductive and has high light transmittance, so as to further improve the effect of the grating coupler region 102 coupling the image light conducted in the optical chip 10 to the image sensor chip 12.

[0084] As an example, a first lead 20 that is insensitive to material thermal mismatch is provided between the substrate 18 and the metal wiring layer 16 in the solder mask opening 152 to achieve electrical connection between the image sensor chip 12 and the substrate 18 by soldering.

[0085] Specifically, as Figure 10 shown, in order to lead out the electrical signal of the image sensor chip 12 to external devices, it is necessary to set a first lead 20 between the substrate 18 and the metal wiring layer 16 in the solder mask opening 152. Among them, the first lead 20 is made of a material that is insensitive to material thermal mismatch. Then, one end of the first lead 20 is soldered to the metal wiring layer 16 in the solder mask opening 152, and the other end of the first lead 20 is soldered to the substrate 18 to achieve electrical connection between the image sensor chip 12 and the substrate 18. On the one hand, the wire bonding technology is mature, which can save packaging costs. On the other hand, it can also avoid packaging problems caused by material thermal mismatch of the packaging structure.

[0086] In step S7, please refer to Figure 1 and Figure 11 , provide a cover plate 21, and the cover plate 21 covers the substrate 18 to complete the packaging of the optical chip 10 and the image sensor chip 12.

[0087] Specifically, as Figure 11 shown, a light window 211 is provided on the cover plate 21, and the light window 211 is disposed opposite to the grating coupling region 101, so that light is coupled into the grating coupling region 101 of the optical chip 10 through the light window 211. After the optical chip 10, the image sensor chip 12 and the substrate 18 are bonded, the cover plate 21 is fixed on the substrate 18 to complete the optoelectronic system packaging of the optical chip 10 and the image sensor chip 12.

[0088] In the preparation method of an optoelectronic system packaging structure according to this embodiment, a first through hole 151 is formed on the back surface of the image sensor chip 12, and a metal wiring layer 16 and a solder mask layer 17 are formed on the first through hole 151 and the back surface of the image sensor chip 12, so as to lead the electrical signal of the image sensor chip 12 from the front surface to the back surface. In this way, the distance between the image sensor chip 12 and the grating coupling surface of the optical chip 10 can be controlled within 10 μm. Thus, while realizing close contact to receive the optical signal of the optical chip 10, the electrical signal of the image sensor chip 12 can also lead the metal wiring layer 16 on the back surface of the image sensor chip 12 to the substrate 18 through the formed solder mask opening 152, effectively reducing the signal transmission difficulty between the optical chip 10, the image sensor chip 12 and other devices.

[0089] Embodiment Two

[0090] This embodiment provides an optoelectronic system packaging structure, as Figure 11 shown, which is a schematic cross-sectional structure diagram of the optoelectronic system packaging structure. The optoelectronic system packaging structure includes: a substrate 18, located at the bottom layer of the optoelectronic system packaging structure, for providing mechanical strength support; a cover plate 21, with a light window 211 provided on the cover plate 21. The cover plate 21 is connected to the substrate 18 and encloses a receiving space with the groove of the substrate 18; an optical chip 10, located in the receiving space and filled with a first curing adhesive 191 between the optical chip 10 and the substrate 18. The surface of the optical chip 10 has a grating coupling-in area 101 and a grating coupling-out area 102; an image sensor chip 12, located above the optical chip 10 and filled with a second curing adhesive 192 between the image sensor chip 12 and the optical chip 10. The image sensor chip 12 has an image area 121 at the central position and a pad area 122 distributed circumferentially along the edge of the image sensor chip 12. A first through hole 151 is formed in the image sensor chip 12 to expose the pad area 122; a metal wiring layer 16, located in the first through hole 151 and on the back surface of the image sensor chip 12, to electrically lead out the pad area 122 to the back surface of the image sensor chip 12; a solder mask layer 17, located on the back surface of the image sensor chip 12. The solder mask layer 17 has a solder mask opening 152 to expose the metal wiring layer 16, and a first lead 20 is provided in the solder mask opening 152. Two ends of the first lead 20 form electrical connections with the metal wiring layer 16 exposed by the solder mask opening 152 and the substrate 18 respectively.

[0091] Preferably, the optical window 211 is disposed opposite to the grating coupling region 101 of the optical chip 10, and the image sensor chip 12 is disposed opposite to the grating coupling-out region 102 of the optical chip 10, so that the image sensor chip 12 can receive the image light that is received by the grating coupling region 101 and conducted to the grating coupling-out region 102.

[0092] As an example, in order to lead out the electrical signals of the image sensor chip 12 to external devices, a first lead 20 needs to be provided between the substrate 18 and the metal wiring layer 16 in the solder mask opening 152. Among them, the first lead 20 is made of a material that is insensitive to thermal mismatch. Then, one end of the first lead 20 is soldered to the metal wiring layer 16 in the solder mask opening 152, and the other end of the first lead 20 is soldered to the substrate 18 to realize the electrical connection between the image sensor chip 12 and the substrate 18, avoiding the problem of thermal mismatch in the packaging structure.

[0093] In summary, the optoelectronic system packaging structure and its preparation method of the present invention, compared with the prior art, form a first through hole on the back surface of the image sensor chip, and form a metal wiring layer and a solder mask layer on the first through hole and the back surface of the image sensor chip, so as to lead the electrical signals of the image sensor chip from the front surface to the back surface. In this way, the distance between the image sensor chip and the grating coupling surface of the optical chip can be controlled within 10 μm. Thus, while realizing close contact to receive the optical signal of the optical chip, the electrical signals of the image sensor chip can also lead the metal wiring layer on the back surface of the image sensor chip to the substrate through the formed solder mask opening, effectively reducing the signal transmission difficulty between the optical chip, the image sensor chip and other devices. In addition, the optoelectronic system packaging structure is relatively simple, with low preparation cost, and can improve the yield and service life of the optoelectronic system packaging structure. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing an optoelectronic system packaging structure, characterized in that: The preparation method comprises the following steps: Providing an optical chip, wherein a surface of the optical chip has a grating in-coupling region and a grating out-coupling region; Providing a temporary carrier and a second wafer, wherein the second wafer comprises a plurality of image sensor chips, each of the image sensor chips is provided with an image area and a pad area, and the second wafer is bonded to the temporary carrier via a release layer; Performing a first etching process to etch the second wafer to form a first through hole, wherein the first through hole exposes a portion of the pad area; A metal wiring layer and a solder resist layer are sequentially formed in the first through hole, one end of the metal wiring layer is connected to the pad area, the other end of the metal wiring layer covers the back side of the second wafer, and the solder resist layer completely covers the second wafer and the metal wiring layer; Photolithography the solder resist layer to form solder resist openings, wherein the solder resist openings reveal the metal wiring layer covering the back side of the second wafer; Providing a substrate, bonding the optical chip to the substrate, and bonding the image sensor chip to the optical chip, wherein a first curing glue is filled between the optical chip and the substrate, and a second curing glue is filled between the image sensor chip and the optical chip, so as to achieve connection and fixation of the image sensor chip, the optical chip and the substrate; A cover plate is provided, on which a light window is arranged, and the cover plate covers the substrate to complete the packaging of the optical chip and the image sensor chip.

2. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The optical window is arranged opposite to the grating coupling-in region of the optical chip, and the image sensor chip is arranged opposite to the grating coupling-out region of the optical chip.

3. The method for preparing the optoelectronic system packaging structure according to claim 2, characterized in that: The second curing glue is an epoxy resin glue that is non-conductive and has high light transmittance.

4. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The image area is located at the center of the image sensor chip, and the pad area is distributed along the circumference of the edge of the image sensor chip.

5. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: Before bonding the optical chip to the substrate, a step of forming a groove in the substrate is also included to accommodate the optical chip and the image sensor chip through the groove, wherein the method of forming the groove includes a laser drilling process.

6. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The method also includes the steps of cutting the wafer according to the preset scribe lines on the second wafer, cutting the second wafer into individual image sensor chips, performing a debonding process on the image sensor chips, and removing the temporary carrier and the release layer.

7. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: A first lead insensitive to material thermal mismatch is provided between the substrate and the metal wiring layer exposed by the solder resist opening, so as to realize electrical connection between the image sensor chip and the substrate by welding.

8. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The substrate includes one of a metal substrate, a glass substrate, a semiconductor substrate, a polymer substrate or a ceramic substrate thermally matched with the optical chip.

9. An optoelectronic system packaging structure, characterized in that: The optoelectronic system packaging structure comprises: The substrate is located at the bottom layer of the optoelectronic system packaging structure and is used to provide mechanical strength support; A cover plate, wherein a light window is provided on the cover plate, the cover plate is connected to the base plate and encloses a receiving space with the groove of the base plate; An optical chip, wherein the optical chip is located in the accommodation space and a first curing adhesive is filled between the optical chip and the substrate, and a surface of the optical chip has a grating coupling-in region and a grating coupling-out region; An image sensor chip, wherein the image sensor chip is located above the optical chip and a second curing adhesive is filled between the image sensor chip and the optical chip, the image sensor chip having an image area located at a central position and a pad area distributed circumferentially along an edge of the image sensor chip, and a first through hole is formed in the image sensor chip to expose the pad area; A metal wiring layer, the metal wiring layer is located in the first through hole and on the back side of the image sensor chip to electrically lead the pad area to the back side of the image sensor chip; A solder resist layer, wherein the solder resist layer is located on the back side of the image sensor chip, the solder resist layer has a solder resist window to expose the metal wiring layer, and a first lead is arranged in the solder resist window, and two ends of the first lead are respectively electrically connected to the metal wiring layer exposed by the solder resist window and the substrate.

10. The optoelectronic system packaging structure according to claim 9, characterized in that: The optical window is arranged opposite to the grating coupling-in region of the optical chip, and the image sensor chip is arranged opposite to the grating coupling-out region of the optical chip.

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