Reduced gate drive for power converters with dynamic switching ratio

Abstract

Circuits and methods for a selectable conversion ratio power converter including a low dropout (EDO) power supply adapted to select a voltage input based on a selected conversion ratio while achieving high efficiency. The EDO power supply limits current through the power FETs of the power converter, thereby mitigating or eliminating potential destructive events. In some embodiments, the first all-gate driven LDO and the second all-gate driven LDO have a "line or" output, which may power a target circuit, such as a pre-driver (and optionally a level shifter) coupled to the gate of the power FET. In some embodiments, the first reduced gate-driven LDO and the second reduced gate-driven LDO have "line OR" outputs, which may power a final driver coupled to the gate of the power FET. Some embodiments have a dual all gate driven LDO that powers a target circuit, such as a pre-driver (and optionally a level shifter), while a dual reduced gate driven LDO that powers a final driver coupled to the gate of the power FET.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Non - Provisional Application No. 17 / 960,712, filed on October 5, 2022, the content of which is incorporated herein by reference in its entirety. The present invention may also relate to U.S. Patent Application Serial No. 17 / 331,594, filed on May 26, 2021, published as U.S. 2022 / 0385178 and entitled "Dynamic Division Ratio Charge Pump Switching", which is assigned to the assignee of the present invention and the content of which is incorporated by reference. Technical Field

[0003] The present invention relates to electronic circuits, and more particularly to power converter circuits including DC - DC converter circuits and current - limiting circuits for such converter circuits. Background Art

[0004] Many electronic products, especially mobile computing and / or communication products and components (e.g., laptop computers, ultra - book computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a radio - frequency (RF) transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuitry may require a low voltage level (e.g., 1V to 2V). There are other circuitry systems that may require intermediate voltage levels (e.g., 5V to 10V).

[0005] Power converters are commonly used to generate lower or higher voltages from a common power source such as a battery. One type of power converter includes a converter circuit (e.g., a charge pump based on a switched - capacitor network), control circuitry, and in some embodiments auxiliary circuitry such as a bias voltage generator, a clock generator, a voltage regulator, a voltage control circuit, etc. As used in this disclosure, the term "charge pump" refers to a switched - capacitor network configured to boost or buck V IN to V OUT Examples of such charge pumps include cascaded multiplier switched - capacitor networks, Dickson switched - capacitor networks, Ladder switched - capacitor networks, series - parallel switched - capacitor networks, Fibonacci switched - capacitor networks, and Doubler switched - capacitor networks, all of which can be configured as multi - phase or single - phase networks. Switched - capacitor network DC - DC converters are typically integrated circuits (ICs) that may have some external components (e.g., capacitors) and are in most cases characterized by having a fixed V IN to V OUTConversion ratio (e.g., 2-divider or 3-divider). As is known in the art, an AC-DC power converter can be constructed from a DC-DC power converter by, for example: first, rectifying the AC input into a DC voltage; and then applying the DC voltage to the DC-DC power converter.

[0006] To provide greater flexibility to system designers and to handle applications where the power supply may need to vary with different conversion ratios (e.g., when the battery discharges and outputs a lower voltage, or when the power supply of the device switches between a battery and an AC-DC power line source), it is useful to utilize a DC-DC power converter with a selectable conversion ratio. For example, U.S. Patent No. 10,263,514B1, entitled "Selectable Conversion Ratio DC-DC Converter," published on April 16, 2019, assigned to the assignee of the present invention and incorporated herein by reference, describes a Dickson DC-DC power converter that can switch between a 2-divider (DIV2) operation mode and a 3-divider (DIV3) operation mode. As another example, U.S. Patent No. 9,203,299B2, entitled "Controller-Driven Reconfiguration of Switched-Capacitor Power Converter," published on December 1, 2015, now assigned to the assignee of the present invention and incorporated herein by reference, describes other DC-DC power converter architectures with reconfigurable conversion ratios.

[0007] A common problem with many FET-based DC-DC power converter architectures is the need to avoid excessive inrush current during startup of the power converter. For example, for a selectable conversion ratio DC-DC converter of the type shown in U.S. Patent No. 10,263,514B1, there is a lack of sufficient protection circuitry such that when the input voltage V IN is first applied, none of the capacitors (sometimes referred to as "flying capacitors") are initially charged, and thus current rushes into the circuit. For example, if the on-resistance R ON of the FET power switch is 1 milliohm (0.001 ohm), and V INIf it is 10V, then due to Ohm's law V = I×R, the inrush current will be a spike of approximately 10,000 amperes. In an integrated circuit implementation, there are parasitic inductances (e.g., due to conductor wiring on the die and printed circuit board conductor wiring), and these parasitic inductances transform the current spike into a voltage spike according to the following inductor theory: V = L×dI / dt. Such a voltage spike subjects the charge pump power switch to excessive electrical stress, thereby affecting its reliability and possibly causing damage. For a 1ns 100A pulse that generates 10V across the charge pump power switch, the parasitic inductance only needs to be approximately 100pH. The resulting 10V spike may exceed the breakdown voltage of many FET switches in the FET switch, and of course, for the same parasitic inductance, a larger current spike results in a larger voltage spike.

[0008] Related problems occur when the flying capacitors of a DC-DC power converter are unbalanced, which means there is a charge difference between the flying capacitors connected through the power switch. If charge balance is not maintained, current spikes and resulting destructive voltage spikes will occur.

[0009] Another design challenge is to achieve high efficiency, which is particularly important for devices with limited battery space (e.g., cellular phones, "smart" watches, and fitness wearable devices).

[0010] Therefore, it would be useful to be able to mitigate or eliminate events in a power converter that can be characterized as "potentially destructive events" (e.g., destructive current spikes that may occur for various reasons, including inrush current, charge transfer current, short circuits, EMI events, etc.) while achieving high efficiency. Summary of the Invention

[0011] The present invention provides a circuit and method for a selectable conversion ratio power converter that includes a low dropout (LDO) power supply adapted to select a voltage input based on a selected conversion ratio while achieving high efficiency. The LDO power supply limits the current through the power FET of the power converter, thereby mitigating or eliminating potentially destructive events. Such a circuit and method provide protection against potentially destructive events, such as current spikes during "soft start" and during dynamic charge balance of the power converter, without the need for added circuitry for these functions.

[0012] The present invention recognizes that the gate voltage to all non-top-level power switches of a power converter is based on V INOr similar voltage levels are inefficient because these supply voltages are higher than the voltages required to switch the power FETs at lower levels. Thus, one aspect of the present invention is to utilize an internal voltage node of the power converter itself to efficiently power the gates of the power switches at lower levels. A complication of using such an internal voltage node is that the voltage division ratio of the power converter can be switched dynamically, due to changes in the switching phases of some of the power FETs (e.g., power switch S2), which affects the voltages available at some of the internal voltage nodes being utilized. Additionally, during the transition between DIV2 and DIV3 operations, an incorrect LDO configuration can cause a cascading effect that can damage the power converter. Thus, another aspect of the present invention is an adaptive circuit architecture that functionally allows for dynamic switching between different voltage supply sources for an LDO used to power an associated level shifter and pre-driver and an LDO used to power an associated final driver.

[0013] In one embodiment, the present invention includes a dual low-dropout circuit configuration that includes: a first low-dropout circuit including an FET circuit configured to be coupled between a first voltage source and a target circuit, the first low-dropout circuit being configured to selectively apply a first voltage to a voltage input node of the target circuit; and a second low-dropout circuit including an FET circuit configured to be coupled between a second voltage source and the target circuit, the second low-dropout circuit being configured to selectively apply a second voltage to the voltage input node of the target circuit.

[0014] In some embodiments, the first low-dropout circuit and the second low-dropout circuit are full-gate drive LDOs with an "ORed" output that can, for example, supply power to a target circuit, such as a pre-driver (and optionally a level shifter) coupled to the gate of a power FET. In some embodiments, the first low-dropout circuit and the second low-dropout circuit are reduced-gate drive LDOs with an "ORed" output that can, for example, supply power to a final driver coupled to the gate of a power FET. In some embodiments, a dual full-gate drive LDO with an "ORed" output supplies power to a target circuit, such as a pre-driver (and optionally a level shifter) coupled to the gate of a power FET, while a dual reduced-gate drive LDO with an "ORed" output supplies power to a final driver coupled to the gate of a power FET.

[0015] Details of one or more embodiments of the present invention are set forth in the following drawings and description. Other features, objects, and advantages of the present invention will be apparent from the description and drawings and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram of one embodiment of a DC-DC selectable conversion ratio power converter.

[0017] Figure 2 It is a block diagram of a part of a power converter, which shows details of the FET implementation of the power switch for this part.

[0018] Figure 3A is Figure 2 a schematic diagram of an implementation of the level shifter / driver block and the LDO block of

[0019] Figure 3B It is a block diagram showing details of an implementation of the switch control block 316.

[0020] Figure 4 It is a schematic block diagram of an implementation of a charge pump.

[0021] Figure 5A It is a block diagram of an implementation of a "source-switching" LDO, which is configured to supply regulated power to a level shifter / pre-driver (comparable to the level shifter and pre-driver of Figure 3A and a final driver (comparable to the final driver of Figure 3A ).

[0022] Figure 5B is Figure 5A a block diagram of the dual full-gate drive LDO section of

[0023] Figure 5C is Figure 5A a block diagram of the dual reduced-gate drive LDO section of

[0024] Figure 5D is Figure 5A a block diagram of an alternative implementation of the dual reduced-gate drive LDO section of

[0025] Figure 6 a schematic diagram of the dual full-gate drive LDO section in the DIV2 configuration of the power switch S2.

[0026] Figure 7A a schematic diagram of the dual reduced-gate drive LDO section when the LDO transitions from DIV3 to DIV2 mode.

[0027] Figure 7B a set of graphs showing the current and voltage of the dual reduced-gate drive LDO varying with time, which depicts the problem of turn-on time overlap.

[0028] Figure 7C is including Figure 7A the fast-discharge switch M FD a set of graphs showing the current and voltage of the dual reduced-gate drive LDO varying with time.

[0029] Figure 8 is a top plan view of a substrate that can be, for example, a printed circuit board or a substrate of a chip module (e.g., a thin film block).

[0030] Figure 9 is a process flow diagram showing a method of supplying power to a voltage input node of a target circuit.

[0031] Figure 10 is a process flow diagram showing a method of supplying power to a voltage input node of a driver circuit for a power FET having a gate and the gate of the power FET.

[0032] Like reference numerals and names in the various figures indicate like elements. DETAILED DESCRIPTION

[0033] The present invention provides a circuit and method for a selectable conversion ratio power converter that includes a low dropout (LDO) power supply adapted to select a voltage input based on a selected conversion ratio while achieving high efficiency. The LDO power supply limits the current through a power FET of the power converter, thereby mitigating or eliminating potentially destructive events. Such a circuit and method provide protection against potentially destructive events, such as current spikes during "soft start" of the power converter and during dynamic charge balancing, without the need for added circuitry for these functions.

[0034] EXAMPLE SELECTABLE CONVERSION RATIO POWER CONVERTER

[0035] Figure 1 is a block diagram of one embodiment of a DC-DC selectable conversion ratio power converter 100. The specifically shown power converter 100 can be selectively configured as a 2-voltage divider (DIV2) Dickson converter or a 3-voltage divider (DIV3) Dickson converter using the same basic circuitry. By inverting the voltage input and voltage output, the same power converter 100 can generally be used for DC-to-DC boost conversion, possibly with some relatively minor design variations. The shown power converter 100 includes two parallel sections 102a, 102b coupled between a voltage source V IN and a reference potential 104 such as circuit ground. Each section 102a, 102b includes three serially connected switches S1 to S3 that are serially coupled to a first branch including two serially connected switches S4 to S5 and serially coupled to a second branch including two serially connected switches S6 to S7. Each switch can include, for example, one or more FETs, and the one or more FETs include one or more MOSFETs.

[0036] In each of the sections 102a, 102b, first capacitors C1a, C1b are coupled between a first upper switch pair S1, S2 and a first branch switch pair S4, S5, and second capacitors C2a, C2b are coupled between a second upper switch pair S2, S3 and a second branch switch pair S6, S7. The first capacitors C1a, C1b have a voltage of V C1a / 2 across their terminals at corresponding nodes V C1b and V IN when charged. The second capacitors C2a, C2b have a voltage of V C2a / 2 (DIV / 2) or V C2b / 3 (DIV / 3) across their terminals at corresponding nodes V IN when charged. Depending on the output ratio configuration (2 - voltage division or 3 - voltage division), each of the sections 102a, 102b can generate an output voltage at a node V IN coupled to an output capacitor C OUT . X

[0037] At least some of the switches S1 to S7 can be selectively controlled by a control circuitry (not shown) to be in an on (conducting) or off (blocking) state. At least some of the switches S1 to S7 can be selectively coupled to one of two non - overlapping complementary clock phases, P1 or P2. Some of the switches S1 to S7 can be permanently coupled to one of two complementary clock phases, P1 or P2. Table 1 below shows the configuration of the state or associated clock phase of each of the switches S1 to S7 for two parallel sections 102a, 102b for both 2 - voltage division and 3 - voltage division configurations.

[0038]

[0039] Table 1

[0040] Note that the clock phase associations for section 102b are complementary to those for section 102a. The complementary phasing of the two parallel sections 102a, 102b provides output ripple smoothing, a more constant output drive current, and additional current capacity. Additional sections can be included to provide an even greater current capacity. The complementary pairs of the additional sections can be phase - controlled by clock signals that are 180° apart and have a phase different from P1 or P2 to provide even greater output ripple smoothing (e.g., 45° or 60° - or multiples of these values - out of phase with respect to P1 and P2).

[0041] ​In a FET-based implementation, an on / off control signal or a clock phase signal is coupled to the gates of each of the switches S1 to S7 through at least a driver circuit and, in many cases, through both a level shifter circuit and a driver circuit (see Figure 2 ) for more details).

[0042] In any configuration, non-overlapping complementary clock signals P1, P2 turn on or off associated power switches, causing charge to transfer from the flying capacitors C1a, C1b, C2a, C2b to C OUT , resulting in a voltage across C OUT of V IN / X, where X = 2 or 3. Further details of the operation of this and similar DC-DC selectable conversion ratio power converters are set forth in U.S. Patent No. 10,263,514 B1.

[0043] Limiting inrush current during soft start

[0044] As described above, destructive current spikes in a power converter can occur for various reasons, including inrush current, charge transfer current, short circuit, etc. For example, with a DC-DC power converter having a selectable conversion ratio, switching from one conversion ratio (e.g., DIV2) to another conversion ratio (e.g., DIV3) can cause charge imbalance across the flying capacitors, resulting in potentially destructive inrush current. Thus, a common practice for avoiding potentially destructive events is to turn off the DC-DC power converter, allow the flying capacitors to discharge, change the conversion ratio configuration (e.g., by changing the clock phasing of switches S1 to S7 as needed), and then turn the power back on, relying on a conventional startup circuitry to mitigate inrush current spikes. The drawback of this practice is that the process takes several milliseconds to complete and cannot be done under load.

[0045] One aspect of the present invention includes circuits and methods for mitigating or eliminating potentially destructive events if a potentially destructive event occurs or is about to occur (e.g., pre-known, such as when the conversion ratio is to be dynamically changed). Mitigating or eliminating potentially destructive events enables switching a selectable conversion ratio DC-DC power converter from one conversion ratio to another under load without turning off the power converter circuitry or pausing the switching of the charge pump power switches.

[0046] As described in U.S. Patent Application Serial No. 17 / 331,594, it is desirable and often necessary to limit the current drawn by a power converter from an input supply during startup to avoid high inrush current, especially when dynamically changing the conversion ratio of the power converter. Refer to Figure 1, a conceptual solution during the "soft start" period before the steady-state operation of the power converter 100 is to enable current sources 106a, 106b respectively coupled to sections 102a, 102b, and operate switches S2 to S7 so as to allow the flying capacitors C1a, C1b, C2a, C2b to be charged by the current sources 106a, 106b to a sufficient state to prevent current spikes. More specifically, the current sources 106a, 106b can be coupled between the node between V IN and the node between switches S1 and S2, which node is also coupled to the corresponding flying capacitors C1a, C1b. Closing switch S2 during the soft start period also couples the current sources 106a, 106b to the corresponding flying capacitors C2a, C2b; when using the current sources 106a, 106b to limit current flow, switch S1 is opened during the soft start period, and substantially all other switches operate as in normal operation. Thus, the power converter 100 operates as a charge pump, but with limited current flow.

[0047] One way to implement the current sources 106a, 106b is by means of a power switch (the power switch and the resistor are thus coupled in parallel with switch S1) serially coupled with a resistor between the node between V IN and the node between switches S1 and S2. To limit the starting current during the soft start period, closing the power switch creates a high-resistance path. Once the power converter output voltage V OUT is close to its regulated value, the power switch is opened. However, such an implementation requires a very large FET for the power switch to withstand the voltage and current during startup, and thus requires a large amount of integrated circuit (IC) die area (up to about 25% in some embodiments).

[0048] In the U.S. patent application with serial number 17 / 331,594, it is realized that switch S1 and its driver circuitry can be adapted to perform the functions of the current sources 106a, 106b, thus eliminating the need for additional large power switches and resistors. In particular, it is realized that when set to the on (conducting) state, the power converter switches S1 to S7 typically operate under "overdrive" or "full drive" conditions. The overdriven FET gate creates a stronger conductive channel, thus effectively reducing the on-resistance R ON of the FET. With this realization, it is further realized that during potential destructive events (e.g., during startup or when dynamically reconfiguring the conversion ratio of the power converter), increasing R ON for some or all of the power FETs in the power converter (especially switch S1) reduces the current flowing through the FET, and thus prevents excessive current spikes.

[0049] Figure 2It is a block diagram of a part 102a of the power converter 200, which shows details of the FET implementation of the power switches S1 to S7 of this part. Although part 102a is shown, a similar configuration exists for part 102b. In the example shown, the power switches S1 to S7 are implemented as FET M CP1 to M CP7 (collectively referred to as "M CPx "). The gate of each FET M CPx is coupled to the level shifter / driver block 202 (not all instances are numbered to avoid clutter). In some cases (e.g., power switches S6 and S7), depending on the V IN voltage and the V OUT voltage, the level shifter / driver block 202 may include only a driver because level shifting may not be required. A level shifter converts an input signal from one voltage domain (e.g., digital logic voltage) to another voltage domain (e.g., transistor control voltage). Thus, the output of the level shifter follows the input signal but within a different voltage range. Power to each level shifter / driver block 202 is provided by the corresponding LDO block 204. A clock phase (P1 or P2 in this example) or an on / off control signal may be coupled to the gate of the corresponding power FET M CPx through the level shifter / driver block 202.

[0050] As described in the above-referenced U.S. patent application Ser. No. 17 / 331,594, at least some of the LDO blocks 204 can selectively increase R ON for the associated power FETs in the power converter by actively controlling the driver voltage to the gates of the power FETs. During normal power converter operation, the power FET driver voltage can be set to overdrive the FET gates to reduce R ON to a desired level that allows high current flow for a particular application. However, for other cases (e.g., during soft start, charge balancing, or a change in conversion ratio mode), the power FET driver voltage can be reduced in order to increase R ON , and thus block the current flowing through the power FET to a desired level.

[0051] LDO power supply implementation with reduced gate drive capability

[0052] Figure 3A is Figure 2 a schematic diagram of an implementation of the level shifter / driver block 202 and the LDO block 204. As Figure 2 shown, the LDO block 204 supplies power to the associated power FET M CPxThe level shifter / driver block 202 for the gate supplies power. The input to the level shifter / driver block 202 (e.g., clock signal P1 or clock signal P2, or an on or off control signal) is applied to the input of the level shifter 302. The output of the level shifter 302 is coupled to the input of the driver circuit 304, and the output of the driver circuit 304 is coupled to the gate of the associated FET M CPx . In the example shown, the driver circuit 304 includes a pre-driver 304a (including a set of three serially-coupled inverters in this example) and a serially-coupled final driver 304b. Internally, the final driver 304b has at least one NMOS FET n and one PMOS FET p having drain-to-drain coupled conductive channels, where each FET n, p has a gate driven by the output of the pre-driver 304a. The drains of the PMOS FET p and the NMOS FET n are coupled to the gate of the associated power FET M CPx . Note that for some embodiments, the level shifter 302 can be placed after the pre-driver 304a, or between a pair of inverters including the pre-driver 304a.

[0053] In some embodiments, the inverters can increase in physical size from inverter to inverter to provide sufficient current driving capability to charge or discharge the gate of the FET M CPx . For example, in the driver circuit 304 having three serially-coupled inverters in the pre-driver 304a, the first inverter can have a relative size of "1", the second inverter can be 3 times larger than the first inverter, and the third inverter can be 9 times larger than the first inverter. Finally, the final driver 304b can be 27 times larger than the first inverter in the pre-driver 304a. The multipliers for each stage can be different from the 1×, 3×, 9×, and 27× ratios, but generally each stage is larger than the previous stage to avoid having very slow rising and falling edges. In alternative embodiments, the number of inverter stages can be fewer or more, and non-inverting stages (buffer amplifiers) can be used instead of inverting stages. Thus, the driver circuit 304 shown is merely exemplary, and other circuits can be used to couple the output of the level shifter 302 to the gate of the associated FET M CPx .

[0054] Power to the level shifter 302 and the driver circuit 304 is provided by the LDO block 204. In the example shown, the power supply for the level shifter 302 and the pre-driver 304a is provided by the first LDO section 310. The first LDO section 310 includes a source follower (common drain) FET M coupled between a capacitor C O1 and the supply voltage V DD-FGD ​LDO1 The capacitor C O1 is also coupled to a floating reference potential 308. The source of the FET M LDO1 provides a driving voltage V to the level shifter 302 and the pre-driver 304a LDO_OUT1 .

[0055] The current source I BIAS1 is serially coupled with a Zener diode D1 between the supply voltage V BIAS1 and the reference potential 308. The current source can be configured by transistors and / or diodes using various circuits and a pull-up resistor. One terminal of the Zener diode D1 is coupled to the gate of the FET M LDO1 . The resistors R1 and C1 are coupled in parallel with the Zener diode D1. When M LDO1 changes from an on state to an off state, the resistor R1 is used to discharge the gate of the FET M LDO1 . Since the output of the LDO block 204 drives the switching circuit, there is a possibility that noise is coupled to the gate of M LDO1 , which can modulate the output driving voltage V LDO_OUT1 . Such noise is mitigated by the capacitor C1. An alternative embodiment may use push-pull driving for the gate of M LDO1 .

[0056] The output V of the current source before the Zener diode D1 BIAS1 provides a substantially constant bias voltage to the gate of the FET M LDO1 . The bias current I BIAS1 flows through the Zener diode D1 and ensures that the diode is always reverse-biased. Different from a conventional diode that blocks any current from flowing through itself when reverse-biased, once the reverse voltage reaches a predetermined value, the Zener diode starts to conduct. Even if there is a large change in current (as long as the current remains between the minimum breakdown current and the maximum rated current of the Zener diode), the applied reverse voltage remains almost constant. The Zener diode continues to regulate its voltage until the holding current of the diode drops below the minimum current value in the reverse breakdown region.

[0057] The final driver 304b is powered by a second LDO section 312 that includes an FET M DD-RGD having a conductive channel (between the drain and the source) coupled between the supply voltage V LDO2 and the final driver 304b. The gate of the FET M LDO2 is coupled to a separate gate driver circuit independent of the gate driver circuitry of the FET M LDO1 . The main function of the gate driver circuit of the second LDO section 312 is to enable at least two different voltage levels at node A to be coupled to the FET MLDO2 of the gate, which in turn determines the output voltage level V provided by the final driver 304b associated with driving the power FET M CPx . Thus, the associated power FET M GATE can be placed in (1) an overdrive or "full gate drive" on state with a low R for normal power converter operation, or (2) at least one current-limiting reduced gate drive on state with a higher R CPx and / or in a saturation mode in which the current is limited. The saturation mode appears like an increased R ON , but is not exactly the same - in the saturation mode, the FET M ON behaves like an ON - OFF switch and can only pass a maximum fixed current regardless of the applied voltage, while a resistor means that a greater voltage allows a greater current. The current - limiting state is selected to provide protection against potentially damaging events (e.g., inrush or charge transfer currents). Potentially damaging events can occur during dynamic reconfiguration of the conversion ratio of the power converter, during startup of the power converter when balancing the charge between the flying capacitors within the power converter, or during a fault event such as a short - circuit event. ON The resistors R2 and capacitor C2 are coupled in parallel with the zener diode D2 and function in substantially the same manner as the resistors R1 and capacitor C1. The storage capacitor C CPx is coupled between the source of the FET M

[0058] and the floating reference potential 308 and provides some initial charge to the gate of the FET M O2 as well as isolation from the floating reference potential 308. LDO2 The gate driver circuit of the FET M CPx includes a variable current source I

[0059] which is coupled in series with the zener diode D2 between the supply voltage V LDO2 and the reference potential 308. The gate of the FET M BIAS2 is coupled to the node A between the current source I BIAS2 and the zener diode D2. The output of the current source I BIAS2 before the zener diode D2 at the node A provides a substantially constant bias voltage V LDO2 to the gate of the FET M BIAS2 . The source of the FET M BIAS2 provides the drive voltage V LDO2 to the final driver 304b. GS_SF The drain of the FET M LDO2 is coupled to the output of the final driver 304b. LDO_OUT2

[0060] In parallel with the Zener diode D2 is a voltage control circuit 314, which includes an FET M serially coupled to a first diode-connected FET D0 and at least one additional diode-connected FET M DN with a reduced gate drive P-type FET switch M SW , where N≥1. The gate of the FET switch M SW is coupled to a switch control block 316, which is coupled to an enable signal EN RGD ; Details of the switch control block 316 are discussed below.

[0061] The first diode-connected FET M D0 and at least one additional diode-connected FET M DN have their conductive channels serially coupled. As shown, the conductive channel of the switching FET switch M SW is coupled between node A and the conductive channel of the first diode-connected FET M D0 . Finally, the conductive channel of the additional serially connected diode-connected FET M DN is coupled to a floating reference potential 308. Note that the switching FET switch M SW can be positioned anywhere along the voltage control circuit 314 to interrupt or enable the current flowing through the circuit. However, as shown in Figure 3, positioning the FET switch M SW can reduce the parasitic effects on the FET M D0 and / or M DN due to the capacitance of, for example, the diode-connected FET M LDO2 .

[0062] The function of the diode-connected FET M D0 is to cancel out the FET M LDO2 , because the threshold voltages of the FET M D0 and the FET M LDO2 effectively cancel each other out. The function of the additional diode-connected FET M DN is: when the FET switch M SW is closed and the current mirror function of the voltage control circuit 314 is in use, to set the current I CPx flowing through the FET M DN in proportion to the size ratio of the FET M CPx . More specifically, the current I MAIN flowing through the FET M CPx is related to the current from the current source I MAIN and the FET M BIAS2 and the FET M DN and the FET M CPxare in proportion in terms of size ratio. For example, if the current source I BIAS2 outputs 1 mA, and the FET M CPx is 1,000 times the size of the FET M DN (W / L M CPx = 1000 × W / L M DN ), then the maximum current through the FET M CPx will be 1,000 × 1 mA = 1 A. This is achieved by ensuring that the gate-to-source voltage V DN of the FET M GS is the same as the gate-to-source voltage V CPx of the FET M GS . The maximum gate voltage of the FET M CPx is the voltage at node A minus the threshold voltage V LDO2 of the FET M TH . Including the FET M D0 increases the voltage at node A by a second threshold voltage V GS , so the voltage at node A = (V DN of the FET M GS ) + (V D0 of the FET M TH ), or 2V GS . If the FET M LDO2 and the FET M D0 are matched (proportionally), then the maximum value that the V CPx of the FET M GS can reach is the same as the V DN of the FET M GS , and this equality tracks across processes, temperature, etc.

[0063] As described, the diode-connected FET M DN is in proportion in terms of size relative to the FET M CPx . In some embodiments, the FET M LDO1 , M LDO2 , M D0 and M CPx can be segmented FETs, meaning that a device intended to act as a large FET is fabricated as a number (e.g., 10,000) of small FETs connected in parallel (each small FET can be referred to as a "finger", reflecting a typical aspect of their physical layout on an IC die). The diode-connected FET M D0 , M DN can be fabricated using the same technology, but can be fabricated with a much smaller number of FET fingers (e.g., as few as one finger). Since the FET M LDO2and the configuration of the final driver 304b, the influence FET M flowing through the voltage control circuit 314 LDO2 at the gate of voltage V GS_SF A small change in the current of causes the FET M CPx associated with the FET M DN The size ratio determines the power FET M flowing through CPx proportionally larger current I MAIN .

[0064] Adding more than one diode-connected FET M DN allows the adjustment of the size ratio of the FET M CPx associated with the FET M DN For example, if the FET M CPx has a width of 100 and 1000 fingers, then the first FET M DN should also have a width of 100 to match, but can have only 1 finger. Therefore, the FET M DN associated with the FET M CPx The size ratio is 1000 to 1, and 1 mA from the current source I BIAS2 means 1 A through the FET M CPx To change the size ratio to 2000 to 1, two diode-connected FET M DN can be coupled in series (source to drain). If the FET width remains 100, then the effective number of fingers of the two diode-connected FET M DN is half, thus giving a size ratio of 2000 to 1 relative to the FET M CPx .

[0065] As described above, an important function of the gate driver circuit is that it provides an adjustable gate bias voltage V LDO2 to the FET M GS_SF , and the FET M LDO2 in turn controls the power supply to the final driver 304b and the voltage output of the final driver 304b. When the FET switch M SW is turned off, then the voltage control circuit 314 is disconnected from node A - and thus from the gate of the FET M LDO2 - and thus has basically no effect on the output of the FET M LDO2 ; therefore, the final driver 304b can fully overdrive the gate of the FETM CPx to a selected level determined by the Zener diode D2.

[0066] When the FET switch M SWWhen closed—for example, during startup of a power converter or when dynamically switching the conversion ratio or rebalancing the charge of the flying capacitor—then the voltage control circuit 314 operates as a bypass to divert the current around diode D2 and reduce the voltage at node A, thereby reducing the drive voltage to FET M LDO2 . The reduced gate drive voltage to FET M LDO2 in turn reduces the power to the final driver 304b, and thus reduces the gate drive voltage to power FET M CPx . Thus, FET M GATE receives a reduced gate drive voltage, which results in an increased R CPx value and / or a limited saturation current compared to the fully overdriven state. The increased limitation of the current flowing through at least some of the power FETs M ON in the power converter can suppress excessive current spikes, thereby protecting the power FETs (and other coupled circuitry) from large voltage spikes. Selectively varying the I CPx current control applied to power FET M BIAS2 enables selection of different current flow limitations. CPx value of V GATE applied to power FET M

[0067] In some embodiments, based on measured parameters (such as the value of V IN , the value of V OUT , the value of the pump capacitor voltage, or the value of the load current) and / or as a result of a sensed event (such as a short circuit event and / or charge imbalance on the pump capacitor), the reduced gate drive operation of power FET M CPx in the on state for limiting current spikes during potentially destructive events can be enabled (triggered) by a control circuit (not shown). In some embodiments, the reduced gate drive operation of power FET M SW in the on state for limiting current spikes during potentially destructive events can be enabled (triggered) based on an external enable signal EN GRD that is valid prior to a known upcoming event (such as a dynamic switching of the conversion ratio). CPx

[0068] The duration of the reduced gate drive operation for the power FET can be set to a fixed time suitable for a particular application or can be determined based on some criteria. For example, the reduced gate drive operation for the power FET can be a function of the output load, or a function of the output load and a selected maximum duration (i.e., a timeout parameter), or a function of the voltage across a flying capacitor that has reached some percentage (e.g., 95%) of a desired target level, or some combination of the values of these and / or other parameters.

[0069] In the voltage control circuit 314 fabricated using the same technology as the power FET M CPx (e.g., NMOSFET), the advantage of using a diode-connected FET is that the devices should essentially have matching characteristics with respect to process / voltage / temperature (PVT) variations.

[0070] In summary, the main function of the gate driver circuit of FET M LDO2 is to enable at least two different voltage levels at node A to be coupled to the gate of FET M LDO2 More specifically, the voltage control circuit 314 can selectively shift the voltage at node A between a first voltage level where the voltage control circuit 314 is not engaged (FET switch M SW is off) and at least a second voltage level where the voltage control circuit 314 is engaged (FET switch M SW is on).

[0071] It should be understood that Figure 3A the second LDO section 312 shown in SW is easy to implement and requires little power and circuit area. However, other devices or circuits providing the same or similar functionality can be used in other embodiments. For example, node A can be coupled to an amplifier having a level-shifted reference voltage as an input through FET switch M

[0072] Note that Figure 3A the LDO block 204 including the second LDO section 312 can be used to power all FET switches in the power converter 100 to limit the current through such switches as may be required (e.g., when dynamically changing the conversion ratio of the power converter 100). In some cases, for some FET switches (e.g., Figure 1 the power switches S5 and S7 in can be directly applied to the associated pre-driver 304a. In such a case, the LDO section 310 may not be required, and the LDO section 312 can be used to drive the pre-driver 304a, thus saving IC area. It should also be noted that the LDO block 204 can be used to provide a regulated power supply to other types of target circuits, not just to the level shifter / driver block 202.

[0073] Figure 3B is a block diagram showing details of one embodiment of the switch control block 316. As shown, the switch control block 316 is coupled to components of the voltage control circuit 314 and includes an NFET M having a first end of its conductive channel coupled to node A through a resistor Ra and a second end of its conductive channel coupled to the floating reference potential 308. The drain of the NFET M is coupled to the gate of the P-type FET switch M SW . The switch Sw, current source I BIAS and resistor Rb are serially coupled between the voltage V BIAS and the floating reference potential 308 as shown. The gate of the NFET M is coupled between the current source I BIAS and the resistor Rb. In an alternative embodiment, a standard level shifter can be used to drive the gate of the FET switch M SW , but it may be at the cost of a larger IC area.

[0074] In operation, if the enable signal EN RGD is logic "1", then the switch Sw closes, causing the NFET M to conduct and pulling down the gate of the P-type FET switch M SW to the floating reference potential 308. As a result, a negative V GS is applied to the P-type FET switch M SW , thereby setting M SW to the conducting state (i.e., closing the switch). In contrast, if the enable signal EN RGD is logic "0", then the switch Sw opens and the NFET M does not conduct; thus, the V SW to the P-type FET switch M GS will be zero, thereby setting M SW to the non-conducting state (i.e., opening the switch).

[0075] The LDO supply voltage

[0076] Figure 2 for each of the power switches S1 to S7 in the LDO block 204 requires at least one voltage supply. In Figure 3A , four voltage sources, V BIAS1 , V DD-FGD , VBIAS2 and V DD-RGD . In some embodiments, V BIAS1 and V BIAS2 may have the same value. In some embodiments, V DD-FGD and V DD-RGD may have the same value. In some embodiments, V BIAS1 and V BIAS2 as well as V DD-FGD and V DD-RGD in combination may have different values.

[0077] Each LDO block 204 should generate a voltage V CPx sufficient to switch the associated power FET M GATE . For the FET implementation of the power switch S1, since the drain voltage to M CP1 is V IN , the corresponding gate voltage V GATE should be equal to or exceed V IN plus the V CP1 of FET M GS . Thus, the V CP1 and V DD-FGD of the LDO block 204 coupled to the level shifter / driver block 202 for the power FET M DD-RGD should ultimately provide this value of V GATE . The voltages V DD-FGD and V DD-RGD can be supplied by an external circuitry coupled to each of the sections 102a, 102b, which provides a voltage V IN greater than V BOOST1 , e.g., greater than V IN 3V to 5V. Each such external circuit can include, for example, a simple charge pump coupled to a startup capacitor. In the simplest implementation, the voltage supplies V DD-FGD and V DD-RGD for the power switches S2 to S7 can be V BOOST1 or V IN (since such switches are at a voltage level below V IN ).

[0078] Since the V DD-FGD and V DD-RGD of the power switch S1 are set to be greater than the V IN of V BOOST1 , the gate voltages to FET M LDO1 to FETM LDO2 should be greater than V BOOST1 in order to turn on properly. Thus, V BIAS1 and V BIAS2It can be provided by an external circuit system coupled to each of the sections 102a, 102b to provide a voltage V greater than V BOOST1 of BOOST2 , for example, V IN +5.5V. Each such external circuit can include, for example, a simple charge pump coupled to a startup capacitor. In the simplest implementation, the voltage supplies V BIAS1 and V BIAS2 for the power switches S2 to S7 can be V BOOST2 or V IN (since such switches are at a lower voltage level).

[0079] Figure 4 is a schematic block diagram of an embodiment of a charge pump 400. Separate instances of the charge pump 400 can be used to generate V BOOST1 and V BOOST2 (collectively referred to as "V BOOSTx "). The clock signals P1 and P2 are complementary and non-overlapping in phase, while the / P1 and / P2 clock signals are the inverted versions of P1 and P2. The PFET M1 and the NFET M3 conduct simultaneously and block the flow of charge, while the NFET M2 and the PFET M4 conduct simultaneously and block the flow of charge (but complementary to the PFET M1 and the NFET M3). The FETs M1 and M2 and the FETs M4 and M3 are coupled in series between the voltage source V DD and the opposite circuit ground. A set of cross-coupled FET pairs (the NFET M5 and the PFET M6 on the left, the NFET M8 and the PFET M7 on the right) are coupled between V IN and the capacitor C OUT , and this capacitor C OUT is in turn coupled to the opposite circuit ground. The switching of the P1 and P2 clock signals (and their complementary versions) periodically connects V IN to the "top" plates of the capacitors C A and C B through the FETs M5 and M8, thereby charging these capacitors to V IN , and then periodically connects V DD to the "bottom" plates of the capacitors C A and C B through the FETs M1 and M4, thereby instantaneously adding V DD to V IN . More specifically, in the first stage, the capacitor C A is charged to V IN through the switches M5 and M2 in the closed (on) state, or the capacitor C B is charged to VIN . In the second stage, capacitor C A discharges to the output terminal at a voltage of V BOOSTx = V IN + V DD through switches M1 and M6 in the closed state, or capacitor C B discharges to the output terminal at a voltage of V BOOSTx = V IN + V DD through switches M4 and M7 in the closed state.

[0080] Returning to the reference Figure 2 , it should be understood that the different power switches S1 to S7 are in different voltage ranges, and only power switch S1 needs to withstand V IN . when in the off state. The remaining power switches S2 to S7 can be designed to withstand lower voltage levels. The present invention recognizes that applying the V GATE voltage to all the lower-level power switches S2 to S7 based on V BOOST1 or V IN is inefficient because these supply voltages are higher than the voltages required to switch the lower-level power FETs. Therefore, one aspect of the present invention is to utilize the internal voltage nodes of the power converter itself to supply V DD-FGD and V DD-RGD in order to efficiently power the lower-level power switches S2 to S7. The complication of using such internal voltage nodes is that the voltage division ratio of the power converter can be dynamically switched, which affects the voltages available at some of the utilized internal voltage nodes due to changes in the switching phases of some power FETs (e.g., power switch S2). In addition, during the transition between DIV2 and DIV3 operations, an incorrect LDO configuration can cause a cascading effect, which can damage the power converter. Therefore, another aspect of the present invention is an adaptive circuit architecture that functionally allows for dynamic switching between different voltage supply sources for the LDO used to power the level shifter 302 and the pre-driver 304a and the LDO used to power the final driver 304b.

[0081] Source-switching LDO

[0082] Figure 5A is a block diagram of an embodiment of a "source-switching" LDO 502 that is configured to supply regulated power to a level shifter / pre-driver 504 (comparable to Figure 3A the level shifter 302 and the pre-driver 304a of Figure 3A ) and a final driver 506 (comparable to CPxThe floating reference potential 308 of the source. The LDO 502 shown includes dual full-gate drive LDO parts 508a, 508b and dual reduced-gate drive LDO parts 510a, 510b. When the power converter is in the DIV2 configuration, the full-gate drive LDO part 508a and the reduced-gate drive LDO part 510a are operable and generate corresponding outputs V LDO_OUT1_DIV2 and V LDO_OUT2_DIV2 . When the power converter is in the DIV3 configuration, the full-gate drive LDO part 508b and the reduced-gate drive LDO part 510b are operable and generate corresponding outputs V LDO_OUT1_DIV3 and V LDO_OUT2_DIV3 .

[0083] As shown, the outputs of the dual full-gate drive LDO parts 508a, 508b can be directly connected ("wired OR" or multiplexed connection) to the level shifter / pre-driver 504, as shown, or coupled through a switch (not shown). Similarly, the outputs of the dual reduced-gate drive LDO parts 510a, 510b can be directly connected to the final driver 506. For power FET M CPx that does not require or does not desire a reduced gate drive voltage, the LDO 502 can include only the dual full-gate drive LDO parts 508a, 508b, and V LDO_OUT1_DIV2 and V LDO_OUT1_DIV3 will be directly connected to the final driver 506 through the conductor 512 (as shown by the dashed line).

[0084] Figure 5B is Figure 5A a block diagram of the dual full-gate drive LDO parts 508a, 508b, which shows more details. As indicated by the comparison with Figure 3A , each full-gate drive LDO part 508a, 508b is essentially Figure 3A an instance of the full-gate drive LDO part 310 of DD-FGD1 , the only difference being that the LDO part 508a is supplied by the first voltage V DD-FGD2 while the LDO part 508b is supplied by the second voltage V

[0085] In the DIV3 mode, the I BIAS1b current to the full-gate drive LDO part 508b is turned on while the I BIAS1a current to the full-gate drive LDO part 508a is turned off. The gate of the FET M LDO1 in the full-gate drive LDO part 508a is pulled down to the floating ground by the corresponding resistor R1. The FET M LDO1 in the LDO part 508a is turned off, and the M LDO1Turns on, thereby supplying power to the associated level shifter / pre-driver 504 (and in some cases, to the final driver 506). In DIV2 mode, a reverse configuration is presented, where the I BIAS1a current to the full gate drive LDO section 508a is turned on, while the I BIAS1b current to the full gate drive LDO section 508a is turned off. Accordingly, the full gate drive LDO section 508a supplies power to the associated level shifter / pre-driver 504 (and in some cases, to the final driver 506), and the full gate drive LDO section 508b is turned off.

[0086] FIG. 5C is a Figure 5A block diagram of the dual-reduced gate drive LDO sections 510a, 510b, which shows more details. As indicated by the comparison with Figure 3A , each reduced gate drive LDO section 510a, 510b is essentially an Figure 3A instance of the reduced gate drive LDO section 312, the only difference being that the LDO section 510a is supplied by the first voltage V DD-RGD1 , while the LDO section 510b is supplied by the second voltage V DD-RGD2 .

[0087] In DIV3 mode, the I BIAS1b current to the full gate drive LDO section 510b is turned on, while the I BIAS1a current to the full gate drive LDO section 510a is turned off. Accordingly, the V GS_SF in the reduced gate drive LDO section 510b is set to that section by I BIAS2 , and the V GS_SF in the reduced gate drive LDO section 510a is pulled down to floating ground by the corresponding resistor R2. The FET M LDO2 in the LDO section 510a is turned off, and the FET M LDO2 in the LDO section 510b is turned on, thereby supplying power to the associated final driver 506. In DIV2 mode, a reverse configuration is presented, where the I BIAS2a current to the reduced gate drive LDO section 510a is turned on, while the I BIAS2b current to the reduced gate drive LDO section 510a is turned off. Accordingly, the reduced gate drive LDO section 510a supplies power to the associated final driver 506, and the reduced gate drive LDO section 510b is turned off.

[0088] FIG. 5D is a Figure 5A block diagram of an alternative embodiment of the dual-reduced gate drive LDO sections 510a, 510b. In the illustrated embodiment, the variable current source IBIAS2 An example 520 of each of the voltage control circuit 314 and the diode D2 is shared with the DIV2 circuit 522a or the DIV3 circuit 522b by means of a switch Sw. The state of the switch Sw will be determined by a control circuitry (not shown) that reconfigures the power converter between the DIV2 operating mode and the DIV3 operating mode. Setting the switch Sw to couple the diode D2 to the DIV2 circuit 522a substantially creates a first reduced gate drive circuit, while setting the switch Sw to couple the diode D2 to the DIV3 circuit 522b substantially creates a second reduced gate drive circuit.

[0089] Considering that a power converter typically has two parallel sections 102a, 102b (see Figure 1 ), for high efficiency, the type of LDO and the voltage supply to the LDO associated with each power FET M CPx can be selected. For example, the LDO for the power switch S1 in the two parallel sections 102a, 102b is preferably of the type shown in Figure 3A because a reduced gate drive capability is typically required to limit inrush current, but "source switching" does not need to be supported. As described above, the V DD inputs to the full gate drive LDO section 310 and the reduced gate drive LDO section 312 can all be supplied by the V BOOST1 circuit because changing the voltage division ratio of the power converter is not a factor. In some embodiments, it may be useful to "wire-or" the outputs of the V BOOST1 circuits to save IC area. As described above, the V BIAS inputs to the full gate drive LDO section 310 and the reduced gate drive LDO section 312 can be supplied by the V BOOST2 circuit.

[0090] As another example, the LDOs for the power switches S6 and S7 in the two parallel sections 102a, 102b can be merely an instance of the first LDO section 310 of Figure 3A because a reduced gate drive capability is typically not required to limit inrush current, and "source switching" does not need to be supported. The V DD input to the LDO section 310 can all be supplied by the V X node voltage. As described above, the V BIAS input to the LDO section 310 can all be supplied by the V BOOST1 circuit.

[0091] In an effective implementation of a power converter, some of the power FET switches may require a dual-gate drive LDO circuit to support "source switching". For example, for better efficiency, power switches S2 and S4 in the power converter can use different power supply sources for DIV2 and DIV3 operating modes. Specifically, the V in the DIV2 mode of the power switch S2 in part 102a of the power converter DD-FGD1 and V DD-RGD1 sources can come from the V of another part 102b of the power converter BOOST1 circuit. In contrast, the V in the DIV3 mode of the power switch S2 in part 102a of the power converter DD-FGD1 and V DD-RGD1 sources can come from the V coupled to the same part 102a BOOST1 circuit.

[0092] As another example, the V in the DIV2 mode of the power switch S4 in part 102a of the power converter DD-FGD1 and V DD-RGD1 sources can come from the V of another part 102b of the power converter C1b node. In contrast, the V in the DIV3 mode of the power switch S4 in part 102a of the power converter DD-FGD1 and V DD-RGD1 sources can come from the V of the same part 102a C1b node.

[0093] Table 2 below shows a set of LDO types and voltage source allocations that can be used in combination with an efficient power converter. "FGD / RGD" represents a full-gate drive / reduced-gate drive LDO of the type shown in Figure 3A . "FGD" simply represents the full-gate drive LDO part 310 shown in Figure 3A (no RGD LDO is required). "Dual FGD / Dual RGD" represents a dual full-gate drive / dual reduced-gate drive LDO of the type shown in Figure 5A . "Dual FGD" simply represents the dual full-gate drive LDOs 508a, 508b shown in Figure 5A (no RGD LDO is required). "Same part" represents parts 102a, 102b in which the switch is located. "Other part" represents parts 102a, 102b in which the switch is not located (e.g., if the switch is in part 102a, then part 102b will be the "other part").

[0094]

[0095] Table 2

[0096] Note that for the power switch S2 in DIV2 mode, the voltage source can be "V C2 other part". However, since "V BOOST1 same part" is greater than "V C2 other part", using "V BOOST1 same part" provides more headroom across the transfer transistor and can have other advantages.

[0097] Enhanced implementation

[0098] In some applications using a "source-switching" dual-gate-driven LDO, such as Figure 5A shown, due to the "wired-OR" of the two LDO outputs, situations that can affect performance or even cause damage may occur.

[0099] As a first example, at high V IN values, problems may occur in the LDO for the power switch S2 (FET M CP2 ). More specifically, when in DIV2 mode, the DIV3 side 508b of the full dual-gate driver LDO or the DIV3 side 510b of the dual-reduced gate driver LDO - for the power switch S2, either of them should be off in DIV2 mode - can turn on at high V IN values, creating an unwanted discharge path through the DIV3 side circuitry.

[0100] For example, Figure 6 is a schematic of the full dual-gate driver LDO parts 508a, 508b in the DIV2 configuration of the power switch S2. The V BIAS1 on the DIV3 side 508b is zero, and thus the gate of the FET M LDO1 in the DIV3 side 508b is pulled down to the floating ground, which is the V IN of the power switch S2. However, if V IN is greater than 2*V Z (the voltage drop across the Zener diode D1), then the FET M LDO1 in the DIV3 side 508b switches to the on state (assuming that in this example the V LDO1 of the FET M TH = 0V). Thus, the current through the FET M LDO1 in the DIV2 side 508a can discharge through path 602, leaving no voltage or insufficient voltage for the associated level shifter / pre-driver 504 and / or the final driver 506. Note that although Figure 6The dual full-gate drive LDO sections 508a, 508b are shown, but the same problem exists for the dual-reduced gate drive LDO sections 510a, 510b.

[0101] Figure 6 The solution to this problem is shown in the form of an added FET pull-up switch M on the DIV3 side 508b PU (inside the dashed oval 604). The conductive channel of the FET pull-up switch M PU is coupled between the gate of the DIV3 side FET M LDO1 and a voltage source (V LDO1 in this example) coupled to the drain of the DIV3 side FET M DD-FGD2 . The gate of the FET pull-up switch M PU is coupled to the gate of the DIV3 side FET M LDO1 . When V IN > 2 * V Z , the FET pull-up switch M PU turns on and pulls the gate of the DIV3 side FET M LDO1 to "V BOOST1 other" (which is greater than V IN ), ensuring that the DIV3 side FET M LDO1 is cutoff at a high V IN value, thus turning off the discharge path 602.

[0102] As a second example of a situation that may affect performance or even cause damage, during the DIV3 to DIV2 mode transition, the DIV3 side 508b of the dual full-gate driver LDO or the DIV3 side 510b of the dual-reduced gate driver LDO may not fully turn off before the corresponding DIV2 side turns on, which can lead to breakdown and damage to the power converter.

[0103] For example, Figure 7A is a schematic diagram of the dual-reduced gate drive LDO sections 510a, 510b of the LDO transitioning from DIV3 to DIV2 mode. Figure 7B is a set of graphs showing the current and voltage of the dual-reduced gate drive LDO over time, depicting the problem of overlapping turn-on times. Note that although Figure 7A shows the dual full-gate drive LDO sections 508a, 508b, the same problem exists for the dual-reduced gate drive LDO sections 510a, 510b.

[0104] Referring to Figure 7B , when the bias current I BIASDIV3 to the DIV3 side of the dual full-gate driver LDO is high, then the bias current to the DIV3 side FET M LDO2The gate voltage V GS_SF_DIV3 is high, and the FET is turned on (i.e., the DIV3 side is connected). When the bias current I BIAS_DIV2 to the DIV2 side of the dual full-gate driver LDO is low, then the gate voltage V LDO2 to the FET M GS_SF_DIV2 on the DIV2 side is low, and the FET is turned on (i.e., the DIV2 side is disconnected). In the absence of a correction circuit, when the dual full-gate driver LDO switches from DIV3 mode to DIV2 mode, the gate of the DIV3 side FET M LDO2 requires a considerable amount of time (the C2*R2 time constant on the DIV3 side) to discharge when the FET transitions from on to off. Therefore, there is a period of time when both the DIV3 side and the DIV2 side of the dual full-gate driver LDO are connected. Thus, the current passing through the DIV2 side FET M LDO2 can discharge through path 702, thus not leaving a voltage or leaving an insufficient voltage for the associated level shifter / pre-driver 504 and / or the final driver 506.

[0105] To address this potential problem, a fast discharge switch M FD (inside the dashed oval 704) is added, where its conductive channel is coupled to node A and floating ground. The gate of the fast discharge switch M FD will be coupled to the control signal CTRL, which will set M FD to the on (conductive) state during the DIV3 to DIV2 transition, thus enabling the gate of the DIV3 side FET M LDO2 to discharge quickly. The result is that the DIV3 side quickly disconnects before the DIV2 side is connected, thus ensuring no overlap between the LDO on states and eliminating the possible discharge path 702. Figure 7C is a set of graphs showing the current and voltage of the dual-reduced gate drive LDO including Figure 7A the fast discharge switch M FD changing over time. During the transition from DIV3 mode to DIV2 mode, the control circuitry (not shown) will activate the CTRL signal, thus turning on M FD , and thus coupling the gate of the DIV3 side FET M LDO2 to floating ground, thus quickly discharging these gates. Therefore, the DIV3 side FET M LDO2 quickly turns off before the DIV2 side FET M LDO2 turns on.

[0106] It should be understood that the dual-gate drive LDO implementation may include Figure 7A the fast discharge switch M FD andFigure 6 pull-up switch M PU Both. Using a fast discharge switch M with a "source switching" dual-gate driven LDO in a "wire-OR" connection FD and / or pull-up switch M PU Avoids having to place an additional switch in the output path of the LDO section, which improves efficiency.

[0107] Benefits

[0108] Embodiments of the present invention may have some or all of the following advantages: current limiting values independent of the power converter switching frequency, device mismatch, and process, voltage, and / or temperature (PVT) variations; accurate soft-start current limiting; reliable operation of power FETs in a power converter with a reconfigurable conversion ratio when dynamically changing the conversion ratio; the ability to maintain a level output voltage when the power converter operates at full load under different operating and PVT conditions; and high efficiency in powering specific power FETs by using existing voltage nodes within the power converter.

[0109] Circuit embodiments

[0110] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as integrated circuits (ICs), which can be encapsulated in IC packages and / or modules for ease of handling, fabrication, and / or performance improvement. In particular, IC embodiments of the present invention are typically used in modules where one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) in one package. Then, typically, the IC and / or module are often combined with other components on a printed circuit board to form part of a final product such as a cellular phone, laptop computer, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs typically implement a communication mode, usually wireless communication.

[0111] As an example of further integration of embodiments of the present invention with other components, Figure 8is a top plan view of a substrate 800 that can be, for example, a printed circuit board or a chip module substrate (e.g., a thin film block). In the example shown, the substrate 800 includes a plurality of ICs 802a to 802d having terminal pads 804 that will be interconnected by traces and / or conductive vias on and / or within the substrate 800 or on the opposite (back) surface of the substrate 800 (for the sake of clarity, surface conductive traces are not shown and not all terminal pads are labeled). The ICs 802a to 802d can include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 802b can include one or more instances of an enhanced LDO power supply circuit similar to the circuitry shown in Figure 3A , Figure 5A to FIGS. 5D, Figure 6 and / or Figure 7A .

[0112] The substrate 800 can also include one or more passive devices 806 embedded in, formed on, and / or attached to the substrate 800. Although shown as generally rectangular, the passive devices 806 can be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., which are interconnected to other passive devices 806 and / or the individual ICs 802a to 802d by conductive traces on or in the substrate 800. The front or back surface of the substrate 800 can be used as a location for forming other structures.

[0113] System Aspects

[0114] Embodiments of the present invention are useful in a variety of applications - including portable computing devices (e.g., laptops, notebooks, cellular phones, tablets), data centers and telecommunications centers with battery backup systems, household appliances and electronics, transportation vehicles (e.g., cars, drones, airplanes, boats, trains, ships), general DC / DC and AC / DC power converters, and radio frequency (RF) circuits and systems.

[0115] The uses of radio systems can include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, such as various types of orthogonal frequency division multiplexing ("OFDM"), quadrature amplitude modulation ("QAM"), code division multiple access ("CDMA"), time division multiple access ("TDMA"), wideband code division multiple access ("W-CDMA"), global system for mobile communications ("GSM"), long term evolution ("LTE"), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0116] Method

[0117] Another aspect of the present invention includes a method of supplying power to at least one voltage input node of a target circuit. For example, Figure 9 FIG. 900 is a process flow diagram showing a method of supplying power to a voltage input node of a target circuit. The method includes: coupling a first low dropout circuit between a first voltage source and the voltage input node of the target circuit, the first low dropout circuit including a first transistor (e.g., FET) circuit configured to selectively apply a first voltage to the voltage input node of the target circuit [block 902]; and coupling a second low dropout circuit between a second voltage source and the voltage input node of the target circuit, the second low dropout circuit including a second transistor (e.g., FET) circuit configured to selectively apply a second voltage to the voltage input node of the target circuit [block 904].

[0118] For example, Figure 10FIG. 1000 is a process flow diagram showing a method of supplying power to a voltage input node of a driver circuit for a power FET having a gate and to the gate of the power FET. The method includes: coupling a first low dropout circuit between a first voltage source and the voltage input node of the driver circuit, the first low dropout circuit including a first FET circuit configured to selectively apply a first voltage to the voltage input node of the driver circuit [block 1002]; coupling a second low dropout circuit between a second voltage source and the voltage input node of the driver circuit, the second low dropout circuit including a second FET circuit configured to selectively apply a second voltage to the voltage input node of the driver circuit [block 1004]; coupling a first reduced drive low dropout circuit between a third voltage source and the gate of the power FET, the first reduced drive circuit including a third FET circuit configured to selectively apply at least a third voltage or a lower fourth voltage to the gate of the power FET such that the current flowing through the power FET in the on state is higher when the third voltage is applied and lower when the lower fourth voltage is applied [block 1006]; and coupling a second reduced drive low dropout circuit between a fourth voltage source and the gate of the power FET, the second reduced drive circuit including a fourth FET circuit configured to selectively apply at least a fifth voltage or a lower sixth voltage to the gate of the power FET such that the current flowing through the power FET in the on state is higher when the fifth voltage is applied and lower when the lower sixth voltage is applied [block 1008].

[0119] Additional aspects of the above method may include one or more of the following: wherein the first voltage source is the same as the second voltage source; wherein the first voltage source is different from the second voltage source; wherein the third voltage source is the same as the fourth voltage source; wherein the third voltage source is different from the fourth voltage source; selectively applying one of a lower fourth voltage or a lower sixth voltage to limit excessive current flowing through the power FET; wherein the first FET circuit or the third FET circuit of at least one of the first full-drive low dropout circuit or the first reduced-drive low dropout circuit includes a FET having a gate, and further includes coupling the conductive channel of the pull-up FET between the gate of the FET and a corresponding one of the first voltage source or the third voltage source, and coupling the gate of the pull-up FET to the gate of the FET; wherein the first FET circuit or the third FET circuit of at least one of the first full-drive low dropout circuit or the first reduced-drive low dropout circuit includes a FET having a gate, and further includes coupling the conductive channel of the fast-discharge FET between the gate of the FET and the reference potential, coupling the gate of the fast-discharge FET to the control signal, and selectively enabling the control signal to discharge the gate of the FET by the fast-discharge FET; and / or wherein the first reduced-drive low dropout circuit and the second reduced-drive low dropout circuit each include a voltage control circuit, wherein each voltage control circuit includes a switch, a first diode-connected FET, and at least one additional diode-connected FET, and the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the reference potential and the corresponding first or second FET circuit.

[0120] Manufacturing techniques and options

[0121] Figures 5B and 5C show the LDO section as being "wired OR" with a level shifter / pre-driver, a final driver, or a power FET gate on the source side of FET M LDO1 or M LDO2 In an alternative implementation of a power converter implemented with a P-type FET (PFET), the LDO section can be substantially inverted and implemented with a PFET to provide an output voltage of the appropriate polarity from the drain side of the FET. Thus, for example, the ground connections shown in Figures 5B and 5C would become the positive voltage rail V IN , and the various voltage sources (e.g., V BIAS1 , V BIAS2 , V DD-FGD1 , V DD-FGD2 , V DD-RGD1 and V DD-RGD2 ) would be negative voltages with respect to V IN . The current source would become a current sink, and the polarities of diodes D1, D2 would be reversed (e.g., the cathodes are coupled to V IN)。The "wired-OR" connection to the level shifter / pre-driver, final driver, or power FET gate will be from the drain side of the FET within the LDO section. Otherwise, the operation remains substantially the same as in the N-type FET implementation. It should be apparent that the circuits of FIGS. 5D, Figure 6 and Figure 7A can also be implemented with PFETs.

[0122] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate whose conductivity is determined by a voltage, and includes an insulated gate having a metal or metal-like, insulator, and / or semiconductor structure. The term "metal" or "metal-like" includes at least one conductive material (such as aluminum, copper, or other metals, or highly doped polysilicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0123] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of approximately 3 kHz to approximately 300 GHz. The term also includes frequencies used in wireless communication systems. The RF frequency can be the frequency of an electromagnetic wave, or can be the frequency of an alternating voltage or current in a circuit.

[0124] Regarding the drawings referenced in this disclosure, the dimensions of the various elements are not drawn to scale; for clarity or emphasis, some dimensions may be significantly enlarged vertically and / or horizontally. Additionally, references to orientation and direction (e.g., "top", "bottom", "above", "below", "lateral", "vertical", "horizontal", etc.) are relative to the exemplary drawings and are not necessarily absolute orientation or direction.

[0125] The various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, the selection of appropriate component values is a matter of design choice. The various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology, including but not limited to MOSFET architectures, or in the form of hybrid circuits or discrete circuits. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the present invention can be implemented in other transistor technologies, such as BJT, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the present invention are particularly useful when fabricated using an SOI- or SOS-based process or a process with similar characteristics. Fabrication using an SOI or SOS process in CMOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all cells, allowing them to be compensated).

[0126] Depending on the specific specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), the voltage levels can be adjusted, and / or the voltage and / or logic signal polarities can be inverted. Component voltage, current, and power handling capabilities can be adjusted as needed, e.g., by adjusting device size, connecting "stacked" components in series (especially FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering the function of the disclosed circuit.

[0127] Conclusion

[0128] Multiple embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the present invention. For example, some of the steps described above can be independent of the order and can therefore be performed in an order different from the described order. In addition, some of the steps described above can be optional. The various activities described with respect to the methods identified above can be performed in a repetitive, serial, and / or parallel manner.

[0129] It should be understood that the foregoing description is intended to illustrate and not limit the scope of the present invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims. In particular, the scope of the present invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracketed notations of claim elements are for convenience of reference to such elements and do not themselves indicate a particular required order or enumeration of the elements; furthermore, such notations may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting sequence of notations).

Claims

1. A dual low dropout circuit configuration, comprising: (a) A first low dropout circuit, the first low dropout circuit including a first transistor circuit configured to be coupled between a first voltage source and a target circuit, the first low dropout circuit being configured to selectively apply a first voltage to a voltage input node of the target circuit; And (b) A second low dropout circuit, the second low dropout circuit including a second transistor circuit configured to be coupled between a second voltage source and the target circuit, the second low dropout circuit being configured to selectively apply a second voltage to the voltage input node of the target circuit.

2. The invention according to claim 1, wherein, The first voltage source is the same as the second voltage source.

3. The invention according to claim 1, wherein, The first voltage source is different from the second voltage source.

4. The invention according to claim 1, wherein, The first transistor circuit includes a FET having a gate, and also includes a pull-up FET, the pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET.

5. The invention according to claim 1, wherein, The first transistor circuit includes a FET having a gate, and also includes a discharge FET, the discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

6. The invention according to claim 1, wherein, The first transistor circuit includes a FET having a gate, and also includes: (a) A pull-up FET, the pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET; and (b) A discharge FET, the discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

7. The invention according to claim 1, wherein, At least one of the first transistor circuit and the second transistor circuit is implemented as a FET, BJT, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT or MESFET circuit.

8. A dual low dropout circuit configuration for regulating the current flowing through a power FET having a gate, comprising: (a) A first low dropout circuit for regulating the current flowing through the power FET, the first low dropout circuit including a first FET circuit configured to be coupled between a first voltage source and the gate of the power FET, the first low dropout circuit being configured to selectively apply at least a first voltage or a lower second voltage to the gate of the power FET, such that the current flowing through the power FET in the on state is higher when the first voltage is applied and lower when the lower second voltage is applied; And (b) A second low dropout circuit for regulating the current flowing through the power FET, the second low dropout circuit including a second FET circuit configured to be coupled between a second voltage source and the gate of the power FET, the second low dropout circuit being configured to selectively apply at least a third voltage or a lower fourth voltage to the gate of the power FET such that the current flowing through the power FET in the on state is higher when the third voltage is applied and lower when the lower fourth voltage is applied.

9. The invention according to claim 7, wherein, The first voltage source is the same as the second voltage source.

10. The invention according to claim 7, wherein, The first voltage source is different from the second voltage source.

11. The invention according to claim 7, wherein, The lower second voltage and the lower fourth voltage are applied to limit excessive current from flowing through the power FET.

12. The invention according to claim 7, wherein, The first FET circuit includes a FET having a gate, and also includes a pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET.

13. The invention according to claim 7, wherein, The first FET circuit includes a FET having a gate, and also includes a discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

14. The invention according to claim 7, wherein, The first FET circuit includes a FET having a gate, and also includes: (a) A pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET; and (b) A discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

15. The invention according to claim 7, wherein, The first low dropout circuit and the second low dropout circuit each include a voltage control circuit, wherein each voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between a reference potential and the corresponding first or second FET circuit.

16. A low dropout circuit configuration configured to couple a voltage input node of a driver circuit for a power FET having a gate and to couple to the gate of the power FET, the low dropout circuit configuration comprising: (a) A first full-drive low dropout circuit including a first FET circuit configured to be coupled between a first voltage source and the driver circuit, the first full-drive low dropout circuit being configured to selectively apply a first voltage to the voltage input node of the driver circuit; And (b) A second full-drive low dropout circuit including a second FET circuit configured to be coupled between a second voltage source and the driver circuit, the second full-drive low dropout circuit being configured to selectively apply a second voltage to the voltage input node of the driver circuit; (c) A first reduced-drive low-dropout circuit for regulating the current flowing through the power FET, the first reduced-drive circuit including a third FET circuit configured to be coupled between a third voltage source and the gate of the power FET, the first reduced-drive low-dropout circuit being configured to selectively apply to the gate of the power FET at least the third voltage or a lower fourth voltage, such that the current flowing through the power FET in the on state is higher when the third voltage is applied and lower when the lower fourth voltage is applied; and (d) A second reduced-drive low-dropout circuit for regulating the current flowing through the power FET, the second reduced-drive circuit including a fourth FET circuit configured to be coupled between a fourth voltage source and the gate of the power FET, the second reduced-drive low-dropout circuit being configured to selectively apply to the gate of the power FET at least a fifth voltage or a lower sixth voltage, such that the current flowing through the power FET in the on state is higher when the fifth voltage is applied and lower when the lower sixth voltage is applied.

17. The invention according to claim 15, wherein, The first voltage source is the same as the second voltage source.

18. The invention according to claim 15, wherein, The first voltage source is different from the second voltage source.

19. The invention according to claim 15, wherein, The third voltage source is the same as the fourth voltage source.

20. The invention according to claim 15, wherein, The third voltage source is different from the fourth voltage source.

21. The invention according to claim 15, wherein, The lower fourth voltage and the lower sixth voltage are applied to limit excessive current from flowing through the power FET.

22. The invention according to claim 15, wherein, The first FET circuit or the third FET circuit of at least one of the first full-drive low-dropout circuit or the first reduced-drive low-dropout circuit includes a FET having a gate, and further includes a pull-up FET having (1) a conductive channel coupled between (a) a corresponding first voltage source or third voltage source and (b) the gate of the FET, and (2) a gate coupled to the gate of the FET.

23. The invention according to claim 15, wherein, The first FET circuit or the third FET circuit of at least one of the first full-drive low-dropout circuit or the first reduced-drive low-dropout circuit includes a FET having a gate, and further includes a discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

24. The invention according to claim 15, wherein, The first FET circuit or the third FET circuit of at least one of the first full-drive low-dropout circuit or the first reduced-drive low-dropout circuit includes a FET having a gate, and further includes: (a) A pull-up FET having (1) a conductive channel coupled between (a) a corresponding first voltage source or third voltage source and (b) the gate of the FET, and (2) a gate coupled to the gate of the FET; and (b) A discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is active, the discharge FET discharges the gate of the FET.

25. The invention according to claim 15, wherein, The first low dropout circuit with reduced drive and the second low dropout circuit with reduced drive each include a voltage control circuit, wherein each voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the reference potential and the corresponding first or second FET circuit.

26. A dual low dropout circuit configuration for controlling current flowing through a power FET having a gate, comprising: (a) A first low dropout circuit including a first FET circuit configured to be coupled between a first voltage source and the gate of the power FET, the first low dropout circuit being configured to selectively apply a first voltage to the gate of the power FET; (b) A second low dropout circuit including a second FET circuit configured to be coupled between a second voltage source and the gate of the power FET, the second low dropout circuit being configured to selectively apply a second voltage to the gate of the power FET; And (c) A shared reduced gate drive circuit capable of being coupled to the first FET circuit and / or the second FET circuit; wherein the shared reduced gate drive circuit is configured to selectively reduce the first voltage to a third voltage or reduce the second voltage to a fourth voltage such that the current flowing through the power FET in the on state is higher when the first voltage or the second voltage is applied and lower when the third voltage or the fourth voltage is applied.

27. The invention according to claim 25, wherein, The shared reduced gate drive circuit includes: (a) A variable current source coupled to the switch; (b) A diode coupled between the switch and the reference potential; and (c) A voltage control circuit coupled in parallel with the diode.

28. According to the invention of claim 26, wherein, The voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein when coupled, the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the reference potential and the FET circuit of the first low dropout circuit or the FET circuit of the second low dropout circuit.

29. According to the invention of claim 25, wherein, The first voltage source is the same as the second voltage source.

30. According to the invention of claim 25, wherein, The first voltage source is different from the second voltage source.

31. According to the invention of claim 25, wherein, The lower third voltage and the lower fourth voltage are applied to limit excessive current from flowing through the power FET.

32. According to the invention of claim 25, wherein, The first FET circuit includes a FET having a gate, and further includes a pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET.

33. According to the invention of claim 25, wherein, The first FET circuit includes a FET having a gate, and further includes a discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

34. According to the invention of claim 25, wherein, The first FET circuit includes a FET having a gate, and further includes: (a) a pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET; and (b) a discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

35. A power converter including a power FET having a gate, the power converter comprising: (a) A first low-dropout circuit for regulating the current flowing through the power FET, the first circuit including a first FET circuit configured to be coupled between a first voltage source and the gate of the power FET, the first low-dropout circuit being configured to selectively apply at least a first voltage or a lower second voltage to the gate of the power FET, such that the current flowing through the power FET in the on state is higher when the first voltage is applied and lower when the lower second voltage is applied; And (b) A second low-dropout circuit for regulating the current flowing through the power FET, the second circuit including a first FET circuit configured to be coupled between a second voltage source and the gate of the power FET, the second low-dropout circuit being configured to selectively apply at least a third voltage or a lower fourth voltage to the gate of the power FET, such that the current flowing through the power FET in the on state is higher when the third voltage is applied and lower when the lower fourth voltage is applied.

36. According to the invention of claim 34, wherein, During dynamic reconfiguration of the conversion ratio of the power converter, one of the first low-dropout circuit or the second low-dropout circuit that is selected applies the corresponding lower second voltage or lower fourth voltage to the gate of the power FET.

37. According to the invention of claim 34, wherein, The first low-dropout circuit and the second low-dropout circuit are configured to limit the current flowing through the power FET when a potentially destructive event occurs.

38. According to the invention of claim 36, wherein, The potentially destructive event is caused by dynamic reconfiguration of the conversion ratio of the power converter.

39. According to the invention of claim 36, wherein, The potentially destructive event is caused by startup of the power converter.

40. According to the invention of claim 36, wherein, The potentially destructive event is caused by charge rebalancing between two or more capacitors within the power converter.

41. According to the invention of claim 36, wherein, The first voltage source is the same as the second voltage source.

42. According to the invention of claim 36, wherein, The first voltage source is different from the second voltage source.

43. The invention according to claim 36, wherein, The lower second voltage and the lower fourth voltage are applied to limit excessive current from flowing through the power FET.

44. The invention according to claim 36, wherein, The first FET circuit includes a FET having a gate, and further includes a pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET.

45. The invention according to claim 36, wherein, The first FET circuit includes a FET having a gate, and further includes a discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

46. The invention according to claim 36, wherein, The first FET circuit includes a FET having a gate, and further includes: (a) A pull-up FET having (1) a conductive channel coupled between the first voltage source and the gate of the FET, and (2) a gate coupled to the gate of the FET; and (b) A discharge FET having (1) a conductive channel coupled between the gate of the FET and a reference potential, and (2) a gate coupled to a control signal, wherein when the control signal is valid, the discharge FET discharges the gate of the FET.

47. The invention according to claim 36, wherein, The first low-dropout circuit and the second low-dropout circuit each include a voltage control circuit, wherein each voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between a reference potential and the corresponding first or second FET circuit.

48. A method for supplying power to a voltage input node of a target circuit, comprising: (a) Coupling a first low-dropout circuit between a first voltage source and the voltage input node of the target circuit, the first low-dropout circuit including a first FET circuit configured to selectively apply a first voltage to the voltage input node of the target circuit; and (b) Coupling a second low-dropout circuit between a second voltage source and the voltage input node of the target circuit, the second low-dropout circuit including a second FET circuit configured to selectively apply a second voltage to the voltage input node of the target circuit.

49. The method according to claim 47, wherein, The first voltage source is the same as the second voltage source.

50. The method according to claim 47, wherein, The first voltage source is different from the second voltage source.

51. The method according to claim 47, wherein, The first FET circuit includes a FET having a gate, and further includes: (a) Coupling the conductive channel of the pull-up FET between the first voltage source and the gate of the FET; and (b) Coupling the gate of the pull-up FET to the gate of the FET.

52. The method according to claim 47, wherein, The first FET circuit includes a FET having a gate, and further includes: (a) Coupling the conductive channel of the discharge FET between the gate of the FET and a reference potential; (b) Coupling the gate of the discharge FET to a control signal; and (c) Selectively validating the control signal to cause the discharge FET to discharge the gate of the FET.

53. The method according to claim 47, wherein, The first low dropout circuit and the second low dropout circuit are full-drive low dropout circuits.

54. The method according to claim 47, wherein, The first low dropout circuit and the second low dropout circuit are reduced-drive low dropout circuits.

55. A method for supplying power to a voltage input node of a driver circuit for a power FET having a gate and to the gate of the power FET, the method comprising: (a) Couple a first low dropout circuit between a first voltage source and the voltage input node of the driver circuit, the first low dropout circuit including a first FET circuit configured to selectively apply a first voltage to the voltage input node of the driver circuit; (b) Couple a second low dropout circuit between a second voltage source and the voltage input node of the driver circuit, the second low dropout circuit including a second FET circuit configured to selectively apply a second voltage to the voltage input node of the driver circuit; (c) Couple a first reduced-drive low dropout circuit between a third voltage source and the gate of the power FET, the first reduced-drive circuit including a third FET circuit configured to selectively apply at least a third voltage or a lower fourth voltage to the gate of the power FET such that the current flowing through the power FET in the on state is higher when the third voltage is applied and lower when the lower fourth voltage is applied; And (d) Couple a second reduced-drive low dropout circuit between a fourth voltage source and the gate of the power FET, the second reduced-drive circuit including a fourth FET circuit configured to selectively apply at least a fifth voltage or a lower sixth voltage to the gate of the power FET such that the current flowing through the power FET in the on state is higher when the fifth voltage is applied and lower when the lower sixth voltage is applied.

56. The method according to claim 54, wherein, The first voltage source is the same as the second voltage source.

57. The method according to claim 54, wherein, The first voltage source is different from the second voltage source.

58. The method according to claim 54, wherein, The third voltage source is the same as the fourth voltage source.

59. The method according to claim 54, wherein, The third voltage source is different from the fourth voltage source.

60. The method according to claim 54, further comprising selectively applying one of the lower fourth voltage or the lower sixth voltage to limit an excessive current flowing through the power FET.

61. The method according to claim 54, wherein, The first FET circuit or the third FET circuit of at least one of the first full-drive low dropout circuit or the first reduced-drive low dropout circuit includes a FET having a gate, and further includes: (a) Couple the conductive channel of the pull-up FET between the gate of the FET and the corresponding one of the first voltage source or the third voltage source; and (b) Couple the gate of the pull-up FET to the gate of the FET.

62. The method according to claim 54, wherein, The first FET circuit or the third FET circuit of at least one of the first full-drive low dropout circuit or the first reduced-drive low dropout circuit includes a FET having a gate, and further includes: (a) Couple the conductive channel of the discharge FET between the gate of the FET and a reference potential; (b) Couple the gate of the discharge FET to a control signal; and (c) Selectively enable the control signal to discharge the gate of the FET by the discharge FET.

63. The method according to claim 54, wherein, The first reduced-drive low dropout circuit and the second reduced-drive low dropout circuit each include a voltage control circuit, wherein each voltage control circuit includes: (a) A switch; (b) First diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between a reference potential and a respective first or second FET circuit.

Images