Accurately reduced gate drive current limiter

Abstract

Circuits and methods of limiting current through a power FET of a power converter to reduce destructive current inrush events, irrespective of switching frequency, device mismatch, and PVT variations. Embodiments utilize a closed loop feedback circuit and / or a calibration compensation circuit to adjust a control voltage VGATE applied to the gate of the power FET substantially independently of frequency. In a reduced gate drive mode, a feedback or compensation circuit is connected to the gate of the LDO source follower FET, enabling adjustment of the gate voltage to control the LDO output voltage to a final inverter coupled to the gate of the power FET, thereby adjusting the VGATE to provide reduced gate drive to the power FET; an output connected to the LDO enables direct regulation of the LDO output voltage to the final inverter to regulate the VGATE; a gate connected to the power FET enables direct setting of the VGATE.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 959,904, filed on October 4, 2022, the content of which is incorporated herein by reference in its entirety. The present invention may be related to U.S. Patent Application No. 17 / 331,594, filed on May 26, 2021, which is published as U.S. 2022 / 0385178 and titled "Dynamic Division Ratio Charge Pump Switching", and is assigned to the assignee of the present invention, the content of which is incorporated by reference. Background Art (1) Technical Field

[0003] The present invention relates to electronic circuits, and more particularly to power converter circuits, including DC - DC converter circuits and current limiting circuits for such converter circuits. (2) Background

[0005] Many electronic products, especially mobile computing and / or communication products and components (e.g., notebook computers, ultra - book computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a radio frequency (RF) transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuitry may require a low voltage level (e.g., 1V to 2V). There are other circuitry systems that may require intermediate voltage levels (e.g., 5V to 10V).

[0006] Power converters are commonly used to generate lower or higher voltages from a common power source such as a battery. One type of power converter includes a converter circuit (e.g., a charge pump based on a switched - capacitor network), control circuitry, and in some embodiments, auxiliary circuitry such as a bias voltage generator, a clock generator, a voltage regulator, a voltage control circuit, etc. As used in this disclosure, the term "charge pump" refers to a switched - capacitor network that is configured to boost or buck V IN to V OUT . Examples of such charge pumps include cascaded multipliers, Dickson, Ladder, series - parallel, Fibonacci, and Doubler switched - capacitor networks, all of which can be configured as multi - phase networks or single - phase networks. Switched - capacitor network DC - DC converters are typically integrated circuits (ICs) that may have some external components (e.g., capacitors), and in most cases are characterized by having a fixed VIN With V OUT Conversion ratio (e.g., 2-step or 3-step). An AC-DC power converter can be constructed from a DC-DC power converter, for example, by first rectifying the AC input to a DC voltage and then applying the DC voltage to the DC-DC power converter.

[0007] To provide system designers with greater flexibility and to handle applications where the power supply may need to vary with different conversion ratios (e.g., when the battery discharges and outputs a lower voltage or when the power supply of the device switches between a battery and an AC-DC power line source), it is useful to utilize a DC-DC power converter with a selectable conversion ratio. For example, U.S. Patent No. 10,263,514B1, entitled "Selectable Conversion Ratio DC-DC Converter," published on April 16, 2019, assigned to the assignee of the present invention and incorporated herein by reference, describes a Dickson DC-DC power converter that can switch between a 2-step operating mode and a 3-step operating mode. As another example, U.S. Patent No. 9,203,299B2, entitled "Controller-Driven Reconfiguration of Switched-Capacitor Power Converter," published on December 1, 2015, now assigned to the assignee of the present invention and incorporated herein by reference, describes other DC-DC power converter architectures with reconfigurable conversion ratios.

[0008] A common problem with many FET-based DC-DC power converter architectures is the need to avoid excessive inrush current during startup of the power converter. For example, for a selectable conversion ratio DC-DC converter of the type shown in U.S. Patent No. 10,263,514B1, if there is no sufficient protection circuitry, when the input voltage V IN is first applied, none of the capacitors (sometimes referred to as "flying capacitors") will be initially charged, and thus current will rush into the circuit. For example, if the ON resistance R ON of the FET power switch is 1 milliohm (0.001 ohm), and V INIf it is 10V, then according to Ohm's law, V = I×R, the inrush current peak is about 10,000 amperes. In the integrated circuit implementation, there are parasitic inductances (e.g., due to on-die conductor wiring and printed circuit board conductor wiring), and these parasitic inductances convert the current peak into a voltage peak according to the following inductor theory: V = L×dI / dt. Such a voltage peak will cause excessive electrical stress on the charge pump power switch, affecting its reliability and even potentially causing its damage. For a 1ns 100A pulse that generates 10V across the charge pump power switch, the parasitic inductance only needs to be about 100pH. The resulting 10V peak may exceed the breakdown voltage of many FET switches in the FET switch, and of course, for the same parasitic inductance, a larger current peak will result in a larger voltage peak.

[0009] Related problems occur when the flying capacitors of the DC-DC power converter are unbalanced, which means there is a charge difference between the flying capacitors connected through the power switch. If the charge balance is not maintained, current peaks and the resulting destructive voltage peaks may occur.

[0010] Therefore, it would be useful to be able to mitigate or eliminate events in the power converter that can be characterized as "potentially destructive events" (e.g., destructive current peaks that may occur due to various reasons, including inrush current, charge transfer current, short circuit, EMI events, etc.). Summary of the Invention

[0011] The present invention provides circuits and methods for limiting the current through the power FET of a power converter independently of the converter switching frequency, device mismatch, and process, voltage, and temperature (PVT) variations, thereby mitigating or eliminating potentially destructive events. Such circuits and methods provide protection against potentially destructive events (e.g., current peaks during "soft start" and dynamic charge balance of the power converter) without the need for additional circuitry for these functions.

[0012] Embodiments of the present invention may have some or all of the following advantages: a current limit value independent of the power converter switching frequency, device mismatch, and process, voltage, and / or temperature (PVT) variations; accurate soft start current limiting; reliable operation of the power FET in a power converter with a reconfigurable conversion ratio when the conversion ratio is dynamically changed; and the ability to maintain a stable output voltage when the power converter is operating at full load under different operating and PVT conditions.

[0013] Compared with the open-loop implementation of the LDO power supply, embodiments of the present invention utilize an additional closed-loop feedback circuit and / or an additional calibration compensation circuit to tightly control the control voltage V applied to the gate of the power FET in a substantially frequency-independent mannerGATE Depending on the nature of the added circuitry, it can be connected to the LDO power supply at one of several nodes. Connecting a feedback or compensation circuit to the gate of the LDO source follower FET enables adjustment of the gate voltage of the source follower FET to control the LDO output voltage to the final inverter coupled to the gate of the power FET, such that V is adjusted GATE to provide a reduced gate drive to the power FET. Connecting a feedback or compensation circuit at the output of the LDO power supply enables direct adjustment of the LDO output voltage to the final inverter, such that V is adjusted GATE to provide a reduced gate drive to the power FET. Connecting a feedback or compensation circuit to the gate of the power FET enables direct setting of V GATE to provide a reduced gate drive to the power FET.

[0014] Details of one or more embodiments of the invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of one embodiment of a DC-DC selectable conversion ratio power converter.

[0016] Figure 2 is a block diagram of a portion of the power converter, showing implementation details of the main switches of a portion.

[0017] Figure 3 is Figure 2 a schematic diagram of one embodiment of the LDO power supply of

[0018] Figure 4A is a graph showing the gate voltage V CP1 of FET M GS and the current I CP1 through FET M MAIN as a function of time at a switching frequency of kHz in a reduced gate drive operating mode.

[0019] Figure 4B is a graph showing the gate voltage V CP1 of FET M GS and the current I CP1 through FET M MAIN as a function of time at a switching frequency of 1 MHz in a reduced gate drive operating mode.

[0020] Figure 5 is a block diagram of the LDO power supply circuit, showing possible connection nodes A, B, and C for adding a feedback or compensation circuit.

[0021] Figure 6A is the block diagram of the first embodiment of an enhanced LDO power supply that uses the closed-loop direct complement of V GS_SF .

[0022] Figure 6B is a graph showing the current I CP1 through the FET M at a switching frequency of 1 MHz in a reduced gate drive operating mode MAIN versus time.

[0023] Figure 7A is the block diagram of an example circuit for generating a complementary feedback offset current I OFFSET .

[0024] Figure 7B is a schematic diagram of the first example embodiment of a current-to-voltage converter.

[0025] Figure 7C is a schematic diagram of the second example embodiment of a current-to-voltage converter.

[0026] Figure 8 is the block diagram of the second embodiment of an enhanced LDO power supply.

[0027] Figure 9A is a graph of V GATE versus time without the benefits of a compensated boost.

[0028] Figure 9B is a graph of V GS_SF versus time showing the periodic enhancement of the normal 2V CHG voltage provided by the application of a compensated boost V GS at node A.

[0029] Figure 9C is a graph of V LDO_OUT2 versus time showing the periodic enhancement of the normal reduced gate drive output voltage due to the application of a properly scaled compensated boost V Figure 5 to node A or node B (see CHG ).

[0030] Figure 9D is a graph of V GATE versus time that has the benefits of a compensated boost to V LDO_OUT2 .

[0031] Figure 10 is the block diagram of the third embodiment of an enhanced LDO power supply.

[0032] Figure 11 is the block diagram of the fourth embodiment of an enhanced LDO power supply.

[0033] Figure 12 It is a block diagram of a fifth embodiment of an enhanced LDO power supply.

[0034] Figure 13 It is a schematic diagram of an LDO.

[0035] Figure 14 It is a top view of a substrate that can be, for example, a printed circuit board or a substrate of a chip module (e.g., a thin film ceramic board).

[0036] Figure 15 It is a process flow diagram showing a first method for protecting a power converter.

[0037] Figure 16 It is a process flow diagram showing a second method for protecting a power converter.

[0038] Figure 17 It is a process flow diagram showing a third method for protecting a power converter.

[0039] Similar reference numerals and names in the various figures indicate similar elements. Detailed Embodiments

[0040] The present invention provides circuits and methods for limiting the current through a power FET of a power converter, thereby mitigating or eliminating potential destructive events, independent of the converter switching frequency, device mismatch, and process, voltage, and temperature (PVT) variations. Such circuits and methods provide protection against potential destructive events (such as current spikes during "soft start" and dynamic charge balancing of a power converter) without the need to add circuitry for those functions.

[0041] Example Selectable Conversion Ratio Power Converter

[0042] Figure 1 It is a block diagram of an embodiment of a DC-DC selectable conversion ratio power converter 100. The specifically shown power converter 100 can be selectively configured as a 2-step Dickson converter or a 3-step Dickson converter using the same basic circuit. By inverting the voltage input and voltage output, the same converter 100 can be used for DC to DC boost conversion. The shown power converter 100 includes being coupled to a voltage source V INTwo parallel sections 102a, 102b between a reference potential 104, e.g., a circuit ground. Each section 102a, 102b includes three switches S1 to S3 connected in series. The switches S1 to S3 are serially coupled to a first branch including two switches S4 to S5 connected in series and a second branch including two switches S6 to S7 connected in series. Each switch may include, for example, one or more FETs, and the one or more FETs include one or more MOSFETs.

[0043] In each section 102a, 102b, first capacitors C1a, C1b are coupled between the first upper pair of switches S1, S2 and the first branch pair of switches S4, S5, and second capacitors C2a, C2b are coupled between the second upper pair of switches S2, S3 and the second branch pair of switches S6, S7. Depending on the output ratio configuration (2-voltage division or 3-voltage division), each section 102a, 102b generates an output voltage at a node V OUT coupled to an output capacitor C X .

[0044] At least some of the switches S1 to S7 can be selectively controlled to an ON (conducting) or OFF (non-conducting) state by a control circuitry (not shown). At least some of the switches S1 to S7 can be selectively coupled to one of two non-overlapping complementary clock phases P1 or P2. Some of the switches S1 to S7 can be permanently coupled to one of two complementary clock phases P1 or P2. For both the 2-voltage division configuration and the 3-voltage division configuration, Table 1 below shows the configuration of the state or associated clock phase of each of the switches S1 to S7 of the two parallel sections 102a, 102b.

[0045] Table 1

[0046]

[0047] Note that the clock phase association of section 102b is complementary to that of section 102a. The complementary phases of the two parallel sections 102a, 102b provide output ripple smoothing and additional current capacity. To provide even greater current capacity, additional sections may also be included. The complementary pairs of the additional sections can be phase-controlled by clock signals spaced 180° and having a phase different from P1 or P2 to provide further output ripple smoothing (e.g., 45° or 60° - or multiples of 45° or 60° - out of phase with respect to P1 and P2).

[0048] In a FET-based implementation, the ON / OFF control signal or clock phase signal is coupled to the gates of each of the switches S1 to S7 through at least a driver circuit, and in many cases, is coupled to the gates of each of the switches S1 to S7 through both a level shifter circuit and a driver circuit (see Figure 2 ).

[0049] In any configuration, non-overlapping complementary clock signals P1, P2 turn on or off associated power switches, causing charge to transfer from the flying capacitors C1a, C1b, C2a, C2b to C OUT such that a voltage of V OUT / X is generated across C IN , where X = 2 or 3. U.S. Patent No. 10,263,514 B1 elaborates additional operational details of this DC-DC selectable conversion ratio power converter and similar power converters.

[0050] Limiting Inrush Current During Soft Start

[0051] As described above, destructive current spikes in a power converter can occur for various reasons, including inrush current, charge transfer current, short circuits, etc. For example, for a DC-DC power converter with a selectable conversion ratio, switching from one conversion ratio (e.g., 2 voltage division or "DIV2") to another conversion ratio (e.g., 3 voltage division or "DIV3") may cause charge imbalance across the flying capacitors, resulting in potentially destructive inrush current. Thus, a common practice for avoiding potentially destructive events is to turn off the DC-DC power converter so that the flying capacitors can discharge, change the conversion ratio configuration (e.g., by changing the clock phases of switches S1 to S7 as needed), and turn the power back on, thus relying on the conventional startup circuitry to mitigate the inrush current spike. The drawback of this practice is that the process may take several milliseconds to complete and cannot be done under load.

[0052] One aspect of the present invention includes circuitry and methods for mitigating or eliminating potentially destructive events if a potentially destructive event occurs or is about to occur (e.g., pre-known, such as when the conversion ratio is to be dynamically changed). Mitigating or eliminating potentially destructive events enables switching a selectable conversion ratio DC-DC power converter from one conversion ratio to another under load without turning off the power converter circuitry or pausing the switching of the charge pump power switches.

[0053] As described in U.S. Patent Application Serial No. 17 / 331,594, it is desirable, and often necessary, to limit the current drawn by a power converter from an input power source during startup to avoid high inrush current, especially when dynamically changing the conversion ratio of the power converter. Refer to Figure 1, during the "soft start" period before the steady-state operation of the power converter 100, a conceptual solution is to enable current sources 106a, 106b respectively coupled to sections 102a, 102b, and operate switches S1 to S7 such that the flying capacitors C1a, C1b, C2a, C2b can be charged to a sufficient state through the current sources 106a, 106b to prevent current spikes. More specifically, the current sources 106a, 106b can be coupled between the node between V IN and the node between switches S1 and S2, which node is also coupled to the respective flying capacitors C1a, C1b. Closing switch S2 during the soft start period can also couple the current sources 106a, 106b to the respective flying capacitors C2a, C2b.

[0054] One way to implement the current sources 106a, 106b is to serially couple a power switch and a resistor between the node between V IN and the node between switches S1 and S2 (so the power switch and the resistor are coupled in parallel with switch S1). During the soft start period, closing the power switch creates a high-impedance path to limit the start-up current. Once the voltage V OUT of the power converter output approaches its regulated value, the power switch is turned off. However, such an implementation requires a very large FET for the power switch to withstand the voltage and current during start-up and thus requires a large amount of integrated circuit (IC) chip area (up to about 25% in some embodiments).

[0055] In U.S. Patent Application Serial No. 17 / 331,594, it is recognized that switch S1 and its driver circuitry can be adapted to perform the functions of the current sources 106a, 106b, thus eliminating the need for additional large power switches and resistors. In particular, it is recognized that the power converter switches S1 to S7 typically operate in an "over-driven" or "fully-driven" condition when set to the ON (conducting) state. The gate of an over-driven FET creates a stronger conductive channel, thus effectively reducing the ON resistance R ON of the FET. With this understanding, it is also recognized that increasing R ON for some or all of the power FETs in the power converter (especially switch S1) during a potentially destructive event (e.g., during start-up or when dynamically reconfiguring the conversion ratio of the power converter) will reduce the current flowing through the FET and thus prevent excessive current spikes.

[0056] Figure 2 is a block diagram of a section 102a of the power converter 200, showing details of the implementation of the main switches of a section. Although section 102a is shown, a similar configuration exists for section 102b. In the example shown, switch S1 is implemented as FET M CP1。The clock phase (P1 in this example) is coupled to the input of the driver circuit 204 through a level shifter 202. The output of the driver circuit 204 is coupled to the gate of M CP1 . In the illustrated example, a low-dropout (LDO) power supply 206 supplies power to the level shifter 202 and the driver circuit 204. As described in the above-mentioned U.S. patent application Ser. No. 17 / 331,594, the LDO power supply 206 can selectively increase the R ON of the power FET in the power converter by actively controlling the gate drive voltage of the power FET. During normal operation of the power converter, the power FET drive voltage can be set to overdrive the gate of the FET to reduce R ON to a desired level that allows high current flow for a particular application. However, for other cases (e.g., during soft start), the power FET drive voltage can be reduced such that R ON is increased, thus blocking the current flowing through the power FET to the required level.

[0057] An LDO power supply implementation with reduced gate drive capability

[0058] Figure 3 is Figure 2 a schematic diagram of an implementation of the LDO power supply 206. As Figure 2 shown, the LDO power supply 206 supplies power to the level shifter 202 and the driver 204 coupled to the gate of the associated power FET M CP1 . The input of the gate control circuit (e.g., clock signal P1 or clock signal P2, or ON or OFF control signal) is applied to the input of the level shifter 202. The level shifter 202 converts the input signal from one voltage domain (e.g., digital logic voltage) to another voltage domain (e.g., transistor control voltage). The output of the level shifter 202 thus follows the input signal but in a different voltage range.

[0059] The output of the level shifter 202 is coupled to the input of the driver circuit 204, and the output of the driver circuit 204 is coupled to the gate of the FET M CP1 . In the illustrated example, the driver circuit 204 includes a pre-driver 204a (including a set of three serially coupled inverters in this example) and a serially coupled final inverter 204b. Internally, the final inverter 204b has at least one NMOS FET n and one PMOS FET p, which have a drain-to-drain coupled conductive channel, and the gates of each FET, namely FET n and FET p, are driven by the output of the pre-driver 204a. The drains of the PMOS FET p and the NMOS FET n are coupled to the power FET MCP1 gate of

[0060] In some embodiments, the inverter can increase in physical size from inverter to inverter to provide sufficient current drive capability to charge the gate of FET M CP1 . For example, in the driver circuit 204 having three inverters coupled in series in the pre-driver 204a, the relative size of the first inverter can be "1", the second inverter can be 3 times larger than the first inverter, and the third inverter can be 9 times larger than the first inverter. Finally, the final inverter 204b can be 27 times larger than the first inverter in the pre-driver 204a. The multiplier for each stage can be different from the 1×, 3×, 9×, and 27× ratios, but generally each stage is larger than the previous stage to avoid having very slow rising and falling edges. In an alternative embodiment, the number of inverter stages can be less or more, and non-inverting stages (buffer amplifiers) can be used instead of inverting stages. Therefore, the shown driver circuit 204 is merely exemplary, and other circuits can be used to couple the output of the level shifter 202 to the gate of FET M CP1 gate.

[0061] Power for the level shifter 202 and the driver circuit 204 is provided by the LDO power supply 206. In the example shown, the power supply for the level shifter 202 and the pre-driver 204a is provided by the first LDO section 300. The first LDO section 300 includes a source follower (common drain) amplifier circuit that includes a regulated FET M LDO1 , and the conductive channel (between the drain and the source) of this regulated FET M LDO1 is coupled in series with the resistor R1 between the power supply voltage V DD and the floating reference potential 302. By way of example, the power supply voltage V DD can be V CP1 of a stage of a charge pump that includes FET M IN , or can be coupled to the voltage output from another stage of the charge pump - basically, any voltage that is high enough and has sufficient drive strength for the circuit. The current source 304 is coupled in series with the Zener diode D1 between V DD and the reference potential 302. The current source can be configured from transistors and / or diodes using various circuits. The output of the current source 304 before the Zener diode D1 provides a substantially constant bias voltage to the gate of FET M LDO1 . The bias current flows through the Zener diode D1 and ensures that the diode is always reverse-biased. The source of FET M LDO1 provides the drive voltage V LDO_OUT1 for the level shifter 202 and the pre-driver 204a.

[0062] Unlike a conventional diode that blocks any current from flowing through itself when reverse-biased, a Zener diode starts conducting as long as the reverse voltage reaches a predetermined value. (As long as the current remains between the minimum breakdown current and the maximum rated current of the Zener diode,) the applied reverse voltage remains almost constant even with large variations in the current. The Zener diode continues to regulate its voltage until the holding current of the diode drops below the minimum current value in the reverse breakdown region.

[0063] Finally, the inverter 204b is powered by the second LDO section 306, which includes a source follower FET M LDO2 , the source follower FET M LDO2 whose conductive channel (between the drain and the source) is coupled between the power supply voltage V DD and the final inverter 204b. The gate of the FET M LDO2 is coupled to a separate gate driver circuit that is independent of the gate driver circuitry of the FET M LDO1 . The main function of the gate driver circuit of the second LDO section 306 is to enable at least two different voltage levels at node A to be coupled to the gate of the FET M LDO2 , thereby determining the output voltage level V CP1 provided by the final inverter 204b that drives the associated power FET M GATE . Thus, the associated power FET M CP1 can be placed in (1) an overdriven or "full gate drive" ON state, which has a lower R ON for normal power converter operation; or (2) at least one reduced gate drive ON state that limits current and has a higher R ON , which is selected to provide protection against potential destructive events (such as inrush current or charge transfer current) during, for example, dynamic reconfiguration of the conversion ratio of the power converter, during power converter startup, during charge balancing between flying capacitors within the power converter, or during a fault event (such as a short circuit event).

[0064] The gate driver circuit of the FET M LDO2 includes a current source 308 that is serially coupled with a Zener diode D2 between V DD and the reference potential 302. The gate of the FET M LDO2 is coupled to node A between the current source 308 and the Zener diode D2. The output I BIAS of the current source 308 before the Zener diode D2 provides a substantially constant bias voltage V LDO2 to the gate of the FET M GS_SF。FET M LDO2 The source of FET M provides the drive voltage V to the final driver 204b LDO_OUT2 。

[0065] In parallel with the Zener diode D2 is a voltage control circuit 310, which includes a reduced gate drive switch Sw RGD ,the reduced gate drive switch Sw RGD is serially coupled to a first diode-connected FET M D0 and at least one additional diode-connected FET M DN (where N≥1). As shown, one terminal of the switch Sw RGD is coupled to node A, and one terminal of the additional diode-connected FET M DN is coupled to the floating reference potential 302. Note that the switch Sw RGD can be positioned at any location along the voltage control circuit 310 to interrupt or enable the current flowing through the circuit. For example, the switch Sw RGD as well as the FET M D0 and the FET M DN The order from node A to the floating reference potential 302 can be: (1) Sw RGD 、M D0 、M DN (as shown); (2) M D0 、Sw RGD 、M DN ; or (3) M D0 、M DN 、Sw RGD 。However, as Figure 3 shown by positioning the switch Sw RGD can reduce the parasitic effects on the FET M D0 and / or the FET M DN due to the capacitance of the FET M LDO2 for example.

[0066] The decoupling capacitor C O is coupled between the source of the FET M LDO2 and the floating reference potential 302. The capacitor CV GS is coupled between the gate of the FET M LDO2 and the floating reference potential 302 to keep the voltage across the Zener diode D2 substantially constant when the floating reference potential 302 switches voltage.

[0067] The function of the diode-connected FET M D0 is to cancel out the FET M LDO2 because the FET M D0 is identical to the FET MLDO2 The threshold voltage of FET M is effectively canceled. DN The function is to switch RGD When the current mirror function of the voltage control circuit 310 is activated, the FET M CP1 and FET M DN The size ratio is proportional to the setting of FET M CP1 The current I MAIN More specifically, through FET M CP1 The current I MAIN and the current I from the current source 308 BIAS and FET M DN With FETM CP1 For example, if the output of current source 308 is 1 mA and FET M CP1 The size of FET M DN 1,000 times (W / LM CP1 =1000×W / LM DN ), then through FET M CP1 The maximum current is 1,000×1mA=1A. By ensuring that FET M DN The gate-to-source voltage V GS With FET M CP1 This is achieved by making the gate-to-source voltage of FET M the same. CP1 The maximum gate voltage is the voltage at node A minus the voltage at FET M LDO2 The threshold voltage V TH . Including FET M D0 The voltage at node A increases by a second threshold voltage V GS , so the voltage at node A = (FET M DN V GS )+(FET M D0 V TH ), or 2V GS If FET M LDO2 and FET M D0 Matching (by ratio), then FET M CP1 V GS The maximum value that can be achieved is related to FET M DN V GS The same, and such equality is consistent in terms of process, temperature, etc.

[0068] As mentioned before, the diode connected FET M DN The size of FET M CP1 In some embodiments, FET MLDO1 , FET M LDO2 , FET M D0 and FET M CP1 can be a segmented FET, which means that a device intended to act as a large FET is fabricated as a number (e.g., 10,000) of small FETs connected in parallel (a single small FET can be referred to as a "finger," reflecting a typical aspect of their physical layout on an IC chip). The diode-connected FET M D0 , FET M DN can be fabricated using the same technology but with a much smaller number of FET fingers (e.g., as few as one finger). Due to the source follower configuration of the final inverter 204b and FET M LDO2 , a small change in the current flowing through the voltage control circuit 310 affects the voltage at the gate of FET M LDO2 , resulting in a proportionally larger current I CP1 flowing through the power FET M MAIN , which is determined by the size ratio of FET M CP1 to FET M DN .

[0069] Adding more than one diode-connected FET M DN enables adjustment of the size ratio of FET M CP1 to FET M DN . For example, if FET M CP1 has a width of 100 and 1,000 fingers, the first FET M DN should also have a width of 100 for matching (but may have only 1 finger). Thus, the size ratio of FET M DN to FET M CP1 is 1,000 to 1, and 1 mA from the current source 308 means 1 A through FET M CP1 . To change the size ratio to 2,000 to 1, two diode-connected FET M DN can be connected in series (source to drain). If the FET width remains 100, the effective number of fingers of the two diode-connected FET M DN is halved, resulting in a size ratio of 2,000 to 1 with respect to FET M CP1 .

[0070] As described above, an important function of the gate driver circuit is that it provides a selectable amount of regulated gate bias voltage V LDO2 to FET M GS_SF , which in turn controls the power and voltage output of the final inverter 204b. When the switch Sw RGDWhen open, the voltage control circuit 310 is disconnected from node A—and thus from the gate of FET M LDO2 —and thus has substantially no effect on the output of FET M LDO2 ; thus, the final inverter 204b can overdrive the gate of FET M CP1 to the selected level determined by the Zener diode D2.

[0071] When the switch Sw RGD is closed—for example, during startup of the power converter or when dynamically switching the conversion ratio or rebalancing the charge of the flying capacitors—then the voltage control circuit 310 acts as a bypass to divert current around the diode D2 and reduce the voltage at node A, thereby reducing the drive voltage to FET M LDO2 . The reduced gate drive voltage of FET M LDO2 in turn reduces the power of the final inverter 204b, thereby reducing the gate drive voltage V CP1 of the power FET M GATE . If the drain-source voltage V DS is high enough such that the power FET M CP1 is in saturation, then the power FET M CP1 acts as a controlled current source. If V DS is below the level that would cause the power FET M CP1 to be in saturation, then the power FET M CP1 should be in its linear operating range, and the R ON value increases compared to the R ON value in the normal overdrive state. In either case—saturation-mode controlled current source or linear-mode increased R ON —at least some of the power FETs in the power converter can limit the current in the FETs, thereby suppressing excessive current spikes and protecting the power FETs (and other coupled circuit systems) from large voltage spikes. Selectively varying the I BIAS current controls the V CP1 value applied to the power FET M GATE , enabling selection of different increased R ON values.

[0072] In some embodiments, a control circuit (not shown) can, based on measured parameters (such as V IN , V OUT, the value of the pump capacitor voltage or load current) and / or due to sensed events (such as short - circuit events and / or charge imbalance on the pump capacitor), to enable (trigger) the reduced gate - drive operation of the power FET in the ON state to limit current spikes during potential damaging events. In some embodiments, it can be based on the external control signal of switch Sw RGD that acts before a known upcoming event (such as the dynamic switching of the conversion ratio) to enable (trigger) the reduced gate - drive operation of the power FET in the ON state to limit current spikes during potential damaging events.

[0073] The duration of the reduced gate - drive operation of the power FET can be set to a fixed time suitable for a particular application or can be determined based on some criteria. For example, the reduced gate - drive operation of the power FET can be based on the output load, or on the output load and a selected maximum duration (i.e., timeout parameter), or on a certain percentage (such as 95%) of the voltage across the flying capacitor reaching a desired target level, or some combination of these values and / or other parameters.

[0074] The advantage of using a diode - connected FET in the voltage - control circuit 310 fabricated using the same technology as the power FET (such as an NMOSFET) is that the device basically has matching characteristics with respect to process / voltage / temperature (PVT) variations.

[0075] In summary, the main function of the gate - driver circuit 306 is to enable at least two different voltage levels at node A to be coupled to the gate of FET M LDO2 . More specifically, the voltage - control circuit 310 can selectively switch the voltage at node A between a first voltage level in which the voltage - control circuit 310 is not enabled (switch Sw RGD open) and at least a second voltage level in which the voltage - control circuit 310 is enabled (switch Sw RGD closed).

[0076] It should be understood that although Figure 3 the second LDO section 306 shown in is preferably a device with simple implementation, low required power, and small circuit area, in other embodiments, other devices or circuits providing the same or similar functions can also be used. For example, node A can be coupled through switch Sw RGD to an amplifier with a level - shifted reference voltage as an input; the gate voltage of FETM LDO2 will be more accurate, but at the expense of complexity, circuit area, and power (and thus efficiency).

[0077] Note that Figure 3The LDO power supply 206 (including the second LDO section 306) can be used to power all the FET switches in the power converter 100 to limit the current through these switches as needed (e.g., when dynamically changing the conversion ratio of the power converter 100). In some cases, some FET switches (e.g., Figure 1 switches S5 and S7 in ) do not require the level shifter 202 circuit, and in this case,

[0078] Enhanced LDO power supply implementation with reduced gate drive capability

[0079] In many applications, Figure 3 the LDO power supply 206 works very well at a specified fixed switching frequency (e.g., 400 kHz). However, in some applications, it may not be desirable to switch at the specified fixed frequency during startup or transition periods. Given that the LDO power supply 206 is an open-loop implementation, there may be operational limitations because the current limiting function (reduced gate drive) of the circuit may vary according to the switching frequency of the associated power converter 100.

[0080] For example, Figure 4A is a graph 400 showing the gate voltage V CP1 of FET M GS and the current I CP1 through FET M MAIN over time at a switching frequency of 200 kHz in the reduced gate drive operating mode. Curve 402 shows that at the selected operating frequency of the associated power converter 100, the rise time of V GS in the reduced gate drive mode is approximately 300 nS (compared to approximately 5 nS to 10 nS in the full gate drive mode). Curve 404 shows that due to the reduced gate drive voltage, the corresponding limited current through FETM CP1 fully stabilizes at the selected operating frequency when V GS is stable. In the example shown, the average current I AVG obtained at the selected operating frequency is approximately 850 mA.

[0081] Figure 4B is a graph showing the gate voltage V CP1 of FET M GS and the current I CP1 through FET M MAINGraph 410 over time. Curve 412 shows that at a selected operating frequency of the associated power converter 100, in a reduced gate drive mode, the rise time of V GS is approximately 300 nS (note Figure 4A the different time scales in Figure 4B ). Curve 414 shows that due to the reduced gate drive voltage, the corresponding limited current flowing through FET M CP1 is still rising and has not stabilized at the higher switching frequency when V GS stabilizes. In the example shown, the average current I AVG obtained at the selected operating frequency is approximately 400 mA. The lower amount of the average current I CP1 through FET M AVG during soft start results in a slower startup of the power converter 100. Thus, the IC may not meet the customer's specification requirements. Additionally, if I AVG is much lower than the typical design current value under some IC PVT corners and operating conditions, the LDO power supply 206 may not be able to output the minimum source current required to support the load current.

[0082] The frequency dependence of the LDO power supply 206 can result in a large current spread between the minimum and maximum currents allowed to pass through FET M CP1 . Other possible factors contributing to the large current spread include mismatches between devices (e.g., mismatches between M D0 and M LDO2 and / or mismatches between M DN and M CP1 ), which may also lead to different current limits for different devices, as well as the dependence of the gate rise time of FET M CP1 on process and temperature variations, which adds an additional spread in device current limits. The large current spread may cause the current I CP1 through FET M MAIN to exceed the current handling capacity of the FET or drop below the minimum current required to support the output load. The large current spread also affects the reliability of the device and may cause the output voltage to drop under full output load.

[0083] The present invention provides several enhanced LDO power supply circuits with reduced gate drive capabilities and corresponding methods that accurately limit the power FET current in a reduced gate drive operating mode and are not affected by switching frequency and device mismatch and PVT variations. The LDO power supply circuits of the present invention provide reliable operation for power FETs within a power converter during dynamic reconfiguration of the conversion ratio of the power converter and also provide a smooth output voltage (substantially no voltage drop) when the power converter is operating at full load under different operating conditions and PVT conditions.

[0084] Compared with Figure 3 the open-loop implementation of the LDO power supply 206, embodiments of the present invention utilize an added closed-loop feedback circuit and / or an added calibration compensation circuit to tightly control the control voltage V CP1 applied to the gate of the power FET M GATE . Depending on the nature of the added circuit, the connection to the LDO power supply 206 can be made at one of several nodes. For example, Figure 5 is a block diagram of an LDO power supply circuit 500 showing possible connection nodes A, B, and C for the added feedback or compensation circuit.

[0085] Connecting the feedback or compensation circuit at node A enables adjustment of the gate voltage V LDO2 of the source follower FET M GS_SF to control the V LDO_OUT2 of the final inverter 204b such that V GATE is adjusted to provide a reduced gate drive that is substantially independent of frequency to the power FET M CP1 . Connecting the feedback or compensation circuit at node B enables direct adjustment of the V LDO_OUT2 of the final inverter 204b such that V GATE is adjusted to provide a reduced gate drive that is substantially independent of frequency to the power FET M CP1 . Connecting the feedback or compensation circuit at node C enables direct setting of V GATE to provide a reduced gate drive that is substantially independent of frequency to the power FET M CP1 . Details of several example embodiments of such feedback or compensation circuits are set forth in the following sections.

[0086] A.V GS_SF closed-loop direct supplement

[0087] Figure 6A is a block diagram of a first embodiment of an enhanced LDO power supply 600 utilizing a closed-loop direct supplement of V GS_SF . The enhanced LDO power supply 600 is in most respects the same as Figure 3is similar to the LDO power supply 206, except that the enhanced LDO power supply 600 includes a closed-loop supplementary variable current source 602 coupled to node A, and the closed-loop supplementary variable current source 602 is configured to directly provide an offset current I OFFSET , and the offset current I OFFSET is designed to increase or decrease the gate voltage V LDO2 of the source follower FET M GS_SF . The offset current I OFFSET is proportional to the target reference current I TARGET minus I MAIN or a current value proportional to I MAIN . Therefore, I OFFSET = K * (I TARGET - I MAIN ), where K is a proportionality constant. For example, the proportionality constant can represent the size ratio of FET M DN (inside the voltage control circuit 310) to FET M CP1 .

[0088] In operation, the second LDO section 306 is initially biased by I BIAS . The current passing through the power FET M CP1 is compared with the target reference current, and a feedback offset current I OFFSET is generated based on any difference. In the reduced gate drive mode, any generated value of I OFFSET is added to I BIAS , and when applied through the voltage control circuit 310, it increases or decreases the gate voltage V LDO2 of the source follower FET M GS_SF , thereby increasing I MAIN until I MAIN equals I TARGET . Therefore, Figure 6A is an example of a closed-loop direct supplement for V GS_SF .

[0089] Regardless of the frequency, the feedback loop adapts I MAIN . As an example, Figure 6B is a graph 620 showing the current I CP1 through FET M MAIN over time at a switching frequency of 1 MHz in the operating mode of reduced gate drive. In this example, the average current I AVG at the selected operating frequency is approximately 400 mA (dashed line 622), but rises to approximately 850 mA (dashed line 624) when the feedback offset current I OFFSET is generated and applied (compare Figure 4A , which shows I AVG at 200 KHz)Approximately equal to 850 mA). The supplementary feedback offset current I OFFSET increases the gate voltage V LDO2 of the source follower FET M GS_SF , thereby increasing I MAIN for a period of time.

[0090] The closed-loop supplementary variable current source 602 can use several circuits. For example, Figure 7A is a block diagram of an example circuit for generating the supplementary feedback offset current I OFFSET . The current I CP1 through the power FET M MAIN is coupled to the current-to-voltage converter 702, which generates an output voltage V MAIN proportional to the magnitude of I CP1 . After being filtered by the low-pass filter 704 to obtain an average value, V CP1 is coupled to the first input terminal of the operational transconductance amplifier (OTA) 706. The second input terminal of the OTA 706 is a reference voltage V TARGET proportional to the target reference current I REF . The OTA 706 outputs or absorbs an output current I OFFSET whose magnitude is proportional to the differential input voltage. As described above, the output current I OFFSET is applied to Figure 6A node A in the circuit.

[0091] Figure 7B is a schematic diagram of a first example embodiment of the current-to-voltage converter 702. The output V GATE of the final inverter 204b is shown coupled to the gate of the power FET M CP1 and the gate of the scaled replica FET M REP . The size of the scaled replica FET M REP can be, for example, 0.001% of the size of the power FET M CP1 , and thus has little impact on the operation of the power FET M CP1 , but conducts a current I MAIN proportional to I SENSE . Applying I SENSE through the resistor R generates the output voltage V CP1 .

[0092] Figure 7C is a schematic diagram of a second example embodiment of the current-to-voltage converter 702. The output V GATE of the final inverter 204b is shown coupled to the gate of the power FET M CP1 , and coupled to the scaled replica FET M REPThe gate of. The scaled - down FET M REP can be, for example, 0.001% of the size of the power FET M CP1 and conducts a current I MAIN proportional to I SENSE . I SENSE and I MAIN are both coupled to the respective first and second input terminals of a differential amplifier 708, which produces an output voltage V SENSE proportional to the difference between I MAIN and I OUT . The output voltage V OUT is coupled to the gate of the feedback FET M FB , and the source of the FET M FB is coupled to the first input terminal of the differential amplifier 708. The drain of the feedback FET M FB is coupled to a resistor R, thereby producing an output voltage V CP1 . Figure 7C An advantage of the current - to - voltage converter 702 shown in is that it maintains the same drain - to - source voltage V CP1 across the power FET M REP and the scaled - down FET M DS , thereby producing a more accurate sensed current I SENSE .

[0093] B. V GS_SF 's closed - loop indirect supplement

[0094] Figure 8 is a block diagram of a second embodiment of the enhanced LDO power supply 800. The enhanced LDO power supply 600 is similar in many respects to the Figure 3 LDO power supply 206, except that the enhanced LDO power supply 600 includes circuitry for generating a closed - loop indirect supplement for V GS_SF .

[0095] More specifically, a discrete full - gate drive current source and a reduced - gate drive current source are provided. More specifically, when the full - gate drive switch Sw RGD is closed and the reduced - gate drive switch Sw RGD is open, the full - gate drive current source I FGD is serially coupled with a diode D between V DD and a floating reference potential 302 (such as circuit ground) to drive the gate of the FET M LDO2 . Conversely, in the reduced - gate drive mode, the full - gate drive switch Sw RGD is open, and the reduced - gate drive switch Sw RGD is closed.

[0096] For a reduced gate drive mode, current source I BIAS is serially coupled with resistor R1 between V DD and a floating reference potential 302. The voltage developed across resistor R1 is coupled to a first input of differential amplifier 802. The output of differential amplifier 802 can be selectively coupled to node A, thereby reducing the gate drive switch Sw RGD is coupled to the gate of FET M LDO2 .

[0097] A second input of differential amplifier 802 is coupled to feedback circuit 804, which includes variable current source I SENSE , the variable current source I SENSE is serially coupled with an RC circuit between V DD and a floating reference potential 302. The RC circuit, which includes resistor R2 and capacitor C2 in parallel, acts as a filter and provides an average voltage at the second input of differential amplifier 802. Current source I SENSE can be, for example, a scaled copy of FET M REP , the FET M REP having a gate coupled to the output V GATE of final inverter 204b, as Figure 7B shown. Thus, I SENSE is proportional to I MAIN (e.g., 1 / 10,000 of I MAIN ). The I th current applied to resistor R2 and capacitor C2 provides an average voltage input to differential amplifier 802. Differential amplifier 802 corrects the difference between I SENSE and the closed-loop feedback current I GS_SF by establishing a corresponding V BIAS voltage. Note that in the SENSE embodiment, since the output of differential amplifier 802 is set to a desired level to provide a reduced gate drive voltage, a Zener diode D2 of the type shown in some of the other novel embodiments is not required in the reduced gate drive mode. Figure 8 The advantage of the Figure 8 embodiment is that it generally has low output impedance and high feedback loop stability.

[0098] C. Example Compensation Circuit Coupled to Node A

[0099] Another method of providing a reduced gate drive to power FET M CP1 that is substantially independent of frequency is to apply a calibrated compensating boost to briefly increase the drive capability of LDO power supply 206, thereby counteracting the effects due to power FET MCP1 a relatively large gate capacitance (e.g., about 20 μF in some MOSFET implementations) resulting in a slow rise time of V from the final inverter 204b. In other words, the boost compensation briefly increases the reduced gate drive voltage of the gate of the power FET to compensate for the gate capacitance of the power FET. GATE

[0100] For example, Figure 9A is a graph of V over time without the benefit of boost compensation. As shown by arrow A, the need to charge the relatively large gate capacitance of the power FET M results in a relatively slow rise of V. GATE CP1 GATE Figure 9B is a graph of V over time showing the periodic enhancement of the normal 2V voltage provided if a boost compensation V is applied at node A. GS_SF CHG GS Figure 9C is a graph of V over time showing the periodic enhancement of the normal reduced gate drive output voltage resulting from applying a proper proportion of boost compensation V to node A or node B (see LDO_OUT2 Figure 5 ) CHG Figure 9D is a graph of V over time with the benefit of boost compensation to V. As shown by arrow B, the increased boost compensation V compensates for the otherwise relatively slow rise of V as shown in GATE LDO_OUT2 CHG such that V has a fast, sharp rise. After the boost compensation V times out, the reduced gate drive of the power FET M by the final inverter 204b powered by V from the second LDO section 306 will continue for the remainder of the period. Figure 9A GATE GATE CHG LDO_OUT2 CP1

[0101] Figure 10 is a block diagram of a third embodiment of the enhanced LDO power supply 1000. The enhanced LDO power supply 1000 is similar in most respects to the LDO power supply 206 of Figure 3 except that the enhanced LDO power supply 1000 includes a calibration compensation circuit 1002 that is coupled to node A and is configured to periodically boost the output voltage V to the final inverter 204b. The calibration compensation circuit 1002 includes a substantially fixed current source I LDO_OUT2 CHG CHGcoupled in series with an RC circuit (including resistor R2 and capacitor C2 in parallel in this example) between V DD and a floating reference potential 302. Switch Sw BOOST selectively couples the voltage across resistor R2 and capacitor C2 to node A.

[0102] In operation, capacitor C2 is pre-charged to a level higher than the 2V GS voltage provided by the voltage control circuit 310. When V GATE rises, switch Sw BOOST is periodically closed for a short time (e.g., the state of switch Sw BOOST can be set or triggered by a control signal that tracks the state of the level shifter (if present) and the input to the driver circuit 204). Closing switch Sw transfers charge from capacitor C2 to capacitor C BOOST thereby adding an additional voltage V VGS to V GS_SF The additional voltage V CHG applied to the gate of the source-follower FET M LDO2 compensates (increases) the charge that is very quickly transferred from the LDO capacitor C CHG to the gate capacitance of the power FET M O when the power FET is ON. Such charge transfer makes the edge of V CP1 sharper (as shown in GATE ) and results in the current I Figure 9D through the power FET M CP1 being substantially independent of frequency in a reduced gate drive mode. MAIN By modeling the enhanced LDO power supply 1000, the amount of charge stored in capacitor C2 required for a particular application and the duration of the closed state of switch Sw

[0103] can be determined quite accurately, and in this sense, the circuit is calibrated. BOOST

[0104] D. Example compensation circuit coupled to node B

[0105] Figure 11 is a block diagram of a fourth embodiment of the enhanced LDO power supply 1100. The enhanced LDO power supply 1100 is similar to the enhanced LDO power supply 1000 of Figure 10 in most respects, except that the enhanced LDO power supply 1100 couples the calibration compensation circuit 1002 at node B (which periodically boosts V LDO_OUT2 ) rather than at node A (which periodically boosts the input to the source-follower FET MLDO2 gate voltage V GS_SF boost). The calibration compensation circuit 1002 is connected at node B such that it can be directly adjusted to the V of the final inverter 204b LDO_OUT2 , thereby adjusting V GATE to provide a reduced gate drive to the power FET M CP1 that is substantially independent of frequency. Similarly, by modeling the enhanced LDO power supply 1000, the amount of charge stored in the capacitor C2 required for a particular application and the duration of the closed state of the switch Sw BOOST can be determined quite accurately, and in this sense, the circuit is calibrated.

[0106] In a variant embodiment, the capacitor C2 can be omitted because the current source I CHG can periodically add charge to the capacitor C BOOST through the switch Sw O to compensate for (increase) the charge transferred from the LDO capacitor C O to the gate capacitance of the power FET M CP1 .

[0107] E. Example Compensation Circuit Coupled to Node C

[0108] Figure 12 is a block diagram of a fifth embodiment of the enhanced LDO power supply 1200. Substantially, during normal full gate drive mode, the first LDO section 300 is enabled to provide V CP1 to the power FET M GATE , while the second LDO section 306 is disabled. Conversely, during reduced gate drive mode, the second LDO section 306 is enabled to provide V CP1 to the power FET M GATE , while the first LDO section 300 is disabled.

[0109] In the example shown, the first LDO section 300 provides V LDO_OUT1 to the level shifter 202, the pre-driver 204a, and the final driver 204b, and the output of the second LDO section 306 is coupled to node C (i.e., coupled to the gate of the power FET M CP1 ). The final driver 204b is shown modified to provide the clock signal RGD to the PMOS FET p in the final driver 204b through the OR gate 1102 only when the control signal EN

[0110] The second LDO section 306 is configured to be similar to Figure 10Enhanced LDO power supply 1000. However, the Figure 10 calibration compensation circuit 1002 is omitted, and the source of the source follower FET M LDO2 is connected to node C, and the power supply to the source follower FET M LDO2 is controlled by PFET M1 coupled between V DD and the drain of the source follower FET M LDO2 . The ON or OFF state of FET M1 is controlled by an OR gate 1104, which is coupled to the control signal (the complementary signal of the EN control signal to the OR gate 1102 RGD ) and the output of the pre-driver 204a. In addition, the voltage control circuit 310 is modified to omit Figure 10 switch Sw RGD (since the entire second LDO section 306 only operates during the reduced gate drive mode, this switch Sw RGD is not required), and the diode D2 and capacitor C shown in Figure 10 are omitted O (since the entire second LDO section 306 only operates during the reduced gate drive mode and there is a direct connection to node C, this diode D2 and capacitor C O are not required). Finally, the optional switch Sw RGD2 is between node A and current source I BIAS , and can be disconnected to disable the voltage control circuit 310 (alternatively, the PFET M1 can be disabled using the control signal, enabling the omission of switch Sw RGD2 ).

[0111] In the full gate drive mode, the control signal EN RGD has a low (LOW) (logical 0) value. Therefore, PFET M1 is set to the OFF state by the complementary control signal , and the clock signal is enabled through the coupling of the OR gate 1102 to the PMOS FET p in the final driver 204b. In addition, the switch Sw RGD2 is disconnected. Therefore, the first LDO section 300 is enabled and the second LDO section 306 is disabled.

[0112] In the reduced gate drive mode, the control signal EN RGD has a high (HIGH) (logical 1) value. Therefore, PFET M1 is set to the ON state by the complementary control signal , and the clock signal passes through the OR gate 1104, PFET M1, and the source follower FET MLDO2 The coupling to the gate of power FET M CP1 is enabled. Additionally, switch Sw RGD2 is closed. Accordingly, the first LDO section 300 is disabled and the second LDO section 306 is enabled. The value of V GS_SF is set to 2V by the voltage control circuit 310 GS , and is set to a target reduced gate drive level for V CP1 when power FET M GATE is ON.

[0113] Figure 12 An advantage of the embodiment of CP1 is that when power FET M LDO2 is ON, additional boost is provided to V GD through the gate-drain capacitance C GS_SF of PFET M1 and M LDO2 without the need for additional circuitry. When PFET M1 is ON, the drain of M DD is pulled up to V LDO2 . The C GD capacitance of M LDO2 couples the rising of the charge at the drain of M GS_SF to V CP1 for a short duration, which provides additional charge to the gate of power FET M

[0114] Alternative embodiments

[0115] It should be understood that both the feedback circuit and the compensation circuit can be used together. For example, in some applications, it may be useful to combine the closed-loop direct compensation of V Figure 6A or Figure 8 shown with the compensation circuit 1002 shown GS_SF (connected to node A) or Figure 10 (connected to node B). Figure 11 In addition, while embodiments of the present disclosure focus on the use of the source follower FET M

[0116] , alternative embodiments can use any circuit (e.g., operational amplifier (op amp), OTA, etc.) that provides a reduced gate drive voltage to the final inverter 204b or to the gate of power FET M LDO2 in response to a change in the reference voltage. CP1 Embodiments of the present invention can also be used to accurately limit the startup current in buck / boost power converters and general LDO power supplies. For example,

[0117] is a schematic diagram of an LDO 1300. Current source I Figure 13 is a schematic of LDO 1300. Current source IREF is serially coupled between V and a floating reference potential with an RC circuit 1302 (including a resistor Ra and a capacitor Ca in parallel). A variable current source I DD is coupled between V and the RC circuit 1302. The current source I OFFSET is coupled between V DD and the RC circuit 1302. The current source I OFFSET can be implemented as described in Figure 6A and Figures 7A to 7C . The currents from I REF and I OFFSET generate a voltage V when applied across the RC circuit 1302. The voltage V REF is coupled to a first input of a differential amplifier 1304. The output of the differential amplifier 1304 is coupled to the gate of a power FET M. The conductive channel of the FET M is serially coupled between V REF and a floating reference potential with resistors Rb and Rc. A feedback voltage between the resistors Rb and Rc is coupled to a second input of the differential amplifier 1304. In operation, the current source I IN adjusts the current on the RC circuit 1302 that generates V OFFSET according to the difference between I TARGET and I MAIN until the difference is substantially eliminated. REF

[0118] Advantages

[0119] Embodiments of the present invention may have some or all of the following advantages: a current limit value independent of the power converter switching frequency, device mismatch, and process, voltage, and / or temperature (PVT) variations; an accurate soft start current limit; reliable operation of the power FET in a power converter with a reconfigurable conversion ratio when the conversion ratio is dynamically changed; and the ability to maintain a smooth output voltage when the power converter operates at full load under different operating and PVT conditions.

[0120] Circuit Embodiments

[0121] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as integrated circuits (ICs) that can be packaged in IC packages and / or modules to facilitate handling, manufacturing, and / or improving performance. In particular, IC embodiments of the present invention are often used in modules where one or more ICs in such an IC are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into a single package. The IC and / or module are then typically combined with other components (often on a printed circuit board) to form part of a final product, such as a cellular phone, laptop computer, or electronic tablet, or to form higher-level modules that can be used in a wide variety of products, such as vehicles, test equipment, medical equipment, etc. Through various configurations of the modules and components, such ICs are generally capable of implementing communication modes, often wireless communication.

[0122] As an example of further integration of embodiments of the present invention with other components, Figure 14 is a top view of a substrate 1400 that can be, for example, a printed circuit board or a chip module substrate (e.g., a thin film sheet). In the example shown, the substrate 1400 includes a plurality of ICs 1402a to 1402d having terminal pads 1404, and the terminal pads 804 will be interconnected by conductive vias and / or traces on and / or within the substrate 1400 or on the opposite (rear) surface of the substrate 1400 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). For example, the ICs 1402a to 1402d can include signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1402b can include one or more instances of an enhanced LDO power circuit, such as Figure 6A , Figure 8 , Figure 10 , Figure 11 and / or Figure 12 the circuits shown in.

[0123] The substrate 1400 can also include one or more passive devices 1406 embedded in, formed on, and / or attached to the substrate 1400. Although shown as generally rectangular, the passive devices 1406 can be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., that are interconnected with other passive devices 1406 and / or individual ICs 1402a to 1402d through conductive traces on or in the substrate 1400. The front or rear surface of the substrate 1400 can be used as a location for forming other structures.

[0124] System aspects

[0125] Embodiments of the present invention can be used in a wide variety of applications, including portable computing devices (e.g., laptop computers, notebook computers, mobile phones, tablet computers), data centers and telecommunications centers with battery backup systems, household appliances and electronic products, vehicles (e.g., cars, drones, airplanes, boats, trains, ships), general DC / DC and AC / DC power converters, and radio frequency (RF) circuits and systems.

[0126] Radio system uses can include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, including various types of orthogonal frequency division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), code division multiple access (“CDMA”), time division multiple access (“TDMA”), wideband code division multiple access (“W-CDMA”), global system for mobile communications (“GSM”), long term evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0127] Method

[0128] Another aspect of the present invention includes a method for protecting a power converter. For example, Figure 15 is a process flow diagram 1500 showing a first method for protecting a power converter. The method includes: controlling the ON resistance R of a power FET in the power converter ON , to reduce the R of the power FET in a first ON state during normal power converter operation ON , and to increase the R of the power FET in a second ON state ON , to limit the current flowing through the power FET (block 1502); generating a feedback current proportional to the current flowing through the power FET (block 1504); and in the second ON state, adjusting the R of the power FET proportionally to the generated feedback current ON , to provide a substantially frequency-independent reduced gate drive to the power FET (block 1506).

[0129] Additional aspects of the above method can include one or more of the following aspects: adjusting the R of the power FET proportionally to the generated feedback current in the second ON state during dynamic reconfiguration of the conversion ratio of the power converter ON ; adjusting the R of the power FET proportionally to the generated feedback current in the second ON state during the startup period of the power converter ON; and / or during a charge rebalancing event between two or more capacitors within the power converter, regulate the R of the power FET in proportion to the generated feedback current in the second ON state ON .

[0130] As another example, Figure 16 FIG. 1600 is a flow chart showing a second method for protecting a power converter. The method includes: controlling the ON resistance R of a power FET in the power converter ON , to reduce the R of the power FET in a first ON state during normal power converter operation ON , and to increase the R of the power FET in a second ON state ON , to limit the current flowing through the power FET (block 1602); and applying a compensating boost to the gate of the power FET in the second ON state to increase the drive voltage to the gate to compensate for the gate capacitance of the power FET (block 1604).

[0131] Additional aspects of the above method may include one or more of the following: applying a compensating boost during a dynamic reconfiguration of the conversion ratio of the power converter; applying a compensating boost during a startup period of the power converter; and / or applying a compensating boost during a charge rebalancing between two or more capacitors within the power converter.

[0132] As yet another example, Figure 17 FIG. 1700 is a flow chart showing a third method for protecting a power converter. The method includes: generating a feedback current proportional to the current flowing through the power FET of the power converter when the power FET is in the ON state (block 1702); generating a reduced gate drive voltage proportional to the generated feedback current, wherein the reduced gate drive voltage is substantially independent of frequency (block 1704); and coupling the reduced gate drive voltage to the gate of the power FET to limit the current flowing through the power FET (block 1706).

[0133] Additional aspects of the above method may include one or more of the following: generating a reduced gate drive voltage during a dynamic reconfiguration of the conversion ratio of the power converter; generating a reduced gate drive voltage during a startup period of the power converter; generating a reduced gate drive voltage during a charge rebalancing event between two or more capacitors within the power converter; wherein the reduced gate drive voltage increases the ON resistance R of the power FET ON ; and / or wherein when the power FET is in a saturation operating mode, the reduced gate drive voltage causes the power FET to act as a controlled current limiting source.

[0134] Manufacturing techniques and options

[0135] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate that determines the conductivity of the transistor, and includes an insulated gate having a metal or metalloid, insulator, and / or semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (such as aluminum, copper, or other metals, or highly doped polysilicon, graphene, or other electrical conductors), the "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials), and the "semiconductor" includes at least one semiconductor material.

[0136] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of approximately 3 kHz to approximately 300 GHz. The term also includes the frequencies used in wireless communication systems. The RF frequency can be the frequency of an electromagnetic wave or the frequency of an alternating voltage or current in a circuit.

[0137] Regarding the drawings referenced in this disclosure, the sizes of the various elements are not drawn to scale; for clarity or emphasis, some sizes may be significantly enlarged vertically and / or horizontally. Additionally, references to orientation and direction (e.g., "top", "bottom", "above", "below", "lateral", "vertical", "horizontal", etc.) are relative to the exemplary drawings and are not necessarily absolute orientation or direction.

[0138] Various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise stated above, selecting appropriate component values is a matter of design choice. The various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)) can be used to fabricate the integrated circuit embodiments. Unless otherwise stated above, the embodiments of the present invention can be implemented in other transistor technologies, such as bipolar transistors, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the embodiments of the present invention are particularly useful when fabricated using an SOI- or SOS-based process or a process having similar characteristics. Fabrication using an SOI or SOS process in CMOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all cells, allowing them to be compensated).

[0139] The voltage level can be adjusted, and / or the voltage and / or logic signal polarities can be inverted, in accordance with specific specifications and / or implementation techniques (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). The component voltage, current, and power handling capabilities can be adjusted as needed, e.g., by sizing the devices, "stacking" components (especially FETs) in series to withstand greater voltages and / or using multiple components in parallel to handle greater currents. Additional circuit components can also be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering the functionality of the disclosed circuit.

[0140] Conclusion

[0141] Multiple embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the present invention. For example, some of the above steps can be order-independent and thus can be performed in an order different from the described order. Additionally, some of the above steps can be optional. The various activities described with respect to the methods identified above can be performed in repetitive, serial, and / or parallel fashion.

[0142] It should be understood that the foregoing description is intended to be illustrative, not limiting, of the scope of the present invention, which is defined by the scope of the following claims, and other embodiments are within the scope of the claims. In particular, the scope of the present invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the following claims. (Note that the bracketed designations of claim elements are for ease of reference to such elements and do not themselves indicate a particular required order or enumeration of the elements; furthermore, such designations can be reused in dependent claims as a reference to additional elements without being regarded as starting a conflicting sequence of designations).

Claims

1. A gate control circuit for regulating the gate drive voltage of a power FET, comprising: (a) A source follower circuit, the source follower circuit including a source follower FET having a conductive channel configured to be coupled to the gate of the power FET, the gate control circuit being configured to selectively apply at least a first gate drive voltage or a second gate drive voltage to the gate of the power FET such that when the second gate drive voltage is applied, the current flowing through the power FET in the on state is limited; And (b) A feedback circuit, the feedback circuit being coupled to the gate of the source follower FET and being configured to generate a feedback signal based on the current flowing through the power FET and to adjust the second gate drive voltage based on the generated feedback signal.

2. The invention according to claim 1, wherein, The second gate drive voltage is substantially independent of frequency.

3. The invention according to claim 1, wherein, The power FET is a component of a power converter, and the gate control circuit applies the second gate drive voltage to the gate of the power FET during a dynamic reconfiguration of the conversion ratio of the power converter.

4. The invention according to claim 1, wherein, The power FET is a component of a power converter, and the gate control circuit applies the second gate drive voltage to the gate of the power FET during a startup period of the power converter.

5. The invention according to claim 1, wherein, The power FET is a component of a power converter, and the gate control circuit applies the second gate drive voltage to the gate of the power FET during a charge rebalancing event between two or more capacitors within the power converter.

6. The invention according to claim 1, wherein, The feedback circuit includes: (a) A current-to-voltage converter configured to output a voltage proportional to the current flowing through the power FET; (b) A filter having an input terminal and an output terminal, the input terminal being coupled to the output terminal of the current-to-voltage converter; (c) An amplifier coupled to the output terminal of the filter and coupled to a reference voltage, the amplifier being configured to output the feedback current.

7. The invention according to claim 1, the source follower circuit further comprises: (a) A current source coupled between a voltage source and the gate of the source follower FET; (b) A voltage regulator coupled to the gate of the source follower FET and configured to provide a voltage; And (c) A voltage control circuit coupled to the gate of the source follower FET and including a first selectable configuration disconnected from the gate of the source follower FET and a second selectable configuration coupled to the gate of the source follower FET, wherein the voltage at the gate of the source follower FET is higher when the voltage control circuit is in the first selectable configuration than when the voltage control circuit is in the second selectable configuration.

8. The invention according to claim 7, wherein, The voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; Wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the gate of the source follower FET and a reference potential.

9. The invention according to claim 7, wherein, The voltage regulator is a Zener diode.

10. A gate control circuit for controlling the on-resistance R ON of a power FET in a power converter, comprising: (a) Source follower circuit, the source follower circuit including a source follower FET having a conductive channel configured to be coupled to the gate of the power FET, the gate control circuit being configured to reduce the R of the power FET in a first conduction state during normal power converter operation ON , and increase the R of the power FET in a second conduction state ON to limit the current flowing through the power FET; And (b) A feedback circuit, the feedback circuit being coupled to the gate of the source follower FET and configured to generate a feedback current proportional to the current flowing through the power FET, and to adjust the R of the power FET in proportion to the generated feedback current in the second conduction state ON to provide a reduced gate drive to the power FET.

11. The invention according to claim 10, wherein, The reduced gate drive of the power FET is substantially independent of frequency.

12. The invention according to claim 10, wherein, During reconfiguring the conversion ratio of the power converter, the gate control circuit raises the R of the power FET in the second conduction state ON .

13. The invention according to claim 10, wherein, During a startup period of the power converter, the gate control circuit raises the R of the power FET in the second conduction state ON .

14. The invention according to claim 10, wherein, During a charge rebalancing event between two or more capacitors within the power converter, the gate control circuit raises the R of the power FET in the second conduction state ON .

15. The invention according to claim 10, wherein, The feedback circuit includes: (a) A current-to-voltage converter configured to output a voltage proportional to the current flowing through the power FET; (b) A filter having an input terminal and an output terminal, the input terminal being coupled to the output terminal of the current-to-voltage converter; (c) An amplifier coupled to the output terminal of the filter and a reference voltage, the amplifier being configured to output the feedback current.

16. The invention according to claim 10, wherein, The source follower circuit further includes: (a) A current source coupled between a voltage source and the gate of the source follower FET; (b) A voltage regulator coupled to the gate of the source follower FET and configured to provide a voltage; and (c) A voltage control circuit coupled to the gate of the source follower FET and including a first selectable configuration disconnected from the gate of the source follower FET and a second selectable configuration coupled to the gate of the source follower FET, wherein the voltage at the gate of the source follower FET is higher when the voltage control circuit is in the first selectable configuration than when the voltage control circuit is in the second selectable configuration.

17. The invention according to claim 16, wherein, The voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the gate of the source follower FET and a reference potential.

18. The invention according to claim 16, wherein, The voltage regulator is a Zener diode.

19. A gate control circuit for regulating the on-resistance R ON of a power FET, comprising: (a) Source follower circuit, the source follower circuit including a source follower FET having a conductive channel configured to be coupled to the gate of the power FET and configured to selectively apply at least a first voltage or a second voltage to the gate of the power FET such that when the first voltage is applied, the R of the power FET in the on state ON is lower, and when the second voltage is applied, the R of the power FET in the on state ON is higher; And (b) A compensation circuit coupled to either the gate of the source follower FET or the output of the source follower FET and configured to apply a compensation boost to compensate a second voltage to the gate of the power FET to compensate for the gate capacitance of the power FET.

20. The invention according to claim 19, wherein, The gate control circuit applies the compensation boost during a dynamic reconfiguration of the conversion ratio of the power converter.

21. The invention according to claim 19, wherein, The gate control circuit applies the compensation boost during a startup period of the power converter.

22. The invention according to claim 19, wherein, The gate control circuit applies the compensation boost during a charge rebalancing event between two or more capacitors within the power converter.

23. The invention according to claim 19, wherein, The compensation circuit is configured to be coupled between a supply voltage and a reference potential and includes: (a) A current source configured to be coupled to the supply voltage; (b) A resistor coupled to the current source and configured to be coupled to the reference potential; and (c) A capacitor coupled to the current source and configured to be coupled to the reference potential, wherein the capacitor is in parallel with the resistor.

24. The invention according to claim 19, wherein, The source follower circuit further includes: (a) A current source coupled between a voltage source and the gate of the source follower FET; (b) A voltage regulator coupled to the gate of the source follower FET and configured to provide a voltage; and (c) A voltage control circuit coupled to the gate of the source follower FET and including a first selectable configuration disconnected from the gate of the source follower FET and a second selectable configuration coupled to the gate of the source follower FET, wherein the voltage at the gate of the source follower FET is higher when the voltage control circuit is in the first selectable configuration than when the voltage control circuit is in the second selectable configuration.

25. The invention according to claim 24, wherein, The voltage control circuit includes: (a) A switch; (b) A first diode-connected FET; and (c) At least one additional diode-connected FET; wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are serially coupled between the gate of the source follower FET and a reference potential.

26. The invention according to claim 24, wherein, The voltage regulator is a Zener diode.

27. A gate control circuit for regulating the on-resistance R ON of a power FET, comprising: (a) Source follower circuit, the source follower circuit including a source follower FET having a conductive channel configured to selectively couple to the gate of the power FET and configured to selectively apply a reduced gate drive voltage to the gate of the power FET such that the R of the power FET in the on state ON limits the flow of current through the power FET; And (b) A compensation circuit coupled to either the gate of the source follower FET or the output of the source follower FET and configured to apply a compensation boost to adjust a reduced gate drive voltage to the gate of the power FET to compensate for the gate capacitance of the power FET.

28. The invention according to claim 27, wherein, The gate control circuit applies the compensation boost during a dynamic reconfiguration of the conversion ratio of the power converter.

29. The invention according to claim 27, wherein, The gate control circuit applies the compensation boost during a startup period of the power converter.

30. The invention according to claim 27, wherein, The gate control circuit applies the compensation boost during a charge rebalancing event between two or more capacitors within the power converter.

31. The invention according to claim 27, wherein, The compensation circuit is configured to be coupled between a supply voltage and a reference potential and includes: (a) A current source configured to be coupled to the supply voltage; (b) A resistor coupled to the current source and configured to be coupled to the reference potential; and (c) A capacitor coupled to the current source and configured to be coupled to the reference potential, wherein the capacitor is in parallel with the resistor.

32. The invention according to claim 27, wherein, The source follower circuit further includes: (a) A current source coupled between a voltage source and the gate of the source follower FET; (b) A voltage regulator coupled to the gate of the source follower FET and configured to provide a voltage; and (c) A voltage control circuit coupled to the gate of the source follower FET.

33. The invention according to claim 32, wherein, The voltage control circuit includes: (a) A first diode-connected FET; and (b) At least one additional diode-connected FET; wherein the first diode-connected FET and the at least one additional diode-connected FET are serially coupled between the gate of the source follower FET and a reference potential.

34. The invention according to claim 32, wherein, The voltage regulator is a capacitor.

35. A method for protecting a power converter, comprising: (a) Control the on-resistance R of the power FET in the power converter ON to reduce the R of the power FET in a first on-state during normal power converter operation ON and increase the R of the power FET in a second on-state ON to limit the flow of current through the power FET; (b) Generate a feedback current proportional to the current flowing through the power FET; And (c) In the second conduction state, adjust the R of the power FET ON proportionally to the generated feedback current to provide a reduced gate drive voltage to the power FET.

36. The method according to claim 35, wherein, The reduced gate drive to the power FET is substantially independent of frequency.

37. The method according to claim 35, further comprising: During dynamically reconfiguring the conversion ratio of the power converter, R of the power FET is adjusted proportionally to the generated feedback current in the second conduction state ON .

38. The method according to claim 35, further comprising: During the start-up period of the power converter, the R of the power FET is adjusted proportionally to the generated feedback current in the second conduction state ON .

39. The method according to claim 35, further comprising: During a charge rebalancing event between two or more capacitors within the power converter, the R of the power FET is adjusted in proportion to the generated feedback current in the second conduction state ON .

40. A method for protecting a power converter, comprising: (a) Control the on-resistance R of the power FET in the power converter ON to reduce the R of the power FET in a first on-state during normal power converter operation ON and increase the R of the power FET in a second on-state ON to limit the flow of current through the power FET; And (b) Applying a compensating boost to the gate of the power FET in the second conduction state to adjust the drive voltage to the gate to compensate for the gate capacitance of the power FET.

41. The method according to claim 40, further comprising: The compensating boost is applied during dynamic reconfiguration of the conversion ratio of the power converter.

42. The method according to claim 40, further comprising: The compensating boost is applied during the startup period of the power converter.

43. The method according to claim 40, further comprising: The compensating boost is applied during a charge rebalancing event between two or more capacitors within the power converter.

44. A method for protecting a power converter, comprising: (a) When the power FET is in the conduction state, generating a feedback current proportional to the current flowing through the power FET of the power converter; (b) Generating a reduced gate drive voltage proportional to the generated feedback current; and (c) Coupling the reduced gate drive voltage to the gate of the power FET to limit the flow of current through the power FET.

45. The method according to claim 44, wherein, The reduced gate drive is substantially independent of frequency.

46. The method according to claim 44, further comprising: The reduced gate drive voltage is generated during dynamic reconfiguration of the conversion ratio of the power converter.

47. The method according to claim 44, further comprising: The reduced gate drive voltage is generated during the startup period of the power converter.

48. The method according to claim 44, further comprising: The reduced gate drive voltage is generated during a charge rebalancing event between two or more capacitors within the power converter.

49. The method according to claim 44, wherein, The reduced gate drive voltage increases the on-resistance R of the power FET ON .

50. The method according to claim 44, wherein, When the power FET is in the saturation operating mode, the reduced gate drive voltage causes the power FET to act as a controlled current limiting source.

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