Display panel and display device
Patent Information
- Application Number
- CN202311765839.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
Smart Images
Figure CN120178563A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art
[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation, and convenient carrying. In recent years, it has developed rapidly and has gradually replaced the traditional Cathode Ray Tube display (CRT), occupying a dominant position in the current flat panel display market. Currently, TFT-LCD has been widely used in various products of different sizes, covering almost all the main electronic products in today's information society, such as liquid crystal TVs, high-definition digital TVs, computers (desktop and notebook), mobile phones, tablet computers, navigators, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays, etc. Summary of the Invention
[0003] A display panel and a display device provided by an embodiment of the present disclosure can improve the aperture ratio and effectively improve the color shift defect.
[0004] The display panel and the display device provided by the embodiment of the present disclosure are specifically as follows:
[0005] On the one hand, an embodiment of the present disclosure provides a display panel, including: an array substrate, and the array substrate includes:
[0006] a substrate, the substrate includes a plurality of sub-pixel regions arranged in an array, and the sub-pixel region includes a bright pixel region and a dark pixel region arranged along a first direction;
[0007] a common electrode line, at least partially wound around the opening region of the bright pixel region and the opening region of the dark pixel region;
[0008] a first gate line, extending along a second direction between the bright pixel region and the dark pixel region, and the second direction intersects with the first direction;
[0009] a second gate line, extending along the second direction between the bright pixel region and the dark pixel region, and the second gate line is located on the side of the first gate line close to the dark pixel region;
[0010] The first transistor is located between the opening area of the bright pixel area and the opening area of the dark pixel area. The gate of the first transistor is electrically connected to the second gate line. The first pole of the first transistor includes a first overlapping portion and a second overlapping portion connected to each other. Among them, the first overlapping portion is located between the second gate line and the opening area of the dark pixel area, and the first overlapping portion overlaps with at least a part of the common electrode line wound around the opening area of the dark pixel area in a direction perpendicular to the substrate to form a first discharge capacitor. The second overlapping portion is located between the first gate line and the opening area of the bright pixel area, and the second overlapping portion overlaps with at least a part of the common electrode line wound around the opening area of the bright pixel area in a direction perpendicular to the substrate to form a second discharge capacitor.
[0011] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, it further includes an opposing substrate disposed opposite to the array substrate, and the opposing substrate includes a common electrode;
[0012] The array substrate further includes a first pixel electrode located in the dark pixel area, and the first pixel electrode is electrically connected to the second pole of the first transistor;
[0013] The first pixel electrode overlaps with the common electrode line in a direction perpendicular to the substrate to form a storage capacitor, and the first pixel electrode overlaps with the common electrode in a direction perpendicular to the substrate to form a liquid crystal capacitor;
[0014] The sum of the first discharge capacitor and the second discharge capacitor is 20% to 30% of the sum of the storage capacitor and the liquid crystal capacitor.
[0015] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the ratio of the opening area of the bright pixel area to the opening area of the dark pixel area is greater than or equal to 1:2 and less than or equal to 1:1.
[0016] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the second pole of the first transistor includes a first electrode portion extending along the second direction, and the orthographic projection of the first electrode portion on the substrate overlaps with the orthographic projection of the first gate line on the substrate.
[0017] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the array substrate further includes a second transistor located between the opening area of the bright pixel area and the opening area of the dark pixel area, and a second pixel electrode located in the bright pixel area;
[0018] The gate of the second transistor is electrically connected to the first gate line, a first pole of the second transistor is electrically connected to the second pixel electrode, and the first pole of the second transistor includes a second electrode portion extending in the second direction. A positive projection of the second electrode portion on the substrate substrate overlaps a part of a positive projection of the first gate line on the substrate substrate.
[0019] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the array substrate further includes a third transistor located between an opening area of the bright pixel area and an opening area of the dark pixel area. A first pole of the third transistor is multiplexed with a second pole of the first transistor, a second pole of the third transistor is multiplexed with a second pole of the second transistor, and a gate of the third transistor is multiplexed with a gate of the second transistor.
[0020] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, an active layer of the second transistor and an active layer of the third transistor are integrally provided, and the first electrode portion and the second electrode portion are symmetrically arranged about an axis of symmetry in the second direction of the integrally provided active layer.
[0021] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, the array substrate further includes a plurality of connection lines and an insulating layer located between a layer where the common electrode line is located and a layer where the connection lines are located;
[0022] The connection line is electrically connected to the common electrode line through a via hole penetrating the insulating layer, and a positive projection of the via hole on the substrate substrate overlaps a part of a positive projection of the common electrode line on the substrate substrate.
[0023] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, an overlapping area size and shape of the first overlapping portion and the common electrode line are different from an overlapping area size and shape of the second overlapping portion and the common electrode line.
[0024] Based on the same inventive concept, embodiments of the present disclosure provide a display device including the above display panel provided by the embodiments of the present disclosure.
[0025] The beneficial effects of the present disclosure are as follows:
[0026] The display panel and display device provided by the embodiments of the present disclosure include an array substrate. The array substrate includes: a substrate substrate, the substrate substrate includes a plurality of sub-pixel regions arranged in an array, and the sub-pixel region includes a bright pixel region and a dark pixel region arranged along a first direction; a common electrode line, at least partially wound around the opening regions of the bright pixel region and the opening regions of the dark pixel region; a first gate line, extending along a second direction between the bright pixel region and the dark pixel region, and the second direction intersects the first direction; a second gate line, extending along the second direction between the bright pixel region and the dark pixel region, and the second gate line is located on the side of the first gate line close to the dark pixel region; a first transistor, located between the opening region of the bright pixel region and the opening region of the dark pixel region, the gate of the first transistor is electrically connected to the second gate line, and the first pole of the first transistor includes a first overlapping portion and a second overlapping portion connected to each other; wherein, the first overlapping portion is located between the second gate line and the opening region of the dark pixel region, and the first overlapping portion and at least part of the common electrode line wound around the opening region of the dark pixel region overlap in a direction perpendicular to the substrate substrate to form a first discharge capacitor; the second overlapping portion is located between the first gate line and the opening region of the bright pixel region, and the second overlapping portion and at least part of the common electrode line wound around the opening region of the bright pixel region overlap in a direction perpendicular to the substrate substrate to form a second discharge capacitor. By arranging the first discharge capacitor between the second gate line and the opening region of the dark pixel region and arranging the second discharge capacitor between the first gate line and the opening region of the bright pixel region, the space between the opening region of the bright pixel region and the opening region of the dark pixel region is reasonably utilized, which is beneficial to improving the pixel aperture ratio. Description of the Drawings
[0027] Figure 1 It is a light effect simulation diagram of 8-domain display;
[0028] Figure 2 It is a schematic structural diagram of a pixel region in the display panel provided by the embodiments of the present disclosure;
[0029] Figure 3 It is Figure 2 An enlarged structural diagram of the array substrate in the M region in
[0030] Figure 4 It is Figure 2 A schematic structural diagram of the layer where the gate line of the array substrate is located in
[0031] Figure 5 It is Figure 2 A schematic structural diagram of the active layer of the array substrate in
[0032] Figure 6 It is Figure 2 A schematic structural diagram of the layer where the data line of the array substrate is located in
[0033] Figure 7 It is Figure 2 A schematic structural diagram of the layer where the via of the array substrate is located in
[0034] Figure 8 is Figure 2 a schematic structural diagram of the layer where the pixel electrode of the array substrate is located;
[0035] Figure 9 is along Figure 2 a schematic cross-sectional structure diagram of line I-II in;
[0036] Figure 10 is along Figure 2 a schematic cross-sectional structure diagram of line III-IV in;
[0037] Figure 11 is Figure 2 an equivalent circuit diagram of a sub-pixel region in;
[0038] Figure 12 a gamma curve diagram provided by an embodiment of the present disclosure;
[0039] Figure 13 another gamma curve diagram provided by an embodiment of the present disclosure. Specific embodiments
[0040] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are enlarged. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic views of idealized embodiments. Thus, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include shape deviations caused by, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features; sharp corners illustrated may be rounded, etc. Thus, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the exact shape of the regions, do not reflect the true scale, and are only intended to schematically illustrate the content of the present disclosure. And the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.
[0041] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in the description and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inner", "outer", "upper", "lower", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0042] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intervening elements or layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.
[0043] With the development of display technology, consumers have increasingly strict requirements for the picture quality of liquid crystal displays. Due to the increasing size, the large viewing angle color shift becomes more and more obvious. Therefore, the color shift of the liquid crystal display at different viewing angles has become an important indicator for evaluating the panel performance. There are many factors affecting the chromaticity of the liquid crystal display, such as the backlight unit (BLU), polarizer (POL), liquid crystal (LC), color filter (CF), and array substrate, etc.
[0044] Multi-domain display can divide different regions within a sub-pixel. The deflection degrees of the liquid crystals in different regions are different. When viewing the liquid crystal display from different angles, the comprehensive effect of the deflection of the liquid crystals in each region is seen, thereby reducing the contrast difference at different angles caused by the same deflection of all the liquid crystals within the pixel, and further reducing the color shift and increasing the viewing angle. For example, in Figure 1In the 8-domain display shown, the color shift effect can be made better by adjusting the brightness ratio between the upper 4 domains and the lower 4 domains. Pixels with higher brightness are called bright pixels, and pixels with lower brightness are called dark pixels. In some embodiments, the dark pixels can be discharged through a discharge capacitor (Charge share) near the dark pixel opening area, making the dark pixels darker. However, this solution sacrifices a certain amount of pixel aperture ratio.
[0045] To at least solve the above technical problems existing in the related art, an embodiment of the present disclosure provides a display panel, including an array substrate. Figure 2 The structure of a pixel region in the display panel is shown. Figure 3 For Figure 2 The enlarged schematic structural diagram of the array substrate in the M region in Figures 4 to 8 For Figure 2 The schematic structural diagram of each film layer on the array substrate in Figure 9 For Figure 2 The cross-sectional structural diagram along the I-II line in Figure 10 For Figure 2 The cross-sectional structural diagram along the III-IV line in Figure 11 For Figure 2 The equivalent circuit diagram of a sub-pixel region in Figures 2 to 11 It can be seen that the array substrate 001 may include:
[0046] A substrate 101, which includes a plurality of sub-pixel regions SPX arranged in an array. The plurality of sub-pixel regions SPX may include a plurality of red sub-pixel regions R, a plurality of green sub-pixel regions G, a plurality of blue sub-pixel regions B, etc. The sub-pixel region SPX includes a bright pixel region H and a dark pixel region L arranged along the first direction Y. Optionally, the bright pixel region H and the dark pixel region L are respectively 4-domain displays, so that each sub-pixel SPX realizes an 8-domain display; the substrate 101 is a substrate that allows visible light to pass through, such as made of glass, quartz, plastic, etc.
[0047] A common electrode line 102, at least partially wound around the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L.
[0048] A first gate line 103, extending along the second direction X between the bright pixel region H and the dark pixel region L, and the second direction X intersects the first direction Y.
[0049] A second gate line 104, extending along the second direction X between the bright pixel region H and the dark pixel region L, and the second gate line 104 is located on the side of the first gate line 103 close to the dark pixel region L.
[0050] In some embodiments, the common electrode line 102, the first gate line 103, and the second gate line 104 are provided in the same layer and made of the same material. Optionally, the material of the first gate line 103 includes metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. The first gate line 103 can be a single-layer structure or a stacked structure. For example, the first gate line 103 is a single-layer structure composed of a molybdenum metal layer;
[0051] The first thin-film transistor TFT1 is located between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L. The gate g1 of the first thin-film transistor TFT1 is electrically connected to the second gate line 104 (for example, a part of the second gate line 104 is multiplexed as the gate g1 of the first thin-film transistor TFT1). The first pole d1 of the first thin-film transistor TFT1 includes a first overlapping portion d11 and a second overlapping portion d12 that are connected to each other; wherein, the first overlapping portion d11 is located between the second gate line 104 and the opening region LO of the dark pixel region L, and the first overlapping portion d11 overlaps with at least a part of the common electrode line 102 wound around the opening region LO of the dark pixel region L in the direction Z perpendicular to the substrate 101 to form a first discharge capacitor Cbuf1; the second overlapping portion d12 is located between the first gate line 103 and the opening region HO of the bright pixel region H, and the second overlapping portion d12 overlaps with at least a part of the common electrode line 102 wound around the opening region HO of the bright pixel region H in the direction Z perpendicular to the substrate 101 to form a second discharge capacitor Cbuf2; it should be understood that both the first discharge capacitor Cbuf1 and the second discharge capacitor Cbuf2 can include a gate insulating layer 105 located between the layer where the first pole d1 of the first thin-film transistor TFT1 is located and the layer where the common electrode line 102 is located; in some embodiments, the first pole d1 of the first thin-film transistor TFT1 is provided in the same layer and made of the same material as the data line 106. For example, the material used for the first pole d1 of the first thin-film transistor TFT1 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. In some embodiments, the layer where the first pole d1 of the first thin-film transistor TFT1 is located can be a single-layer structure or a stacked structure. Exemplarily, the layer where the first pole d1 of the first thin-film transistor TFT1 is located is a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer; optionally, the first discharge capacitor Cbuf1 and the second discharge capacitor Cbuf2 are provided at one end of the pixel electrode far from the data line 106.
[0052] In the above display panel provided by the embodiments of the present disclosure, by providing the first discharge capacitor Cbuf1 between the second gate line 104 and the opening region LO of the dark pixel region L and providing the second discharge capacitor Cbuf2 between the first gate line 103 and the opening region HO of the bright pixel region H, the reasonable utilization of the space between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L is realized, which is beneficial to improving the pixel aperture ratio.
[0053] In some embodiments, the first overlapping portion d11 and the second overlapping portion d12 can be flexibly set according to the wiring space between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel L. For example, in Figure 3 the size and shape of the first overlapping portion d11 are different from those of the second overlapping portion d12, resulting in the overlapping area size and shape of the first overlapping portion d11 with the common electrode line 102 being different from those of the second overlapping portion d12 with the common electrode line 102. In the present disclosure, the area of the overlapping capacitor on the side close to the bright pixel region H is larger than the area of the overlapping capacitor on the side close to the dark pixel region L.
[0054] In some embodiments, such as Figures 2 to 11As shown, the display panel may further include a counter substrate 002 disposed opposite to the array substrate 001. The counter substrate 002 includes a common electrode 201, and the common electrode 201 may be disposed over the entire display area AA and cover all sub-pixel areas SPX. The array substrate 001 further includes a first pixel electrode 107 located in the dark pixel area L, and the first pixel electrode 107 is electrically connected to the second pole s1 of the first thin film transistor TFT1. Optionally, the first pixel electrode 107 is electrically connected to the second pole s1 of the first thin film transistor TFT1 through a first via hole h1 penetrating through the passivation layer 108 and the planarization layer 109. In some embodiments, the present disclosure may also not provide the planarization layer 109, such that the first pixel electrode 107 is electrically connected to the second pole s1 of the first thin film transistor TFT1 through the first via hole h1 penetrating through the passivation layer 108. The present disclosure is illustrated by taking the case where the planarization layer 109 is provided as an example. In some embodiments, the material of the first pixel electrode 107 includes, but is not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). Optionally, the first pixel electrode 107 and the common electrode line 102 overlap in the direction Z perpendicular to the substrate 101 to form a first storage capacitor Cst1, and the first pixel electrode 107 may overlap with the common electrode 201 in the direction Z perpendicular to the substrate 101 to form a first liquid crystal capacitor Cpx1. Among them, the first storage capacitor Cst1 is used to charge the first pixel electrode 107 during the period when the first gate line 103 is turned off and maintain the voltage on the first pixel electrode 107 (which can be equivalent to the voltage after discharging the charge) until the next frame update. The first liquid crystal capacitor Cpx1 is used to cause the liquid crystal molecules corresponding to the dark pixel area L to deflect under the electric field in the first liquid crystal capacitor Cpx1 during the period when the first gate line 103 is turned on to achieve dark display. The first discharge capacitor Cbuf1 and the second discharge capacitor Cbuf2 are used to store the released charge of the first pixel electrode 107 during the period when the first gate line 104 is turned on. To effectively improve color deviation, the present disclosure may set the sum of the first discharge capacitor Cbuf1 and the second discharge capacitor Cbuf2 to be 20% - 30% of the sum of the first storage capacitor Cst1 and the first liquid crystal capacitor Cst2, for example, it may be 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, etc.
[0055] Figure 12 Graphs of gamma for the sum of the first discharge capacitor Cbuf1 and the second discharge capacitor Cbuf2 being 20% and 25% of the sum of the first storage capacitor Cst1 and the first liquid crystal capacitor Cst2. The closer to the standard curve gamma 2.2, the less obvious the color deviation. Combining Figure 12As can be seen from the two gamma curves, the gamma shifts of the 25% and 20% schemes relative to the standard curve gamma 2.2 are both small. In other words, both schemes have a certain effect on improving color deviation; and from Figure 12 It can be seen that in the L60 - L200 gray scale, the 25% scheme has a better effect on improving color deviation than the 20% scheme. When the gray scale is greater than L200 or less than L60, the effect of the 25% scheme on improving color deviation is slightly deteriorated compared to the 20% scheme.
[0056] In some embodiments, the orthographic projection of the first overlapping portion d11 on the substrate 101 may be located within the orthographic projection of the common electrode line 102 on the substrate 101, or a partial orthographic projection of the first overlapping portion d11 on the substrate 101 may be located within the orthographic projection of the common electrode line 102 on the substrate 101. That is, the first overlapping portion d11 may completely fall within the region of the common electrode line 102, or only a part of the first overlapping portion d11 may fall within the region of the common electrode line 102; similarly, the orthographic projection of the second overlapping portion d11 on the substrate 101 may be located within the orthographic projection of the common electrode line 102 on the substrate 101, or a partial orthographic projection of the second overlapping portion d11 on the substrate 101 may be located within the orthographic projection of the common electrode line 102 on the substrate 101. That is, the second overlapping portion d11 may completely fall within the region of the common electrode line 102, or only a part of the second overlapping portion d11 may fall within the region of the common electrode line 102. As long as the sum of the first discharge capacitance cbuf1 formed by the overlap of the first overlapping portion d11 and the common electrode line 102 and the second discharge capacitance cbuf2 formed by the overlap of the second overlapping portion d12 and the common electrode line 102 is 20% - 30% of the sum of the above first storage capacitance Cst1 and the first liquid crystal capacitance Clc1.
[0057] In some embodiments, the present disclosure can also improve color deviation by adjusting the ratio between the opening area HO of the bright pixel region H and the opening area LO of the dark pixel region L. Optionally, the ratio of the area of the opening area HO of the bright pixel region H to the area of the opening area LO of the dark pixel region L in the present disclosure is greater than or equal to 1:2 and less than or equal to 1:1, such as 1:1, 1:1.1, 1:1.2, 1:1.3, 1:1.4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, 1:2, etc.
[0058] Figure 13 Are gamma curve graphs where the ratios of the area of the opening area HO of the bright pixel region H to the area of the opening area LO of the dark pixel region L are 1.5:1 and 1:1.5 respectively. The closer to the standard curve gamma 2.2, the less obvious the color deviation. Combining Figure 13It can be seen from the two gamma curves that the 1:1.5 scheme has a significantly better effect on improving color deviation than the 1.5:1 scheme below the L120 gray level. In the L120 - L190 gray level range, the 1.5:1 Gamma shift scheme is slightly better than the 1:1.5 scheme. Therefore, from the overall benefit analysis, the 1:1.5 scheme has a better effect on improving color deviation than the 1.5:1 scheme.
[0059] Combined with Figure 12 and Figure 13 it can be known that the area ratio of the opening region has a greater influence on the middle - low gray levels, and the discharge capacitance has a higher influence on the middle - high gray levels. To achieve a better color deviation improvement effect, the present disclosure preferably sets the ratio of the area HO of the opening region of the bright pixel region H to the area LO of the opening region of the dark pixel region L to 1:1.5, and sets the sum of the first discharge capacitance Cbuf1 and the second discharge capacitance Cbuf2 to 25% of the sum of the first storage capacitance Cst1 and the first liquid crystal capacitance Cst2.
[0060] It should be noted that as long as at least one of the following two conditions is met, the color deviation defect can be improved: the ratio of the area HO of the opening region of the bright pixel region H to the area LO of the opening region of the dark pixel region L is greater than or equal to 1:2 and less than or equal to 1:1, and the sum of the first discharge capacitance Cbuf1 and the second discharge capacitance Cbuf2 is 20% - 30% of the sum of the first storage capacitance Cst1 and the first liquid crystal capacitance Cst2. Therefore, the present disclosure does not need to limit the shape of the second pixel electrode 110 covering the opening region HO of the bright pixel region H and the shape of the first pixel electrode 110 covering the opening region LO of the dark pixel region L. In some embodiments, the shape of the first pixel electrode 110 and the shape of the second pixel electrode 110 can be the same or different.
[0061] In some embodiments, in the above - mentioned display panel provided by the embodiments of the present disclosure, as Figure 3 shown, the second pole s1 of the first transistor TFT1 includes a first electrode portion s11 extending along the second direction X. The orthographic projection of the first electrode portion s11 on the substrate 101 partially overlaps with the orthographic projection of the first gate line 103 on the substrate 101. It can be understood that the first electrode portion s11 is partially hanging on the first gate line 103. Compared with the case where the first electrode portion s11 is completely outside the first gate line 103 region, by locally arranging the first electrode portion s11 within the first gate line 103 region, the size of the opening region HO of the bright pixel H and the opening region LO of the dark pixel L in the first direction Y can be appropriately reduced, which is beneficial to improving the aperture ratio. At the same time, compared with the scheme where the first electrode portion s11 is completely arranged within the first gate line 103 region, by locally arranging the first electrode portion s11 within the first gate line 103 region in the present disclosure, the coupling capacitance between the first electrode portion s11 and the first gate line 103 can be reduced, and the mutual interference between the two can be reduced.
[0062] In some embodiments, in the above display panel provided by the embodiments of the present disclosure, as Figures 2 to 11 shown, the array substrate 001 further includes a second transistor TFT2 located between the opening region HO of the bright pixel region H and the opening region HO of the dark pixel region L, and a second pixel electrode 110 located in the bright pixel region H; the gate g2 of the second transistor TFT2 is electrically connected to the first gate line 103 (for example, a part of the first gate line 103 is multiplexed as the gate g2 of the second transistor TFT2), the first pole d2 of the second transistor TFT2 is electrically connected to the second pixel electrode 110 through a second via hole h2 penetrating through the passivation layer 108 and the planarization layer 109. Optionally, the second pixel electrode 110 and the common electrode line 102 overlap in the direction Z perpendicular to the substrate 101 to form a second storage capacitor Cst2, and the second pixel electrode 110 can overlap with the common electrode 201 in the direction Z perpendicular to the substrate 101 to form a second liquid crystal capacitor Cpx2; wherein, the second storage capacitor Cst2 is used to charge the second pixel electrode 110 during the period when the first gate line 103 is turned off and maintain the voltage on the second pixel electrode 110 (equivalent to the data voltage loaded on the data line 106) until the next frame update, and the second liquid crystal capacitor Cpx2 is used to drive the liquid crystal molecules corresponding to the bright pixel region H to deflect under the electric field in the second liquid crystal capacitor Cpx2 to achieve bright display during the period when the first gate line 103 is turned on.
[0063] In some embodiments, as Figure 3 shown, the first pole d2 of the second transistor TFT2 includes a second electrode portion d21 extending in the second direction X, and the orthographic projection of the second electrode portion d21 on the substrate 101 partially overlaps with the orthographic projection of the first gate line 103 on the substrate 101. It can be understood that the second electrode portion d21 is semi-hung on the first gate line 103. Compared with the case where the second electrode portion d21 is completely located outside the first gate line 103 region, by locally arranging the second electrode portion d21 within the first gate line 103 region, the size of the opening region HO of the bright pixel H and the opening region LO of the dark pixel L in the first direction Y can be appropriately reduced, which is beneficial to improving the aperture ratio. At the same time, compared with the scheme where the second electrode portion d21 is completely arranged within the first gate line 103 region, in the present disclosure, by locally arranging the second electrode portion d21 within the first gate line 103 region, the coupling capacitance between the second electrode portion d21 and the first gate line 103 can be reduced, and the mutual interference between the two can be reduced.
[0064] In some embodiments, as Figures 4 to 6As shown, the array substrate 001 further includes a third transistor TFT3 located between the opening region HO in the bright pixel region H and the opening region LO in the dark pixel region L. The first pole d3 of the third transistor TFT3 is multiplexed with the second pole s1 of the first transistor TFT1. The gate g3 of the third transistor TFT3 is multiplexed with the gate g2 of the second transistor TFT2. The second pole s3 of the third transistor TFT3 is multiplexed with the second pole s2 of the second transistor TFT2. In some embodiments, the second pole s3 of the third transistor TFT3 is connected to the data line 106, and a part of the second pole s3 of the third transistor TFT3 is located between the first gate line 103 and the second gate line 104. Optionally, to ensure that the channel width-to-length ratio of the second transistor TFT2 is the same as that of the third transistor TFT3, so as to charge the first pixel electrode 107 and the second pixel electrode 110 synchronously through the second transistor TFT2 and the third transistor TFT3, as Figure 3 shown, the active layer a2 of the second transistor TFT2 and the active layer a3 of the third transistor TFT3 can be set as an integral structure, and the first electrode part d11 and the second electrode part d21 are symmetrically arranged with respect to the symmetry axis AS of the integrally arranged active layer (i.e., the whole shown by a2 and a3) in the second direction X.
[0065] Continue to refer to Figure 3 It can be seen that in the present disclosure, the array substrate 001 may further include a plurality of connection lines 111 and an insulating layer located between the layer where the common electrode line 102 is located and the layer where the connection lines 111 are located. Optionally, the connection lines 111 are arranged on the same layer and made of the same material as the first pixel electrode 107 and the second pixel electrode 110. The common electrode line 102 is arranged on the same layer and made of the same material as the first gate line 103 and the second gate line 104. The insulating layer includes a gate insulating layer 105, a passivation layer 108, and a planarization layer 109. The connection lines 111 can be electrically connected to the common electrode line 102 through a third via hole h3 penetrating the insulating layer, so that the common electrode line 102 forms a mesh structure to improve the uniformity of the common voltage. Optionally, the orthographic projection of the third via hole h3 on the substrate 101 partially overlaps with the orthographic projection of the common electrode line 102 on the substrate 101. With such a setting, a step can be formed at the third via hole h3 due to the presence of the common electrode line 102, which is beneficial to the flow of the alignment liquid (such as PI liquid), improves the uniformity of the PI film formation, and enhances the alignment effect.
[0066] In some embodiments, such as Figure 8As shown, the connection line 111 can be disposed between the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L in the blue sub-pixel B. The connection line 111 can have a design structure with wide ends and a narrow middle. And to avoid short-circuiting with the first pixel electrode 107 and the second pixel electrode 110 disposed on the same layer, the first pixel electrode 107 and the second pixel electrode 110, which are on the same layer and made of the same material as the connection line 111 in the blue sub-pixel region B, are provided with cut corners at the ends of the connection line 111. This has a certain impact on the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L in the blue sub-pixel region B. However, considering that the pixel brightness of the blue sub-pixel region B in the red sub-pixel region R, the green sub-pixel region G, and the blue sub-pixel region B is the lowest, therefore, even if a part of the aperture ratio of the blue sub-pixel region B is sacrificed, it will not have a great impact on the overall transmittance of the product.
[0067] In some embodiments, the first pixel electrode 107 and the second pixel electrode 110 can be block electrodes or slit electrodes. Optionally, the slits form a cross shape or a zigzag shape.
[0068] In some embodiments, as Figure 4 and Figure 6 shown, the common electrode line 102 can include a plurality of hollow structures OW. The hollow structures OW expose the data lines 106 between the opening regions LO of the dark pixel regions L and the data lines 106 between the opening regions HO of the bright pixel regions H to reduce the parasitic capacitance between the common electrode line 102 and the data lines 106.
[0069] In some embodiments, according to different materials, the transistors of the present disclosure can be P-type transistors or N-type transistors; according to different gate positions, the transistors of the present disclosure can be bottom-gate transistors, top-gate transistors, or double-gate transistors, etc., which are not limited herein. Additionally, the first pole of the transistor in the present disclosure can be the source electrode and the second pole can be the drain electrode, or the first pole of the transistor can be the drain electrode and the second pole can be the source electrode; the active layer material of the transistor can be amorphous silicon (a-Si), polysilicon (poly), oxide (Oxide, such as indium gallium zinc oxide IGZO), etc.
[0070] In some embodiments, as Figure 2 、 Figure 9 and Figure 10 shown, the opposing substrate 002 can further include a substrate 202, a black matrix 203 located between the substrate 202 and the common electrode 201, and a color resist 204 located between the black matrix 203 and the common electrode 201. Among them, the black matrix 203 covers the common electrode line 102, the first gate line 103, the second gate line 104, the first transistor TFT1, the second transistor TFT2, the third transistor TFT3, and the connection line 111, and the black matrix 203 exposes the opening region HO of the bright pixel region H and the opening region LO of the dark pixel region L.
[0071] In some embodiments, the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer between the array substrate and the counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, and the polarization directions of the first polarizer and the second polarizer are perpendicular to each other. Other essential components in the display panel should be understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present disclosure.
[0072] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure, and a backlight module located on the light incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, a reflective sheet, a light guide plate, a diffusion sheet, a prism group, etc. that are stacked, and the light bar is located on one side in the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffusion plate, a brightness enhancement film, etc. that are stacked on the light emitting side of the matrix light source, and the reflective sheet includes openings that are disposed opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light emitting diodes (LEDs), such as micro light emitting diodes (Mini LED, Micro LED, etc.).
[0073] Micro light emitting diodes in the sub-millimeter scale or even the micrometer scale, like organic light emitting diodes (OLEDs), belong to self-luminous devices. Similar to organic light emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and a very large viewing angle. And because inorganic light emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, compared with organic light emitting diodes that emit light based on organic substances, they have the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life. Moreover, when micro light emitting diodes are used as a backlight source, a more precise dynamic backlight effect can be achieved, effectively improving the screen brightness and contrast while also solving the glare phenomenon caused by traditional dynamic backlights between the bright and dark areas of the screen and optimizing the visual experience.
[0074] In some embodiments, the display device provided by the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness bracelet, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided by the present disclosure includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip, etc. Optionally, the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc. For example, the control chip may further include a memory and a power module, etc., and realizes the power supply and signal input / output functions through separately provided wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors such as logic chips, transistors, or other discrete components; the hardware circuit may also include a field programmable gate array, a programmable array logic, a programmable logic device, etc. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure. In other words, the display device provided by the embodiments of the present disclosure may include more or fewer of the above components, or combine some components, or have different component arrangements.
[0075] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.
[0076] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.
Claims
1. A display panel, characterized in that, Comprising: An array substrate, the array substrate comprising: A substrate substrate, the substrate substrate comprising a plurality of sub-pixel regions arranged in an array, the sub-pixel regions comprising a bright pixel region and a dark pixel region arranged along a first direction; A common electrode line, at least partially wound around the opening regions of the bright pixel regions and the opening regions of the dark pixel regions; A first gate line, extending along a second direction between the bright pixel region and the dark pixel region, the second direction intersecting the first direction; A second gate line, extending along the second direction between the bright pixel region and the dark pixel region, and the second gate line being located on a side of the first gate line closer to the dark pixel region; A first transistor, located between the opening region of the bright pixel region and the opening region of the dark pixel region, a gate of the first transistor being electrically connected to the second gate line, a first pole of the first transistor comprising a first overlapping portion and a second overlapping portion connected to each other; wherein, the first overlapping portion is located between the second gate line and the opening region of the dark pixel region, and the first overlapping portion and at least a part of the common electrode line wound around the opening region of the dark pixel region overlap in a direction perpendicular to the substrate substrate to form a first discharge capacitor; the second overlapping portion is located between the first gate line and the opening region of the bright pixel region, and the second overlapping portion and at least a part of the common electrode line wound around the opening region of the bright pixel region overlap in a direction perpendicular to the substrate substrate to form a second discharge capacitor.
2. The display panel according to claim 1, characterized in that, Further comprising an opposing substrate disposed opposite to the array substrate, the opposing substrate comprising a common electrode; The array substrate further comprises a first pixel electrode located in the dark pixel region, the first pixel electrode being electrically connected to a second pole of the first transistor; The first pixel electrode and the common electrode line overlap in a direction perpendicular to the substrate substrate to form a storage capacitor, and the first pixel electrode and the common electrode overlap in a direction perpendicular to the substrate substrate to form a liquid crystal capacitor; The sum of the first discharge capacitor and the second discharge capacitor is 20% to 30% of the sum of the storage capacitor and the liquid crystal capacitor.
3. The display panel according to claim 1, characterized in that, The ratio of the area of the opening region of the bright pixel region to the area of the opening region of the dark pixel region is greater than or equal to 1:2 and less than or equal to 1:
1.
4. The display panel according to any one of claims 1 to 3, characterized in that, The second pole of the first transistor comprises a first electrode portion extending along the second direction, and a positive projection of the first electrode portion on the substrate substrate partially overlaps a positive projection of the first gate line on the substrate substrate.
5. The display panel according to any one of claims 1 to 3, characterized in that, The array substrate further comprises a second transistor located between the opening region of the bright pixel region and the opening region of the dark pixel region, and a second pixel electrode located in the bright pixel region; A gate of the second transistor is electrically connected to the first gate line, a first pole of the second transistor is electrically connected to the second pixel electrode, and the first pole of the second transistor comprises a second electrode portion extending in the second direction, and a positive projection of the second electrode portion on the substrate substrate partially overlaps a positive projection of the first gate line on the substrate substrate.
6. The display panel according to claim 5, characterized in that, The array substrate further includes a third transistor located between the opening region of the bright pixel region and the opening region of the dark pixel region. A first pole of the third transistor is multiplexed with a second pole of the first transistor. A second pole of the third transistor is multiplexed with a second pole of the second transistor. A gate of the third transistor is multiplexed with a gate of the second transistor.
7. The display panel according to claim 6, characterized in that, An active layer of the second transistor and an active layer of the third transistor are integrally provided. The first electrode portion and the second electrode portion are symmetrically arranged about the axis of symmetry of the integrally provided active layer in the second direction.
8. The display panel according to any one of claims 1 to 3, 6, and 7, characterized in that, The array substrate further includes a plurality of connection lines and an insulating layer located between the layer where the common electrode line is located and the layer where the connection lines are located. The connection lines are electrically connected to the common electrode line through vias penetrating the insulating layer. A positive projection of the via on the substrate partially overlaps a positive projection of the common electrode line on the substrate.
9. The display panel according to any one of claims 1 to 3, 6, and 7, characterized in that, An overlapping area size and shape of the first overlapping portion and the common electrode line are different from an overlapping area size and shape of the second overlapping portion and the common electrode line.
10. A display device, characterized in that, A display panel includes the display panel according to any one of claims 1 to 9.