Dose control system and control method of direct writing equipment

Abstract

The invention discloses a dose control system and control method for direct writing equipment, and the system comprises an exposure instruction generation module which is used for generating an exposure control instruction; the preceding-stage data buffering module is used for buffering exposure control instruction data; the exposure clock preprocessing module is used for reading exposure control instruction data, and if an exposure clock adjusting instruction is read in the exposure control instruction data, the clock adjusting module is controlled to output a clock with required frequency; the post-stage data buffer module is used for caching exposure control instruction data; the state register module is used for storing a clock adjustment state value; the clock adjusting module is used for outputting a clock with required frequency; the clock selection module is used for outputting a clock; the instruction execution module is used for reading and executing exposure control instruction data and updating an instruction execution result to the output control interface module; and the output control interface module is used for receiving the control value and realizing output updating of a physical interface. The method has the advantages of low cost, high precision and the like.

Description

Technical Field

[0001] The present invention mainly relates to the field of semiconductor technology, and particularly relates to a dose control system and a control method for a direct writing device. Background Art

[0002] In the field of semiconductor manufacturing, a direct writing device draws a pattern on a photoresist above a substrate material by controlling the deflection and on / off of an energy beam (light, electrons, ions, etc.), and then realizes the fabrication of a circuit structure through subsequent processes such as etching, deposition, and development.

[0003] The direct writing device has no mask plate, and its working process is to expose the pattern in the input layout design file. The exposure control of the pattern is generally executed by a pattern generator. Taking electron beam exposure as an example, the specific exposure process is as follows:

[0004] First, calculate the exposure time of an exposure point in a shape according to the characteristics, thickness of the photoresist, and beam current. Then, when performing the exposure of a shape, the following steps are executed in sequence:

[0005] 1. Control the deflection amplifier circuit to deflect the electron beam to the starting point of the shape;

[0006] 2. Open the beam shutter to keep the electron beam always on;

[0007] 3. Stay at an exposure point for the exposure time length;

[0008] 4. Control the deflection amplifier circuit to deflect the electron beam to the next exposure point;

[0009] 5. Repeat steps 3 and 4 in sequence until a shape is completed;

[0010] 6. Close the beam shutter.

[0011] Cooperating with the movement of the workpiece stage and repeating the exposure of all shapes can complete the exposure of the design layout.

[0012] The control of the execution frequency of steps 3 and 4 above is dose control. The existing dose control is generally achieved by frequency division of an independent high-frequency counting module, which has the following problems:

[0013] 1. The counter frequency division setting interface control occupies additional IO ports or communication interfaces;

[0014] 2. The high-frequency counting module will increase the system cost;

[0015] 3. The clock frequency adjustment has insufficient subdivision degree. Summary of the Invention

[0016] In view of the technical problems existing in the prior art, the present invention provides a dose control system and control method for a direct writing device with low cost and high precision.

[0017] To solve the above technical problems, the technical solution proposed by the present invention is as follows:

[0018] A dose control system for a direct writing device, comprising an exposure instruction generation module, a pre-stage data buffer module, an exposure clock preprocessing module, a post-stage data buffer module, a status register module, a clock adjustment module, a clock selection module, an instruction execution module, and an output control interface module;

[0019] The exposure instruction generation module is used to generate exposure control instructions;

[0020] The pre-stage data buffer module is used to cache the exposure control instruction data sent by the exposure instruction generation module;

[0021] The exposure clock preprocessing module is used to read the exposure control instruction data and write the exposure control instruction data into the post-stage data buffer module; if an exposure clock adjustment instruction is read in the exposure control instruction data, the status value in the status register is read, and after status judgment, clock adjustment parameters are configured for the clock adjustment module, and the clock adjustment module is controlled to output a clock with the required frequency;

[0022] The post-stage data buffer module is used to cache the exposure control instruction data written by the exposure clock preprocessing module;

[0023] The status register module is used to save the clock adjustment status value;

[0024] The clock adjustment module is used to output a clock with the required frequency to the clock selection module;

[0025] The clock selection module is used to output the clock of the clock adjustment module to the instruction execution module;

[0026] The instruction execution module is used to sequentially read and execute the exposure control instruction data in the post-stage data buffer module, and update the instruction execution result to the output control interface module; when the exposure clock adjustment instruction is executed, the status value in the status register is read, and after status judgment, the clock selection module is controlled to output the corresponding clock;

[0027] The output control interface module is used to receive the control value of the instruction execution module and implement the output update of the physical interface.

[0028] Preferably, the pre-stage data buffer module, the exposure clock preprocessing module, the post-stage data buffer module, the status register module, the clock adjustment module, the clock selection module, the instruction execution module, and the output control interface module are all integrated on the FPGA.

[0029] Preferably, both the pre-stage data buffer module and the post-stage data buffer module are FIFOs of the FPGA.

[0030] Preferably, the clock adjustment module includes a plurality of clock adjustment units.

[0031] Preferably, the status register module is an independent module, or a register of the exposure clock preprocessing module itself or a register of the instruction execution module itself.

[0032] The present invention also discloses a control method for a dose control system of a direct writing device as described above, including the steps of:

[0033] The exposure instruction generation module generates an exposure control instruction;

[0034] The pre-stage data buffer module caches the exposure control instruction data sent by the exposure instruction generation module;

[0035] The exposure clock preprocessing module reads the exposure control instruction data and writes the exposure control instruction data into the post-stage data buffer module; if an exposure clock adjustment instruction is read in the exposure control instruction data, the status value in the status register is read, and after status judgment, clock adjustment parameters are configured for the clock adjustment module, and the clock adjustment module is controlled to output a clock with the required frequency;

[0036] The post-stage data buffer module caches the exposure control instruction data written by the exposure clock preprocessing module;

[0037] The status register module saves the clock adjustment status value;

[0038] The clock adjustment module outputs a clock with the required frequency to the clock selection module; the clock adjustment module includes a first clock adjustment unit and a second clock adjustment unit;

[0039] The clock selection module outputs the clock of the clock adjustment module to the instruction execution module;

[0040] The instruction execution module sequentially reads and executes the exposure control instruction data in the post-stage data buffer module, and updates the instruction execution result to the output control interface module; when the exposure clock adjustment instruction is executed, the status value in the status register is read, and after status judgment, the clock selection module is controlled to output the corresponding clock;

[0041] The output control interface module receives the control value of the instruction execution module and realizes the output update of the physical interface.

[0042] Preferably, the exposure control instruction data consists of exposure instruction codes, the exposure instruction codes are aligned in 8-byte units, the exposure instruction code consists of an instruction, its parameters, and padding, where the instruction occupies 1 byte, and the parameter and padding part occupy 7 bytes, and the instruction includes an exposure clock adjustment instruction.

[0043] Preferably, when generating the exposure clock adjustment instruction, the exposure instruction generation module traverses and calculates or looks up the pre-generated coefficient frequency correspondence table according to the required clock frequency to obtain the input division coefficient, multiplication coefficient, and output division coefficient corresponding to the frequency closest to the required clock frequency, and fills them into the exposure clock adjustment instruction in the form of parameters.

[0044] Preferably, the exposure clock preprocessing module sequentially reads instructions from the front-stage data buffer module in 8-byte units. If a non-exposure clock adjustment instruction is read, the currently read instruction code is copied and written to the rear-stage data buffer module; if an exposure clock adjustment instruction is read, the register value of the status register module is read again. If it is 0 or 1, the input division coefficient, multiplication coefficient, and output division coefficient in the exposure clock adjustment instruction code are written to the first clock adjustment unit. After the clock adjustment is completed, the register value is set to 10, and the currently read exposure clock adjustment instruction code is copied and written to the rear-stage data buffer module; if it is 2, the above coefficients are written to the second clock adjustment unit. After the clock adjustment is completed, the register value is set to 20, and the currently read exposure clock adjustment instruction code is copied and written to the rear-stage data buffer module; if it is 10 or 20, after waiting for several clock cycles, the register value of the status register module is read again, and the above logic is executed.

[0045] Preferably, the first clock adjustment unit and the second clock adjustment unit are implemented based on the dynamic configuration function of the internal PLL of the FPGA, and the parameters used for dynamic configuration include the input division coefficient, multiplication coefficient, and output division coefficient.

[0046] Compared with the prior art, the advantages of the present invention are as follows:

[0047] The dose control system of the present invention provides a fully integrated clock adjustment architecture, completes the frequency adjustment function inside the chip, eliminates the dependence on external IO ports or independent communication interfaces, simplifies the hardware design and reduces the system complexity.

[0048] The dose control system of the present invention abandons the traditional high-frequency counting module and adopts the programmable frequency division / multiplication coefficient combination control technology of FPGA (the input frequency division coefficient, multiplication coefficient, and output frequency division coefficient are multi-level linked). In the target frequency range of 1 MHz - 100 MHz, more than 200,000 frequency values that meet the PLL constraints can be generated through parameter configuration, and the subdivision accuracy is improved by two orders of magnitude compared with the traditional high-frequency counting module (only supporting <2,000 discrete frequencies at a working frequency of 2 GHz);

[0049] Based on the flexible adaptation ability of the subdivision parameters, the dose control system of the present invention screens the output frequency closest to the required value from a large number of optional frequencies, significantly reducing the frequency error of dose control and solving the dose deviation problem caused by insufficient frequency resolution in the traditional scheme.

[0050] Through the collaborative innovation of the above-mentioned hardware architecture and software control method, the present invention realizes low-cost and high-precision dose control of the direct writing device without the constraint of a high-frequency counter, providing a feasible path for the precise regulation of core process parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a block diagram of the dose control system of the direct writing device of the present invention in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0053] As Figure 1 shown, the dose control system of the direct writing device provided by the embodiment of the present invention includes an exposure instruction generation module, a pre-stage data buffer module, an exposure clock preprocessing module, a post-stage data buffer module, a status register module, a clock adjustment module (specifically including a first clock adjustment unit and a second clock adjustment unit), a clock selection module, an instruction execution module, and an output control interface module;

[0054] The exposure instruction generation module is used to generate exposure control instructions;

[0055] The pre-stage data buffer module is used to cache the exposure control instruction data sent by the exposure instruction generation module;

[0056] The exposure clock preprocessing module is used to read the exposure control instruction data and write the exposure control instruction data into the post-stage data buffer module; if an exposure clock adjustment instruction is read in the exposure control instruction data, the status value in the status register is read, and after status judgment, clock adjustment parameters are configured for the first clock adjustment unit or the second clock adjustment unit, and the first clock adjustment unit and the second clock adjustment unit are controlled to output a clock with the required frequency;

[0057] The post-stage data buffer module is used to cache the exposure control instruction data written by the exposure clock preprocessing module;

[0058] The status register module is used to save the status related to clock adjustment;

[0059] The first clock adjustment unit is controlled by the exposure clock preprocessing module and is used to output a clock with the required frequency to the clock selection module;

[0060] The second clock adjustment unit is controlled by the exposure clock preprocessing module and is used to output a clock with the required frequency to the clock selection module;

[0061] The clock selection module is controlled by the instruction execution module and is used to output the clock of the first clock adjustment unit or the clock of the second clock adjustment unit to the instruction execution module;

[0062] The instruction execution module is used to sequentially read and execute the exposure control instruction data in the post-stage data buffer module, and update the instruction execution result to the output control interface module; when an exposure clock adjustment instruction is executed, it reads the status value in the status register, and after status judgment, it controls the clock selection module to output the clock of the first clock adjustment unit or the clock of the second clock adjustment unit;

[0063] The output control interface module is used to receive the control value of the instruction execution module and implement the output update of the physical interface.

[0064] The exposure instruction generation module is implemented on the host computer, and other modules are implemented on the FPGA. Of course, in other embodiments, the exposure instruction generation module is not limited to being implemented on the host computer, and it can also be other processing platforms.

[0065] The dose control system of the present invention provides a fully integrated clock adjustment architecture, which completes the frequency adjustment function inside the chip, eliminates the dependence on external IO ports or independent communication interfaces, simplifies the hardware design and reduces the system complexity.

[0066] The dose control system of the present invention abandons the traditional high-frequency counting module and adopts the programmable frequency division / multiplication coefficient combination control technology of the FPGA (multi-level linkage of input frequency division coefficient, multiplication coefficient, and output frequency division coefficient). In the target frequency range of 1MHz - 100MHz, more than 200,000 frequency values that meet the PLL constraints can be generated through parameter configuration, and the subdivision accuracy is improved by two orders of magnitude compared with the traditional high-frequency counting module (only supporting <2000 discrete frequencies at a working frequency of 2GHz);

[0067] Based on the flexible adaptation ability of the subdivision parameters, the dose control system of the present invention screens the output frequency closest to the required value from a large number of selectable frequencies, significantly reducing the frequency error of dose control and solving the dose deviation problem caused by insufficient frequency resolution in the traditional solution.

[0068] Through the collaborative innovation of the above-mentioned hardware architecture and software control method, the present invention realizes low-cost and high-precision dose control of the direct writing device without the constraint of a high-frequency counter, providing a feasible path for the precise regulation of core process parameters.

[0069] To better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the specification drawings and specific implementation manners.

[0070] The exposure instruction generation module generates exposure control instruction data; the exposure control instruction data consists of exposure instruction codes, the exposure instruction codes are aligned in 8-byte units, the exposure instruction codes are composed of instructions, their parameters, and padding. Among them, the instruction occupies 1 byte, and the parameter and padding part occupy 7 bytes. The instructions include exposure clock adjustment instructions and other control instructions. Of course, in other embodiments, it can also be limited to other numbers of bytes.

[0071] When the exposure instruction generation module generates an exposure clock adjustment instruction, according to the required clock frequency, it traverses and calculates or looks up the pre-generated coefficient frequency correspondence table to obtain the input frequency division coefficient, multiplication coefficient, and output frequency division coefficient corresponding to the frequency closest to the required clock frequency, and fills them into the exposure clock adjustment instruction in the form of parameters.

[0072] The exposure instruction generation module writes the generated exposure instruction data into the pre-stage data buffer module, where the pre-stage data buffer module is implemented by a FIFO. Of course, in other embodiments, it can also be implemented by other modules with data sequential writing and reading functions.

[0073] The exposure clock preprocessing module sequentially reads instructions from the previous-stage data buffer module in units of 8 bytes. If a non-exposure clock adjustment instruction is read, the instruction code read currently is copied and written into the subsequent-stage data buffer module. If an exposure clock adjustment instruction is read, the register value of the status register module is read again. If it is 0 or 1, the input division factor, multiplication factor, and output division factor in the exposure clock adjustment instruction code are written into the first clock adjustment unit. After the clock adjustment is completed, the register value is set to 10, and the exposure clock adjustment instruction code read currently is copied and written into the subsequent-stage data buffer module. If it is 2, the above coefficients are written into the second clock adjustment unit. After the clock adjustment is completed, the register value is set to 20, and the exposure clock adjustment instruction code read currently is copied and written into the subsequent-stage data buffer module. If it is 10 or 20, after waiting for several clock cycles, the register value of the status register module is read continuously, and the above logic is executed.

[0074] After the status register module is initialized, the register value is 0. The specific form of the status register module can be an independent module, or a register of the exposure clock preprocessing module or the instruction execution module itself.

[0075] The subsequent-stage data buffer module is implemented by a FIFO. Of course, in other embodiments, it can also be implemented by other modules with the functions of sequential data writing and reading.

[0076] The first clock adjustment unit and the second clock adjustment unit are implemented based on the dynamic configuration function of the internal PLL of the FPGA. The parameters used in this embodiment for dynamic configuration include: input division factor, multiplication factor, and output division factor.

[0077] The outputs of the first clock adjustment unit and the second clock adjustment unit are clock signals with specific frequencies, which are connected to the inputs of the clock selection module. Of course, in other embodiments, the number of clock adjustment units can also be three or more.

[0078] The clock selection module is controlled by the instruction execution module to select to connect the output of the first clock adjustment unit or the second clock adjustment unit to its own output.

[0079] The present invention uses two clock adjustment units, which can independently adjust these two clocks, and can enable the instruction execution module to use the clock of one clock adjustment unit while the exposure clock preprocessing module can perform clock adjustment on the other clock adjustment unit.

[0080] The instruction execution module sequentially reads instructions from the post-stage data buffer module in units of 8 bytes and executes them. If a non-exposure clock adjustment instruction is read, the corresponding instruction is executed, and the execution result is written to the output control interface module. If an exposure clock adjustment instruction is read, the register value of the status register module is read again. If it is 10, the clock selection module is controlled to output the clock of the first clock adjustment unit, and the register value of the status register module is set to 2. If it is 20, the clock selection module is controlled to output the clock of the second clock adjustment unit, and the register value of the status register module is set to 1.

[0081] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A dosage control system for a direct writing device, characterized in that: It includes an exposure instruction generation module, a front-stage data buffer module, an exposure clock preprocessing module, a rear-stage data buffer module, a status register module, a clock adjustment module, a clock selection module, an instruction execution module and an output control interface module; The exposure instruction generating module is used to generate an exposure control instruction; The front-stage data buffer module is used to buffer the exposure control instruction data sent by the exposure instruction generation module; The exposure clock preprocessing module is used to read the exposure control instruction data and write the exposure control instruction data into the post-stage data buffer module; If the exposure clock adjustment instruction is read in the exposure control instruction data, the state value in the state register is read, and after state judgment, the clock adjustment parameter is configured for the clock adjustment module, and the clock adjustment module is controlled to output a clock of the required frequency; The post-stage data buffer module is used to cache the exposure control instruction data written by the exposure clock preprocessing module; The status register module is used to store the clock adjustment status value; The clock adjustment module is used to output a clock of a required frequency to the clock selection module; The clock selection module is used to output the clock of the clock adjustment module to the instruction execution module; The instruction execution module is used to sequentially read and execute the exposure control instruction data in the post-stage data buffer module, and update the instruction execution results to the output control interface module; when the exposure clock adjustment instruction is executed, the state value in the state register is read, and after state judgment, the clock selection module is controlled to output the corresponding clock; The output control interface module is used to receive the control value of the instruction execution module and implement the output update of the physical interface.

2. The dosage control system of the direct writing device according to claim 1, characterized in that: The front-stage data buffer module, exposure clock preprocessing module, rear-stage data buffer module, status register module, clock adjustment module, clock selection module, instruction execution module and output control interface module are all integrated on the FPGA.

3. The dosage control system of the direct writing device according to claim 2, characterized in that: The front-stage data buffer module and the rear-stage data buffer module are both FIFOs of FPGA.

4. The dosage control system of the direct writing device according to claim 1, 2 or 3, characterized in that: The clock adjustment module includes a plurality of clock adjustment units.

5. The dosage control system of the direct writing device according to claim 1, 2 or 3, characterized in that: The status register module is an independent module, or a register of the exposure clock preprocessing module itself or a register of the instruction execution module itself.

6. A control method for a dose control system of a direct writing device according to any one of claims 1 to 5, characterized in that: Includes steps: The exposure instruction generating module generates an exposure control instruction; The front-stage data buffer module caches the exposure control instruction data sent by the exposure instruction generation module; The exposure clock preprocessing module reads the exposure control instruction data and writes the exposure control instruction data into the post-stage data buffer module; If the exposure clock adjustment instruction is read in the exposure control instruction data, the state value in the state register is read, and after state judgment, the clock adjustment parameter is configured for the clock adjustment module, and the clock adjustment module is controlled to output a clock of the required frequency; The post-stage data buffer module caches the exposure control instruction data written by the exposure clock preprocessing module; The status register module stores the clock adjustment status value; The clock adjustment module outputs a clock of a required frequency to the clock selection module; the clock adjustment module comprises a first clock adjustment unit and a second clock adjustment unit; The clock selection module outputs the clock of the clock adjustment module to the instruction execution module; The instruction execution module sequentially reads and executes the exposure control instruction data in the post-stage data buffer module, and updates the instruction execution results to the output control interface module; when the exposure clock adjustment instruction is executed, the state value in the state register is read, and after state judgment, the clock selection module is controlled to output the corresponding clock; The output control interface module receives the control value of the instruction execution module and implements the output update of the physical interface.

7. The control method according to claim 6, characterized in that: The exposure control instruction data consists of an exposure instruction code, which is aligned to 8 bytes. The exposure instruction code consists of an instruction, its parameters and padding, wherein the instruction occupies 1 byte, and the parameters and padding part occupy 7 bytes. The instruction includes an exposure clock adjustment instruction.

8. The control method according to claim 6 or 7, characterized in that: When generating an exposure clock adjustment instruction, the exposure instruction generation module traverses and calculates or looks up a pre-generated coefficient frequency correspondence table according to the required clock frequency to obtain the input division coefficient, multiplication coefficient and output division coefficient corresponding to the frequency closest to the required clock frequency, and fills them into the exposure clock adjustment instruction in the form of parameters.

9. The control method according to claim 6 or 7, characterized in that: The exposure clock preprocessing module sequentially reads instructions from the front-stage data buffer module in units of 8 bytes. If a non-exposure clock adjustment instruction is read, the currently read instruction code is copied and written into the back-stage data buffer module; If the exposure clock adjustment instruction is read, the register value of the status register module is read again. If it is 0 or 1, the input frequency division coefficient, multiplication coefficient and output frequency division coefficient in the exposure clock adjustment instruction code are written into the first clock adjustment unit. After the clock adjustment is completed, the register value is set to 10, and the currently read exposure clock adjustment instruction code is copied and written into the post-stage data buffer module; If it is 2, the above coefficient is written into the second clock adjustment unit. After the clock adjustment is completed, the register value is set to 20, and the currently read exposure clock adjustment instruction code is copied and written into the post-stage data buffer module; if it is 10 or 20, after waiting for several clock cycles, continue to read the status register module register value and execute the above logic.

10. The control method according to claim 6 or 7, characterized in that: The first clock adjustment unit and the second clock adjustment unit are implemented based on the dynamic configuration function of the PLL inside the FPGA, and the dynamically configured parameters used include an input frequency division coefficient, a frequency multiplication coefficient, and an output frequency division coefficient.

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