High-precision ultra-low dropout linear regulator circuit

Abstract

The invention discloses a high-precision ultra-low dropout linear regulator circuit, and belongs to the technical field of analog integrated circuits. The circuit comprises an error amplifier circuit, a driving stage circuit, a dynamic zero compensation circuit and a power stage circuit. The power level circuit adopts an NMOS tube as a power tube, and the power tube is driven by the driving level circuit to generate a feedback end voltage and input the feedback end voltage to the error amplifier circuit. The error amplifier circuit compares the feedback end voltage with the reference voltage, and the difference value is used for adjusting the power tube gate end voltage in the power level circuit. The dynamic zero compensation circuit is provided with a sampling tube, and the sampling tube mirrors the load current flowing through the power tube, generates a zero point changing along with the load, and compensates the output pole of the whole voltage stabilizer circuit. The LDO provided by the invention has the characteristics that the output precision is + / -1%, the 115mV ultra-low dropout is realized, the stability of a system can be kept by matching with any output capacitor or not using the output capacitor, and the like, and can supply power to systems such as a digital IP (Internet Protocol) module, an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and an SOC (System On Chip).

Description

Technical Field

[0001] The present invention relates to a high-precision ultra-low dropout linear regulator circuit, belonging to the technical field of analog integrated circuits. Background Art

[0002] With the continuous development of highly integrated and portable electronic devices in recent years, the requirement for chip integration has become higher and higher. In order to reduce the chip area, single power supply is more frequently used. Due to the diversification of system-on-chip integrated chips, it is required that the single power supply can provide sufficient current to ensure the normal operation of each functional module. As an important member of the power management chip category, the LDO supplies power to many high-precision devices relying on its characteristics such as small ripple and low cost. How to improve the load-carrying capacity of the linear regulator while ensuring loop stability within a wide load range has become the main difficulty for high-power LDOs.

[0003] Traditional LDOs need an external output capacitor to ensure loop stability and good transient response. However, in order to minimize the chip area to a greater extent, chip-external capacitors are widely used, which can not only reduce the PCB board area but also save costs. Although chip-external capacitors have many advantages, they also increase the design difficulty of loop stability.

[0004] The biggest disadvantage of the LDO linear regulator compared with the switching power supply regulator is its low efficiency. The size of the dropout voltage determines the efficiency. The lower the dropout voltage, the higher the efficiency. At the same time, a low dropout voltage means low power consumption. For the same output, a lower input voltage is required. For power management chips, power consumption determines the chip's lifespan and standby time. Especially for electronic products such as mobile phones and computers, standby time is an important factor for consumers to choose. Therefore, high precision, high stability, and ultra-low dropout have become the current research hotspots.

[0005] Regarding the problem of high-power loop stability, traditional LDOs adopt a compensation method of an internal fixed capacitor or an external large output capacitor. Especially for chip-external capacitors, relatively large capacitors are usually built-in. Under different output load conditions, the change of load zero-poles leads to the change of the unity-gain bandwidth and phase margin, and it is difficult to ensure loop stability within a wide load current range. On the other hand, since the traditional LDO loop often relies on the zero-point generated by the output capacitor and the equivalent series impedance, there are restrictions on the type selection of the output capacitor in the system. The small-size and compact-shaped ceramic capacitors on the market are increasingly favored by system designers. However, the ESR resistance value of the ceramic capacitor is too small, and in applications, it often brings stability problems.

[0006] For the problem of ultra-low dropout voltage, traditional LDOs usually use PMOS transistors to achieve. The dropout voltage range of PMOS transistors is the smallest, and it is better to select PMOS for the regulating transistor than NMOS. NMOS has a relatively low output impedance, large bandwidth, good transient response characteristics, and is easy to achieve frequency compensation; when the load current and the gate voltage of the power transistor are the same, the size of NMOS as the regulating transistor is smaller, saving more area on the layout; secondly, when the size and gate voltage of the power transistor are the same, NMOS can obtain a larger output current; it avoids the change of the load current caused by the slight change of the source power supply voltage when PMOS is used as the power transistor, and has a higher PSRR. The gate terminal voltage range of the NMOS transistor determines the output voltage range, and it has relatively high requirements for the pre-stage drive circuit, which requires both sufficient driving ability and a relatively high output range. The PMOS transistor requires the pre-stage circuit to have a relatively high gain to drive the power transistor. Therefore, the power transistor determines the load driving range, voltage difference and system architecture of the system. Summary of the Invention

[0007] The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, a high-precision ultra-low dropout linear regulator circuit is proposed, which has the characteristics of ±1% output accuracy, 115mV ultra-low dropout voltage, and can keep the system stable whether using any output capacitor or not using the output capacitor, and can supply power to systems such as digital IP modules, FPGAs, DSPs, and SOCs.

[0008] The technical solution of the present invention is:

[0009] A high-precision ultra-low dropout linear regulator circuit, including an error amplifier circuit, a drive stage circuit, a dynamic zero compensation circuit, and a power stage circuit;

[0010] The power stage circuit uses an NMOS transistor as the power transistor, and the power transistor is driven by the drive stage circuit to generate a feedback terminal voltage and input it to the error amplifier circuit;

[0011] The error amplifier circuit compares the feedback terminal voltage with the reference voltage, and the difference is used to adjust the gate terminal voltage of the power transistor in the power stage circuit;

[0012] The dynamic zero compensation circuit is provided with a sampling transistor, and the sampling transistor mirrors the load current flowing through the power transistor in the power stage circuit to generate a zero point that changes with the load, compensating the output pole of the entire regulator circuit.

[0013] Further, the power stage circuit includes a power transistor M N , resistor R 1-1 , resistor R 1-2 , resistor R L、 , capacitor C L ; where:

[0014] The non-inverting terminal of the error amplifier is connected to the reference voltage, and the inverting terminal of the error amplifier is connected to the negative terminal of resistor R 1-1 and the positive terminal of resistor R 1-2 The output terminal of the error amplifier is connected to the non-inverting terminal of the driver stage circuit. The inverting terminal of the driver stage circuit is connected to the output terminal of the driver stage, the gate terminal of power transistor M N and the gate terminal of the sampling transistor;

[0015] The input terminal of the dynamic zero-point compensation circuit is connected to the drain terminal and the gate terminal of the sampling transistor. The output terminal of the dynamic zero-point compensation circuit is connected to the error amplifier circuit. The source terminal of power transistor M N is connected to the source terminal of the sampling transistor;

[0016] The power supply terminal of the error amplifier, the power supply terminal of the driver stage circuit, and the power supply terminal of the dynamic zero-point compensation circuit are connected to the first input power supply V BIAS The drain terminal of power transistor M N is connected to the second input power supply V IN The source terminal of power transistor M N is connected to the positive terminal of resistor R 1-1 the positive terminal of capacitor C L the positive terminal of load resistor R L and is connected;

[0017] The negative terminal of resistor R 1-2 is grounded, the negative terminal of capacitor C L is grounded, and the negative terminal of resistor R L is grounded.

[0018] Furthermore, the error amplifier circuit adopts a folded cascode structure, including capacitor C 2-2 , resistor R 2-3 , MOS transistors M 2-1 ~M 2-23 and current source I BIAS2 ;

[0019] The gate terminal of MOS transistor M 2-1 is connected to the feedback terminal voltage V FB The gate terminal of MOS transistor M 2-2 is connected to the reference voltage. The drain terminal of MOS transistor M 2-1 is connected to the drain terminal of MOS transistor M 2-6 , the source terminal of MOS transistor M 2-4 , and the drain terminal of MOS transistor M 2-12 The drain terminal of MOS transistor M 2-2 is connected to the drain terminal of MOS transistor M 2-5 , the source terminal of MOS transistor M 2-3 , and the drain terminal of MOS transistor M 2-11 The source terminals of MOS transistors M 2-1 , M 2-2 are connected to MOS transistor M2-14 is connected to the leakage end, MOS transistor M 2-5 's source end, MOS transistor M 2-6 's source end, MOS transistor M 2-22 's source, MOS transistor M 2-23 's source end is grounded, MOS transistor M 2-5 's gate end, MOS transistor M 2-6 's gate end, MOS transistor M 2-22 's gate end, MOS transistor M 2-23 's gate end, MOS transistor M 2-23 's leakage end, current source I BIAS2 is connected, MOS transistor M 2-3 's gate end, MOS transistor M 2-4 's gate end is connected to MOS transistor M 2-19 's gate end, MOS transistor M 2-20 's gate end, MOS transistor M 2-21 's gate end is connected, MOS transistor M 2-3 's leakage end is connected to MOS transistor M 2-7 's leakage end, MOS transistor M 2-9 's gate end, MOS transistor M 2-10 's gate end is connected, MOS transistor M 2-4 's leakage end is connected to MOS transistor M 2-8 's leakage end, capacitor C 2-2 's positive end is connected to the driving stage circuit;

[0020] MOS transistor M 2-7 's gate end is connected to MOS transistor M 2-8 's gate end, MOS transistor M 2-16 's gate end, MOS transistor M 2-17 's gate end, MOS transistor M 2-18 's gate end is connected, MOS transistor M 2-7 's source end is connected to MOS transistor M 2-9 's leakage end, MOS transistor M 2-8 's source end is connected to MOS transistor M 2-10 's leakage end; MOS transistor M 2-9 's source end, MOS transistor M 2-10 's source end, MOS transistor M 2-13 's source end, MOS transistor M 2-14 's source end, MOS transistor M 2-15 's source end, MOS transistor M 2-16 's source end is connected to the first power supply V BIAS , MOS transistor M 2-11 's gate end is grounded, MOS transistor M 2-11 's source end is connected to MOS transistor M 2-12 's source end, MOS transistor M 2-13 's leakage end is connected, MOS transistor M 2-12The output of the gate terminal connection dynamic zero - point compensation circuit, MOS transistor M 2-13 The gate terminal of, MOS transistor M 2-14 The gate terminal of, MOS transistor M 2-15 The gate terminal is connected to the dynamic zero - point compensation circuit;

[0021] MOS transistor M 2-16 The drain terminal is connected to the source terminal of MOS transistor M 2-17 The drain terminal of, MOS transistor M 2-17 The drain terminal is connected to the source terminal of MOS transistor M 2-18 The drain terminal of, MOS transistor M 2-18 The drain terminal is connected to the drain terminal of MOS transistor M 2-22 The drain terminal of, MOS transistor M 2-19 The drain terminal is connected to the drain terminal of MOS transistor M 2-15 The drain terminal of, MOS transistor M 2-19 The source terminal is connected to the drain terminal of MOS transistor M 2-20 The drain terminal of, MOS transistor M 2-20 The source terminal is connected to the drain terminal of MOS transistor M 2-21 The drain terminal of, MOS transistor M 2-21 The source terminal is grounded, and the negative terminal of capacitor C 2-2 is connected to the positive terminal of resistor R 2-3 The positive terminal of R 2-3 The negative terminal is grounded.

[0022] Furthermore, the dynamic zero - point compensation circuit includes resistor R 2-1 ~R 2-2、 capacitor C 2-1 , MOS transistor M 2-24 ~M 2-35 , current source I BIAS1 , sampling transistor M C ; Among them, the sampling transistor M C is of the same type as the power transistor;

[0023] The positive terminal of resistor R 2-1 , the source terminal of MOS transistor M 2-35 , the source terminal of MOS transistor M 2-32 , the source terminal of MOS transistor M 2-33 , the source terminal of MOS transistor M 2-34 is connected to the first power supply V BIAS ; R 2-1 The negative terminal is connected to the drain terminal of MOS transistor M 2-24 , the drain terminal of MOS transistor M 2-26 , the gate terminal of MOS transistor M 2-24 is connected to the input voltage, the source terminal of MOS transistor M 2-24 is connected to the drain terminal of M 2-25 , the gate terminal of MOS transistor M 2-25 , the gate terminal of MOS transistor M 2-26 is connected to the gate terminal of the power transistor M NThe gate terminal V of G , the source terminal of MOS transistor M 2-25 , the source terminal of MOS transistor M 2-26 is connected to the positive terminal of capacitor C 2-1 , the negative terminal of capacitor C 2-1 is connected to the drain terminal of MOS transistor M 2-27 , the positive terminal of resistor R 2-2 , the gate terminal of MOS transistor M 2-27 is connected to the gate terminal of MOS transistor M 2-28 , the gate terminal of MOS transistor M 2-29 , the gate terminal of MOS transistor M 2-29 , the drain terminal of MOS transistor M 2-30 , the drain terminal of MOS transistor M 2-35 , the drain terminal of MOS transistor M 2-27 is connected to the drain terminal of MOS transistor M 2-28 , the source terminal of MOS transistor M 2-28 , the source terminal of R 2-2 , the negative terminal of MOS transistor M 2-29 , the source terminal of MOS transistor M is grounded 2-30 , the gate terminal of MOS transistor M is connected to the gate terminal of M 2-31 , the gate terminal of MOS transistor M 2-31 , the drain terminal of sampling transistor M C , the drain terminal V of C is connected. The source terminal of MOS transistor M 2-30 is connected to the drain terminal of MOS transistor M 2-32 , the source terminal of MOS transistor M 2-31 is connected to the drain terminal of MOS transistor M 2-33 , the source terminal of MOS transistor M 2-34 , the gate terminal of MOS transistor M is connected to the drain terminal of MOS transistor M 2-34 , the gate terminal of MOS transistor M 2-33 , the gate terminal of MOS transistor M 2-32 , the gate terminal of MOS transistor M 2-35 , the gate terminal of MOS transistor M, current source I BIAS1 are connected.

[0024] Further, sampling transistor M c samples the current of the power transistor. Through MOS transistors M 2-30 and MOS transistor M 2-31 's mirror image, a sampling current I O proportional to the load current I S is formed. I S is the current flowing through MOS transistor M 2-30 tube, and I S :I O = 1:n, where n represents the mirror ratio of MOS transistors M 2-30 and MOS transistor M 2-31 , power transistor; sampling current I S and fixed bias current IB Commonly flow into MOS tube M 2-29 , I B is the current flowing through MOS tube M 2-35 The current of the tube makes the MOS tube M 2-29 The gate voltage of the tube becomes the bias gate voltage V related to the load current. G29 , so that the zero point changes with the load current.

[0025] Furthermore, the error amplifier circuit adopts a two-stage operational amplifier structure consisting of a PMOS and NMOS dual-input pair of tubes:

[0026] The first stage is divided into a folded cascode amplifier composed of an NMOS pair of tubes, which works when the input voltage is higher than the intermediate level; a folded cascode amplifier composed of a PMOS pair of tubes, which works when the input voltage is lower than the intermediate level;

[0027] The second stage is a dual-input single-output operational amplifier to achieve a rail-to-rail input common-mode level range and ensure full conduction within the input voltage range.

[0028] Furthermore, the driving stage circuit includes a MOS tube M 3-1 ~M 3-32 , transistor Q 3-1 ~Q 3-10 ; In the first stage, the folded cascode amplifier composed of NMOS tubes is composed of M 3-1 ~M 3-10 and Q 3-1 ~Q 3-8 The folded cascode amplifier composed of a PMOS pair consists of M 3-11 ~M 3-25 The second stage dual-input single-output operational amplifier consists of M 3-26 ~M 3-32 and Q 3-9 ~Q 3-10 Tube composition.

[0029] Furthermore, the circuit structure of the driving stage circuit is:

[0030] MOS tube M 3-1 The gate and drain of the MOS tube M are connected 3-2 The gate terminal of MOS tube M 3-7 The gate terminal of MOS tube M 3-8 The gate terminal of MOS tube M 3-9 Gate terminal, MOS tube M 3-10 The gate terminal of MOS tube M 3-11 The gate terminal of MOS tube M 3-18 The gate terminal of MOS tube M 3-26 The gate terminal and MOS tube current source I BIAS3 Connected, MOS tube M3-1 source terminal of, MOS transistor M 3-2 source terminal of, MOS transistor M 3-7 source terminal of, MOS transistor M 3-8 source terminal of, MOS transistor M 3-9 source terminal of, MOS transistor M 3-10 source terminal of, MOS transistor M 3-11 source terminal of, MOS transistor M 3-18 source terminal of, MOS transistor M 3-26 source terminal of, MOS transistor R 3-3 negative terminal of, triode Q 3-3 collector of, triode Q 3-4 collector is grounded, MOS transistor M 3-2 drain terminal is connected to MOS transistor M 3-2 source terminal of, MOS transistor M 3-4 source terminal of, MOS transistor M 3-3 gate terminal is connected to the output of the error amplifier, MOS transistor M 3-16 gate terminal of, MOS transistor M 3-3 drain terminal is connected to MOS transistor M 3-5 drain terminal of, triode Q 3-6 base of, triode Q 3-7 base of, C 3-1 negative terminal is connected, MOS transistor M 3-4 gate terminal is connected to MOS transistor M 3-32 drain terminal of, MOS transistor M 3-17 gate terminal of, MOS transistor M 3-30 drain terminal of, gate terminal of the power transistor V G , MOS transistor M 3-4 drain terminal is connected to MOS transistor M 3-6 drain terminal of, triode Q 3-5 base of, base of triode Q8, C 3-2 negative terminal is connected, MOS transistor M 3-5 gate terminal is connected to Q 3-7 emitter of, MOS transistor M 3-25 gate terminal of, triode Q 3-3 emitter of, MOS transistor M 3-10 drain terminal is connected, MOS transistor M 3-6 gate terminal is connected to Q 3-8 emitter of, MOS transistor M 3-24 gate terminal of, triode Q 3-4 emitter of, MOS transistor M 3-9 drain terminal is connected;

[0031] triode Q 3-5 emitter is connected to triode Q 3-1 emitter of, triode Q 3-6 emitter is connected to triode Q3-2 The emitter of the triode Q 3-1 The base of which is connected to the triode Q 3-4 The base of the triode Q 3-1 The collector of which is connected to M 3-7 The drain of the triode Q 3-2 The base of which is connected to the triode Q 3-2 The collector of the triode Q 3-3 The base of the MOS transistor M 3-8 The drain of which is connected to the triode Q 3-5 The collector of the triode Q 3-6 The collector of the triode Q 3-7 The collector of the triode Q 3-8 The collector of the MOS transistor M 3-5 The source of the MOS transistor M 3-6 The source of C 3-1 The positive terminal of C 3-2 The positive terminal of the MOS transistor M 3-12 The source of the MOS transistor M 3-13 The source of the MOS transistor M 3-14 The source of the MOS transistor M 3-21 The source of the MOS transistor M 3-24 The source of the MOS transistor M 3-25 The source of the MOS transistor M 3-27 The source of the MOS transistor M 3-28 The source of the MOS transistor M 3-29 The source of the MOS transistor M 3-30 The source of which is connected to the power supply, MOS transistor M 3-11 The drain of which is connected to the MOS transistor M 3-12 The drain of the MOS transistor M 3-12 The gate of the MOS transistor M 3-13 The gate of the MOS transistor M 3-14 The gates of which are connected, MOS transistor M 3-13 The drain of which is connected to the MOS transistor M 3-16 The source of the MOS transistor M 3-17 The source of the MOS transistor M 3-14 The drain of which is connected to the MOS transistor M 3-15 The source of the MOS transistor M 3-15 The gate of which is connected to the MOS transistor M 3-15 The drain of R 3-1 The negative terminal of the MOS transistor M 3-19 The drain of R 3-2 The negative terminal of the MOS transistor M 3-20 The drain of R 3-3 The positive terminals of which are connected, MOS transistor M 3-16 The drain of which is connected to the MOS transistor M 3-19 The source of the MOS transistor M 3-22The leakage terminal of 3-10 is connected to the base of the triode Q 3-17 The leakage terminal of the MOS transistor M 3-20 is connected to the source terminal of the MOS transistor M 3-23 The leakage terminal of the MOS transistor M 3-9 is connected to the base of the triode Q 3-1 The positive terminal of R 3-19 is connected to the gate terminal of the MOS transistor M 3-2 The positive terminal of R 3-20 is connected to the gate terminal of the MOS transistor M 3-18 The leakage terminal of the MOS transistor M 3-21 is connected to the gate terminal of the MOS transistor M 3-21 The leakage terminal of the MOS transistor M 3-22 is connected to the gate terminal of the MOS transistor M 3-23 is connected to the gate terminal of the MOS transistor M 3-22 The source terminal of the MOS transistor M 3-24 is connected to the leakage terminal of the MOS transistor M 3-23 The source terminal of the MOS transistor M 3-25 is connected to the leakage terminal of the MOS transistor M 3-26 The leakage terminal of the MOS transistor M 3-9 is connected to the emitter of the triode Q 3-10 The emitter of the triode Q 3-9 The collector of the triode Q 3-27 is connected to the leakage terminal of the MOS transistor M 3-10 The collector of the triode Q 3-28 is connected to the leakage terminal of the MOS transistor M 3-28 is connected to the gate terminal of the MOS transistor M 3-29 The gate terminal of the MOS transistor M 3-27 The gate terminal of the MOS transistor M 3-30 is connected to the gate terminal of the MOS transistor M 3-29 The leakage terminal of the MOS transistor M 3-31 is connected to the leakage terminal of the MOS transistor M 3-31 is connected to the gate terminal of the MOS transistor M 3-32 The gate terminal.

[0032] The advantages of the present invention compared with the prior art are as follows:

[0033] (1) Aiming at the current LDO high-power loop stability problem, the circuit of the present invention proposes a dynamic zero-point compensation circuit. The zero and pole of the circuit follow the change of the load current, ensuring that the system can be stable under all conditions when the circuit is used with any output capacitor or without an output capacitor.

[0034] (2) Aiming at the large current and ultra-low dropout problem, the circuit of the present invention adopts a dual-power supply mode. The power transistor uses an NMOS transistor and is powered separately, and the rest of the circuit uses the same power supply, solving the problem of large voltage difference of the NMOS transistor and achieving an ultra-low dropout of 115 mV.

[0035] (3) The present invention proposes a novel driver stage circuit, which uses PMOS and NMOS dual input pair transistors to achieve a rail-to-rail input common-mode level range, ensuring that the power stage circuit is turned on within the full output voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. In the drawings:

[0037] Figure 1 is the circuit structure block diagram of the high-precision ultra-low dropout linear regulator circuit according to the embodiment of the present invention;

[0038] Figure 2 is the circuit structure schematic diagram of the error amplifier with built-in dynamic zero compensation according to the embodiment of the present invention;

[0039] Figure 3 is the circuit structure schematic diagram of the driver circuit according to the embodiment of the present invention;

[0040] Figure 4 is the curve graph of the circuit phase margin varying with the output capacitance according to the embodiment of the present invention. (a) is the curve of the phase margin varying with the output capacitance under a 3A load and different power supply voltages, and (b) is the curve of the phase margin varying with the output capacitance under a 5mA load and different power supply voltages;

[0041] Figure 5 is the output voltage curve graph according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0043] The present invention proposes a high-precision ultra-low dropout linear regulator circuit (abbreviated as LDO), and the circuit is as Figure 1 shown, including an error amplifier, a driver stage circuit, a dynamic zero compensation circuit, and a power stage circuit. The circuit adopts a dual power supply mode, and the error amplifier and the driver stage circuit are powered by V BIAS while the power stage circuit is powered by V INPower supply ensures that the circuit has extremely low dropout voltage performance. The error amplifier, driver stage circuit, dynamic zero - point compensation circuit, and power stage circuit form a feedback loop. When the output voltage is too high, this feedback loop adjusts to reduce the gate voltage of the power transistor, thereby reducing the output voltage, and vice versa. The driver stage circuit uses PMOS and NMOS dual - input pair transistors to achieve a rail - to - rail input common - mode level range, ensuring that the power stage circuit is conducting within the full output voltage range. The sampling transistor M C mirrors the power transistor M N current, feeds the load current back to the dynamic zero - point compensation circuit. The dynamic zero - point compensation circuit generates a zero point that varies with the load, compensates for the LDO output pole, ensures that the circuit can maintain system stability whether using any output capacitor or not using an output capacitor, and the feature of no off - chip capacitor will greatly save the board - level system area, achieving high - precision and ultra - low dropout voltage performance, and providing an easy - to - use and robust power management solution for a variety of applications.

[0044] The overall circuit structure designed in this embodiment is as follows: The non - inverting terminal of the error amplifier is connected to a 0.8V voltage, the inverting terminal of the error amplifier is connected to the negative terminal of resistor R 1-1 and the positive terminal of resistor R 1-2 The output terminal of the error amplifier is connected to the non - inverting terminal of the driver stage circuit. The inverting terminal of the driver stage circuit is connected to the output terminal of the driver stage, the gate terminal of power transistor M N , and the gate terminal of sampling transistor M C The input terminal of the dynamic zero - point compensation circuit is connected to the drain terminal and the gate terminal of sampling transistor M C , and the output terminal of the dynamic zero - point compensation circuit is connected to the gate terminal of transistor M 2-12 in the error amplifier circuit. The source terminal of power transistor M N is connected to the source terminal of sampling transistor M C The power supply terminals of the error amplifier, the driver stage circuit, and the dynamic zero - point compensation circuit are connected to the input V BIAS . The drain terminal of power transistor M N is connected to the input terminal V IN . The source terminal of power transistor M N is connected to the positive terminal of resistor R 1-1 , the positive terminal of capacitor C L , and the positive terminal of load resistor R L . The negative terminal of resistor R 1-2 is grounded, the negative terminal of capacitor C L is grounded, and the negative terminal of resistor R L is grounded.

[0045] (1) Error amplifier circuit

[0046] The error amplifier circuit adopts a folded cascode structure to provide a large gain and ensure the output accuracy under various conditions. Considering that the input voltage of 0.8V is relatively small, PMOS is selected as the input differential pair transistor. Using a low-voltage cascode structure can increase the output swing and meet the usage requirements.

[0047] Such as Figure 2 The error amplifier circuit designed for this embodiment includes capacitor C 2-2 , resistor R 2-3 , MOS transistor M 2-1 ~M 2-23 , current source I BIAS2 . The circuit structure is as follows: The gate terminal of M 2-1 is connected to the feedback terminal voltage V FB , the gate terminal of M 2-2 is connected to a 0.8V voltage, the drain terminal of M 2-1 is connected to the drain terminal of M 2-6 , the source terminal of M 2-4 , and the drain terminal of M 2-12 ; the drain terminal of M 2-2 is connected to the drain terminal of M 2-5 , the source terminal of M 2-3 , and the drain terminal of M 2-11 ; the source terminal of M 2-1 , the source terminal of M 2-2 is connected to the drain terminal of M 2-14 ; the source terminal of M 2-5 , the source terminal of M 2-6 , the source terminal of M 2-22 , the source of M 2-23 and the source terminal of M 2-5 are grounded; the gate terminal of M 2-6 , the gate terminal of M 2-22 , the gate terminal of M 2-23 , the gate terminal of M 2-23 , the drain terminal of M BIAS2 are connected; the gate terminal of M 2-3 , the gate terminal of M 2-4 are connected to the gate terminal of M 2-19 , the gate terminal of M 2-20 , the gate terminal of M 2-21 ; the drain terminal of M 2-3 is connected to the drain terminal of M 2-7 , the gate terminal of M 2-9 , the gate terminal of M 2-10 ; the drain terminal of M 2-4 is connected to the drain terminal of M 2-8 , the positive terminal of C 2-2 , and the gate terminal of M 3-3 in the driver stage circuit; the gate terminal of M 2-7 is connected to the gate terminal of M 2-8 , the gate terminal of M 2-16 ​2-17 The gate terminal of, M 2-18 is connected to the gate terminal of, M 2-7 The source terminal of is connected to M 2-9 The drain terminal of, M 2-8 The source terminal of is connected to M 2-10 The drain terminal of, M 2-9 The source terminal of, M 2-10 The source terminal of, M 2-13 The source terminal of, M 2-14 The source terminal of, M 2-15 The source terminal of, M 2-16 The source terminal of is connected to V BIAS , M 2-11 The gate terminal of is grounded, M 2-11 The source terminal of is connected to M 2-12 The source terminal of, M 2-13 is connected to the drain terminal of, M 2-12 The gate terminal of is connected to the output of the dynamic zero - point compensation circuit (C 2-1 negative terminal), M 2-13 The gate terminal of, M 2-14 The gate terminal of, M 2-15 The gate terminal of is connected to the M in the dynamic zero - point compensation circuit 2-34 gate of, M 2-16 The drain terminal of is connected to M 2-17 The source terminal of, M 2-17 The drain terminal of is connected to M 2-18 The source terminal of, M 2-18 The drain terminal of is connected to M 2-22 The drain terminal of, M 2-19 The drain terminal of is connected to M 2-15 The drain terminal of, M 2-19 The source terminal of is connected to M 2-20 The drain terminal of, M 2-20 The source terminal of is connected to M 2-21 The drain terminal of, M 2-21 The source terminal of is grounded, C 2-2 The negative terminal of is connected to R 2-3 positive terminal of, R 2-3 The negative terminal of is grounded.

[0048] (2) Dynamic zero - point compensation circuit

[0049] The dynamic zero - point compensation circuit includes resistors R 2-1 ~R 2-2、 capacitor C 2-1 , MOS transistor M 2-24 ~M 2-35 , current source I BIAS1 , sampling transistor M C . Sampling transistor M C Sampling power transistor M N The current of is passed through M 2-30 and M 2-31Mirror formation and load current I O Current I proportional to S (I S is the current flowing through M 2-30 tube), and I S :I O = 1:n (n represents the mirror ratio of M 2-30 and M 2-31 、M N tubes), the sampling current I S and the fixed bias current I B (I B is the current flowing through M 2-35 tube) flow into M 2-29 together, making the gate voltage of M 2-29 tube become the bias gate voltage V G29 related to the magnitude of the load current. Adding I B ensures that when the no-load or light-load I S is too small, M 29 can still operate in the saturation region. Thus, from the MOS saturation region V / I characteristic equation, we can obtain:

[0050]

[0051] where V G2-28 represents the gate terminal voltage of M 2-28 tube, V G2-29 represents the gate terminal voltage of M 2-29 tube, μn represents the electron mobility, Cox represents the gate oxide capacitance per unit area, (W / L) 2-29 represents the width-to-length ratio of M 2-29 tube, and Vth1 represents the threshold of M 2-29 tube.

[0052] M 28 operates in the deep linear region, similar to a voltage-controlled resistor R 28 , (W / L) 28 :(W / L) 29 = k:1 (k is the proportionality coefficient). Combining Equation (1-1) and using the MOS linear region V / I characteristic equation, we can obtain:

[0053]

[0054] where (W / L) 28 represents the width-to-length ratio of M 2-28 tube, and Vth2 represents the threshold of M 2-28 tube. The zero-point formula is as shown in (1-3). This zero point can follow the change of the load current, ensuring that the circuit can maintain system stability whether it is used with any output capacitor or without an output capacitor. Among them, g m27 represents M2-27 Transconductance of the tube.

[0055]

[0056] Such as Figure 2 The dynamic zero - point compensation circuit designed for this embodiment: R 2-1 The positive terminal of, M 2-35 The source terminal of, M 2-32 The source terminal of, M 2-33 The source terminal of, M 2-34 The source terminal of is connected to V BIAS R 2-1 The negative terminal of is connected to the drain terminal of M 2-24 The drain terminal of, M 2-26 The drain terminal of, M 2-24 The gate terminal of is connected to a 0.8V voltage, the source terminal of M 2-24 The source terminal of is connected to the drain terminal of M 2-25 The drain terminal of, M 2-25 The gate terminal of, M 2-26 The gate terminals of the power tube M N The gate voltage V G M 2-25 The source terminal of, M 2-26 The source terminal of is connected to the positive terminal of C 2-1 C 2-1 The negative terminal of is connected to the drain terminal of M 2-27 The drain terminal of, R 2-2 The positive terminal of, M 2-27 The gate terminal of is connected to the gate terminals of M 2-28 The gate terminal of, M 2-29 The gate terminal of, M 2-29 The drain terminal of, M 2-30 The drain terminal of, M 2-35 The drain terminal of, M 2-27 The source terminal of is connected to the drain terminal of M 2-28 The drain terminal of, M 2-28 The source terminal of, R 2-2 The negative terminal of, M 2-29 The source terminal of is grounded, the gate terminal of M 2-30 The gate terminal of is connected to the gate terminal of M2 - 31, the drain terminal of M 2-31 The drain terminal of, the sampling tube M C The drain voltage V C Connected, the source terminal of M 2-30 The source terminal of is connected to the drain terminal of M 2-32 The drain terminal of, M 2-31 The source terminal of is connected to the drain terminal of M 2-33 The drain terminal of, M 2-34 The gate terminal of is connected to the drain terminal of M 2-34 The drain terminal of, M 2-33 The gate terminal of, M 2-32 The gate terminal of, M 2-35 The gate terminal of, the current source I BIAS1 Connected.

[0057] (3) Driver stage circuit

[0058] The driver stage circuit provides driving ability for the power stage circuit, improving the load-carrying capacity of the power transistor M N The circuit adopts a two-stage operational amplifier structure composed of PMOS and NMOS dual-input pair transistors. The first stage is divided into a folded cascode amplifier composed of NMOS pair transistors, which consists of M 3-2 ~M 3-10 , Q 3-1 ~Q 3-8 and works when the input voltage is higher than the intermediate level; a folded cascode amplifier composed of PMOS pair transistors, which consists of M 3-11 ~M 3-25 and works when the input voltage is lower than the intermediate level. The second stage is a dual-input single-output operational amplifier, which consists of M 3-26 ~M 3-32 , Q 3-9 ~Q 3-10 transistors to achieve a rail-to-rail input common-mode level range and ensure full conduction within the input voltage range of 0.8 to 4.0V.

[0059] Figure 3 For the driver stage circuit designed in this embodiment, the circuit structure is as follows: the gate and drain of M 3-1 are connected and connected to the gate terminal of M 3-2 , the gate terminal of M 3-7 , the gate terminal of M 3-8 , the gate terminal of M 3-9 , the gate terminal of M 3-10 , the gate terminal of M 3-11 , the gate terminal of M 3-18 , the gate terminal of M 3-26 , the gate terminal of M BIAS3 , and the current source I 3-1 , the source terminal of M 3-2 , the source terminal of M 3-7 , the source terminal of M 3-8 , the source terminal of M 3-9 , the source terminal of M 3-10 , the source terminal of M 3-11 , the source terminal of M 3-18 , the source terminal of M 3-26 , the negative terminal of R 3-3 , the collector of Q 3-3 , the collector of Q 3-4 is grounded. The drain terminal of M 3-2 is connected to the source terminal of M 3-2 , the source terminal of M 3-4 . The gate terminal of M 3-3 is connected to the output of the error amplifier, the gate terminal of M 3-16 . The drain terminal of M 3-3 is connected to M 3-5The drain terminal of, Q 3-6 The base terminal of, Q 3-7 The base terminal of, C 3-1 Is connected to the negative terminal of, M 3-4 The gate terminal of is connected to M 3-32 The drain terminal of, M 3-17 The gate terminal of, M 3-30 The drain terminal of, power transistor M N The gate terminal V of G , M 3-4 The drain terminal is connected to M 3-6 The drain terminal of, Q 3-5 The base terminal of, the base terminal of Q8, C 3-2 Is connected to the negative terminal of, M 3-5 The gate terminal is connected to Q 3-7 The emitter terminal of, M 3-25 The gate terminal of, Q 3-3 The emitter terminal of, M 3-10 Is connected to the drain terminal of, M 3-6 The gate terminal of is connected to Q 3-8 The emitter terminal of, M 3-24 The gate terminal of, Q 3-4 The emitter terminal of, M 3-9 Is connected to the drain terminal of, Q 3-5 The emitter terminal is connected to Q 3-1 The emitter terminal of, Q 3-6 The emitter terminal is connected to Q 3-2 The emitter terminal of, Q 3-1 The base terminal is connected to Q 3-4 The base terminal of, Q 3-1 The collector terminal is connected to the drain terminal of M3 - 7, Q 3-2 The base terminal of is connected to Q 3-2 The collector terminal of, Q 3-3 The base terminal of, M 3-8 Is connected to the drain terminal of, Q 3-5 The collector terminal of, Q 3-6 The collector terminal of, Q 3-7 The collector terminal of, Q 3-8 The collector terminal of, M 3-5 The source terminal of, M 3-6 The source terminal of, C 3-1 The positive terminal of, C 3-2 The positive terminal of, M 3-12 The source terminal of, M 3-13 The source terminal of, M 3-14 The source terminal of, M 3-21 The source terminal of, M 3-24 The source terminal of, M 3-25 The source terminal of, M 3-27 The source terminal of, M 3-28 The source terminal of, M 3-29 The source terminal of, M 3-30 The source terminal is connected to the power supply, M 3-11 The drain terminal of is connected to M3-12 the drain terminal of, M 3-12 the gate terminal of, M 3-13 the gate terminal of, M 3-14 is connected to the gate terminal of, M 3-13 the drain terminal of is connected to M 3-16 the source terminal of, M 3-17 the source terminal of, M 3-14 the drain terminal of is connected to M 3-15 the source terminal of, M 3-15 the gate of is connected to M 3-15 the drain terminal of, R 3-1 the negative terminal of, M 3-19 the drain terminal of, R 3-2 the negative terminal of, M 3-20 the drain terminal, R 3-3 is connected to the positive terminal of, M 3-16 the drain terminal of is connected to M 3-19 the source terminal of, M 3-22 the drain terminal of, Q 3-10 is connected to the base of, M 3-17 the drain terminal of is connected to M 3-20 the source terminal of, M 3-23 the drain terminal of, Q 3-9 is connected to the base of, the positive terminal of R3-1 is connected to M 3-19 the gate terminal of, R 3-2 the positive terminal of is connected to M 3-20 the gate terminal of, M 3-18 the drain terminal of is connected to M 3-21 the gate terminal of, M 3-21 the drain terminal of, M 3-22 the gate terminal of, M 3-23 is connected to the gate terminal of, M 3-22 the source terminal of is connected to M 3-24 the drain terminal of, M 3-23 the source terminal of is connected to M 3-25 the drain terminal of, M 3-26 the drain terminal of is connected to Q 3-9 the emitter, Q 3-10 the emitter of, Q 3-9 the collector of is connected to M 3-27 the drain terminal, Q 3-10 the collector of is connected to M 3-28 the drain terminal, M 3-28 the gate terminal of, M 3-29 the gate terminal of, M 3-27 the gate terminal of is connected to M 3-30 the gate terminal of, M 3-29 the drain terminal of is connected to M 3-31 the drain terminal of, M 3-31 the gate terminal of, M 3-32 the gate terminal of.

[0060] (4) Power stage circuit

[0061] The drive-stage circuit provides driving ability for the power-stage circuit, improving the load-carrying capacity of power transistor M N . The circuit adopts a two-stage operational amplifier structure composed of PMOS and NMOS dual-input pair transistors. The first stage is divided into a folded cascode amplifier composed of NMOS pair transistors, which is composed of M 3-2 ~M 3-10 , Q 3-1 ~Q 3-8 and works when the input voltage is higher than the intermediate level; a folded cascode amplifier composed of PMOS pair transistors, which is composed of M 3-11 ~M 3-25 and works when the input voltage is lower than the intermediate level. The second stage is a dual-input single-output operational amplifier, which is composed of M 3-26 ~M 3-32 , Q 3-9 ~Q 3-10 transistors to achieve a rail-to-rail input common-mode level range and ensure full conduction within the input voltage range of 0.8 to 4.0V.

[0062] Figure 3 The drive-stage circuit designed in this embodiment has a circuit structure as follows: the gate and drain of M 3-1 are connected and connected to the gate terminals of M 3-2 , M 3-7 , M 3-8 , M 3-9 , M 3-10 , M 3-11 , M 3-18 , M 3-26 , and the gate terminal of current source I BIAS3 . The source terminals of M 3-1 , M 3-2 , M 3-7 , M 3-8 , M 3-9 , M 3-10 , M 3-11 , M 3-18 , M 3-26 , the negative terminal of R 3-3 , the collector of Q 3-3 , and the collector of Q 3-4 are grounded. The drain terminal of M 3-2 is connected to the source terminals of M 3-2 and M 3-4 . The gate terminal of M 3-3 is connected to the output of the error amplifier and the gate terminal of M 3-16 . The drain terminal of M 3-3 is connected to the drain terminals of M 3-5 , the base of Q 3-6 , the base of Q 3-7 , and C3-1 is connected to the negative terminal of, M 3-4 The gate terminal of is connected to M 3-32 The drain terminal of, M 3-17 The gate terminal of, M 3-30 The drain terminal of, power transistor M N The gate terminal V of G , M 3-4 The drain terminal is connected to M 3-6 The drain terminal of, Q 3-5 The base terminal of, the base terminal of Q8, C 3-2 is connected to the negative terminal of, M 3-5 The gate terminal is connected to Q 3-7 The emitter terminal of, M 3-25 The gate terminal of, Q 3-3 The emitter terminal of, M 3-10 The drain terminal is connected to M 3-6 The gate terminal of is connected to Q 3-8 The emitter terminal of, M 3-24 The gate terminal of, Q 3-4 The emitter terminal of, M 3-9 The drain terminal is connected to Q 3-5 The emitter terminal of is connected to Q 3-1 The emitter terminal of, Q 3-6 The emitter terminal of is connected to Q 3-2 The emitter terminal of, Q 3-1 The base terminal of is connected to Q 3-4 The base terminal of, Q 3-1 The collector terminal of is connected to the drain terminal of M3 - 7, Q 3-2 The base terminal of is connected to Q 3-2 The collector terminal of, Q 3-3 The base terminal of, M 3-8 The drain terminal is connected to Q 3-5 The collector terminal of, Q 3-6 The collector terminal of, Q 3-7 The collector terminal of, Q 3-8 The collector terminal of, M 3-5 The source terminal of, M 3-6 The source terminal of, C 3-1 The positive terminal of, C 3-2 The positive terminal of, M 3-12 The source terminal of, M 3-13 The source terminal of, M 3-14 The source terminal of, M 3-21 The source terminal of, M 3-24 The source terminal of, M 3-25 The source terminal of, M 3-27 The source terminal of, M 3-28 The source terminal of, M 3-29 The source terminal of, M 3-30 The source terminal of is connected to the power supply, M 3-11 The drain terminal of is connected to M 3-12 The drain terminal of, M 3-12 The gate terminal of, M 3-13The gate terminal of, M 3-14 is connected to the gate terminal of, M 3-13 The drain terminal of is connected to M 3-16 The source terminal of, M 3-17 The source terminal of, M 3-14 The drain terminal of is connected to M 3-15 The source terminal of, M 3-15 The gate of is connected to M 3-15 The drain terminal of, R 3-1 The negative terminal of, M 3-19 The drain terminal of, R 3-2 The negative terminal of, M 3-20 Drain terminal, R 3-3 is connected to the positive terminal of, M 3-16 The drain terminal of is connected to M 3-19 The source terminal of, M 3-22 The drain terminal of, Q 3-10 is connected to the base of, M 3-17 The drain terminal of is connected to M 3-20 The source terminal of, M 3-23 The drain terminal of, Q 3-9 is connected to the base of, The positive terminal of R3-1 is connected to M 3-19 The gate terminal of, R 3-2 The positive terminal of is connected to M 3-20 The gate terminal of, M 3-18 The drain terminal of is connected to M 3-21 The gate terminal of, M 3-21 The drain terminal of, M 3-22 The gate terminal of, M 3-23 is connected to the gate terminal of, M 3-22 The source terminal of is connected to M 3-24 The drain terminal of, M 3-23 The source terminal of is connected to M 3-25 The drain terminal of, M 3-26 The drain terminal of is connected to Q 3-9 Emitter, Q 3-10 The emitter of, Q 3-9 The collector of is connected to M 3-27 Drain terminal, Q 3-10 The collector of is connected to M 3-28 Drain terminal, M 3-28 The gate terminal of, M 3-29 The gate terminal of, M 3-27 The gate terminal of is connected to M 3-30 The gate terminal of, M 3-29 The drain terminal of is connected to M 3-31 The drain terminal of, M 3-31 The gate terminal of, M 3-32 The gate terminal.

[0063] In use, for a high-precision ultra-low dropout linear regulator circuit proposed by the present invention, phase values under different output capacitor conditions are as Figure 4As shown in (a) and (b) of the figure, within the full input voltage range with a load of 3 A and an output capacitance of 0 to 1 mF, the phase margin is greater than 39°; within the full input voltage range with a load of 5 mA and an output capacitance of 0 to 100 uF, the phase margin is greater than 30°. The output voltage curve is as Figure 5 shown. Within the full input voltage range with a load of 0 to 3 A, the output accuracy reaches -0.1% to 0.3%, the load regulation rate is less than 0.0005% / V, and the linear regulation rate is less than 0.03% / A.

[0064] The above-described embodiments are only relatively preferred specific embodiments of the present invention. Ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-precision ultra-low voltage dropout linear regulator circuit, characterized in that: It includes an error amplifier circuit, a driving stage circuit, a dynamic zero compensation circuit and a power stage circuit; The power stage circuit uses an NMOS tube as a power tube, which is driven by a driver stage circuit to generate a feedback terminal voltage which is input to the error amplifier circuit; The error amplifier circuit compares the feedback terminal voltage with the reference voltage, and the difference is used to adjust the gate terminal voltage of the power tube in the power stage circuit; The dynamic zero compensation circuit is provided with a sampling tube, which mirrors the load current flowing through the power tube in the power stage circuit, generates a zero point that changes with the load, and compensates the output pole of the entire voltage regulator circuit.

2. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 1, characterized in that: The power stage circuit includes a power tube M N , resistor R 1-1 , resistor R 1-2 , resistor R L、 Capacitor C L ;in: The same-direction terminal of the error amplifier is connected to the reference voltage, and the negative terminal of the error amplifier is connected to the resistor R 1-1 Negative terminal and resistor R 1-2 The positive end is connected to the positive end, the output end of the error amplifier is connected to the same direction end of the driving stage circuit, and the reverse end of the driving stage circuit is connected to the output end of the driving stage and the power tube M N The gate end of the sampling tube is connected to the gate end of the sampling tube; The input end of the dynamic zero compensation circuit is connected to the drain and gate ends of the sampling tube, and the output end of the dynamic zero compensation circuit is connected to the error amplifier circuit. N The source end of the sampling tube is connected to the source end of the sampling tube; The power supply end of the error amplifier, the power supply end of the drive stage circuit, the power supply end of the dynamic zero compensation circuit and the input first power supply V BIAS Connected, power tube M N The drain terminal is connected to the second power supply V IN Connected, power tube M N Source terminal and resistor R 1-1 Positive terminal, capacitor C L Positive terminal, load resistance R L The positive end is connected; Resistor R 1-2 The negative terminal of capacitor C L The negative terminal of the resistor R L The negative terminal is grounded.

3. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 1, characterized in that: The error amplifier circuit adopts a folded common source and common gate structure, including a capacitor C 2-2 , resistor R 2-3 、MOS tube M 2-1 ~M 2-23 and current source I BIAS2 ; MOS tube M 2-1 The gate terminal feedback voltage V FB , MOS tube M 2-2 The gate terminal reference voltage of MOS tube M 2-1 The drain end of the MOS tube M 2-6 The drain end of MOS tube M 2-4 The source end of MOS tube M 2-12 The drain end of MOS tube M is connected to 2-2 The drain end of the MOS tube M 2-5 The drain end of MOS tube M 2-3 The source end of MOS tube M 2-11 The drain end of MOS tube M is connected to 2-1 The source end of MOS tube M 2-2 The source end and MOS tube M 2-14 The drain end of MOS tube M 2-5 The source end of MOS tube M 2-6 The source end of MOS tube M 2-22 Source, MOS tube M 2-23 The source end of the MOS tube M is grounded. 2-5 The gate terminal of MOS tube M 2-6 The gate terminal of MOS tube M 2-22 The gate terminal of MOS tube M 2-23 The gate terminal of MOS tube M 2-23 The drain terminal, current source I BIAS2 Connected, MOS tube M 2-3 The gate terminal of MOS tube M 2-4 The gate terminal and MOS tube M 2-19 The gate terminal of MOS tube M 2-20 The gate terminal of MOS tube M 2-21 The gate end of MOS tube M is connected to 2-3 The drain end of the MOS tube M 2-7 The drain end of MOS tube M 2-9 The gate terminal of MOS tube M 2-10 The gate end of MOS tube M is connected to 2-4 The drain end of the MOS tube M 2-8 The drain terminal, capacitor C 2-2 The positive terminal and the driving stage circuit are connected; MOS tube M 2-7 The gate terminal and MOS tube M 2-8 The gate terminal of MOS tube M 2-16 The gate terminal of MOS tube M 2-17 The gate terminal of MOS tube M 2-18 The gate end of MOS tube M is connected to 2-7 The source terminal of MOS tube M 2-9 The drain end of MOS tube M 2-8 The source terminal of MOS tube M 2-10 The drain end of MOS tube M 2-9 The source end of MOS tube M 2-10 The source end of MOS tube M 2-13 The source end of MOS tube M 2-14 The source end of MOS tube M 2-15 The source end of MOS tube M 2-16 The source terminal is connected to the first power supply V BIAS , MOS tube M 2-11 The gate terminal of MOS tube M is grounded. 2-11 The source end and MOS tube M 2-12 The source end of MOS tube M 2-13 The drain end of MOS tube M 2-12 The gate terminal is connected to the output of the dynamic zero compensation circuit, and the MOS tube M 2-13 The gate terminal of MOS tube M 2-14 The gate terminal of MOS tube M 2-15 The gate terminal is connected to a dynamic zero compensation circuit; MOS tube M 2-16 The drain terminal of MOS tube M 2-17 The source end of MOS tube M 2-17 The drain terminal of MOS tube M 2-18 The source end of MOS tube M 2-18 The drain terminal of MOS tube M 2-22 The drain end of MOS tube M 2-19 The drain terminal of MOS tube M 2-15 The drain end of MOS tube M 2-19 The source terminal of MOS tube M 2-20 The drain end of MOS tube M 2-20 The source terminal of MOS tube M 2-21 The drain end of MOS tube M 2-21 The source end is grounded, and the capacitor C 2-2 The negative terminal resistor R 2-3 The positive end, R 2-3 The negative terminal is grounded.

4. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 1, characterized in that: The dynamic zero compensation circuit includes a resistor R 2-1 ~R 2-2、 Capacitor C 2-1 , MOS tube M 2-24 ~M 2-35 , current source I BIAS1 、Sampling tube M C ; Among them, sampling tube M C Same type as power tube; Resistor R 2-1 The positive terminal of MOS tube M 2-35 The source end of MOS tube M 2-32 The source end of MOS tube M 2-33 The source end of MOS tube M 2-34 The source terminal is connected to the first power supply V BIAS ; R 2-1 The negative terminal is connected to the MOS tube M 2-24 The drain end of MOS tube M 2-26 The drain end of MOS tube M 2-24 The gate terminal input voltage of MOS tube M 2-24 The source terminal M 2-25 The drain end of MOS tube M 2-25 The gate terminal of MOS tube M 2-26 The gate terminal power tube M N The gate terminal V G , MOS tube M 2-25 The source end of MOS tube M 2-26 The source termination capacitance C 2-1 The positive terminal of capacitor C 2-1 The negative terminal is connected to the MOS tube M 2-27 The drain terminal, resistor R 2-2 The positive terminal of MOS tube M 2-27 The gate terminal and MOS tube M 2-28 The gate terminal of MOS tube M 2-29 The gate terminal of MOS tube M 2-29 The drain end of MOS tube M 2-30 The drain end of MOS tube M 2-35 The drain end of MOS tube M 2-27 The source terminal of MOS tube M 2-28 The drain end of MOS tube M 2-28 The source end, R 2-2 The negative terminal of MOS tube M 2-29 The source end of the MOS tube M is grounded. 2-30 The gate terminal and M 2-31 The gate terminal of MOS tube M 2-31 Drain end, sampling tube M C The drain terminal V C Connected, MOS tube M 2-30 The source terminal of MOS tube M 2-32 The drain end of MOS tube M 2-31 The source terminal of MOS tube M 2-33 The drain end of MOS tube M 2-34 The gate terminal and MOS tube M 2-34 The drain end of MOS tube M 2-33 The gate terminal of MOS tube M 2-32 The gate terminal of MOS tube M 2-35 The gate terminal, current source I BIAS1 connected.

5. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 4, characterized in that: Sampling tube M c The current of the sampling power tube is passed through the MOS tube M 2-30 And MOS tube M 2-31 The image formation and load current I O Proportional to the sampled current I S , I S is the current flowing through MOS tube M 2-30 The tube current, and I S :I O =1:n, n represents MOS tube M 2-30 And MOS tube M 2-31 , mirror ratio of power tube; sampling current I S and a fixed bias current I B Commonly flow into MOS tube M 2-29 , I B is the current flowing through MOS tube M 2-35 The current of the tube makes the MOS tube M 2-29 The gate voltage of the tube becomes the bias gate voltage V related to the load current. G29 , so that the zero point changes with the load current.

6. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 1, characterized in that: The error amplifier circuit uses a two-stage op amp structure consisting of a PMOS and NMOS dual-input pair of tubes: The first stage is divided into a folded cascode amplifier composed of an NMOS pair of tubes, which works when the input voltage is higher than the intermediate level; a folded cascode amplifier composed of a PMOS pair of tubes, which works when the input voltage is lower than the intermediate level; The second stage is a dual-input single-output operational amplifier to achieve a rail-to-rail input common-mode level range and ensure full conduction within the input voltage range.

7. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 6, characterized in that: The driving circuit includes a MOS tube M 3-1 ~M 3-32 , transistor Q 3-1 ~Q 3-10 ; In the first stage, the folded cascode amplifier composed of NMOS tubes is composed of M 3-1 ~M 3-10 and Q 3-1 ~Q 3-8 The folded cascode amplifier composed of a PMOS pair consists of M 3-11 ~M 3-25 The second stage dual-input single-output operational amplifier consists of M 3-26 ~M 3-32 and Q 3-9 ~Q 3-10 Tube composition.

8. The high-precision ultra-low voltage dropout linear regulator circuit according to claim 7, characterized in that: The circuit structure of the driver stage circuit is: MOS tube M 3-1 The gate and drain of the MOS tube M are connected 3-2 The gate terminal of MOS tube M 3-7 The gate terminal of MOS tube M 3-8 The gate terminal of MOS tube M 3-9 Gate terminal, MOS tube M 3-10 The gate terminal of MOS tube M 3-11 The gate terminal of MOS tube M 3-18 The gate terminal of MOS tube M 3-26 The gate terminal and MOS tube current source I BIAS3 Connected, MOS tube M 3-1 The source end of MOS tube M 3-2 The source end of MOS tube M 3-7 The source end of MOS tube M 3-8 The source end of MOS tube M 3-9 The source end of MOS tube M 3-10 The source end of MOS tube M 3-11 The source end of MOS tube M 3-18 The source end of MOS tube M 3-26 The source end of MOS tube R 3-3 The negative terminal of transistor Q 3-3 The collector of transistor Q 3-4 The collector of MOS tube M is grounded. 3-2 The drain terminal of MOS tube M 3-2 The source end of MOS tube M 3-4 The source end of MOS tube M 3-3 The gate terminal is connected to the output of the error amplifier, MOS tube M 3-16 The gate end of MOS tube M 3-3 The drain terminal and MOS tube M 3-5 The drain terminal of transistor Q 3-6 The base of transistor Q 3-7 The base of C 3-1 The negative terminal of MOS tube M 3-4 The gate terminal MOS tube M 3-32 The drain end of MOS tube M 3-17 The gate terminal of MOS tube M 3-30 The drain end and the gate end of the power tube V G , MOS tube M 3-4 The drain terminal and MOS tube M 3-6 The drain terminal of transistor Q 3-5 The base of transistor Q8, C 3-2 The negative terminal of MOS tube M 3-5 Gate terminal and Q 3-7 The emitter of MOS tube M 3-25 The gate terminal of transistor Q 3-3 The emitter of MOS tube M 3-10 The drain end of MOS tube M 3-6 The gate terminal Q 3-8 The emitter of MOS tube M 3-24 The gate terminal of transistor Q 3-4 The emitter of MOS tube M 3-9 The drain end is connected to Transistor Q 3-5 The emitter of transistor Q 3-1 The emitter of transistor Q 3-6 The emitter of transistor Q 3-2 The emitter of transistor Q 3-1 The base of transistor Q 3-4 The base of transistor Q 3-1 The collector is connected to M 3-7 Drain terminal, transistor Q 3-2 The base of transistor Q 3-2 The collector of transistor Q 3-3 The base of MOS tube M 3-8 The drain end of transistor Q 3-5 The collector of transistor Q 3-6 The collector of transistor Q 3-7 The collector of transistor Q 3-8 The collector of MOS tube M 3-5 The source end of MOS tube M 3-6 The source end, C 3-1 The positive end, C 3-2 The positive terminal of MOS tube M 3-12 The source end of MOS tube M 3-13 The source end of MOS tube M 3-14 The source end of MOS tube M 3-21 The source end of MOS tube M 3-24 The source end of MOS tube M 3-25 The source end of MOS tube M 3-27 The source end of MOS tube M 3-28 The source end of MOS tube M 3-29 The source end of MOS tube M 3-30 The source terminal is connected to the power supply, MOS tube M 3-11 The drain end of the MOS tube M 3-12 The drain end of MOS tube M 3-12 The gate terminal of MOS tube M 3-13 The gate terminal of MOS tube M 3-14 The gate end of MOS tube M is connected to 3-13 The drain terminal of MOS tube M 3-16 The source end of MOS tube M 3-17 The source end of MOS tube M 3-14 The drain terminal of MOS tube M 3-15 The source end of MOS tube M 3-15 The gate and MOS tube M 3-15 The drain terminal, R 3-1 The negative terminal of MOS tube M 3-19 The drain terminal, R 3-2 The negative terminal of MOS tube M 3-20 Drain, R 3-3 The positive end of MOS tube M 3-16 The drain end of the MOS tube M 3-19 The source end of MOS tube M 3-22 The drain terminal of transistor Q 3-10 The base of MOS tube M is connected to 3-17 The drain end of the MOS tube M 3-20 The source end, M 3-23 The drain terminal of transistor Q 3-9 The base of 3-1 The positive terminal MOS tube M 3-19 The gate terminal, R 3-2 The positive terminal MOS tube M 3-20 The gate end of MOS tube M 3-18 The drain end of the MOS tube M 3-21 The gate terminal of MOS tube M 3-21 The drain end of MOS tube M 3-22 The gate terminal of MOS tube M 3-23 The gate end of MOS tube M is connected to 3-22 The source terminal of MOS tube M 3-24 The drain end of MOS tube M 3-23 The source terminal of MOS tube M 3-25 The drain end of MOS tube M 3-26 The drain terminal of transistor Q 3-9 Emitter, transistor Q 3-10 The emitter of transistor Q 3-9 The collector of MOS tube M 3-27 Drain terminal, transistor Q 3-10 The collector of MOS tube M 3-28 Drain, MOS tube M 3-28 The gate terminal of MOS tube M 3-29 The gate end of MOS tube M 3-27 The gate terminal MOS tube M 3-30 The gate end of MOS tube M 3-29 The drain terminal of MOS tube M 3-31 The drain end of MOS tube M 3-31 The gate terminal of MOS tube M 3-32 gate end.

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