Voltage following control circuit and chip
By designing a voltage following control circuit including a voltage divider module, a comparator and a voltage conversion module, the problem of high power consumption when the output range changes is solved, and synchronous changes in the power supply voltage and the output voltage are realized, reducing power consumption and cost.
Patent Information
- Application Number
- CN202510336448.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-06-20
AI Technical Summary
When the output range of the DAC circuit changes greatly, the power supply voltage remains above the maximum output voltage plus the margin voltage, resulting in high power consumption, low energy efficiency, and heating.
Design a voltage follow-up control circuit, including the power supply voltage terminal, reference voltage terminal, voltage divider module, comparator, voltage conversion module, buffer and boost driver, and generate voltage divider voltage through the voltage divider module. The comparator and voltage converter module realize synchronous changes in the power supply voltage and the output voltage to reduce power consumption.
By reducing the delay and high voltage recovery of the feed back circuit, the power consumption and cost of the DAC circuit are reduced, while improving energy efficiency and output voltage accuracy.
Smart Images
Figure CN120179009A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular, to a voltage following control circuit and a chip. Background Art
[0002] For a digital-to-analog conversion (DAC) circuit, when the output range changes greatly, maintaining the power supply voltage above the maximum value of the output voltage plus the margin voltage will result in high power consumption, leading to problems such as low energy efficiency and high heat generation. Summary of the Invention
[0003] It would be advantageous to provide a mechanism that alleviates, mitigates, or even eliminates one or more of the above problems.
[0004] According to one aspect of the present disclosure, there is provided a voltage following control circuit, comprising: a power supply voltage terminal configured to provide a power supply voltage; a reference voltage terminal configured to provide a reference voltage; a voltage dividing module electrically connected to the power supply voltage terminal to generate a divided voltage; a comparator including a first input terminal, an output terminal, and a second input terminal electrically connected to the voltage dividing module; a voltage conversion module including an input terminal electrically connected to the reference voltage terminal, a first output terminal, and a second output terminal electrically connected to the first input terminal of the comparator; a first buffer including an output terminal and an input terminal electrically connected to the first output terminal of the voltage conversion module; and a boost driver including an input terminal electrically connected to the output terminal of the comparator and an output terminal electrically connected to the power supply voltage terminal, and wherein the voltage conversion module is configured to provide a first conversion voltage to the first buffer based on the reference voltage, and provide a second conversion voltage to the first input terminal of the comparator based on the reference voltage.
[0005] According to another aspect of the present disclosure, there is provided a chip including the above voltage following control circuit.
[0006] These and other aspects of the present disclosure will be apparent from, and will be elucidated with reference to, the embodiments described hereinafter. Brief Description of the Drawings
[0007] In the following description of the exemplary embodiments with reference to the accompanying drawings, more details, features, and advantages of the present disclosure are disclosed. In the drawings:
[0008] Figure 1 is a schematic circuit diagram illustrating a voltage following control circuit according to an exemplary embodiment of the present disclosure;
[0009] Figure 2 is a schematic circuit diagram illustrating a voltage following control circuit of a specific circuit with a voltage conversion module according to an exemplary embodiment of the present disclosure;
[0010] Figure 3 FIG. is a schematic circuit diagram showing a specific circuit having a voltage conversion module and a voltage follower control circuit of a third digital-to-analog converter according to an exemplary embodiment of the present disclosure;
[0011] Figure 4 FIG. is a schematic circuit diagram showing a voltage follower control circuit of another specific circuit having a voltage conversion module according to an exemplary embodiment of the present disclosure;
[0012] Figure 5 FIG. is a schematic circuit diagram showing a voltage follower control circuit of another specific circuit having a voltage conversion module and a fifth digital-to-analog converter according to an exemplary embodiment of the present disclosure;
[0013] Figure 6 FIG. is a specific circuit diagram showing a first digital-to-analog converter and a second digital-to-analog converter in a voltage follower control circuit according to an exemplary embodiment of the present disclosure; and
[0014] Figure 7 FIG. is another specific circuit diagram showing a first digital-to-analog converter and a second digital-to-analog converter in a voltage follower control circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0015] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section without departing from the teachings of the present disclosure.
[0016] Spatial relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, an element described as "below" or "beneath" or "under" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can cover both orientations of above and below. Terms such as "before" or "in front of" and "after" or "subsequent to" can similarly be used, for example, to indicate the order in which light passes through an element. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly. Additionally, it will also be understood that when a layer is referred to as "between two layers", it can be the only layer between the two layers, or there can also be one or more intermediate layers.
[0017] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" includes only A, only B, and both A and B.
[0018] It will be understood that when an element or layer is referred to as "on another element or layer", "connected to another element or layer", "coupled to another element or layer", or "adjacent to another element or layer", it can be directly on the other element or layer, directly connected to the other element or layer, directly coupled to the other element or layer, or directly adjacent to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on another element or layer", "directly connected to another element or layer", "directly coupled to another element or layer", "directly adjacent to another element or layer", there are no intervening elements or layers. However, in any case, "on" or "directly on" should not be construed as requiring one layer to completely cover the underlying layer.
[0019] Embodiments of the present disclosure are described herein with reference to schematic illustrations of idealized embodiments of the present disclosure (and intermediate structures). As such, variations in the illustrated shapes are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein, but should include, for example, shape deviations resulting from manufacturing. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the present disclosure.
[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0021] In the prior art, the DAC uses a feedback circuit and high-voltage sampling to achieve the follow-up control of the power supply voltage and the output voltage, but there are problems such as high delay caused by the feedback circuit, high cost caused by high-voltage back-sampling, and high power consumption.
[0022] Exemplary embodiments of the present disclosure will be described in detail below, which can be used to benefit for many reasons, for example, to alleviate or mitigate these undesirable side effects.
[0023] Figure 1 is a schematic circuit diagram illustrating a voltage follow-up control circuit according to an exemplary embodiment of the present disclosure. Referring Figure 1 , the voltage follow-up control circuit 100 may include: a power supply voltage terminal HV, configured to provide a power supply voltage V H ; a reference voltage terminal VREF, configured to provide a reference voltage V REF; A voltage division module, electrically connected to the power supply voltage terminal HV to generate a divided voltage V i ; A comparator EA, including a first input terminal, an output terminal, and a second input terminal electrically connected to the voltage division module; A voltage conversion module, including an input terminal electrically connected to the reference voltage terminal VREF, a first output terminal, and a second output terminal electrically connected to the first input terminal of the comparator EA; A first buffer BUF1, including an output terminal and an input terminal electrically connected to the first output terminal of the voltage conversion module; And a boost driver, including an input terminal electrically connected to the output terminal of the comparator EA and an output terminal electrically connected to the power supply voltage terminal HV, and wherein the voltage conversion module is configured to provide a first conversion voltage V to the first buffer BUF1 based on the reference voltage V REF and provide a second conversion voltage V to the first input terminal of the comparator EA based on the reference voltage V C1 REF C2 .
[0024] In some embodiments, the voltage division module includes: a reference voltage terminal GND; a first resistor R1; and a second resistor R2, and the first resistor R1 and the second resistor R2 are connected in series between the power supply voltage terminal V H and the reference voltage terminal GND.
[0025] It should be understood that the voltage division module can also obtain the divided voltage V through a buffer, a high-voltage switch, or other conventional means known to those skilled in the art, and no limitation is made here. i .
[0026] In some embodiments, when the second conversion voltage V C2 is greater than the voltage V at the node between the first resistor R1 and the second resistor R2 i , the boost driver starts to raise the power supply voltage V H .
[0027] It should be understood that the first buffer BUF1 can provide a certain gain for V C1 , and the gain magnitude is matched with the voltage division multiple of the voltage division module.
[0028] In combination Figure 1 for illustration, the digital inputs (codes) of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, and when the precisions of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, the voltage conversion module converts the reference voltage V REF into a homologous first conversion voltage V C1 and a second conversion voltage V C2 , and at this time V C1 = V C2 . The power supply voltage VH A divided voltage V is generated at the node between the first resistor R1 and the second resistor R2 i = V H *R2 / (R1 + R2). When the second conversion voltage V C2 is greater than the divided voltage V i , the comparator EA outputs a flip to activate the boost driver, causing V H to rise to V C2 *(R1 + R2) / R2. Meanwhile, the first buffer BUF1 can provide a gain of (R1 + R2) / R2 for V C1 , such that V OUT = V C1 *(R1 + R2) / R2, thereby achieving synchronous variation of the power supply voltage V H and the output voltage V OUT .
[0029] In the example, the first buffer BUF1 is powered by HV, and the other parts of the circuit can be powered by other power supplies, for example, a fixed - voltage low - voltage power supply (not shown in the figure).
[0030] Thus, through the first conversion voltage V REF and the second conversion voltage V C1 from the same source (i.e., the same reference voltage V C2 ), synchronous variation of the power supply voltage V H and the output voltage V OUT is achieved, which can not only reduce the delay caused by the feedback circuit but also eliminate the need for high - voltage feedback, thus reducing costs.
[0031] It should be understood that Figure 1 the specific circuit of the boost driver not shown in
[0032] is a conventional setting in the art and will not be elaborated herein. Figure 1 It should be understood that the "GND" ground terminal in
[0033] Figure 2 is only an example of the "reference voltage terminal". In some embodiments, the reference voltage terminal can be a voltage terminal configured to receive a ground voltage, a negative power supply voltage, or a certain fixed potential voltage. Figure 2 is a schematic circuit diagram of the voltage - following control circuit 100 with a voltage conversion module according to an exemplary embodiment of the present disclosure. Referring to C1; and a second digital-to-analog converter DAC2, electrically connected between the reference voltage terminal VREF and the first input terminal of the comparator EA to provide a second conversion voltage V C2 .
[0034] In some examples, the second digital-to-analog converter DAC2 can be a DAC with an accuracy of N bits, and the first digital-to-analog converter DAC1 can also be a DAC with an accuracy of N bits, or a DAC with an accuracy greater than N bits, for example, a DAC with an accuracy of N+M bits, where both N and M are integers greater than 0.
[0035] For the DAC circuit, the HV supplies power to the first buffer BUF1 and requires a voltage higher than its output voltage V OUT and leave enough margin voltage V headroom to ensure the accuracy of the output voltage V OUT .
[0036] In some embodiments, the second conversion voltage V C2 is the first conversion voltage V C1 plus the offset voltage V headroom used to generate the margin voltage V offset .
[0037] In some other embodiments, the comparator EA can be configured to provide the offset voltage V headroom for generating the margin voltage V offset .
[0038] It should be understood that the offset voltage V offset can also be provided by other conventional settings known to those skilled in the art, and is not limited to the above several methods.
[0039] In some embodiments, when the second conversion voltage V C2 is greater than the voltage V i at the node between the first resistor R1 and the second resistor R2, the boost driver starts to raise the power supply voltage V H .
[0040] Combined Figure 2 for illustration, the digital inputs (codes) of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, and when the accuracies of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, the first digital-to-analog converter DAC1 converts the reference voltage V REF into the first conversion voltage V C1 , and the second digital-to-analog converter DAC2 converts the reference voltage V REF into the second conversion voltage V C2 , where V C2 =V C1 +Voffset The power supply voltage V H generates a divided voltage V at the node between the first resistor R1 and the second resistor R2 i = V H * R2 / (R1 + R2). When the second conversion voltage V C2 is greater than the divided voltage V i , the comparator EA outputs a flip to start the boost driver, such that V H rises to V C2 * (R1 + R2) / R2. At this time, the margin voltage V headroom = V offset * (R1 + R2) / R2. Meanwhile, the first buffer BUF1 can provide a gain of (R1 + R2) / R2 for V C1 , such that V OUT = V C1 * (R1 + R2) / R2, thereby achieving synchronous variation between the power supply voltage V H and the output voltage V OUT , and leaving sufficient margin voltage V headroom to ensure the accuracy of the output voltage V OUT .
[0041] Figure 3 FIG. shows a schematic circuit diagram of a specific circuit having a voltage conversion module and a voltage follower control circuit 100 of a third digital - to - analog converter DAC3 according to an exemplary embodiment of the present disclosure. Referring to Figure 3 , the voltage conversion module further includes: a third digital - to - analog converter DAC3, electrically connected between the input terminals of the first digital - to - analog converter DAC1 and the first buffer BUF1 to improve the accuracy of the first conversion voltage V C1 .
[0042] Thus, by cascading additional DACs, a high - precision output of V OUT can be achieved.
[0043] Figure 4 FIG. shows a schematic circuit diagram of a voltage follower control circuit 100 of another specific circuit having a voltage conversion module according to an exemplary embodiment of the present disclosure. Referring to Figure 4 , the voltage conversion module in the voltage follower control circuit 100 may include: a fourth digital - to - analog converter DAC4, including a first output terminal, an input terminal electrically connected to the reference voltage terminal VREF, and a second output terminal electrically connected to the input terminal of the first buffer BUF1; and a second buffer BUF2, including a first input terminal electrically connected to the first output terminal of the fourth digital - to - analog converter DAC4, a second input terminal, and an output terminal electrically connected to the second input terminal of the second buffer BUF2.
[0044] Continuing to refer toFigure 4 , in some embodiments, the voltage conversion module further includes: a current source I1; and a third resistor R3, the current source I1 and the third resistor R3 are connected in series between the power supply voltage terminal HV and the output terminal of the second buffer BUF2, for providing an offset voltage V for generating a margin voltage V headroom . offset , and wherein, the first input terminal of the comparator EA is electrically connected to the node between the current source I1 and the third resistor R3.
[0045] In some other embodiments, the comparator EA may be configured to provide an offset voltage V for generating a margin voltage V headroom . offset .
[0046] It should be understood that the offset voltage V offset can also be provided by other conventional settings known to those skilled in the art, and is not limited to the above several ways.
[0047] In some embodiments, when the sum of the second conversion voltage V C2 and the offset voltage V offset is greater than the voltage at the node between the first resistor R1 and the second resistor R2, the boost driver is activated to raise the power supply voltage.
[0048] In conjunction with Figure 4 for illustration, the digital inputs (codes) of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, and when the precisions of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 are the same, the first digital-to-analog converter DAC1 converts the reference voltage V REF into the first conversion voltage V C1 , the second digital-to-analog converter DAC2 converts the reference voltage V REF into the second conversion voltage V C2 , wherein, V C2 = V C1 . The power supply voltage V H generates a divided voltage V i = V H *R2 / (R1 + R2) at the node between the first resistor R1 and the second resistor R2. The current source I1 and the third resistor R3 provide V offset . When the sum of the second conversion voltage V C2 and the offset voltage V offset is greater than V i , the output of the comparator EA flips to activate the boost driver, such that V H rises to (V C2 + V offset )*(R1 + R2) / R2. At this time, the margin voltage V headroom = Voffset *(R1 + R2) / R2. At the same time, the first buffer BUF1 can be V C1 to provide a gain of (R1 + R2) / R2, such that V OUT = V C1 *(R1 + R2) / R2, thereby achieving that the power supply voltage V H varies synchronously with the output voltage V OUT and leaving enough margin voltage V headroom to ensure the accuracy of the output voltage V OUT .
[0049] Figure 5 is a schematic circuit diagram showing another specific circuit with a voltage conversion module and a voltage follower control circuit 100 of a fifth digital-to-analog converter DAC5 according to an exemplary embodiment of the present disclosure. Refer to Figure 5 , the voltage conversion module further includes: a fifth digital-to-analog converter DAC5, electrically connected between the input terminal of the fourth digital-to-analog converter DAC4 and the input terminal of the first buffer BUF1 to improve the accuracy of the first conversion voltage V C1 .
[0050] Thus, by cascading additional DACs, a high-precision output of V OUT can be achieved.
[0051] Figure 6 is a schematic circuit diagram showing a first digital-to-analog converter DAC1 with an accuracy of N bits and a second digital-to-analog converter DAC2 with an accuracy of N bits and an offset voltage V offset in the voltage follower control circuit 100 according to an exemplary embodiment of the present disclosure. Refer to Figure 6 , the first digital-to-analog converter DAC1 includes a resistor Rt, xRu, 2 N Ru in series, and 2 N taps connected in series between the reference voltage terminal VREF and the reference voltage terminal GND in sequence. The second digital-to-analog converter DAC2 includes a resistor Rt, 2 N Ru, xRu, and 2 N taps connected in series between the reference voltage terminal VREF and the reference voltage terminal GND in sequence. Among them, the resistance value of Rt in the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can be adjusted flexibly according to requirements, and xRu in the second digital-to-analog converter DAC2 is used to provide the offset voltage V offset .
[0052] Figure 7 is a schematic circuit diagram showing a first digital-to-analog converter DAC1 with an accuracy of N + M bits and a second digital-to-analog converter DAC2 with an accuracy of N bits and an offset voltage V offsetAnother specific circuit diagram of the second digital-to-analog converter DAC2. Refer to Figure 7 , the first digital-to-analog converter DAC1 includes a resistor Rt, xRu, 2 N+M Ru in series between the reference voltage terminal VREF and the reference voltage terminal GND in sequence, and 2 N+M taps. The second digital-to-analog converter DAC2 includes a resistor Rt, 2 N Ru*2 M , xRu and 2 N taps in series between the reference voltage terminal VREF and the reference voltage terminal GND in sequence. Among them, the resistance value of Rt in the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 can be flexibly adjusted according to requirements. The xRu in the second digital-to-analog converter DAC2 is used to provide the offset voltage V offset .
[0053] Compared with Figure 6 the first digital-to-analog converter DAC1 with an accuracy of N bits in Figure 7 the first digital-to-analog converter DAC1 in OUT has a higher accuracy of N+M. Thus, by adding additional switch taps, a high-precision output of V
[0054] can be achieved. OUT In some examples, to improve the output accuracy of V
[0055] According to one aspect of the present disclosure, a chip is provided, including the voltage follower control circuit described above.
[0056] Although the present disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and schematic, rather than restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art can understand and implement variations of the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims
1. A voltage follower control circuit, comprising: A power supply voltage terminal configured to provide a power supply voltage; A reference voltage terminal, configured to provide a reference voltage; A voltage dividing module, electrically connected to the power supply voltage terminal to generate a divided voltage; A comparator, comprising a first input terminal, an output terminal, and a second input terminal electrically connected to the voltage dividing module; a voltage conversion module, comprising an input terminal electrically connected to the reference voltage terminal, a first output terminal, and a second output terminal electrically connected to the first input terminal of the comparator; A first buffer including an output terminal and an input terminal electrically connected to the first output terminal of the voltage conversion module; as well as a boost driver including an input terminal electrically connected to the output terminal of the comparator and an output terminal electrically connected to the power supply voltage terminal, and The voltage conversion module is configured to provide a first conversion voltage to the first buffer based on the reference voltage, and to provide a second conversion voltage to the first input terminal of the comparator based on the reference voltage.
2. The voltage follower control circuit according to claim 1, wherein: The voltage divider module comprises: Reference voltage terminal; a first resistor; and A second resistor, the first resistor and the second resistor are connected in series between the power supply voltage terminal and the reference voltage terminal.
3. The voltage follower control circuit according to claim 2, wherein: When the second conversion voltage is greater than a voltage of the node between the first resistor and the second resistor, the boost driver is activated to increase the power supply voltage.
4. The voltage follower control circuit according to any one of claims 1 to 3, wherein: The voltage conversion module comprises: a first digital-to-analog converter electrically connected between the reference voltage terminal and an input terminal of the first buffer to provide the first conversion voltage; and The second digital-to-analog converter is electrically connected between the reference voltage terminal and the first input terminal of the comparator to provide the second conversion voltage.
5. The voltage follower control circuit according to claim 4, wherein: The second conversion voltage is the first conversion voltage plus an offset voltage for generating a margin voltage.
6. The voltage follower control circuit according to claim 4, wherein: The comparator is configured to provide an offset voltage that generates a headroom voltage.
7. The voltage follower control circuit according to claim 4, wherein: When the second conversion voltage is greater than a voltage of the node between the first resistor and the second resistor, the boost driver is activated to increase the power supply voltage.
8. The voltage follower control circuit according to claim 4, wherein: The voltage conversion module also includes: A third digital-to-analog converter is electrically connected between the first digital-to-analog converter and the input terminal of the first buffer to improve the accuracy of the first conversion voltage.
9. The voltage follower control circuit according to any one of claims 1 to 3, wherein: The voltage conversion module comprises: a fourth digital-to-analog converter comprising a first output terminal, an input terminal electrically connected to the reference voltage terminal, and a second output terminal electrically connected to the input terminal of the first buffer; and The second buffer includes a first input terminal electrically connected to the first output terminal of the fourth digital-to-analog converter, a second input terminal, and an output terminal electrically connected to the second input terminal of the second buffer.
10. The voltage follower control circuit according to claim 9, wherein: The voltage conversion module also includes: a current source; and a third resistor, the current source and the third resistor are connected in series between the power supply voltage terminal and the output terminal of the second buffer to provide an offset voltage for generating a margin voltage, and The first input terminal of the comparator is electrically connected to a node between the current source and the third resistor.
11. The voltage follower control circuit according to claim 9, wherein: The comparator is configured to provide an offset voltage that generates a headroom voltage.
12. The voltage follower control circuit according to claim 10, wherein: When the sum of the second conversion voltage and the offset voltage is greater than the voltage of the node between the first resistor and the second resistor, the boost driver is activated to increase the power supply voltage.
13. The voltage follower control circuit according to claim 9, wherein: The voltage conversion module also includes: A fifth digital-to-analog converter is electrically connected between the fourth digital-to-analog converter and an input terminal of the first buffer to improve the accuracy of the first conversion voltage.
14. A chip comprising the voltage follower control circuit according to any one of claims 1 to 13.