Cache management method and device, electronic equipment and storage medium

Abstract

The invention discloses a cache management method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps: when first data sent by a central processing unit is received, obtaining a dirty bit value of each cache line in all cache lines in a magnetic resistance cache at the current moment as a first number of the first dirty bit value; determining a target interval where the first number is located according to the first number, a first threshold value and a second threshold value; determining a target data processing mode corresponding to the target interval in the at least one data processing mode, wherein the target data processing mode comprises a target compression mode; and compressing the first data according to the target compression mode to obtain second data, and storing the second data in a target cache line in the magnetic resistance cache. According to the method and the device, the problem that the error rate of data read from the magnetic resistance cache is relatively high due to the fact that the error correction capability of a single-bit error correction-double-bit error detection mode is limited in the prior art can be solved.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a cache management method, apparatus, electronic device, and storage medium. Background Art

[0002] Traditional computer architectures typically use dynamic random access memory as a cache between the central processing unit (CPU) and memory. However, dynamic random access memory is a volatile memory and there is a risk of data loss when power is off. In contrast, non-volatile memory, due to its property of not losing data after power-off, becomes a more ideal choice for the reliability and security of cached data, especially magnetoresistive random access memory (MRAM). However, MRAM also faces problems such as read errors, write errors, and retention errors.

[0003] In related technologies, the single-bit error correction - double-bit error detection (SEC-DED) mode in traditional error detection and correction coding methods is usually used to protect the data in MRAM. However, due to the limited error correction ability of the SEC-DED mode, the error rate of the data read from MRAM is relatively high. Summary of the Invention

[0004] This application provides a cache management method, apparatus, electronic device, and storage medium to at least solve the problem in related technologies that due to the limited error correction ability of the single-bit error correction - double-bit error detection mode, the error rate of the data read from the magnetoresistive cache is relatively high.

[0005] This application provides a cache management method, which includes: when receiving the first data sent by the central processing unit, obtaining the first quantity of the first dirty bit values of each cache line in all cache lines in the magnetoresistive cache at the current moment, where the first dirty bit value is used to indicate that the data stored in each cache line has been modified but not yet written to the flash memory; determining the target interval where the first quantity is located according to the first quantity, the first threshold, and the second threshold; determining the target data processing mode corresponding to the target interval in at least one data processing mode, where the target data processing mode includes the target compression mode; compressing the first data according to the target compression mode to obtain the second data, and storing the second data in the target cache line in the magnetoresistive cache.

[0006] The present application also provides a cache management device, which includes: a transceiver module, configured to, when receiving first data sent by a central processing unit, obtain a first quantity of cache lines in all cache lines of a magnetoresistive cache at the current moment, where the dirty bit value of each cache line is a first dirty bit value, and the first dirty bit value is used to indicate that the data stored in each cache line has been modified but not yet written into the flash memory; a processing module, configured to determine a target interval where the first quantity is located according to the first quantity, a first threshold, and a second threshold; the processing module is further configured to determine a target data processing mode corresponding to the target interval in at least one data processing mode, and the target data processing mode includes a target compression mode; the processing module is further configured to compress the first data according to the target compression mode to obtain second data, and store the second data in a target cache line in the magnetoresistive cache.

[0007] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above cache management methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above cache management methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any of the above cache management methods are implemented.

[0010] Through the present application, when the controller receives the first data, it can obtain the first quantity of the first dirty bit values in the magnetoresistive cache at the current moment, and the first quantity of the first dirty bit values can represent the read / write frequency of the magnetoresistive cache at this stage. Furthermore, based on the first quantity of the first dirty bit values in the magnetoresistive cache, a compression mode matching the first quantity can be determined, that is, based on the read / write frequency of the magnetoresistive cache, it can be determined whether to adjust the data security to ensure that the data is error-free, that is, it can be determined whether to increase the storage space reserved for the check data. Different compression modes have different compression capabilities and different sizes of the storage space reserved for the check data. Therefore, the compression mode determined based on the first quantity of the first dirty bit values in the magnetoresistive cache can effectively improve the reliability and security of the data. Different compression modes can provide the best data protection in different working states of the system, reducing the risk of data errors and losses. Especially in the working scenario of high-frequency read / write, the integrity of the data is significantly improved.

[0011] In addition, by adopting different levels of compression modes, without significantly increasing the system complexity, more storage space can be freed up for check data storage through compression technology. This not only increases the fault tolerance of the storage system but also improves the utilization efficiency of the storage space. Description of the Drawings

[0012] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0013] Figure 1 It is a topology diagram of a cache management system provided by an embodiment of the present application;

[0014] Figure 2 It is a flowchart of a cache management method provided by an embodiment of the present application;

[0015] Figure 3 It is a schematic diagram of a cache line provided by an embodiment of the present application;

[0016] Figure 4 It is a schematic diagram of a cache line before and after compression provided by an embodiment of the present application;

[0017] Figure 5 It is a flowchart of another cache management method provided by an embodiment of the present application;

[0018] Figure 6 It is a schematic diagram of data from flash memory to the upper - level cache provided by an embodiment of the present application;

[0019] Figure 7 It is a structural block diagram of a cache management device provided by an embodiment of the present application;

[0020] Figure 8 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0022] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0023] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further describes this application in detail with reference to the accompanying drawings and specific embodiments.

[0024] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the caching method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0025] The embodiment of this application is applied to the scenario where the cache between the central processing unit and the memory is a magnetoresistive random access memory (MRAM), and data reading and writing between the central processing unit and the memory (such as flash memory) is performed through the MRAM.

[0026] Dynamic random access memory is a volatile memory, and there is a risk of data loss when power is off. To ensure the integrity of data when power is off, it is usually necessary to design a large-volume supercapacitor to ensure that data can be successfully written into the memory, which not only increases the complexity of the system but also occupies a large amount of space. Therefore, MRAM becomes a more ideal choice for the reliability and security of cached data. MRAM not only has non-volatility but also has nearly unlimited read and write cycles, and its write latency is compatible with dynamic random access memory.

[0027] However, MRAM also faces problems such as read errors, write errors, and retention errors. For example, during the write operation, due to the randomness and asymmetry of the state change, the write failure probability of the 0→1 transition is significantly higher than that of the 1→0 transition. Another example is that during the read operation, the small current applied may cause read interference, resulting in read errors. For another example, during the data retention phase, due to the influence of temperature changes and other factors, the magnetic moment of the storage unit of MRAM may flip, increasing the risk of data errors. In related technologies, the error correction ability of the single-bit error correction - double-bit error detection mode in the traditional error checking and correcting code (ECC) is limited, resulting in a relatively high data error rate when reading data from MRAM.

[0028] To solve the above technical problems, an embodiment of the present application provides a cache management method. When receiving the first data sent by the central processing unit, obtain the first quantity of the first dirty bit values of each cache line in all cache lines in the magnetoresistive cache at the current moment. The first dirty bit value is used to indicate that the data stored in each cache line has been modified but not yet written into the flash memory; determine the target interval where the first quantity is located according to the first quantity, the first threshold, and the second threshold; determine the target data processing mode corresponding to the target interval in at least one data processing mode, and the target data processing mode includes the target compression mode; compress the first data according to the target compression mode to obtain the second data, and store the second data in the target cache line in the magnetoresistive cache, so as to determine the matching compression mode based on the first quantity of the first dirty bit values in the magnetoresistive cache, store the compressed data in the target storage line, and then reserve a suitable remaining memory space to store the check data, reducing the data reading error rate in the magnetoresistive cache.

[0029] The following takes Figure 1 the cache management system 100 shown as an example to describe the method provided by the embodiment of the present application.

[0030] As Figure 1 shown, Figure 1 it is a topology diagram of a cache management system provided by an embodiment of the present application. Figure 1 In it, the cache management system 100 may include a central processing unit 101, a controller 102, a magnetoresistive cache 103, and a flash memory 104.

[0031] The central processing unit (CPU) 101 in the embodiment of the present application is the core component of the computer system, mainly responsible for executing instructions in the computer program, performing data processing and arithmetic operations, etc. For example, the central processing unit 101 may be a single-core processor or a multi-core processor. Among them, the central processing unit 101 includes multiple cores (core 0 and core 1) and multiple levels of caches (L1 cache, L2 cache, and L3 cache). The L1 cache is divided into an instruction cache (I-cache) and a data cache (D-cache).

[0032] The controller 102 in the embodiment of the present application may be any kind of storage controller. The controller 102 includes a NAND controller, an MRAM controller, an encoding unit, a decoding unit, a compression unit, a decompression unit, and a monitoring unit. Among them, the monitoring unit is used to detect the quantity of the dirty bit values of each cache line in the MRAM cache that are the preset numerical values.

[0033] The NAND controller is used to manage the read and write operations of the flash memory 104.

[0034] The MRAM controller is used to manage the read and write operations of the magnetoresistive cache 103.

[0035] The encoding unit is used to perform encoding processing on the data written to the magnetoresistive cache 103 using the corresponding encoding mode.

[0036] The decoding unit is used to perform decoding processing on the data read from the magnetoresistive cache 103 using the decoding mode corresponding one-to-one to the encoding mode.

[0037] The compression unit is used to perform compression processing on the data written to the magnetoresistive cache 103 using the corresponding compression mode.

[0038] The decompression unit is used to perform decompression processing on the data read from the magnetoresistive cache 103 using the decompression mode corresponding one-to-one to the compression mode.

[0039] The monitoring unit is used to monitor the status of the dirty bit value (dirty bit) in the MRAM, count the number of the first dirty bit values, set different first thresholds and second thresholds, and switch different compression modes and decompression modes as well as switch different encoding modes and decoding modes.

[0040] The magnetoresistive cache 103 in the embodiments of the present application can be any kind of magnetoresistive random access memory. For example, the magnetoresistive cache 103 can be a Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). The data storage of the magnetoresistive cache 103 is in units of cache lines.

[0041] The flash memory (NAND Flash) 104 in the embodiments of the present application can be any kind of non-volatile memory.

[0042] Figure 1 The shown cache management system 100 is only for illustration and is not used to limit the technical solutions of the present application. Those skilled in the art should understand that in the specific implementation process, the cache management system 100 may further include other devices, which are not limited.

[0043] According to the embodiments of the present application, an embodiment of a cache management method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0044] In this embodiment, a cache management method is provided, which can be used for the above controller. Figure 2 The flowchart of a cache management method provided for the embodiments of the present application is as Figure 2 shown, and this process includes the following steps:

[0045] S201: When receiving the first data sent by the central processing unit, obtain the first quantity of the dirty bit values of each cache line in all cache lines in the magnetoresistive cache at the current moment as the first dirty bit value.

[0046] Among them, the cache line is also called the Cache line. As Figure 3 shown, Figure 3 is a schematic diagram of a cache line provided by an embodiment of the present application. In Figure 3 each cache line includes a dirty bit value (i.e., the dirty value), stored data (Data), and parity check data (ECC data).

[0047] The first dirty bit value is used to indicate that the data stored in each cache line has been modified but not yet written into the flash memory. The first dirty bit value can be 1. Optionally, the dirty bit value of each cache line can also be a second dirty bit value. The second dirty bit value can be 0. The second dirty bit value is used to indicate that the data stored in each cache line has not been modified and is stored in the flash memory.

[0048] It can be understood that since the storage space occupied by each cache line is certain and the number of data bits of the Data of each cache line is fixed, the storage space occupied by the ECC data is also fixed accordingly.

[0049] S202: Determine the target interval where the first quantity is located according to the first quantity, the first threshold, and the second threshold.

[0050] Among them, the first threshold is less than the second threshold.

[0051] In some alternative embodiments, if the first quantity is less than or equal to the first threshold, the controller determines that the target interval where the first quantity is located is the first interval; if the first quantity is greater than the first threshold and less than the second threshold, it is determined that the target interval where the first quantity is located is the second interval; if the first quantity is greater than or equal to the second threshold, it is determined that the target interval where the first quantity is located is the third interval.

[0052] As shown in Table 1 below, Table 1 shows the data processing modes in different intervals. The first threshold is represented by threshold 1; the second threshold is represented by threshold 2; the first quantity is represented by α.

[0053]

[0054] Table 1

[0055] Among them, the first interval corresponds to the first data processing mode. The first data processing mode includes a first compression mode, a first encoding mode, a first decompression mode matching the first compression mode, and a first decoding mode matching the first encoding mode. The first encoding mode is the SEC-DED encoding mode. The first compression mode is used to indicate that the data written to the cache line does not need to be compressed. Therefore, the first decompression mode indicates that the data read from the cache line does not need to be decompressed.

[0056] It can be understood that in the first data processing mode, the first quantity is less than or equal to the first threshold, which means that the data in the MRAM changes less. Therefore, data compression and decompression operations are not performed, and the SEC-DED encoding mode is adopted at the same time.

[0057] The second interval corresponds to the second data processing mode. The second data processing mode includes a second compression mode, a second encoding mode, a second decompression mode matching the second compression mode, and a second decoding mode matching the second encoding mode. The second compression mode is the Zero-Coefficient Approximation (ZCA) compression mode. The second encoding mode is the Double-Error-Correcting and Triple-Error-Detecting Code (DEC-TED) encoding mode.

[0058] It can be understood that since the cache line is in the second data processing mode, the ZCA compression mode can be adopted to compress the data written to the cache line, leaving more space for verifying the data. The encoding and decoding modes are also upgraded and switched to DEC-TED to enhance the error correction ability of the data.

[0059] The third interval corresponds to the third data processing mode. The third data processing mode includes a third compression mode, a third encoding mode, a third decompression mode matching the third compression mode, and a third decoding mode matching the third encoding mode. The third encoding mode is the Three-bit Error Correction-Four-bit Error Detection (TEC-QED) encoding mode. The third compression mode is the Base-Delta-Immediate Compression (BDI) mode. Optionally, the third compression mode can also be the Frequent Pattern Compression (FCA).

[0060] In one example, the compression ability of the first compression mode is less than that of the second compression mode, and the compression ability of the second compression mode is less than that of the third compression mode.

[0061] Understandably, different compression modes provide different levels of compression capabilities. The stronger the compression capability of a compression mode, the higher the compression efficiency, and the corresponding increase in compression and decompression latency. The smaller the storage space occupied by the data stored in the cache line.

[0062] In yet another example, the error correction capability of the first coding mode is less than that of the second compression mode, and the error correction capability of the second compression mode is less than the compression capability of the third compression mode.

[0063] Understandably, the stronger the error correction capability of a coding mode, the more parity data is generated. By adopting different levels of compression modes, more storage space can be freed up for parity data storage through compression technology without significantly increasing the system complexity. This not only increases the fault tolerance of the storage system but also improves the utilization efficiency of the storage space. By adopting different levels of coding modes, the system can dynamically select an appropriate error correction strategy according to the state of the MRAM cache, thus significantly enhancing the error correction capability of the system. Especially in the case where the probability of multiple-bit errors is relatively high, it can effectively reduce the occurrence of data errors and improve the reliability of the overall system.

[0064] S203: Determine the target data processing mode corresponding to the target interval in at least one data processing mode.

[0065] Among them, the target data processing mode includes a target compression mode, a target decompression mode, a target coding mode, and a target decoding mode. The target decoding mode matches the target coding mode, and the target decompression mode matches the target compression mode.

[0066] S204: Compress the first data according to the target compression mode to obtain the second data, and store the second data in the target cache line in the magnetoresistive cache.

[0067] In some alternative embodiments, the controller encodes the second data based on the target coding mode to generate parity data; stores the parity data in the target cache line, and updates the dirty bit value stored in the target cache line to the first dirty bit value.

[0068] Among them, the parity data is used to correct errors or verify the second data. The target cache line stores the second data, the parity data, and the first dirty bit value.

[0069] Exemplarily, as Figure 4 shown, Figure 4 is a schematic diagram of a cache line before and after compression provided by an embodiment of the present application. In Figure 4Among them, the storage space occupied by Data in the cache line before compression is larger than the storage space occupied by Data in the cache line after compression, and the storage space occupied by ECC data in the cache line before compression is smaller than the storage space occupied by ECC data in the cache line after compression.

[0070] In some alternative embodiments, when the second data needs to be written into the flash memory, the controller verifies the second data based on the target decoding mode and the parity data; if the verification is successful, the second data is decompressed based on the target decompression mode to obtain the first data, and the first data is written into the flash memory.

[0071] Optionally, after the controller writes the first data into the flash memory, it updates the dirty bit value stored in the target cache line to the second dirty bit value.

[0072] It can be understood that when data is written from the upper-level cache into the magnetoresistive cache, it first undergoes compression processing by the compression unit, then enters the encoding unit for encoding, and the data is written into the magnetoresistive cache, while setting the corresponding dirty bit to "1". When the data in the magnetoresistive cache needs to be written into the flash memory, the data is first sent to the decoding unit for verification, and after passing the verification, it is decompressed, and finally the decompressed data is stored in the flash memory.

[0073] Based on the above Figure 2 According to the method shown, when the controller receives the first data, it can obtain the first quantity of the first dirty bit value in the magnetoresistive cache at the current moment, and the first quantity of the first dirty bit value can represent the read / write frequency of the magnetoresistive cache at this stage. Furthermore, based on the first quantity of the first dirty bit value in the magnetoresistive cache, a compression mode matching the first quantity can be determined, that is, based on the read / write frequency of the magnetoresistive cache, it is determined whether to adjust the data security to ensure that the data is error-free, that is, it is determined whether to increase the storage space reserved for the parity data. Different compression modes have different compression capabilities and different sizes of the storage space reserved for the parity data. Therefore, the compression mode determined based on the first quantity of the first dirty bit value in the magnetoresistive cache can effectively improve the reliability and security of the data. Different compression modes can provide the best data protection under different working states of the system, reserve an appropriate remaining memory space to store the parity data, reduce the data read error rate in the magnetoresistive cache, and reduce the risk of data errors and losses. Especially in the working scenario of high-frequency read / write, the integrity of the data is significantly improved.

[0074] In addition, by monitoring the status of the dirty bit values in the magnetoresistive cache in real time and adjusting the compression and encoding strategies in a timely manner, the controller can optimize the processing speed of the system while ensuring data reliability. The flexible switching between different compression modes and encoding modes ensures performance optimization under different workloads, reduces data processing latency, and improves the system's response speed. The dynamic management mechanism not only enhances data reliability but also reduces the system's power consumption to a certain extent. By adjusting the compression and encoding modes according to data changes, unnecessary compression and decompression operations can be reduced, thereby reducing the system's computational overhead and extending the device's service life, especially suitable for application scenarios with high energy efficiency requirements.

[0075] Further, the controller can also receive a read request sent by the central processing unit and read data from the MRAM or flash memory, as Figure 5 shown Figure 5 is a flowchart of another cache management method provided by an embodiment of the present application. The controller can also perform the following steps:

[0076] S501: Receive a read request sent by the central processing unit.

[0077] Among them, the read request is used to read the third data. The read request carries the address information of the third data.

[0078] S502: Based on the address information, determine the first cache line in the magnetoresistive cache where the third data is located.

[0079] Among them, the address information can be the memory address of the third data.

[0080] Exemplarily, the controller determines the first cache line in the magnetoresistive cache where the third data corresponding to the address information is located based on the address information.

[0081] S503: Read the fourth data and the first check data from the first cache line.

[0082] Among them, the fourth data is obtained by compressing the third data according to the corresponding compression mode.

[0083] S504: Check the fourth data based on the decoding mode corresponding to the third data and the first check data.

[0084] S505: Detect whether the check is successful.

[0085] S506: If the check is successful, return the third data to the upper-level cache.

[0086] The upper-level cache can be any set of caches in the central processing unit.

[0087] In one example, if the verification is successful, the controller decompresses the fourth data based on the decompression mode corresponding to the third data to obtain the third data, and returns the third data to the upper-level cache.

[0088] S507: If the verification fails, error correction is performed on the fourth data based on the decoding mode corresponding to the third data and the first verification data.

[0089] S508: Detect whether the number of error bits in the fourth data is greater than the error correction capability of the decoding mode corresponding to the third data.

[0090] It can be understood that if the SEC-DED coding mode is used for error correction, the error correction capability is weak, and only 1-bit error can be corrected and 2-bit errors can be detected, and the situation of error correction failure may occur.

[0091] S509: If not, it is determined that the error correction is successful, and the third data is returned to the upper-level cache.

[0092] In one example, if it is determined that the error correction is successful, the controller decompresses the fourth data based on the decompression mode corresponding to the third data to obtain the third data, and returns the third data to the upper-level cache.

[0093] S510: If so, it is determined that the error correction fails, and the dirty bit value is read from the first cache line.

[0094] S511: Detect whether the read dirty bit value is the first dirty bit value.

[0095] S512: If not, the third data stored in the flash memory is read into the magnetoresistive cache, and the third data is read from the magnetoresistive cache.

[0096] Specifically, if the dirty bit value read by the controller is not the first dirty bit value, the controller obtains the second quantity of the dirty bit values of each cache line in all cache lines in the magnetoresistive cache at the current moment being the first dirty bit value; determines the compression mode corresponding to the third data and the coding mode corresponding to the third data according to the second quantity, the first threshold, and the second threshold; compresses the third data stored in the flash memory according to the corresponding compression mode of the third data to obtain the fifth data; encodes the fifth data according to the coding mode corresponding to the third data to generate the second verification data; writes the fifth data and the second verification data into the second cache line in the magnetoresistive cache; reads the third data from the second cache line in the magnetoresistive cache.

[0097] It can be understood that if the dirty bit value read by the controller is not the first dirty bit value, cache miss will occur, and it is necessary to read data from the flash memory into the magnetoresistive cache and pass the data to the upper-level cache in sequence.

[0098] S513: If so, it is determined that the third data is lost, and the third data has been modified but not yet stored in the flash memory.

[0099] It can be understood that, as Figure 6 shown, Figure 6 is a schematic diagram of data from the flash memory to the upper-level cache provided by the embodiments of the present application. When Figure 6 the central processing unit issues a read command, the controller first reads the data from the flash memory into the magnetoresistive cache. Specifically, the controller reads the data from the flash memory, sends it to the compression unit, selects a suitable compression mode, performs data compression processing, the compressed data is sent to the encoding unit, adopts a corresponding encoding mode, generates check data, and sends the data together into the magnetoresistive cache. After the data is read from the flash memory to the magnetoresistive cache, the data reaches the upper-level cache from the magnetoresistive cache. First, it passes through the decoding unit for data verification, and then is sent to the decompression unit and finally reaches the upper-level cache.

[0100] In some alternative embodiments, when the system starts up, the controller reads data from the NAND Flash, passes through the encoding unit, enters the magnetoresistive cache, and then reads the data from the magnetoresistive cache into the L3 cache, L2 cache, and L1 cache.

[0101] It can be understood that the write operation of the CPU will change the data state in the magnetoresistive cache, and the monitoring unit of the controller sets the dirty value in the cache data that has been modified and not yet stored in the NAND Flash to "1".

[0102] In some alternative embodiments, when the number of the first dirty bit values obtained by the controller increases, the magnetoresistive cache is in a state of frequent reading and writing at this stage, and it is necessary to enhance data security to ensure that the data is error-free. When the number of the first dirty bit values is greater than the first threshold, the newly entered data into the magnetoresistive cache adopts the ZCA compression mode and the DEC-TED encoding mode, and the data passes through the compression unit and the encoding unit in sequence and enters the magnetoresistive cache. It can be understood that the compression ratio of the ZCA compression mode is relatively low, and at the same time its compression and decompression delays are relatively low. Cooperating with the DEC-TED encoding mode, it can enhance the error correction and error detection capabilities of the data and improve the security of the data stored in the magnetoresistive cache.

[0103] In addition, if there is still old data in the magnetoresistive cache (i.e., the data encoded using the SEC-DED encoding mode), when the old data leaves the magnetoresistive cache and enters the decoding unit, the SEC-DED is still used to prevent errors caused by the encoding method.

[0104] When switching from the first data processing mode to the second data processing mode, the controller can mark the data in the magnetoresistive cache as the first data processing mode and the newly entered data as the second data processing mode for easy data management.

[0105] In some alternative embodiments, when the number of first dirty bit values obtained by the controller is greater than a second threshold, the newly entered magnetoresistive cache data adopts a third data processing mode. It can be understood that the BDI compression mode is further enhanced compared to the ZCA compression mode, but the compression and decompression delays increase. When used in conjunction with TEC-QED, the error correction and detection capabilities are further enhanced.

[0106] It can be understood that the controller can mark the newly entered data as the third mode. If there is still data in the magnetoresistive cache in the first data processing mode and the second data processing mode, when these data leave the MRAM, they still adopt the corresponding compression / decompression mode and encoding / decoding / mode.

[0107] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0108] The embodiments of the present application also provide a cache management device, as Figure 7 shown Figure 7 is a structural block diagram of a cache management device provided by an embodiment of the present application; the device includes:

[0109] A transceiver module 701, configured to, when receiving first data sent by a central processing unit, obtain a first quantity of first dirty bit values of each cache line in all cache lines in the magnetoresistive cache at the current moment, where the first dirty bit value is used to indicate that the data stored in each cache line has been modified but not yet written into the flash memory.

[0110] A processing module 702, configured to determine a target interval where the first quantity is located according to the first quantity, a first threshold, and a second threshold.

[0111] The processing module 702 is further configured to determine a target data processing mode corresponding to the target interval among at least one data processing mode, where the target data processing mode includes a target compression mode;

[0112] The processing module 702 is further configured to compress the first data according to the target compression mode to obtain second data, and store the second data in a target cache line in the magnetoresistive cache.

[0113] In some alternative embodiments, the target data processing mode further includes a target encoding mode; the processing module 702 is further configured to encode the second data based on the target encoding mode to generate check data, where the check data is used to correct errors in the second data; store the check data in the target cache line, and update the dirty bit value stored in the target cache line to the first dirty bit value.

[0114] In some alternative embodiments, the target data processing mode further includes a target decoding mode and a target decompression mode, where the target decoding mode matches the target encoding mode, and the target decompression mode matches the target compression mode; the processing module 702 is further configured to, when the second data needs to be written into the flash memory, verify the second data based on the target decoding mode and the verification data; if the verification is successful, decompress the second data based on the target decompression mode to obtain the first data, and write the first data into the flash memory.

[0115] In some alternative embodiments, the first threshold is less than the second threshold; specifically, the processing module 702 is configured to, if the first quantity is less than or equal to the first threshold, determine that the target interval where the first quantity is located is the first interval, and the first interval corresponds to the first data processing mode, where the first data processing mode includes a first compression mode and a first encoding mode; if the first quantity is greater than the first threshold and less than the second threshold, determine that the target interval where the first quantity is located is the second interval, and the second interval corresponds to the second data processing mode, where the second data processing mode includes a second compression mode and a second encoding mode; if the first quantity is greater than or equal to the second threshold, determine that the target interval where the first quantity is located is the third interval, and the third interval corresponds to the third data processing mode, where the third data processing mode includes a third compression mode and a third encoding mode.

[0116] Wherein, the compression ability of the first compression mode is less than that of the second compression mode, and the compression ability of the second compression mode is less than that of the third compression mode; the error correction ability of the first encoding mode is less than that of the second compression mode, and the error correction ability of the second compression mode is less than that of the third compression mode.

[0117] In some alternative embodiments, the transceiver module 701 is further configured to receive a read request sent by the central processing unit, where the read request is used to read the third data, and the read request carries the address information of the third data; the processing module 702 is further configured to, based on the address information, determine the first cache line where the third data is located in the magnetoresistive cache; read the fourth data and the first verification data from the first cache line, where the fourth data is obtained by compressing the third data according to the corresponding compression mode; verify the fourth data based on the decoding mode corresponding to the third data and the first verification data; if the verification fails, correct the fourth data based on the decoding mode corresponding to the third data and the first verification data; if the correction fails, read the dirty bit value from the first cache line; if the read dirty bit value is not the first dirty bit value, read the third data stored in the flash memory into the magnetoresistive cache, and read the third data from the magnetoresistive cache.

[0118] In some alternative embodiments, the processing module 702 is further specifically configured to, if the read dirty bit value is not the first dirty bit value, obtain a second quantity of cache lines in all cache lines in the magnetoresistive cache at the current moment, where the dirty bit value of each cache line is the first dirty bit value; determine a compression mode corresponding to the third data and an encoding mode corresponding to the third data according to the second quantity, a first threshold, and a second threshold; compress the third data stored in the flash memory according to the corresponding compression mode of the third data to obtain a fifth data; encode the fifth data according to the encoding mode corresponding to the third data to generate second check data; write the fifth data and the second check data into a second cache line in the magnetoresistive cache; and read the third data from the second cache line in the magnetoresistive cache.

[0119] In some alternative embodiments, the processing module 702 is further configured to, if the read dirty bit value is the first dirty bit value, determine that the third data is lost.

[0120] For the description of the features in the corresponding embodiments of the cache management device, reference may be made to the relevant descriptions in the corresponding embodiments of the cache management method, which will not be elaborated here one by one.

[0121] An embodiment of the present application further provides an electronic device, as Figure 8 shown, Figure 8 is a schematic hardware structure diagram of the electronic device provided by the embodiment of the present application. The electronic device includes a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the cache management method.

[0122] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned embodiments of the cache management method when running.

[0123] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0124] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned embodiments of the cache management method are implemented.

[0125] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the cache management method are implemented.

[0126] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0127] The above has introduced in detail a cache management method, device, electronic device, and storage medium provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A cache management method, characterized in that: The method comprises: When receiving the first data sent by the central processing unit, obtaining the dirty bit value of each cache line in all cache lines in the magnetic resistance cache at the current moment as a first number of first dirty bit values, wherein the first dirty bit value is used to indicate that the data stored in each cache line has been modified but has not yet been written to the flash memory; Determine a target interval within which the first number falls according to the first number, the first threshold, and the second threshold; Determining a target data processing mode corresponding to the target interval in at least one data processing mode, the target data processing mode comprising a target compression mode; The first data is compressed according to the target compression mode to obtain second data, and the second data is stored in a target cache line in the magnetoresistive cache.

2. The cache management method according to claim 1, characterized in that: The target data processing mode also includes a target encoding mode; the method also includes: Based on the target coding mode, encode the second data to generate verification data, where the verification data is used to correct errors of the second data; The verification data is stored in the target cache line, and the dirty bit value stored in the target cache line is updated to be the first dirty bit value.

3. The cache management method according to claim 2, characterized in that: The target data processing mode also includes a target decoding mode and a target decompression mode, the target decoding mode matches the target encoding mode, and the target decompression mode matches the target compression mode; The method further comprises: When the second data needs to be written into the flash memory, verifying the second data based on the target decoding mode and the verification data; If the verification is successful, the second data is decompressed based on the target decompression mode to obtain the first data, and the first data is written into the flash memory.

4. The cache management method according to claim 3, characterized in that: The first threshold is less than the second threshold; and determining the target interval where the first quantity is located according to the first quantity, the first threshold and the second threshold, includes: If the first number is less than or equal to the first threshold, determining that the target interval where the first number is located is a first interval, the first interval corresponds to a first data processing mode, and the first data processing mode includes a first compression mode and a first encoding mode; If the first number is greater than the first threshold and less than the second threshold, determining that the target interval where the first number is located is a second interval, the second interval corresponds to a second data processing mode, and the second data processing mode includes a second compression mode and a second encoding mode; If the first number is greater than or equal to the second threshold, determining that the target interval where the first number is located is a third interval, the third interval corresponds to a third data processing mode, and the third data processing mode includes a third compression mode and a third encoding mode; The compression capability of the first compression mode is smaller than that of the second compression mode, and the compression capability of the second compression mode is smaller than that of the third compression mode; The error correction capability of the first encoding mode is smaller than that of the second compression mode, and the error correction capability of the second compression mode is smaller than the compression capability of the third compression mode.

5. The cache management method according to claim 3, characterized in that: The method further comprises: receiving a read request sent by the central processing unit, wherein the read request is used to read third data, and the read request carries address information of the third data; Based on the address information, determining a first cache row where the third data is located from the magnetoresistive cache; Reading fourth data and first verification data from the first cache line, wherein the fourth data is obtained by compressing the third data according to a corresponding compression mode; Verifying the fourth data based on a decoding mode corresponding to the third data and the first verification data; If the verification fails, performing error correction on the fourth data based on the decoding mode corresponding to the third data and the first verification data; If the error correction fails, reading the dirty bit value from the first cache line; If the dirty bit value read is not the first dirty bit value, the third data stored in the flash memory is read into the magnetoresistive cache, and the third data is read from the magnetoresistive cache.

6. The cache management method according to claim 5, characterized in that: If the dirty bit value read is not the first dirty bit value, writing the third data stored in the flash memory into the magnetoresistive cache, and reading the third data from the magnetoresistive cache, comprises: If the dirty bit value read is not the first dirty bit value, obtaining the dirty bit value of each cache line in all cache lines in the magnetoresistive cache at the current moment as a second quantity of the first dirty bit value; determining, according to the second number, the first threshold, and the second threshold, a compression mode corresponding to the third data and an encoding mode corresponding to the third data; Compressing the third data stored in the flash memory according to the corresponding compression mode of the third data to obtain fifth data; Encode the fifth data according to the encoding mode corresponding to the third data to generate second verification data; Writing the fifth data and the second verification data into a second cache line in the magnetoresistive cache; The third data is read from the second cache line in the magnetoresistive cache.

7. The cache management method according to claim 5, characterized in that: The method further comprises: If the dirty bit value read is the first dirty bit value, it is determined that the third data is lost.

8. A cache management device, characterized in that: The cache management device comprises: A transceiver module, configured to, when receiving first data sent by a central processing unit, obtain a first number of dirty bit values ​​of each cache line in all cache lines in the magnetic resistance cache at a current moment, wherein the first dirty bit value is used to indicate that the data stored in each cache line has been modified but has not yet been written to the flash memory; A processing module, configured to determine a target interval in which the first number is located according to the first number, a first threshold and a second threshold; The processing module is further used to determine a target data processing mode corresponding to the target interval in at least one data processing mode, wherein the target data processing mode includes a target compression mode; The processing module is further configured to compress the first data according to the target compression mode to obtain second data, and store the second data in a target cache line in the magnetoresistive cache.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the cache management method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the cache management method according to any one of claims 1 to 7.

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