Data processing method, processor and computing equipment

Abstract

The embodiment of the invention provides a data processing method and device, a processor and computing equipment, and the method achieves the purpose of shuffling any bit of to-be-shuffled data in cooperation with a TBL instruction in a mode of generating a target index sequence for the TBL instruction. Specifically, the shuffling operation of the to-be-shuffled data with different lengths can be realized according to the adjustment of the number of index values in the target index element without being limited by the length of the to-be-shuffled operation, for example, when 8-bit indexes exist in the target index element, the shuffling operation of 64 (8 * 8)-bit to-be-shuffled data can be realized in cooperation with a TBL instruction, and the shuffling efficiency of the to-be-shuffled data is improved. And when 4-bit indexes exist in the target index element, the shuffling operation of 32 (4 * 8)-bit data to be shuffled can be realized in cooperation with the TBL instruction, and the purposes of improving the applicability of the data processing method and meeting the multi-scene data shuffling requirement are achieved.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to instruction set technologies in the field of computer application technologies, and more specifically, to a data processing method, apparatus, processor, computing device, and computer-readable storage medium. Background Art

[0002] Shuffle is a common operation in the process of computer data processing, and shuffle can achieve the purpose of rearranging data elements. Currently, shuffle operations are usually applied in fields such as binary translation of programs, multimedia applications, graphics processing, and vector calculations.

[0003] However, currently, in some devices with specific instruction set architectures, there are no instructions and methods for implementing data shuffle, which cannot meet the data shuffle requirements in multiple scenarios. Summary of the Invention

[0004] Embodiments of this specification provide a data processing method, apparatus, processor, computing device, and computer-readable storage medium, achieving the purpose of improving the applicability of the data processing method and meeting the data shuffle requirements in multiple scenarios.

[0005] To achieve the above technical objectives, embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of this specification provides a data processing method, which is characterized by including:

[0007] In response to an index generation instruction carrying a first register identifier and a data bit number parameter, determine multiple target index elements in an initial index sequence; the first register identifier is used to represent a source register, and the source register stores multiple target data; the data bit number parameter is used to represent the bit width of the target data, the initial index sequence includes multiple index elements, and the index element includes multiple index values; the index element corresponds to an index identifier one by one, and the data value at a predetermined position of the multiple target data in the source register represents the index identifier corresponding to the target index element;

[0008] Generate a target index sequence according to the multiple target index elements;

[0009] According to the target index sequence, use a table branch lookup (TBL) instruction to perform a shuffle operation on multiple data to be shuffled, where the multiple data to be shuffled includes the multiple target data; the index value corresponds to multiple bits of data in the target data, and the index value is used to instruct the TBL instruction to store the multiple bits of data corresponding to the index value in a target register.

[0010] Second aspect, an embodiment of this specification provides a data processing device, the data processing device comprising:

[0011] An index determination module, configured to determine a plurality of target index elements in an initial index sequence in response to an index generation instruction carrying a first register identifier and a data bit width parameter; the first register identifier is used to represent a source register, and a plurality of target data are stored in the source register; the data bit width parameter is used to represent the bit width of the target data, the initial index sequence includes a plurality of index elements, and the index elements include a plurality of index values; the index elements are in one-to-one correspondence with index identifiers, and the data value at a predetermined position of the plurality of target data in the source register represents the index identifier corresponding to the target index element;

[0012] A sequence generation module, configured to generate a target index sequence according to the plurality of target index elements;

[0013] A shuffle operation module, configured to perform a shuffle operation on a plurality of data to be shuffled according to the target index sequence by using a table branch lookup TBL instruction, the plurality of data to be shuffled including the plurality of target data; the index value corresponds to multiple bits of data in the target data, and the index value is used to instruct the TBL instruction to store the multiple bits of data corresponding to the index value in a target register.

[0014] Third aspect, an embodiment of this specification further provides a processor, characterized by comprising:

[0015] A decoder, configured to decode a computation instruction into a decoded instruction;

[0016] An execution unit, configured to execute the decoded instruction to implement the data processing method described in any one of the above.

[0017] Fourth aspect, a computing device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the computer program, the data processing method described above is implemented.

[0018] Fifth aspect, an embodiment of this specification further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the data processing method described above is implemented.

[0019] Sixth aspect, an embodiment of this specification provides a computer program product or a computer program. The computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium. A processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, the steps of the above data processing method are implemented.

[0020] As can be seen from the above technical solutions, the data processing method provided by the embodiments of this specification first responds to an index generation instruction carrying a first register identifier and a data bit parameter, and determines a plurality of target index elements in an initial index sequence. Then, according to the plurality of target index elements, a target index sequence is generated. Finally, according to the target index sequence, using the table branch lookup TBL instruction, a shuffle operation is performed on a plurality of data to be shuffled, achieving the purpose of performing a shuffle operation on a plurality of data to be shuffled. That is, the data processing method realizes the purpose of cooperating with the TBL instruction to shuffle data to be shuffled with any number of bits by generating a target index sequence for the TBL instruction. Specifically, the method can adjust the shuffle operation on data to be shuffled with different lengths according to the number of index values in the target index elements, and is not limited by the length limit of the shuffle operation. For example, when there are 8-bit indexes in the target index elements, the shuffle operation of 64 (8×8)-bit data to be shuffled can be realized in cooperation with the TBL instruction, and when there are 4-bit indexes in the target index elements, the shuffle operation of 32 (4×8)-bit data to be shuffled can be realized in cooperation with the TBL instruction, achieving the purpose of improving the applicability of the data processing method and meeting the data shuffle requirements in multiple scenarios. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0022] Figure 1 Schematic diagram of the correspondence between index values and data to be shuffled provided for an embodiment of this specification;

[0023] Figure 2 Schematic diagram of the correspondence between index elements and data to be shuffled provided for an embodiment of this specification;

[0024] Figure 3 Schematic diagram of the process of a target index sequence cooperating with the TBL instruction to achieve a shuffle operation provided for an embodiment of this specification;

[0025] Figure 4Schematic diagram of the correspondence between index elements and data to be shuffled provided for another embodiment of this specification;

[0026] Figure 5 Schematic diagram of the process of implementing a shuffle operation with a target index sequence in cooperation with a TBL instruction provided for one embodiment of this specification;

[0027] Figure 6 Schematic flowchart of a data processing method provided for one embodiment of this specification;

[0028] Figure 7 Schematic diagram of the process of implementing a shuffle operation with a target index sequence in cooperation with a TBL instruction provided for yet another embodiment of this specification;

[0029] Figure 8 Schematic diagram of the structure of an index generation instruction provided for another embodiment of this specification;

[0030] Figure 9 Schematic diagram of the structure of a shift device provided for one embodiment of this specification;

[0031] Figure 10 Schematic diagram of the structure of a processor provided for one embodiment of this specification;

[0032] Figure 11 Schematic diagram of the structure of a computing device provided for one embodiment of this specification. Detailed implementation manners

[0033] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the ordinary meanings understood by those of ordinary skill in the field to which this specification pertains. The "first", "second" and similar terms used in the embodiments of this specification do not denote any order, quantity or importance, but are only used to avoid confusion of components.

[0034] Unless otherwise required by the context, throughout this specification, "a plurality of" means "at least two", and "including" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of this specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0035] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this specification without creative efforts shall fall within the scope of protection of this specification.

[0036] Overview

[0037] As described in the background art, in scenarios such as binary translation of programs, it is usually necessary to shuffle multiple data elements to effectively organize the data. The SHUFPS instruction in the X86 instruction set is an instruction that selects single-precision floating-point data elements from xmm1 and xmm2 / m128 according to the given instructions and saves the selection result to the xmm1 register. Its function is to perform an element shuffle operation on two vectors to achieve data rearrangement and selection. Among them, xmm1 and xmm2 / m128 are two XMM registers, which are used to save the source vector and the target vector respectively. The SHUFPS instruction may also include the imm8 parameter, and imm8 is an 8-bit immediate number that specifies the element selection order. It can be found from the above description that in a system based on the X86 instruction set, a special SHUFPS instruction can be used to shuffle data elements. However, in some systems based on specific instruction sets (such as systems based on the ARM (Advanced RISC Machines) instruction set), there is no special shuffle instruction. And in some scenarios, taking the ARM instruction set as an example, it is necessary to perform data shuffle operations based on the ARM instruction set. For example, in the process of binary translation from an X86 program to an ARM program, it is necessary to implement a similar data shuffle operation in the ARM program. However, in the ARM instruction set, there is no special shuffle instruction that can implement shuffle operations on data with more than 8 bits.

[0038] The inventor found through research that the characteristics of the TBL (Table Branch Lookup) instruction can be utilized to implement the shuffling operation of data to be shuffled with different bit widths by generating a specific index sequence for the TBL instruction. Specifically, first, through studying the characteristics of the TBL instruction, it is found that the main function of the TBL instruction is to perform a table lookup operation, retrieve data from the lookup table in the source register according to the index value, and place the retrieved data in the appropriate position in the destination register. Then, each data segment in each data to be shuffled among multiple data to be shuffled can be associated with different index values. At this time, the TBL instruction can be used to find the data segment corresponding to the index value in each data to be shuffled according to these index values. When the TBL instruction is used to operate on 8-bit data, the data segment in the data to be shuffled can be a data segment with a length of 8 bits. For example, refer to Figure 1 , Figure 1 shows the correspondence between the data segments in each data to be shuffled among multiple data to be shuffled and the index values. Suppose there are 16 index values: 0x0, 0x1, 0x2, 0x3, 0x4, 0x5... 0xd, 0xe, and 0xf. This group of index values respectively correspond to the data segments in 4 data to be shuffled, namely 1 to 4. Specifically, data to be shuffled 1 includes data segments c, d, e, and f, and these data segments respectively correspond to index values 0xc, 0xd, 0xe, and 0xf; data to be shuffled 2 includes data segments 8, 9, a, and b, and these data segments respectively correspond to index values 0x8, 0x9, 0xa, and 0xb; data to be shuffled 3 includes data segments 4, 5, 6, and 7, and these data segments respectively correspond to index values 0x4, 0x5, 0x6, and 0x7; data to be shuffled 4 includes data segments 0, 1, 2, and 3, and these data segments respectively correspond to index values 0x0, 0x1, 0x2, and 0x3. In this way, the correspondence between these index values and data segments is stored in the index table.

[0039] Furthermore, a set of initial index sequences can be set for multiple data to be shuffled. This initial index sequence stores the index values respectively corresponding to each data to be shuffled among multiple data to be shuffled, and the multiple index values in the initial index sequence are divided into multiple index elements so that each index element corresponds to a data to be shuffled. In this way, we only need to determine the target index sequence composed of target index elements in the follow-up to cooperate with the TBL instruction to achieve the shuffling of multiple data to be shuffled. For example, refer to Figure 2 , we can divide 16 index values into multiple index elements so that each index element corresponds to a data to be shuffled. In Figure 2Among them, index element 1 includes index values 0xc, 0xd, 0xe, and 0xf, which enables the TBL instruction to operate on the data to be shuffled 1 in cooperation with index element 1; similarly, index element 2 includes index values 0x8, 0x9, 0xa, and 0xb, which enables the TBL instruction to operate on the data to be shuffled 2 in cooperation with index element 2; index element 3 includes index values 0x4, 0x5, 0x6, and 0x7, which enables the TBL instruction to operate on the data to be shuffled 3 in cooperation with index element 3; index element 4 includes index values 0x0, 0x1, 0x2, and 0x3, which enables the TBL instruction to operate on the data to be shuffled 4 in cooperation with index element 4.

[0040] Then, in order to implement the shuffling operation of the data to be shuffled, a correspondence between the index element and the index identifier can be established, and then the target index element can be determined by the value taken at a specific position in each data to be shuffled, and then the target index sequence containing multiple target index elements can be determined. For specific reference, Figure 3 , since there are four index elements (i.e., index elements 1 to 4), at least two binary values are required for the index identifier to distinguish these index elements. In Figure 3 , index element 1 corresponds to the index identifier 00, index element 2 corresponds to the index identifier 01, index element 3 corresponds to the index identifier 10, and index element 4 corresponds to the index identifier 11. After that, when shuffling the data to be shuffled 1 to 4, the data to be shuffled 1 to 4 can be placed in register 1, and the value taken at a predetermined position in the data to be shuffled 1 to 4 is used as the target index element. In Figure 3 , assuming that two-bit data values in the lower 8 bits of each data to be shuffled are used as the target index element, the value taken at the predetermined position of the data to be shuffled 1 is "00", corresponding to index element 1; the value taken at the predetermined position of the data to be shuffled 2 is "00", corresponding to index element 1; the value taken at the predetermined position of the data to be shuffled 3 is "01", corresponding to index element 2, and the value taken at the predetermined position of the data to be shuffled 4 is "11", corresponding to index element 4. In this way, by utilizing the randomness of the values taken at the predetermined positions in each data to be shuffled, the purpose of randomly determining the target index element is achieved. After determining the above target index elements, the target index elements can be placed in register 2 in a certain order to form a target index sequence. Finally, using the TBL instruction, the data segments corresponding to the index values in each index element in the target index sequence are placed in the destination register, and the shuffling of the data to be shuffled 1 to 4 can be achieved. In Figure 3 , after shuffling the data to be shuffled 1 to 4, the shuffling result of "data to be shuffled 1, data to be shuffled 1, data to be shuffled 2, and data to be shuffled 4" is obtained.

[0041] In some cases, the data to be shuffled stored in register 1 can be referred to as target data. For example, in some cases, the number of data to be shuffled can exceed the number of target data. For example, referring to Figure 4 and Figure 5 , assume that in addition to the data to be shuffled 1 to 4, there are also data to be shuffled 5 to 8, but the final output shuffled result is 4 data to be shuffled. Referring to Figure 4 , assume that each data to be shuffled still includes 4 data segments, and each data segment corresponds to an index identifier. The index values in index elements 1 to 4, and the corresponding relationship between index elements 1 to 4 and the data to be shuffled 1 to 4 are the same as in the above example. In addition, index elements 5 to 8 are respectively set to correspond to the data to be shuffled 5 to 8, that is, index element 5 includes index values 0x10, 0x11, 0x12, and 0x13, and these index values respectively correspond to data segments 10, 11, 12, and 13 in the data to be shuffled 5; index element 6 includes index values 0x14, 0x15, 0x16, and 0x17, and these index values respectively correspond to data segments 14, 15, 16, and 17 in the data to be shuffled 6; index element 7 includes index values 0x18, 0x19, 0x1a, and 0x1b, and these index values respectively correspond to data segments 18, 19, 1a, and 1b in the data to be shuffled 7; index element 8 includes index values 0x1c, 0x1d, 0x1e, and 0x1f, and these index values respectively correspond to data segments 1c, 1d, 1e, and 1f in the data to be shuffled 8.

[0042] To distinguish these eight index elements, an index identifier represented by a three-bit binary value can be used to mark index elements 1 to 8. In Figure 4 , index element 1 can be marked with the index identifier 000, index element 2 can be marked with the index identifier 001, index element 3 can be marked with the index identifier 010, index element 4 can be marked with the index identifier 011, index element 5 can be marked with the index identifier 100, index element 6 can be marked with the index identifier 101, index element 7 can be marked with the index identifier 110, and index element 8 can be marked with the index identifier 111. When performing the shuffle operation, assume that 4 data to be shuffled need to be output as the shuffle result, then referring to Figure 5 , any 4 data to be shuffled can be put into register 1, Figure 5The data to be shuffled, namely 1, 5, 7, and 3, are placed in register 1. Based on the values of the predetermined positions of the data to be shuffled, which are "000", "010", "111", and "101", as the target index identifiers, the corresponding target index elements are determined to be index element 1, 3, 8, and 6 respectively. The target index elements are placed in register 2 to obtain the target index sequence. Finally, using the TBL instruction, the data segments corresponding to the index values in the target index sequence are placed in the destination register. The final output shuffle result is: "The data to be shuffled 1, 3, 8, 6". In this way, the shuffle operation of randomly selecting 4 data to be shuffled from 8 data to be shuffled is achieved.

[0043] In Figure 4 and Figure 5 In the embodiment shown, the 4 data to be shuffled placed in register 1 can be referred to as target data for determining the target index elements. That is, the 4 target data placed in register 1 can determine 4 target index elements, thus cooperating with the TBL instruction to achieve the purpose of outputting the shuffle result of 4 data to be shuffled.

[0044] It can be understood that if the number of data to be shuffled is 16, the number of index elements is also 16. The 16 index elements correspond one-to-one with the 16 data to be shuffled, and the index identifiers corresponding to the index elements can be represented by the values of four-bit binary data. These situations are not exhaustively listed in this specification.

[0045] From the above description, it can be found that by adjusting the number of index values in the index elements, the shuffle operation of data to be shuffled with different bit numbers can be achieved. For example, when the number of index values of the index elements is 2, if the TBL instruction can operate on 8-bit data according to 1 index value, then the shuffle of 16-bit data to be shuffled can be achieved; when the number of index values of the index elements is 4, if the TBL instruction can operate on 8-bit data according to 1 index value, then the shuffle of 32-bit data to be shuffled can be achieved; when the number of index values of the index elements is 8, if the TBL instruction can operate on 8-bit data according to 1 index value, then the shuffle of 64-bit data to be shuffled can be achieved. In this way, this data processing method realizes the purpose of cooperating with the TBL instruction to shuffle data to be shuffled with any bit number by generating a target index sequence for the TBL instruction.

[0046] Based on the above concept, the embodiments of this specification provide a data processing method to solve the problem that a computing device based on the ARM architecture cannot perform a shuffle operation on data to be shuffled with any bit number. Next, the data processing method provided by the embodiments of this specification will be described exemplarily in conjunction with the drawings.

[0047] Exemplary Method

[0048] Reference Figure 6 , taking the processor 11 in the computing device 10 as an example, an embodiment of this specification provides a data processing method, including:

[0049] S601: In response to an index generation instruction carrying a first register identifier and a data bit number parameter, determine multiple target index elements in the initial index sequence; the first register identifier is used to represent a source register, and multiple target data are stored in the source register; the data bit number parameter is used to represent the bit width of the target data, the initial index sequence includes multiple index elements, and the index elements include multiple index values; the index elements are in one-to-one correspondence with index identifiers, and the data values at predetermined positions of the multiple target data in the source register represent the index identifiers corresponding to the target index elements;

[0050] S602: Generate a target index sequence according to the multiple target index elements;

[0051] S603: According to the target index sequence, use the table branch lookup TBL instruction to perform a shuffle operation on multiple data to be shuffled, where the multiple data to be shuffled include the multiple target data; the index value corresponds to multiple bits of data in the target data, and the index value is used to indicate that the TBL instruction stores the multiple bits of data corresponding to the index value in a target register.

[0052] In Figure 6 , the shown application scenario is a scenario where the processor 11 shuffles the data to be shuffled to obtain the shuffled data. Although Figure 6 the data to be shuffled and the shuffled data in

[0053] are externally represented by the processor 11, it can be understood that in an actual processing scenario, the data to be shuffled and the shuffled data can also be located inside the processor 11. This specification does not make any limitations in this regard. The processor 11 can perform a shuffle operation on the data to be shuffled of various lengths through the data processing method provided by the embodiment of this specification when executing tasks such as binary compilation.

[0054] As described above, the data to be shuffled can refer to the data waiting to perform the shuffle operation. Among multiple data to be shuffled, it can include multiple target data placed in the source register. Or rather, after the data to be shuffled is placed in the source register, it can be called target data. According to Figures 2 - 5 and the relevant descriptions above, it is not difficult to understand that the target data in the source register does not necessarily appear in the final shuffle result, and the target data in the source register can be used to determine the target index element.

[0055] In one embodiment, a method for determining the target data stored in the source register according to the relationship between the number of target data and the number of data to be shuffled is provided. Specifically, the data processing method further includes:

[0056] Obtain N data to be shuffled, where N is an integer greater than 1;

[0057] If the number of the multiple target data is equal to N, then take the N data to be shuffled as the multiple target data and store them in the source register in a random order;

[0058] If the number of the multiple target data is less than N, then take M data to be shuffled from the N data to be shuffled as the multiple target data and store them in the source register in a random order; M is an integer less than N and greater than 1.

[0059] The number of target data can be used to represent the number of data to be shuffled in the final shuffle result output by the shuffle operation. For example, assume there are a total of 8 data to be shuffled. When it is necessary to output a shuffle result including 4 data to be shuffled, then 4 data to be shuffled can be taken from the 8 data to be shuffled as the target data and stored in the source register. At this time, the number of the multiple target data (4) is less than N (N = 8); assume there are a total of 2 data to be shuffled. When it is necessary to output a shuffle result including 2 data to be shuffled, then the 2 data to be shuffled can be taken as the target data and stored in the source register. At this time, the number of the multiple target data (2) is equal to N (N = 2).

[0060] Through this method, the shuffle requirements for different situations can be met.

[0061] In one embodiment, both the source register and the destination register can be vector registers. To represent the bit widths of the source register and the destination register, the data bit number parameter can be included in an assembly symbol. In addition to including the data bit number parameter, this assembly symbol can also represent the bit width of the destination register. For example, assuming the assembly symbol is 2D, it means the data bit number parameter is 64 bits (D = 64 bits), and the bit widths of the destination register and the source register can be 128 bits (2 × 64 bits); assuming the assembly symbol is 4S, it means the data bit number parameter is 32 bits (S = 32 bits), and the bit widths of the destination register and the source register can be 128 bits (4 × 32 bits), and so on. Through the assembly symbol, the data bit number parameter and the bit width of the destination register can be obtained conveniently and quickly, facilitating the selection of the appropriate number of target data.

[0062] In some embodiments, referring to Figure 3 , the number of index elements included in the initial index sequence is equal to N. The N index elements correspond one by one to the N data to be shuffled. Multiple index values in the index elements respectively correspond to multiple data segments in the data to be shuffled corresponding to the index elements. The data segment includes multiple bits of data.

[0063] In Figure 3 , the initial index sequence includes 4 index elements 1 to 4, which respectively correspond one by one to the 4 data to be shuffled 1 to 4. In some embodiments, the data segment includes 8-bit data. In this case, register 1 is the source register, which can store the data to be shuffled 1 to 4. The storage order of the 4 data to be shuffled in the source register can be random storage or stored in a certain order. This specification does not make a limitation on this, and it depends on the actual situation specifically.

[0064] As described above, in order to enable the index identifier to meet the identification requirements of multiple index elements, in one embodiment of this specification, the number of bits of the index identifier is X bits, where X is an integer greater than or equal to 1; 2 to the power of X is greater than or equal to N.

[0065] In one embodiment of this specification, 2 to the power of X is equal to N. That is, if there are 2 index elements, the number of bits of the index identifier can be 1 bit, satisfying 2 to the power of 1 equals 2; if there are 4 index elements, the number of bits of the index identifier can be 2 bits, satisfying 2 to the power of 2 equals 4; if there are 8 index elements, the number of bits of the index identifier can be 3 bits, satisfying 2 to the power of 3 equals 8, and so on. In this way, a relatively small number of data bits can be used as the index identifier, without having to process a large amount of data when determining the index identifier in the data to be shuffled.

[0066] Correspondingly, determining a plurality of target index elements in the initial index sequence includes:

[0067] Taking the X-bit data at a predetermined position of a plurality of the target data in the source register as a target index identifier;

[0068] Taking the index element corresponding to the target index identifier as the target index element.

[0069] Reference Figure 7 , Figure 7 shows a case of 2 data to be shuffled and 2 index elements. At this time, the assembly symbol can be 2D, indicating that the data bits in the destination register are divided into 2 64-bit parts for storing 2 64-bit data to be shuffled respectively. Each index element includes 8 index values, and each index value is used to operate 8-bit data. Index element 1 includes index values: 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, and 0xf; index element 2 includes index values: 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, and 0x0; index element 1 and index element 2 correspond to data to be shuffled 1 and data to be shuffled 2 respectively, and index values: 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, and 0xf correspond to data segments 8 to f in data to be shuffled 1 respectively, and index values: 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, and 0x0 correspond to data segments 7 to 0 in data to be shuffled 2 respectively. Register 1 stores data to be shuffled 1 and 2 as the source register, takes the X-bit (1 bit in this example) data at a predetermined position of data to be shuffled 1 and data to be shuffled 2 as the target index identifier, and determines the target index element in the target index sequence stored in register 2. Finally, use the TBL instruction to perform shuffling according to the target index sequence to obtain the shuffling result stored in the destination register: data to be shuffled 2, data to be shuffled 1. In this embodiment, the position adjustment of the data to be shuffled is realized.

[0070] In Figure 7 In the shown case, when the assembly symbol is 2D, register 2 can be divided into two parts [0:63] and [64:127] from low to high according to the data bits, and each part writes 64-bit index values. The second bit from the low position of each part can be used as the X-bit data at the predetermined position, that is, using b1 bit and b65 bit as the target index identifier to identify the target index element.

[0071] In Figure 3In the shown scenario, the assembly symbol is 4S. Register 2 can be divided into four parts, namely [0:31], [32:63], [64:95], and [96:127] from low to high data bits, and each part writes a 32-bit index value. Since there are four index elements, the two low-order bits of each part of the data stored in register 2 can be used as the target index identifier, that is, the [1:0] bit, [33:32] bit, [65:64] bit, and [97:96] bit are used as the target index identifier.

[0072] In Figure 4 the shown scenario, the assembly symbol is still 4S, but since there are eight index elements, 3-bit data is required as the index identifier. For example, the three low-order bits of each part of the data stored in register 2 can be used as the target index identifier, that is, the [2:0] bit, [34:32] bit, [66:64] bit, and [98:96] bit are used as the target index identifier.

[0073] Still referring to Figures 3 - 5 and Figure 7 , generating a target index sequence according to the multiple target index elements includes:

[0074] Placing the target index element at the corresponding position in the second register according to the storage position of the target index identifier corresponding to the target index element in the source register.

[0075] Referring to Figures 3 - 5 and Figure 7 , placing the target index element at the corresponding position in the second register according to the storage position of the target index identifier corresponding to the target index element in the source register may mean: storing each target index element in the second register in the storage order from low to high of the target index identifier corresponding to each target index element in the source register (i.e., register 1). For example, taking the scenario in Figure 7 as an example, the index identifier "0" corresponding to index element 1 is stored at a relatively low position in register 1, so the storage position of index element 1 in register 2 is the 64-bit from the lowest bit, while the index identifier "1" corresponding to index element 2 is stored at a relatively high position in register 1, so the storage position of index element 2 in register 2 is from the relatively high position, that is, the [64:127] bit.

[0076] In some embodiments, the target data stored in register 1 can be randomly selected from multiple data to be shuffled, and the order of the target data stored in register 1 can also be random. Thus, the value at a predetermined position in register 1 is random, making the determination of the index identifier random. Then, based on this, the index elements determined according to the index identifier and the finally generated target index sequence are random. Based on this target index sequence and in cooperation with the TBL instruction, the shuffling operation of the data to be shuffled can be achieved. Specifically, performing the shuffling operation on multiple data to be shuffled by using the table branch lookup TBL instruction according to the target index sequence may include:

[0077] Using the TBL instruction, store the multiple-bit data corresponding to each index value in the target index sequence in the target register in sequence according to the position of the index value in the target index sequence.

[0078] In this embodiment, by using the TBL instruction to store the multiple-bit data corresponding to each index value in the target register in sequence according to the position of the index value in the target index sequence, the shuffling of multiple data to be shuffled can be achieved.

[0079] In an alternative embodiment, a feasible structure of an index generation instruction is provided, as Figure 8 shown. In this index generation instruction, Vn represents the first register identifier, Vd represents the destination register identifier, size represents an assembly symbol. In this index generation instruction, the value of size can be 2D, 4S, etc. D represents 64 bits, and S represents 32 bits; other parameters such as op0, op1, Q, and 0 are fixed parameters filled in accordance with the fixed format of this type of instruction for generating indexes in the ARM instruction.

[0080] Exemplary Apparatus

[0081] In an exemplary embodiment of this specification, a shift device is further provided, which is characterized in that it is applied to a computing device, as Figure 9 shown. The data processing device includes:

[0082] An index determination module 801, configured to determine multiple target index elements in an initial index sequence in response to an index generation instruction carrying a first register identifier and a data bit number parameter; the first register identifier is used to represent a source register, and multiple target data are stored in the source register; the data bit number parameter is used to represent the bit width of the target data, the initial index sequence includes multiple index elements, and the index elements include multiple index values; the index elements are in one-to-one correspondence with index identifiers, and the data value at a predetermined position of the multiple target data in the source register represents the index identifier corresponding to the target index element;

[0083] A sequence generation module 802, configured to generate a target index sequence according to a plurality of the target index elements;

[0084] A shuffle operation module 803, configured to perform a shuffle operation on a plurality of data to be shuffled according to the target index sequence by using a table branch lookup TBL instruction, where the plurality of data to be shuffled includes the plurality of target data; the index value corresponds to multiple bits of data in the target data, and the index value is used to indicate that the TBL instruction stores the multiple bits of data corresponding to the index value in a target register.

[0085] In one embodiment, the data processing device further includes:

[0086] A target determination module, configured to obtain N data to be shuffled, where N is an integer greater than 1;

[0087] If the number of the plurality of target data is equal to N, then use the N data to be shuffled as the plurality of target data and store them in the source register in a random order;

[0088] If the number of the plurality of target data is less than N, then take out M data to be shuffled from the N data to be shuffled as the plurality of target data and store them in the source register in a random order; M is an integer less than N and greater than 1.

[0089] In one embodiment, the number of index elements included in the initial index sequence is equal to N, the N index elements correspond to the N data to be shuffled one by one, and multiple index values in the index elements respectively correspond to multiple data segments in the data to be shuffled corresponding to the index elements, and the data segment includes multiple bits of data.

[0090] In one embodiment, the number of bits of the index identifier is X bits, where X is an integer greater than or equal to 1; 2 to the power of X is greater than or equal to N.

[0091] In one embodiment, the index determination module determines multiple target index elements in the initial index sequence specifically for:

[0092] Use X bits of data at a predetermined position of the multiple target data in the source register as a target index identifier;

[0093] Use the index element corresponding to the target index identifier as the target index element.

[0094] In one embodiment, the sequence generation module generates a target index sequence according to a plurality of the target index elements specifically for:

[0095] Place the target index element at the corresponding position in the second register according to the storage position of the target index identifier corresponding to the target index element in the source register.

[0096] In one embodiment, the data bit number parameter is included in the assembly symbol.

[0097] In one embodiment, the shuffle operation module performs a shuffle operation on multiple data to be shuffled according to the target index sequence by using a table branch lookup TBL instruction, specifically for:

[0098] Use the TBL instruction to store the multi-bit data corresponding to each index value in the target index sequence in the target register in sequence according to the position of the index value in the target index sequence.

[0099] For the specific limitations of the data processing device, reference can be made to the limitations of the data processing method in the above text, which will not be elaborated here. Each module in the above data processing device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of it, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0100] Exemplary Processor and Computing Device

[0101] One embodiment of this specification provides a processor, such as Figure 10 shown, the processor 1001 includes:

[0102] A decoder 1002 for decoding a computing instruction into a decoded instruction;

[0103] An execution unit 1003 for executing the decoded instruction to implement the data processing method described in any of the above embodiments or the data processing method described in any of the above embodiments.

[0104] In addition to the above structure, the processor 1001 may further include a plurality of registers 1004 to cooperate with the execution unit 1003 to execute tasks. Both the register 1004 and the decoder 1002 are connected to the execution unit 1003. Another embodiment of this application also proposes a computing device, see Figure 11 shown, one exemplary embodiment of this specification also provides a computing device, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the steps in the data processing method described in the above embodiments of this specification according to various embodiments of this specification.

[0105] The internal structure of this computing device can be asFigure 11 As shown, the computing device includes a processor, a memory, a network interface, and an input device connected via a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it performs the steps in the data processing method according to various embodiments of this specification described in the above embodiments of this specification.

[0106] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0107] The memory stores a program for implementing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0108] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0109] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0110] The output device may include a device for allowing information to be output to a user, such as a display screen, a printer, a speaker, etc.

[0111] The communication interface may include a device of any transceiver type for communicating with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0112] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any one of the data processing methods provided in the foregoing embodiments of the present application.

[0113] The computing device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, a trackball, or a touchpad provided on the housing of the computing device, or an external keyboard, touchpad, or mouse, etc.

[0114] Those skilled in the art can understand that Figure 11 the structure shown in is only a block diagram of some structures related to the solution of this specification, and does not constitute a limitation on the computing device to which the solution of this specification is applied. The specific computing device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0115] Exemplary Computer Program Product and Storage Medium

[0116] In addition to the above methods and devices, the data processing method provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor is caused to execute the steps in the data processing methods according to various embodiments of this specification described in the "Exemplary Method" section above of this specification.

[0117] The computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of this specification. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0118] In addition, the embodiments of this specification further provide a computer-readable storage medium, on which a computer program is stored, and the computer program is executed by a processor to perform the steps in the data processing methods according to various embodiments of this specification described in the "Exemplary Method" section above of this specification.

[0119] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this specification can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0120] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0121] The above-described embodiments merely represent several implementation manners of this specification. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the solutions provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A data processing method, characterized in that, including: In response to an index generation instruction carrying a first register identifier and a data bit width parameter, determining a plurality of target index elements in an initial index sequence; The first register identifier is used to represent a source register, and a plurality of target data are stored in the source register; the data bit width parameter is used to represent the bit width of the target data, the initial index sequence includes a plurality of index elements, and the index elements include a plurality of index values; the index elements are in one-to-one correspondence with index identifiers, and the data values at predetermined positions of the plurality of target data in the source register represent the index identifiers corresponding to the target index elements; Generating a target index sequence according to the plurality of target index elements; According to the target index sequence, using a table branch lookup TBL instruction to perform a shuffle operation on a plurality of data to be shuffled, the plurality of data to be shuffled including the plurality of target data; The index value corresponds to a plurality of bits of data in the target data, and the index value is used to instruct the TBL instruction to store the plurality of bits of data corresponding to the index value in a target register.

2. The method according to claim 1, characterized in that, It further includes: Obtaining N data to be shuffled, where N is an integer greater than 1; If the number of the plurality of target data is equal to N, then taking the N data to be shuffled as the plurality of target data and storing them in the source register in a random order; If the number of the plurality of target data is less than N, then taking M data to be shuffled out of the N data to be shuffled as the plurality of target data and storing them in the source register in a random order; M is an integer less than N and greater than 1.

3. The method according to claim 2, characterized in that, The number of index elements included in the initial index sequence is equal to N, the N index elements are in one-to-one correspondence with the N data to be shuffled, and the plurality of index values in the index elements are respectively in one-to-one correspondence with a plurality of data segments in the data to be shuffled corresponding to the index elements, and the data segments include a plurality of bits of data.

4. The method according to claim 2, characterized in that, The number of bits of the index identifier is X bits, where X is an integer greater than or equal to 1; 2 to the power of X is greater than or equal to N.

5. The method according to claim 4, characterized in that, The determining a plurality of target index elements in the initial index sequence includes: Taking the X-bit data at a predetermined position of the plurality of target data in the source register as a target index identifier; Taking the index element corresponding to the target index identifier as the target index element.

6. The method according to claim 5, characterized in that, The generating a target index sequence according to the plurality of target index elements includes: Placing the target index element at a corresponding position in a second register according to the storage position of the target index identifier corresponding to the target index element in the source register.

7. The method according to any one of claims 1 to 6, characterized in that, The data bit width parameter is included in an assembly symbol.

8. The method according to any one of claims 1 to 6, characterized in that, The using a table branch lookup TBL instruction to perform a shuffle operation on a plurality of data to be shuffled according to the target index sequence includes: Using the TBL instruction to sequentially store the plurality of bits of data corresponding to each index value in the target index sequence in the target register according to the position of the index value in the target index sequence.

9. A data processing device, characterized in that, The data processing device includes: An index determination module, configured to determine a plurality of target index elements in an initial index sequence in response to an index generation instruction carrying a first register identifier and a data bit width parameter; the first register identifier is used to represent a source register, and a plurality of target data are stored in the source register; the data bit width parameter is used to represent the bit width of the target data, the initial index sequence includes a plurality of index elements, and the index elements include a plurality of index values; the index elements are in one-to-one correspondence with index identifiers, and the data values at predetermined positions of the plurality of target data in the source register represent the index identifiers corresponding to the target index elements; A sequence generation module, configured to generate a target index sequence according to the plurality of target index elements; A shuffle operation module, configured to perform a shuffle operation on a plurality of data to be shuffled according to the target index sequence by using a table branch lookup TBL instruction, where the plurality of data to be shuffled includes the plurality of target data; the index value corresponds to multiple bits of data in the target data, and the index value is used to instruct the TBL instruction to store the multiple bits of data corresponding to the index value in a target register.

10. A processor, characterized in that, Comprising: A decoder, configured to decode a computation instruction into a decoded instruction; An execution unit, configured to execute the decoded instruction to implement the data processing method according to any one of claims 1 to 8.

11. A computing device, characterized in that, Comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the data processing method according to any one of claims 1 to 8 when executing the computer program.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and the data processing method according to any one of claims 1 to 8 is implemented when the computer program is executed by a processor.

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