Address allocation method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides an address allocation method and device, a storage medium and electronic equipment, and relates to the technical field of computers.The method comprises the steps that in response to a write-in request, snapshot information is obtained; according to a mapping rule, allocating a physical block address corresponding to a logic block address of at least one piece of data by utilizing the snapshot information; wherein the snapshot information is used for allocating adjacent logical block addresses to physical block addresses located in different areas. Thus, the adjacent logic block addresses are allocated to different physical areas, the situation that part of data are intensively distributed in a high page is avoided, and therefore the reading performance and the user experience are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to an address allocation method, apparatus, storage medium, and electronic device. Background Art

[0002] Non-volatile solid-state storage has shown a development trend of high density. Currently, manufacturers at home and abroad have completed the productization of solid-state storage based on four-bit storage cell (QLC, Quad-Level Cell) particles, leading a new direction for the development of SSDs.

[0003] The flash translation layer (FTL, Flash Translation Layer) is used to shield the physical characteristics of the flash memory from users and implement software management inside the SSD. It mainly consists of key algorithms such as address mapping, garbage collection, and wear leveling. Address mapping is one of the key functions of the FTL. This function allocates flash addresses for write commands initiated by the host (host) and realizes the conversion from logical addresses to physical addresses. In related technologies, a method under the super management mode has been proposed. A commonly used method is to allocate all physical block addresses (PBAs, Physical Block Addresses) on a certain multi-word line (MWL, Multi-Word Line) layer by layer according to pages (Pages). This method effectively improves the parallelism of data reading and writing.

[0004] However, the above physical address allocation method does not consider the error characteristics of each page of the QLC. The 4 pages of each word line (WL, Word Line) of the QLC particle are named LSB (Least Significant Bit), CSB (Central Significant Bit), MSB (Most Significant Bit), and TSB (Top Significant Bit) from bottom to top. Research shows that the read latency of high pages (such as MSB and TSB) is usually greater than that of low pages (such as LSB and CSB). This is mainly due to the following three reasons: 1) Reading high pages requires more reference voltages; 2) High pages are more likely to have errors and a higher bit error rate; 3) The error correction process increases the reading time consumption.

[0005] Therefore, if host data is processed according to the ordinary address allocation method in QLC solid-state storage, it is possible that some data is concentratedly distributed on high pages, which seriously affects the reading performance and user experience. Summary of the Invention

[0006] The present disclosure provides an address allocation method, apparatus, storage medium, and electronic device to at least solve the above technical problems existing in the prior art.

[0007] The technical solution of the embodiments of the present disclosure is implemented as follows: In a first aspect, an embodiment of the present disclosure provides an address allocation method applied to a solid-state drive. The method includes: In response to a write request, obtain snapshot information; According to a mapping rule, use the snapshot information to allocate physical block addresses corresponding to at least one logical block address of data; wherein, the snapshot information is used to allocate physical block addresses located in different regions to adjacent logical block addresses.

[0008] In the above solution, the method further includes: Generate snapshot information, where the snapshot information includes: an offset snapshot; the offset snapshot is used to record the offset relationship between physical block addresses.

[0009] In the above solution, the using the snapshot information to allocate physical block addresses corresponding to at least one logical block address of data includes: Use the snapshot information to allocate physical block addresses corresponding to at least one logical block address of data on each multi-word line.

[0010] In the above solution, generating the offset snapshot includes: Obtain a first quantity and a second quantity of multi-word lines, where the first quantity is the number of page layers of each word line, and the second quantity is the number of planes involved in the parallel storage operation of word lines; Construct a first matrix, a second matrix, and a third matrix according to the first quantity and the second quantity; Obtain an offset snapshot according to the first matrix, the second matrix, and the third matrix; Wherein, the first matrix is used to record the pages of physical block addresses that can be allocated using the diagonal; The second matrix is used to translate the allocation order of the pages; The third matrix is used to accumulate the number of pages of physical block addresses that can be allocated.

[0011] In the above solution, the number of rows of the first matrix is related to the first quantity, and the number of columns of the first matrix is related to the second quantity; The number of rows of the second matrix is related to the second quantity, and the number of columns of the second matrix is related to the second quantity; The number of rows of the third matrix is related to the first quantity, and the number of columns of the third matrix is related to the second quantity.

[0012] In the above solution, obtaining the offset snapshot according to the first matrix, the second matrix, and the third matrix includes: Determining the total number of iterations according to the second quantity; Successively processing the sequential matrix according to the total number of iterations to obtain a target sequential matrix, and each processing includes: determining the product of the iteration number and the third matrix, adding the product to the first matrix to obtain a translation result; multiplying the translation result by the second matrix and then adding it to the sequential matrix of the previous round; Determining the offset snapshot according to the target sequential matrix.

[0013] In the above solution, the target sequential matrix is used to indicate the planes corresponding to multiple physical block addresses, and the corresponding LSB, CSB, MSB, or TSB; Determining the offset snapshot according to the target sequential matrix includes: Determining the planes where multiple physical block addresses are located according to the target sequential matrix, and the LSB, CSB, MSB, or TSB where they are located; each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSB, CSB, MSB, or TSB of physical block addresses with adjacent allocation orders are different.

[0014] In the above solution, allocating the physical block address corresponding to the logical block address of at least one data on each multi-word line by using the snapshot information includes: Allocating an index set to the multi-word line, where the index set includes indexes of at least one physical block address, and the index represents the allocation order of the physical block address; Allocating the first physical block address corresponding to the first logical block address according to the index set, where the first logical block address is the logical block address of the starting data on the multi-word line; Allocating the second physical block address corresponding to the second logical block address according to the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot; the second logical block address is the logical block address of other data except the starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0015] In the above solution, the method further includes: Querying whether the block where the physical block address is located is a bad block; If the block where the physical block address is located is a bad block, updating the index set to delete or skip the physical block addresses related to the bad block.

[0016] In the above solution, the method further includes: Determine a mapping table according to the logical block address of each piece of data and the physical block address in the solid-state storage unit, where the mapping table is used to record the mapping relationship between the logical block address and the physical block address of each piece of data; Receive a read request, query the mapping table according to the logical block address carried in the read request, and determine the physical block address corresponding to the read request.

[0017] In the above solution, the solid-state drive is a QLC solid-state drive, the QLC solid-state drive includes multiple planes, each plane includes multiple blocks, each block includes multiple pages, and the multiple pages include: LSB, CSB, MSB, TSB; The physical block addresses in different regions include: The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0018] In a second aspect, an embodiment of the present disclosure provides an address allocation device, which is applied to a solid-state drive, and the device includes: An acquisition module, configured to acquire snapshot information in response to a write request; A processing module, configured to allocate physical block addresses corresponding to the logical block addresses of at least one piece of data according to a mapping rule by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses located in different regions to adjacent logical block addresses.

[0019] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute any one of the address allocation methods.

[0020] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the address allocation method according to any one of the above.

[0021] The embodiments of the present disclosure have the following beneficial effects: Applying the address allocation method, device, storage medium and electronic device provided by the embodiments of the present disclosure, in response to a write request, snapshot information is obtained; according to the mapping rule, at least one physical block address corresponding to the logical block address of the data is allocated by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses located in different regions for adjacent logical block addresses. In this way, by allocating adjacent logical block addresses to different physical regions, the situation where some data is concentratedly distributed in high pages (such as MSB, TSB) is avoided, thereby improving the reading performance and user experience.

[0022] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the organization form of a flash memory and a traditional physical address allocation method; Figure 2 It is a schematic flowchart of an address allocation method provided by an embodiment of the present disclosure; Figure 3 It is a schematic comparison diagram of the allocation order of MWL physical block addresses provided by an embodiment of the present disclosure; Figure 4 It is a schematic flowchart of a PBA allocation method for a QLC solid-state storage provided by an embodiment of the present disclosure; Figure 5 It is a schematic diagram of the structure of a solid-state drive provided by an embodiment of the present disclosure; Figure 6 It is a schematic diagram of the structure of an address allocation device provided by an embodiment of the present disclosure; Figure 7 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present disclosure.

[0025] In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0026] If similar descriptions such as "first / second" appear in the application documents, the following explanation shall be added. In the following description, the terms "first / second / third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that, where permitted, "first / second / third" can be interchanged in a specific order or sequence so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0028] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0029] A solid-state drive (SSD) is a hard drive based on flash storage technology that uses flash memory cells instead of the spinning disks of a traditional hard disk drive (HDD). The advantages of an SSD include faster read and write speeds, lower power consumption, and higher shock resistance. The core storage area of an SSD is typically flash memory.

[0030] A QLC (Quad-Level Cell, four-bit storage cell, i.e., 4bit / cell) solid-state drive is a type of storage in which each storage cell can store 4 bits of data. Compared with other types of solid-state drives (such as single-bit storage cells (SLC, Single-Level Cell, i.e., 1 bit / cell), multi-bit storage cells (MLC, Multi-Level Cell, i.e., 2bit / cell), trinary-bit storage cells (TLC, Trinary-Level Cell, i.e., 3bit / cell)), QLC solid-state drives provide higher storage density, thus reducing storage costs.

[0031] The storage area is divided into multiple planes, each plane contains multiple blocks, and each block includes multiple pages.

[0032] Plane: The division unit of storage units in a solid-state drive. Multiple Planes (usually 4, 6, or 8) form a LUN (Logical Unit Number), and multiple LUNs can form a storage chip. Each Plane has an independent cache register and page register and can perform read and write operations independently.

[0033] Block: In an SSD, the storage unit is further divided into multiple blocks, and each block consists of multiple Pages. Each block is the smallest unit for the erasure operation of the solid-state drive.

[0034] Word Line (WL): Each block is usually composed of multiple WLs, and WL is the smallest unit for writing.

[0035] Page: The smallest data storage unit in each block, usually with a size between 2KB and 16KB. The read operation of the SSD is usually performed by page.

[0036] Logical Block Address (LBA): It is the virtual address used when the operating system or storage controller interacts with the storage device (such as the solid-state drive controller interacting with the solid-state drive). It is a logical address and is the data mapping method between the operating system and the hard disk. Users and the operating system usually use the logical block address to specify the location of data.

[0037] Physical Block Address (PBA): It is the actual physical address inside the storage device, indicating the physical location of data on the storage medium (such as a solid-state drive). It is the address that the storage controller actually uses to access data.

[0038] Figure 1 It is a schematic diagram of an organization form of flash memory and a traditional physical address allocation method. As Figure 1 shown, in the write operation, LBA0 to LBA3 are respectively assigned to WL0 and Page0 of Plane0 to Plane3; when transmitting the data of LBA0 to the page register, the data transmission of LBA1 can be initiated simultaneously; similarly, when reading LBA0 - LBA3, the read operation of Plane1 can be immediately started when the page register of Plane0 transfers data to the bus.

[0039] It can be seen that if Figure 1In the method shown, if host data is processed according to the ordinary address allocation method in QLC solid-state storage, it may occur that some data is concentrated in high pages (such as MSB, TSB). Because the pages are higher and the bit error rate is higher, the high-page read latency is larger, which seriously affects the read performance and user experience.

[0040] Based on this, embodiments of the present disclosure provide an address allocation method, apparatus, storage medium, and electronic device. In response to a write request, snapshot information is obtained; according to a mapping rule, at least one physical block address corresponding to a logical block address of data is allocated by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses of adjacent logical block addresses in different regions. In this way, by allocating adjacent logical block addresses to different physical regions, the situation where some data is concentrated in high pages (such as MSB, TSB) is avoided, thereby improving the read performance and user experience.

[0041] Figure 2 The flowchart of an address allocation method provided by an embodiment of the present disclosure is shown as Figure 1 shown. The method is applied to a solid-state drive, and the address allocation method includes: Step 201, in response to a write request, obtain snapshot information; Step 202, according to a mapping rule, allocate at least one physical block address corresponding to a logical block address of data by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses of adjacent logical block addresses in different regions.

[0042] Here, the solid-state drive can receive IO commands from a host, such as read requests, write requests, etc.; The snapshot information records information providing physical block addresses corresponding to allocated logical block addresses, and the mapping rule stipulates a method of how to map logical block addresses to physical block addresses. This can be implemented through FTL (Flash Translation Layer).

[0043] Allocating physical block addresses of adjacent logical block addresses in different regions by using the snapshot information means that although some logical block addresses are adjacent, these adjacent logical block addresses will be allocated to different physical regions (such as different types of Pages). In this way, they are sequentially distributed in high pages (such as MSB, TSB) and low pages (such as LSB, CSB), avoiding the situation where some data is concentrated in high pages (such as MSB, TSB), thereby improving the read performance and user experience.

[0044] In some embodiments, the method further includes: Generate snapshot information, where the snapshot information includes: an offset snapshot; the offset snapshot is used to record the offset relationship between physical block addresses.

[0045] Specifically, snapshot information is a backup of the state of a storage system at a certain moment, used to track changes in stored data. It can contain information in multiple aspects, providing guidance for saving computing time during writing or reading. In actual applications, snapshot information can include multiple different types of snapshots. For example, in addition to the offset snapshot, it can also include: Plane snapshot.

[0046] The offset snapshot is used to record the offset relationship between different physical block addresses. The offset relationship refers to the relative position or difference between physical block addresses. For example, the offset snapshot can describe the distance between a certain physical block address and another physical block address or their offset in the storage medium. In this way, when mapping a new physical block address, the offset relationship between the already allocated physical block address and the new physical block address can be referred to determine the new physical block address.

[0047] Regarding the Plane snapshot, Plane refers to a hierarchical structure in a storage device (such as a solid-state drive), used to represent the physical levels on the storage medium. In a solid-state drive, it can be divided into multiple Planes, each Plane contains multiple blocks, and each block includes multiple WLs (such as Figure 1 WL1, WL2, etc.), and each WL can include multiple Pages (such as Figure 1 Page0, Page1, etc.). The Plane snapshot is used to record information related to the physical storage hierarchy, such as the specific situation of storage area distribution and management.

[0048] For example, the Plane snapshot is denoted as Plane_snapshot; Plane_snapshot={0,1,2,3,1,2,3,0,2,3,0,1,3,0,1,2}; It means there are four Planes, namely Plane0, Plane1, Plane2, and Plane3; when sequentially allocating physical block addresses, the physical block addresses are successively located in Plane0, Plane1, Plane2, Plane3, and then, are successively allocated to Plane1, Plane2, Plane3, Plane0, and so on. Subsequently, they are Plane2, Plane3, Plane0, Plane1, and Plane3, Plane0, Plane1, Plane2. The allocation of physical block addresses to different Planes.

[0049] In some embodiments, the logic for allocating physical block addresses corresponding to at least one logical block address of the data by using the snapshot information includes: Allocating physical block addresses corresponding to the logical block addresses of at least one data on each multi-word line (MWL) by using the snapshot information.

[0050] Here, to improve the data transfer rate and the parallelism of storage operations, the multi-word line technology allows multiple word lines to be activated simultaneously within one clock cycle. Here, the solid-state drive can read or write multiple Pages at the same time by using the multi-word line, thereby improving the data access speed.

[0051] Specifically, multiple data blocks correspond to each multi-word line, and physical block addresses corresponding to the logical block addresses of each data on the multi-word line can be allocated, and the physical block address refers to the specific address on the Plane, Block, and Page.

[0052] In some embodiments, generating the offset snapshot includes: Obtaining a first quantity and a second quantity of the multi-word line, where the first quantity is the number of page layers of each word line, and the second quantity is the number of planes involved in the parallel storage operation of the word lines; Constructing a first matrix, a second matrix, and a third matrix according to the first quantity and the second quantity; Obtaining an offset snapshot according to the first matrix, the second matrix, and the third matrix; where the first matrix is used to record the pages with allocable physical block addresses by using the diagonal; The second matrix is used to shift the allocation order of the pages; The third matrix is used to accumulate the number of pages with allocable physical block addresses.

[0053] Specifically, the first quantity represents the number of page layers of each word line, that is, the number of Pages in each word line. For example, Figure 1 WL0 has 4 Pages, and the first quantity is 4; The second quantity is the number of planes involved in the parallel storage operation of the word lines, that is, the number of Planes. For example, Figure 1 it has Plane0, Plane1, Plane2, Plane3, and the second quantity is 4.

[0054] In some embodiments, the number of rows of the first matrix is related to the first quantity, and the number of columns of the first matrix is related to the second quantity; The number of rows of the second matrix is related to the second quantity, and the number of columns of the second matrix is related to the second quantity; The number of rows of the third matrix is related to the first quantity, and the number of columns of the third matrix is related to the second quantity.

[0055] Here, according to the first quantity and the second quantity, a first matrix (denoted as A), a second matrix (denoted as T), and a third matrix (denoted as D) are designed; In one example, each word line in the multi-word line has 4 layers of Page and 4 planes. The corresponding first matrix (denoted as A), second matrix (denoted as T), and third matrix (denoted as D) are as follows:

[0056]

[0057]

[0058] In another example, each word line in the multi-word line has 4 layers of Page and 8 planes. The corresponding first matrix (denoted as A), second matrix (denoted as T), and third matrix (denoted as D) are as follows:

[0059]

[0060]

[0061] In some embodiments, obtaining the offset snapshot according to the first matrix, the second matrix, and the third matrix includes: Determining the total number of iterations according to the second quantity; Successively processing the sequential matrix according to the total number of iterations to obtain a target sequential matrix. Each processing includes: determining the product of the iteration number and the third matrix, adding the product to the first matrix to obtain a translation result; multiplying the translation result by the second matrix and adding it to the sequential matrix of the previous round; Determining the offset snapshot according to the target sequential matrix.

[0062] Specifically, in combination with the example where each word line has 4 layers of Page and 8 planes above, the initial value of U is A, and the target sequential matrix is calculated using the following formula:

[0063] where i is the iteration number, adjusted according to the actual situation of the second quantity. When i = 0, initialization is performed, and at this time U = A. Subsequently at this time, the calculation is performed as shown in the above formula; represents the product of the iteration number and the third matrix; It means that the product is added to the first matrix to obtain the translation result, that is, the first matrix (A) is translated using the second matrix (D).

[0064] Combining the above examples, for 4 layers of Pages and 4 Planes, the target order matrix U is calculated as follows:

[0065] For 4 layers of Pages and 8 Planes, the target order matrix U is calculated as follows:

[0066] In some embodiments, the target order matrix is used to indicate the planes corresponding to multiple physical block addresses, and the corresponding LSB, CSB, MSB, or TSB; Determining the offset snapshot according to the target order matrix includes: According to the target order matrix, determine the planes where multiple physical block addresses are located, and the LSB, CSB, MSB, or TSB where they are located; each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSB, CSB, MSB, or TSB of physical block addresses with adjacent allocation orders are different.

[0067] Here, the QLC solid-state drive adopts a four-level cell storage technology. The 4 Pages of each word line in the QLC granule are, from bottom to top: LSB (Least Significant Bit): This is the lowest bit of storage, representing the least influential part of the data.

[0068] CSB (Central Significant Bit): Between the LSB and the MSB, representing the middle significant bit. In the QLC granule, it represents the second page among the four pages, and the data part it affects is in the middle position.

[0069] MSB (Most Significant Bit): In the QLC granule, the MSB corresponds to the third page among the four pages, having a higher significant bit weight.

[0070] TSB (Top Significant Bit): The top bit in the QLC granule, representing the most important data bit. Among the four pages, the TSB is the top page, having the highest significant bit weight.

[0071] The planes of the physical block addresses in adjacent allocation orders are all different, indicating that when data is allocated in adjacent order, adjacent physical blocks (storage units) will be different in both plane and page. For example, the first physical block address and the second physical block address will not be located in the same Plane at the same time.

[0072] The LSB, CSB, MSB, or TSB of the physical block addresses in adjacent allocation orders are different, indicating that when physical block addresses are allocated in order, the storage bits (LSB, CSB, MSB, TSB) of the physical block addresses in adjacent allocation orders will also be different. For example, the first physical block address and the second physical block address will not be the same type of Page, that is, they will not be the same LSB, CSB, MSB, or TSB.

[0073] In some embodiments, allocating the physical block address corresponding to the logical block address of at least one data on each multi-word line by using the snapshot information includes: Allocating an index set to the multi-word line, the index set including indexes of at least one physical block address, and the indexes indicating the allocation order of the physical block addresses; Allocating the first physical block address corresponding to the first logical block address according to the index set, where the first logical block address is the logical block address of the starting data on the multi-word line; Allocating the second physical block address corresponding to the second logical block address according to the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot; the second logical block address is the logical block address of other data except the starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0074] Here, the index set includes multiple indexes. For example, for 4-layer Page and 4 Planes, 16 indexes can be correspondingly allocated and denoted as 0 - 15; for 4-layer Page and 8 Planes, 32 indexes can be correspondingly allocated and denoted as 0 - 31.

[0075] The indexes indicate the allocation order of the physical block addresses, and the physical block addresses are allocated in the allocation order. For example, the index set includes 0 - 15, and when allocating physical block addresses, the physical block addresses indexed as 0, 1... 15 are respectively indexed according to the index order.

[0076] For example, define the pba_offset_snapshot array variable, which represents the PBA offset snapshot and is used to record the offset of each physical block address index (Index) relative to the starting physical block address in the multi-word line.

[0077] Index refers to the position in an allocation sequence, and the corresponding PBA offset is the offset relative to the starting physical block address of the multi-word line. Assuming the starting physical block address is s_pba, the pba corresponding to the Index-th allocation sequence is pba = s_pba + pba_offset_snapshot[Index], where pba_offset_snapshot[Index] represents the PBA offset in the offset snapshot.

[0078] Take Figure 3 as an example. Figure 3 FIG. is a comparative schematic diagram of the allocation sequence of the MWL physical block address provided by an embodiment of the present disclosure; it is a Page distribution of a 4Plane, 4Page QLC type MWL, which is the smallest unit of the multi-Plane program commonly used in the industry. This figure assumes that each Page corresponds to a PBA (physical block address). Usually, the size of a QLC Page is 16KiB, and considering that QLC is often used in large-capacity storage scenarios, to reduce the DRAM resource cost, designers usually set the mapping granularity to be greater than or equal to 16KiB. Figure 3 In, the horizontal direction is the Plane increasing direction, corresponding to different blocks in different Planes; the vertical axis is the Page increasing direction, respectively representing the LSB, CSB, MSB, and TSB of the QLC. The numbers represent the allocation sequence of the PBA and the PBA index (Index).

[0079] Figure 3 The left side in is a schematic diagram of an example of the allocation sequence using the traditional allocation method. It can be seen that the allocation sequence is sequentially allocated according to the Page order of the MWL. Figure 3 The right side in is a schematic diagram of an example of the allocation sequence using the method provided by the embodiment of the present disclosure. It can be seen that the allocation sequence combines the Plane and the LSB, CSB, MSB, and TSB of the Page. The planes of the physical block addresses of adjacent allocation sequences (such as 0 and 1, 1 and 2, and so on) are different, and the LSB, CSB, MSB, or TSB of the physical block addresses of adjacent allocation sequences are different (for example, 0 and 1 are located in Page0 of Plane0 and Page1 of Plane1, respectively).

[0080] Take Figure 3 the right figure in as an example, which is generated according to the 4Page, 4Plane situation.

[0081] Correspondingly, when the host re-initiates the reading of LBA0, LBA1, LAB2, and LAB3, the PBA indexes Index12 - 15 are on different planes and different pages respectively. The left-side Index12 - 15 are concentrated on the high pages (TSB), which is likely to result in a relatively long error correction time. The right-side example avoids the situation of long error correction delay caused by data being concentrated on high pages during reading, thereby improving the reading performance and user experience.

[0082] In some embodiments, the method further includes: Querying whether the block where the physical block address is located is a bad block; If the block where the physical block address is located is a bad block, updating the index set to delete or skip the physical block addresses related to the bad block.

[0083] Here, if the block is a bad block, all physical block addresses in the block need to be processed, that is, deleting the physical block address indexes of all bad blocks in the index set.

[0084] In this way, subsequent data access will no longer attempt to write to or read from the bad block, which can avoid data loss or read failure caused by the bad block.

[0085] In some embodiments, the method further includes: Determining a mapping table according to the logical block address of each data and the physical block address in the solid-state storage unit, where the mapping table is used to record the mapping relationship between the logical block address and the physical block address of each data; Receiving a read request, querying the mapping table according to the logical block address carried in the read request, and determining the physical block address corresponding to the read request.

[0086] Here, each data has a logical block address, which is an abstract address assigned by the operating system or file system. The physical block position where the data is actually stored is provided by the solid-state drive. To ensure that data can be read correctly, the system maintains a mapping table to record the relationship between the logical block address and the physical block address.

[0087] In an actual read operation, after receiving a read request containing a logical block address, query the mapping table according to the logical block address to find the corresponding physical block address. Then, read the data from the corresponding physical block address.

[0088] In this way, the storage system can effectively manage data storage and access, hiding the complexity of the underlying hardware and enabling the application program to only focus on the management of logical addresses.

[0089] In some embodiments, the solid-state drive is a QLC solid-state drive. The QLC solid-state drive includes multiple planes, each plane includes multiple blocks, and each block includes multiple pages. The multiple pages include: LSB, CSB, MSB, and TSB; The physical block addresses in different regions include: The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0090] Here, the physical block addresses are allocated according to the error characteristics of different Pages (referring to LSB, CSB, MSB, and TSB) of QLC particles. While taking into account the Plane parallelism, it is ensured as much as possible that adjacent logical block addresses are on different types of Pages, thereby reducing the latency caused by read error correction and improving the user experience.

[0091] The method provided by the embodiments of the present disclosure solves the performance bottleneck problem that some data is concentrated and distributed in high pages (such as MSB and TSB) in QLC solid-state storage due to the ordinary address allocation method by allocating adjacent logical blocks to different physical regions and avoiding centralized storage in the high-page region. In this way, the storage system can evenly distribute the read and write loads, thereby effectively avoiding the overuse of hot spots, and significantly improving the read performance and system response speed.

[0092] First, by dispersing the storage of data, frequent access to the same high-page region is avoided, the pressure on a single region caused by high-frequency read and write operations is reduced, and the occurrence of performance bottlenecks is thus avoided. In this way, the system can achieve a higher parallel reading ability, improve the overall data reading speed, reduce the access latency, and make the user experience smoother when using the storage device.

[0093] Second, by evenly allocating data, the service life of the storage device can be effectively extended. Under the traditional storage allocation method, frequent read and write operations concentrated in certain regions will accelerate the wear of these regions. Especially in flash memory, due to the limited number of write cycles, excessive overwriting will cause the device to age prematurely. A reasonable allocation method can balance the loads of different regions, avoid excessive overwriting of certain regions, reduce the failure rate of the device, and thus extend the overall service life of the device.

[0094] In addition, by optimizing the allocation of data, the storage space is utilized more efficiently. The evenly distributed data reduces the waste of space in certain regions, improves the overall utilization rate of storage resources, and further optimizes the working efficiency of the storage device.

[0095] In summary, by avoiding the storage method that concentrates data in the high-page area, the performance bottleneck problem caused by high-frequency reading and writing is solved, and the effects of improving the reading performance, extending the service life of the device, and optimizing the storage space utilization are achieved.

[0096] Figure 4 FIG. is a schematic flow chart of a PBA allocation method for QLC solid-state storage provided by an embodiment of the present disclosure; as Figure 4 shown, the method is applied to a QLC solid-state drive, and the method includes: Step 401, initialize snapshot information; Here, the snapshot information includes: offset snapshot, Plane snapshot.

[0097] The offset snapshot is used to record the offset relationship between different physical block addresses, and the offset relationship refers to the relative position or difference between physical block addresses.

[0098] The Plane snapshot is used to record information related to the physical storage hierarchy, such as specific situations regarding storage area distribution and management.

[0099] Step 402, in response to a write request, set an index set, and set the starting Index to 0; Here, when a write request is received, use the snapshot information to allocate corresponding physical block addresses for the logical block addresses of at least one data carried by the write request. Specifically, set an index set, including multiple indexes, specifically indexes of physical block addresses, and each index can represent the allocation order of physical block addresses. Set the starting Index (index) to 0, as Figure 3 shown in the example, including 16 indexes from 0 to 15.

[0100] Step 403, determine whether the Index is less than the total number of Pages; if the Index is less than the total number of Pages, enter Step 404; otherwise, enter Step 406; Here, the total number of Pages is the total number of Pages that can be allocated. If the total number of Pages is less than or equal to the Index, it means that there are no more Pages available for allocation or the allocation has been completed.

[0101] Step 404, determine whether the block is valid. If it is valid, enter Step 405; otherwise, update Index = Index + 1 and enter Step 403; Here, determining whether the block is valid specifically refers to determining whether the block where the physical block address corresponding to the Index is located is valid (whether it is a bad block).

[0102] Step 405, allocate a physical block address and update the mapping table; Here, if the block where the physical block address corresponding to Index is located is valid, the corresponding physical block address is allocated, and the mapping relationship between the allocated physical block address and the corresponding logical block address is saved in the mapping table.

[0103] Step 406: Determine the physical block address allocation for each piece of data in the write request; Here, for each piece of data in the write request, adjacent logical block addresses are allocated to physical block addresses located in different regions. For example, the physical block addresses allocated to adjacent logical block addresses are in different planes, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0104] Through the above method, when writing data, adjacent logical block addresses are evenly allocated to physical block addresses located on different Planes and different types of Pages (specifically, on the four Pages of LSB, CSB, MSB, and TSB), so as to balance the read parallelism and avoid the situation of long error correction delay caused by data concentration on high pages during reading, thereby improving the reading performance and user experience.

[0105] Figure 5 A schematic structural diagram of a solid-state drive provided by an embodiment of the present disclosure; as Figure 5 shown, the solid-state drive includes: an IO command pre-processing unit, an FTL PBA allocation module, an IO command post-processing unit, and a flash memory (such as the QLC flash memory in the figure); Here, the IO command pre-processing unit is used to perform front-end processing of commands from the host and pre-processing of FTL, including: command parsing, buffer allocation, data transfer, etc.

[0106] Among them, the host can send IO commands to the solid-state drive through the IO interface. For example, the IO commands can include: Read commands, Write commands, etc. Command parsing means parsing these IO commands. During the parsing process, the FTL extracts the target logical block address (LBA) and data content from the IO command. Then, the FTL converts the logical address (LBA) into a physical address (PBA) according to the stored mapping table. For example, if the IO command is a Read command, the FTL checks whether the data has been stored in the QLC flash memory according to the LBA. If the IO command is a Write command, the FTL needs to ensure that the data can be effectively written into the QLC flash memory and allocate a suitable physical block position for the data.

[0107] Before performing a write operation, the FTL needs to allocate a buffer to temporarily store the data to be written. This is because the write operation of flash memory needs to follow specific rules. For example, when writing, the original data cannot be directly overwritten, and the data must be written to a new free area. Due to the write / erase cycle limit of flash memory, the FTL also considers the data validity and available space when allocating the buffer. If invalid data is found in the target storage area, the FTL will first migrate or clean up this invalid data to make room for new data. Buffer allocation also involves data persistence and sequential writing. The FTL will reasonably manage the storage location of data according to the internal structure of the SSD to optimize the write performance and extend the service life of flash memory.

[0108] Data migration refers to the process of moving data from one location to another in flash memory. This usually occurs when writing new data, especially when the data at the original location needs to be updated or replaced. The FTL will select a suitable location for data writing according to the requirements. When writing new data, the FTL will migrate the original data to a new location and then store the new data at the target location. Data migration should occur during small-granularity writing. For example, if the mapping granularity of flash memory is 16 KiB, when a 4 KiB needs to be updated, the remaining 12 KiB and the 4 KiB for storing the updated data need to be combined into a new 16 KiB and then written to a new physical block address. At this time, the 12 KiB of data has undergone data migration.

[0109] Here, the FTL PBA allocation module includes: A snapshot calculation unit, which is used to calculate the offset snapshot and Plane snapshot during firmware initialization and store the snapshot calculation results in the snapshot storage unit; A snapshot storage unit, which is used to store the above snapshot calculation results; A PBA allocation unit, which is used to allocate the PBA of the MWL one by one according to the snapshot information.

[0110] Here, the IO command post-processing unit is used to perform post-processing and backend processing of the FTL on the IO command, including PBA information configuration, programming message configuration, etc., and send the programming message to the flash memory to complete the processing of a write command issued by the host. That is, the write operation request sent by the host has been correctly processed and written to the QLC flash memory.

[0111] Among them, in the SSD, IO commands (such as read and write commands) will first be issued by the host and enter the solid-state drive.

[0112] Post-processing means that after the FTL processes the IO command, further operations are performed. For example, after determining the mapping relationship between the logical block address and the physical block address, the management of the free blocks corresponding to the physical block address, garbage collection, etc. are carried out.

[0113] Backend processing refers to operations performed inside the flash memory chip, such as data writing, data erasing, etc. Backend processing usually involves interaction with hardware to ensure that data can be correctly written into the flash memory.

[0114] Specifically, PBA information configuration refers to associating a logical block address with an actual physical block address according to the mapping relationship between the logical block address and the physical block address.

[0115] In a flash memory, a write operation is actually a programming operation, which refers to storing data into the flash memory. Programming message configuration refers to configuring relevant parameters required for the programming operation, such as the data block to be written, the starting address of the data, etc.

[0116] Sending the programming message to the flash memory means that when writing data into the flash memory, sending relevant programming information into the flash memory so as to perform the write operation.

[0117] Figure 6 Schematic diagram of a structure of an address allocation device provided for an embodiment of the present disclosure; as Figure 6 shown, the device is applied to a solid-state drive, and the device includes: An acquisition module, configured to acquire snapshot information in response to a write request; A processing module, configured to allocate physical block addresses corresponding to logical block addresses of at least one data according to a mapping rule by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses located in different regions for adjacent logical block addresses.

[0118] In some embodiments, the device further includes: a generation module, configured to generate snapshot information, and the snapshot information includes: an offset snapshot; the offset snapshot is used to record the offset relationship between physical block addresses.

[0119] In some embodiments, the processing module is configured to allocate physical block addresses corresponding to logical block addresses of at least one data on each multi-word line by using the snapshot information.

[0120] In some embodiments, the generation module is configured to acquire a first quantity and a second quantity of multi-word lines, where the first quantity is the number of page layers each word line has, and the second quantity is the number of planes involved in the parallel storage operation of the word lines; Construct a first matrix, a second matrix, and a third matrix according to the first quantity and the second quantity; Obtain an offset snapshot according to the first matrix, the second matrix, and the third matrix; wherein, the first matrix is used to record, by using the diagonal line, the pages of physical block addresses that can be allocated; The second matrix is used to translate the allocation order of the pages; The third matrix is used to accumulate the number of pages of the assignable physical block addresses.

[0121] In some embodiments, the number of rows of the first matrix is related to the first quantity, and the number of columns of the first matrix is related to the second quantity; The number of rows of the second matrix is related to the second quantity, and the number of columns of the second matrix is related to the second quantity; The number of rows of the third matrix is related to the first quantity, and the number of columns of the third matrix is related to the second quantity.

[0122] In some embodiments, the generating module is configured to determine the total number of iterations according to the second quantity; Process the sequential matrix successively according to the total number of iterations to obtain a target sequential matrix. Each process includes: determining the product of the number of iterations and the third matrix, adding the product to the first matrix to obtain a translation result; multiplying the translation result by the second matrix and adding it to the sequential matrix of the previous round; Determine the offset snapshot according to the target sequential matrix.

[0123] In some embodiments, the target sequential matrix is used to indicate the planes corresponding to multiple physical block addresses, and the corresponding LSB, CSB, MSB or TSB; The generating module is configured to determine the planes where multiple physical block addresses are located, and the LSB, CSB, MSB or TSB where they are located according to the target sequential matrix; each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSB, CSB, MSB or TSB of physical block addresses with adjacent allocation orders are different.

[0124] In some embodiments, each data on the multi-word line corresponds to a logical block address with an index; The processing module is configured to allocate an index set to the multi-word line. The index set includes indexes of at least one physical block address, and the index represents the allocation order of the physical block address; Allocate the first physical block address corresponding to the first logical block address according to the index set. The first logical block address is the logical block address of the starting data on the multi-word line; Allocate the second physical block address corresponding to the second logical block address according to the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot; the second logical block address is the logical block address of other data except the starting data on the multi-word line; the index of the first physical block address takes precedence over the index of the second physical block address.

[0125] In some embodiments, the processing module is further configured to query whether the block where the physical block address is located is a bad block; If the block where the physical block address is located is a bad block, update the index set to delete or skip the physical block addresses related to the bad block.

[0126] In some embodiments, the processing module is further configured to determine a mapping table according to the logical block address of each piece of data and the physical block address in the solid-state storage unit, where the mapping table is used to record the mapping relationship between the logical block address and the physical block address of each piece of data; Receive a read request, query the mapping table according to the logical block address carried in the read request, and determine the physical block address corresponding to the read request.

[0127] In some embodiments, the solid-state drive is a QLC solid-state drive, the QLC solid-state drive includes a plurality of planes, each plane includes a plurality of blocks, each block includes a plurality of pages, and the plurality of pages include: LSB, CSB, MSB, TSB; The physical block addresses in different regions include: The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

[0128] It can be understood that when implementing the corresponding address allocation method, the address allocation device provided in the above embodiments can, as needed, allocate the above processing to different program modules to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the embodiments of the corresponding method belong to the same concept, and the specific implementation process can be seen in the method embodiments and will not be repeated here.

[0129] An embodiment of the present application provides a computer program product or a computer program, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the address allocation method.

[0130] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, where the executable instructions are stored, and when the executable instructions are executed by a processor, the processor will be caused to execute the address allocation method provided in the embodiments of the present application.

[0131] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0132] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as a stand-alone program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0133] As an example, the executable instructions may or may not correspond to a file in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program in question, or, stored in multiple cooperating files (e.g., files that store one or more modules, subroutines, or portions of code).

[0134] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one site, or, on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0135] Figure 7 Schematic diagram of a structure of an electronic device provided for an embodiment of the present disclosure; as Figure 7 shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform: In response to a write request, obtain snapshot information; according to a mapping rule, use the snapshot information to allocate physical block addresses corresponding to at least one logical block address of data; wherein, the snapshot information is used to allocate physical block addresses located in different regions to adjacent logical block addresses.

[0136] The electronic device may be a solid-state drive, and the processor may be a controller of the solid-state drive, and this controller performs physical block address allocation based on an address allocation method.

[0137] The electronic device provided in the above embodiment and the embodiment of the corresponding address allocation method belong to the same concept. For the specific implementation process, refer to the method embodiment, which will not be elaborated here.

[0138] In actual application, the electronic device 70 may further include: at least one network interface 703. Each component in the electronic device 70 is coupled together through a bus system 704. It can be understood that the bus system 704 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 7 all kinds of buses are labeled as the bus system 704. Among them, the number of the processors 701 can be at least one, and the number of the memories 702 can be at least one. The network interface 703 is used for the communication between the electronic device 70 and other devices in a wired or wireless manner.

[0139] The memory 702 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 70.

[0140] The method disclosed in the above embodiments of the present disclosure can be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip with the ability to process signals. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 701 or the instructions in the form of software. The above-mentioned processor 701 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 701 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by the hardware decoding processor, or executed and completed by the combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 702. The processor 701 reads the information in the memory 702 and combines its hardware to complete the steps of the foregoing address allocation method.

[0141] In some embodiments, the electronic device 70 may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components, and is used to execute the foregoing method.

[0142] It should be understood that the various forms of the processes shown above may be used, and steps may be reordered, added, or deleted. For example, the steps described in this disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and no limitation is imposed herein.

[0143] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0144] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those skilled in the technical field to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0145] It should be understood that in the various embodiments of this disclosure, the magnitude of the serial numbers of the various implementation processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this disclosure.

[0146] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise specifically defined.

[0147] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims described above.

Claims

1. An address allocation method, characterized in that, The method is applied to a solid state drive, and the method includes: In response to a write request, obtaining snapshot information; According to a mapping rule, using the snapshot information to allocate physical block addresses corresponding to logical block addresses of at least one piece of data; wherein, the snapshot information is used to allocate physical block addresses located in different regions to adjacent logical block addresses.

2. The method according to claim 1, characterized in that, The method further includes: Generating snapshot information, where the snapshot information includes: an offset snapshot; the offset snapshot is used to record the offset relationship between physical block addresses.

3. The method according to claim 1, characterized in that, The using the snapshot information to allocate physical block addresses corresponding to logical block addresses of at least one piece of data includes: Using the snapshot information to allocate physical block addresses corresponding to logical block addresses of at least one piece of data on each multi-word line.

4. The method according to claim 2, characterized in that, Generating the offset snapshot includes: Obtaining a first quantity and a second quantity of multi-word lines, where the first quantity is the number of page layers each word line has, and the second quantity is the number of planes involved in the parallel storage operation of the word lines; Constructing a first matrix, a second matrix, and a third matrix according to the first quantity and the second quantity; Obtaining an offset snapshot according to the first matrix, the second matrix, and the third matrix; Wherein, the first matrix is used to record the pages of physical block addresses that can be allocated using the diagonal; The second matrix is used to translate the allocation order of the pages; The third matrix is used to accumulate the number of pages of physical block addresses that can be allocated.

5. The method according to claim 4, characterized in that, The number of rows of the first matrix is related to the first quantity, and the number of columns of the first matrix is related to the second quantity; The number of rows of the second matrix is related to the second quantity, and the number of columns of the second matrix is related to the second quantity; The number of rows of the third matrix is related to the first quantity, and the number of columns of the third matrix is related to the second quantity.

6. The method according to claim 4, characterized in that, The obtaining an offset snapshot according to the first matrix, the second matrix, and the third matrix includes: Determining the total number of iterations according to the second quantity; Successively processing an order matrix according to the total number of iterations to obtain a target order matrix, and each processing includes: determining the product of the number of iterations and the third matrix, adding the product to the first matrix to obtain a translation result; multiplying the translation result by the second matrix and adding it to the order matrix of the previous round; Determining the offset snapshot according to the target order matrix.

7. The method according to claim 6, characterized in that, The target order matrix is used to indicate the planes corresponding to multiple physical block addresses, and the corresponding least significant bit LSB, middle significant bit CSB, most significant bit MSB, or top significant bit TSB; Determining the offset snapshot according to the target order matrix includes: According to the target order matrix, determining the planes where multiple physical block addresses are located, and the LSB, CSB, MSB, or TSB where they are located; each physical block address corresponds to an allocation order, and the planes of physical block addresses with adjacent allocation orders are different, and the LSB, CSB, MSB, or TSB of physical block addresses with adjacent allocation orders are different.

8. The method according to claim 3, characterized in that, Using the snapshot information to allocate physical block addresses corresponding to logical block addresses of at least one piece of data on each multi-word line includes: Assign an index set to the multi-word lines, the index set including indexes of at least one physical block address, the indexes characterizing the allocation order of the physical block addresses; Allocate a first physical block address corresponding to a first logical block address according to the index set, the first logical block address being the logical block address of the starting data on the multi-word lines; Allocate a second physical block address corresponding to a second logical block address according to the physical block address corresponding to the first logical block address, the difference between the first physical block address and the second physical block address, and the offset snapshot; the second logical block address being the logical block address of other data except the starting data on the multi-word lines; the index of the first physical block address has priority over the index of the second physical block address.

9. The method according to claim 8, characterized in that, The method further includes: Query whether the block where the physical block address is located is a bad block; If the block where the physical block address is located is a bad block, update the index set to delete or skip the physical block addresses related to the bad block.

10. The method according to claim 1, wherein The method further includes: Determine a mapping table according to the logical block address of each data and the physical block address in the solid-state storage unit, the mapping table being used to record the mapping relationship between the logical block address and the physical block address of each data; Receive a read request, query the mapping table according to the logical block address carried in the read request, and determine the physical block address corresponding to the read request.

11. The method according to claim 1, wherein The solid-state drive is a four-bit storage unit QLC solid-state drive, the QLC solid-state drive includes multiple planes, each plane includes multiple blocks, each block includes multiple pages, and the multiple pages include: LSB, CSB, MSB, TSB; The physical block addresses in different regions include: The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

12. An address allocation device, wherein The device is applied to a solid-state drive, and the device includes: An acquisition module, configured to acquire snapshot information in response to a write request; A processing module, configured to allocate physical block addresses corresponding to logical block addresses of at least one data according to mapping rules by using the snapshot information; wherein, the snapshot information is used to allocate physical block addresses located in different regions to adjacent logical block addresses.

13. The device according to claim 12, wherein The solid-state drive is a QLC solid-state drive, the QLC solid-state drive includes multiple planes, each plane includes multiple blocks, each block includes multiple pages, and the multiple pages include: LSB, CSB, MSB, TSB; The physical block addresses in different regions include: The planes of the physical block addresses are different, and the LSB, CSB, MSB, or TSB of the physical block addresses are different.

14. An electronic device, wherein Includes: At least one processor; And a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein The computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 11.

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