Communication method and device for OSPI and double four-wire off-chip memories
Through the OSPI module, the communication with two four-wire off-chip memory is solved by using the method of copying instructions and addresses, and the problem of low speed and space limitations when the chip communicates with four-wire off-chip memory is solved, achieving more efficient communication and a wider range of application scenarios.
Patent Information
- Application Number
- CN202311762474.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2025-06-20
AI Technical Summary
When the chip communicates with four-wire off-chip memory, there are problems such as low communication rate and limited storage space.
Communication with two four-wire off-chip memory through the OSPI module, using the method of copying instructions and addresses, the original and copy data are sent through two sets of four pins respectively to improve communication efficiency.
It improves the communication rate of the chip and the utilization of external storage space, and expands the application scenarios and reduces the communication cost compared with a single four-wire off-chip memory communication.
Smart Images
Figure CN120179593A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip processing technology, and in particular, to a communication method and device between an OSPI and a dual four-wire external memory. Background Art
[0002] XSPI (Serial Peripheral Interface) can be configured into single-line (Standard SPI), dual-line (Dual SPI), four-line (Quard SPI), and eight-line (Octal SPI) modes. When configured into the Octal SPI mode, the OSPI can parallel-transmit 8-bit data within one SCK (Continuous Serial Clock) cycle, greatly improving the data transmission efficiency. When the XSPI module of the chip is configured into the eight-line (Octal SPI) mode, the chip can achieve high-speed communication with an external eight-line memory through the OSPI interface.
[0003] In practical applications, compared with eight-line memories, four-wire external memories are more widely used, cheaper in cost, and more favored by users. However, when the chip communicates with a four-wire external memory through the XSPI module, there are problems of low communication rate and limited storage space. Summary of the Invention
[0004] In view of the above problems in the prior art, this application provides a communication solution between an OSPI and a dual four-wire external memory, which can improve the communication rate of the chip and the utilization rate of the external storage space while saving communication costs.
[0005] According to the first aspect of this application, a communication method between an OSPI and a dual four-wire external memory is provided, characterized in that the first group of four pins and the second group of four pins in the OSPI are respectively connected to the dual four-wire external memory, and the method includes:
[0006] According to a configuration instruction, determine a first working mode of the OSPI and a second working mode of the dual four-wire external memory, wherein the first working mode corresponds to the second working mode;
[0007] Corresponding to the first working mode, copy the original instruction and the original address to be sent by a specified pin in the first group of four pins to obtain a copied instruction and a copied address;
[0008] Indicate to send the original instruction and the original address through the specified pin in the first group of four pins;
[0009] Indicate to send the copied instruction and the copied address through the specified pin in the second group of four pins; and
[0010] Instruct the dual quad SPI external memory to receive the original instruction, the original address, the copy instruction, and the copy address according to the second working mode.
[0011] According to a second aspect of the present application, there is provided a communication device between an OSPI and a dual quad SPI external memory, characterized in that the first group of four pins and the second group of four pins in the OSPI are respectively connected to the dual quad SPI external memory, and the device includes:
[0012] A mode determination module, configured to determine a first working mode of the OSPI and a second working mode of the dual quad SPI external memory according to a configuration instruction, wherein the first working mode corresponds to the second working mode;
[0013] A copy module, configured to copy the original instruction and the original address to be sent by a specified pin in the first group of four pins corresponding to the first working mode to obtain a copy instruction and a copy address;
[0014] A first indication sending module, configured to indicate to send the original instruction and the original address through a specified pin in the first group of four pins;
[0015] A second indication sending module, configured to indicate to send the copy instruction and the copy address through a specified pin in the second group of four pins; and
[0016] An indication receiving module, configured to instruct the dual quad SPI external memory to receive the original instruction, the original address, the copy instruction, and the copy address according to the second working mode.
[0017] According to a third aspect of the present application, there is provided an electronic device, including:
[0018] A processor; and
[0019] A memory storing computer instructions, which, when executed by the processor, cause the processor to execute the method described in the first aspect.
[0020] According to a fourth aspect of the present application, there is provided a non-transitory computer storage medium storing a computer program, which, when executed by a plurality of processors, causes the processors to execute the method described in the first aspect.
[0021] According to the communication method and device between the OSPI and the dual four-wire external memory provided by the present application, the chip communicates with two four-wire external memories through the OSPI module, and can simultaneously send instructions, addresses, and data to the two four-wire external memories. Compared with the communication with a single four-wire external memory, the communication rate of the chip and the utilization rate of the external storage space are improved; compared with the communication with an eight-wire external memory, the four-wire external memory adopted is more widely used and cheaper in cost, so the application scenario of the proposed solution is wider and the communication cost is lower. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exceeding the scope claimed by the present application.
[0023] Figure 1 FIG. is a schematic diagram of the OSPI communicating with two four-wire external memories simultaneously according to an embodiment of the present application.
[0024] Figure 2 FIG. is a flowchart of the communication method between the OSPI and the dual four-wire external memory according to an embodiment of the present application.
[0025] Figure 3 FIG. is a timing diagram of the OSPI output in the instruction single-line address single-line mode according to an embodiment of the present application.
[0026] Figure 4 FIG. is a timing diagram of the OSPI output in the instruction single-line address eight-line mode according to an embodiment of the present application.
[0027] Figure 5 FIG. is a timing diagram of the OSPI output in the instruction eight-line address eight-line mode according to an embodiment of the present application.
[0028] Figure 6 FIG. is a schematic diagram of the communication device between the OSPI and the dual four-wire external memory according to an embodiment of the present application.
[0029] Figure 7 FIG. is a structural diagram of an electronic device provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.
[0031] Figure 1 is a schematic diagram of an OSPI in an embodiment of the present application communicating with two four-wire external memories simultaneously. As Figure 1 shown, the XSPI module of the chip is configured in an Octal SPI mode, and the XSPI module is the OSPI module. Eight pins in the OSPI module are configured to communicate with two four-wire external memories. In the specific implementation process, the selected eight pins are connected to the corresponding pins of the two four-wire external memories. Among the eight selected pins in the OSPI module, they are divided into two groups, including the first group of four pins and the second group of four pins. As Figure 1 shown, the first group of four pins includes IO0 - IO3, and the second group of four pins includes IO4 - IO7. The two four-wire external memories are external memory - 1 and external memory - 2. The pins IO0 - IO3 are connected to external memory - 1, and the pins IO4 - IO7 are connected to external memory - 2. As Figure 1 shown, the communication between the OSPI and the two four-wire external memories includes 4 stages. The present application focuses on the instruction stage and the address stage in the communication.
[0032] Next, the process of the OSPI communicating with two four-wire external memories simultaneously will be described. Figure 2 is a flowchart of a communication method between an OSPI and a dual four-wire external memory according to an embodiment of the present application. As Figure 2 shown, the method includes the following steps.
[0033] Step S201, according to the configuration instruction, determine the first working mode of the OSPI and the second working mode of the dual four-wire external memories, where the first working mode and the second working mode correspond to each other.
[0034] Before the OSPI starts communicating with the two four-wire external memories, it is necessary to configure the working modes of the OSPI and the two four-wire external memories respectively. In the actual operation process, the user can configure the working modes of the OSPI and the two four-wire external memories through the configuration instruction. The configured working mode of the OSPI needs to match the working modes of the two four-wire external memories to ensure normal communication between both sides.
[0035] According to some embodiments, the four-wire off-chip memory can be configured into the following three modes: (1) Instruction single-wire, address single-wire: That is, off-chip memory-1 and off-chip memory-2 receive instructions and addresses through the pins for sending instructions and addresses in the OSPI. For example, off-chip memory-1 receives instructions and addresses through the IO0 pin; off-chip memory-2 receives instructions and addresses through the IO4 pin; (2) Instruction single-wire, address four-wire: That is, off-chip memory-1 receives instructions through the pin for sending instructions in the OSPI (such as the IO0 pin), and receives addresses through the first group of four pins IO0-IO3; off-chip memory-2 receives instructions through the pin for sending instructions in the OSPI (such as the IO4 pin), and receives addresses through the second group of four pins IO4-IO7; (3) Instruction four-wire, address four-wire: That is, off-chip memory-1 receives instructions and addresses through the first group of four pins IO0-IO3; off-chip memory-2 receives instructions and addresses through the second group of four pins IO4-IO7.
[0036] When the four-wire off-chip memory is configured into (1) instruction single-wire, address single-wire, the OSPI needs to be configured as the host and eight-wire mode, and both the instruction and the address are sent in the single-wire mode. For example, both the instruction and the address are output through IO0; when the four-wire off-chip memory is configured into (2) instruction single-wire, address four-wire, the OSPI needs to be configured as the host and eight-wire mode, and the instruction is configured in the single-wire mode (for example, the instruction is output through IO0), and the address is configured in the eight-wire mode (the address is output through IO0-IO7); when the four-wire off-chip memory is configured into (3) instruction four-wire, address four-wire, the OSPI needs to be configured as the host and eight-wire mode, and both the instruction and the address are configured in the eight-wire mode (both the instruction and the address are output through IO0-IO7).
[0037] Step S202, corresponding to the first working mode, copy the original instruction and the original address to be sent by the specified pin among the first group of four pins to obtain a copied instruction and a copied address;
[0038] Step S203, instruct to send the original instruction and the original address through the specified pin among the first group of four pins;
[0039] Step S204, instruct to send the copied instruction and the copied address through the specified pin among the second group of four pins; and
[0040] Step S205, instruct the pins specified by the second working mode to receive the original instruction and the original address and the copied instruction and the copied address.
[0041] According to some embodiments, in the OSPI instruction single-line address single-line mode, before the communication starts, turn on the dual four-line mode enable switch. If the pin for sending the instruction and the address is a specified pin among the first group of four pins, for example, IO0, during the stage of sending the instruction and the address (i.e., Figure 1 the stage-1 and stage-2 in Figure 1 ), copy the original instruction and the original address to be sent by the IO0 pin to obtain a copied instruction and a copied address, and send the copied instruction and the copied address through a specified pin among the second group of four pins (for example, IO4). The off-chip memory-1 and the off-chip memory-2 receive the instruction and the address through the pins corresponding to the IO0 pin and the IO4 pin respectively. In this way
[0042] the off-chip memory-1 and the off-chip memory-2 in
[0043] can receive the instruction and the address synchronously, and the received instruction and address are exactly the same.
[0043] According to some embodiments, in the case where both of the two four-line off-chip memories are configured in the instruction single-line address single-line mode, if write operations are performed on the off-chip memory-1 and the off-chip memory-2 simultaneously, and the write instructions of the off-chip memory-1 and the off-chip memory-2 are both 0x32, the write addresses are both 0x5f, and the write data are both 0xe5, then the timing diagram output by the OSPI when the two four-line off-chip memories are configured as instruction single-line and address single-line is as Figure 3 shown.
[0044] According to some embodiments, in the OSPI instruction single-line address eight-line mode, before the communication starts, turn on the dual four-line mode enable switch. If the pin for sending the instruction is a specified pin among the first group of four pins, for example, IO0, during the stage of sending the instruction (i.e., Figure 1 the stage-1 in Figure 1 ), copy the original instruction to be sent by the IO0 pin to obtain a copied instruction, and send the copied instruction through a specified pin among the second group of four pins (for example, IO4). During the stage of sending the address (i.e., Figure 1 the stage-2 in
[0045] ), the address needs to be extended, and the extension method is as follows:
[0045] Assume that the address for the read / write operations on off-chip memory - 1 and off-chip memory - 2 simultaneously is addr[n:0] (the address valid bit width is (n + 1) bits). Then, the read / write operation address sent by the bus to the OSPI is still addr[n:0], and the address valid length ADDR_L of the OSPI is still configured by software to be (n + 1) bits. At this time, the bit width of the read / write operation address addr[n:0] needs to be hardware-expanded from (n + 1) bits to 2*(n + 1) bits. If the extended address is addr_extend[(2*n + 1):0], then:
[0046] addr_extend[(2*n + 1):0] =
[0047] {{2{addr[n:n - 3]}},{2{addr[n - 4:n - 7]}},……{2{addr[3:0]}}}。
[0048] Thus, step S202 may specifically include:
[0049] Copy the original instruction to be sent by the first designated pin among the first group of four pins to obtain a copied instruction; and
[0050] Expand the original address to be sent by the first group of four pins in sequence according to the length of the off-chip memory address valid bit width to obtain a copied address.
[0051] Step S203 may specifically include: sending the original instruction through the first designated pin among the first group of four pins; and sending the original address through the first group of four pins.
[0052] Step S204 may specifically include: sending the copied instruction through the second designated pin among the second group of four pins; and sending the copied address through the second group of four pins.
[0053] Step S205 may specifically include: instructing the pins corresponding to the first designated pin and the second designated pin in the dual four-wire off-chip memory to receive the original instruction and the copied instruction; and instructing the pins corresponding to the first group of four pins and the second group of four pins in the dual four-wire off-chip memory to receive the original address and the copied address.
[0054] According to some embodiments, when both of the two four-wire off-chip memories are configured in the instruction single-wire address four-wire mode, if write operations are simultaneously performed on off-chip memory - 1 and off-chip memory - 2, and the write operation addresses of off-chip memory - 1 and off-chip memory - 2 are both 0x5f (the address valid bit width is 8 bits), then the write operation address sent by the bus to the OSPI is still 0x5f, and the address valid length ADDR_L of the OSPI is still configured by software to be 8 bits. At this time, the write operation address 0x5f needs to be hardware-expanded to 0x55ff (the actual valid length of the address is also hardware-expanded by a factor of two). In this way, off-chip memory - 1 and off-chip memory - 2 need two SCK clocks to receive the write address, and the received addresses are both 0x5f. Assuming that the write instructions of off-chip memory - 1 and off-chip memory - 2 are both 0x32 and the write data are both 0xe5, then when the two four-wire off-chip memories are configured in the instruction single-wire address four-wire mode and the OSPI is configured in the instruction single-wire address eight-wire mode, the output timing of the OSPI is as Figure 4 shown.
[0055] According to some embodiments, in the OSPI instruction eight-wire address eight-wire mode, for example, the instructions and addresses are both output through the Figure 1 pin IO0 - IO7. Before the communication starts, the dual four-wire mode enable switch is turned on. During the instruction sending stage (i.e., stage - 1 in Figure 1 ), the instructions need to be extended. During the address sending stage (i.e., stage - 2 in Figure 1 ), the addresses need to be extended. Among them, the address extension method is the same as the extension method when the above four-wire off-chip memory is configured in the instruction single-wire and address four-wire mode, which will not be elaborated here.
[0056] According to some embodiments, the instruction extension method is as follows:
[0057] Assume that the instructions for simultaneously performing read / write operations on off-chip memory - 1 and off-chip memory - 2 are inst[m:0] (the instruction valid bit width is (m + 1) bits). Then the read / write operation instructions sent by the bus to the XSPI are still inst[m:0], and the instruction valid length INST_L of the XSPI is still configured by software to be (m + 1) bits. At this time, the bit width of the read / write operation instruction inst[m:0] needs to be hardware-expanded from (m + 1) bits to 2*(m + 1) bits.
[0058] If the extended instruction is inst_extend[(2*m + 1):0], then:
[0059] inst_extend[(2*m + 1):0] =
[0060] {{2{inst[m:m - 3]}}, {2{inst[m - 4:m - 7]}}, …… {2{inst[3:0]}}}。
[0061] Thus, step S202 may specifically include:
[0062] Successively expand the original instruction to be sent by the first group of four pins according to the length of the instruction effective bit width of the off - chip memory to obtain a copied instruction; and
[0063] Successively expand the original address to be sent by the first group of four pins according to the length of the address effective bit width of the off - chip memory to obtain a copied address.
[0064] Step S203 may specifically include: sending the original instruction and the original address through the first group of four pins.
[0065] Step S204 may specifically include: sending the copied instruction and the copied address through the second group of four pins.
[0066] Step S205 may specifically include: instructing the pins corresponding to the first group of four pins and the second group of four pins in the dual - four - wire off - chip memory to receive the original instruction and the original address, as well as the copied instruction and the copied address.
[0067] According to some embodiments, when both of the two four - wire off - chip memories are configured in the instruction four - wire address four - wire mode, if write operations are simultaneously performed on off - chip memory - 1 and off - chip memory - 2, and the write operation instructions for both off - chip memory - 1 and off - chip memory - 2 are 0x32 (instruction effective bit width is 8 bit), and the write operation addresses are both 0x5f (address effective bit width is 8 bit), then the write operation instruction sent by the bus to XSPI is still 0x32, the sent write operation address is still 0x5f, and the instruction effective length INST_L and address effective length ADDR_L of XSPI are still configured by software to be 8 bit. At this time, the write operation instruction 0x32 needs to be hardware - extended to 0x3322 (the actual effective length of the instruction is also hardware - extended by a factor of two), and the write operation address 0x5f needs to be hardware - extended to 0x55ff (the actual effective length of the address is also hardware - extended by a factor of two). In this way, off - chip memory - 1 and off - chip memory - 2 need two SCK clocks to receive the write instruction, and the received instruction is 0x32 for both. They also need two SCK clocks to receive the write address, and the received address is 0x5f for both. Assuming that the data written to off - chip memory - 1 and off - chip memory - 2 is both 0xe5, then when the two four - wire off - chip memories are configured as instruction four - wire and address four - wire, the output timing of XSPI is as follows Figure 5 as shown.
[0068] Based on the above communication method between the OSPI and the dual-four-wire external memory, according to another aspect of the present application, there is provided a communication device between the OSPI and the dual-four-wire external memory, wherein the first group of four pins and the second group of four pins in the OSPI are respectively connected to the dual-four-wire external memory, as Figure 6 shown. The device includes: a mode determination module 601, a replication module 602, a first indication sending module 603, a second indication sending module 604, and an indication receiving module 605. Among them, the mode determination module 601 is configured to determine a first working mode of the OSPI and a second working mode of the dual-four-wire external memory according to a configuration instruction, wherein the first working mode corresponds to the second working mode; the replication module 602 is configured to, corresponding to the first working mode, replicate the original instruction and the original address to be sent by a specified pin among the first group of four pins to obtain a replicated instruction and a replicated address; the first indication sending module 603 is configured to indicate to send the original instruction and the original address through the specified pin among the first group of four pins; the second indication sending module 604 is configured to indicate to send the replicated instruction and the replicated address through the specified pin among the second group of four pins; the indication receiving module 605 is configured to indicate that the dual-four-wire external memory receives the original instruction and the original address and the replicated instruction and the replicated address according to the second working mode.
[0069] According to some embodiments, when the four-wire external memory is configured in an instruction single-line address single-line mode and the OSPI is configured in an instruction single-line address single-line mode, the indication receiving module 605 may specifically be configured to: indicate that the pins corresponding to the first specified pin and the second specified pin in the dual-four-wire external memory receive the original instruction and the original address and the replicated instruction and the replicated address.
[0070] According to some embodiments, when the four-wire external memory is configured in an instruction single-line address four-wire mode and the OSPI is configured in an instruction single-line address eight-wire mode:
[0071] The replication module 602 may specifically be configured to:
[0072] replicate the original instruction to be sent by the first specified pin among the first group of four pins to obtain a replicated instruction; and
[0073] extend the original address to be sent by the first group of four pins in sequence according to the length of the external memory address valid bit width to obtain a replicated address.
[0074] The first indication sending module 603 may specifically be configured to: send the original instruction through the first specified pin among the first group of four pins; and send the original address through the first group of four pins.
[0075] The second instruction sending module 604 may specifically be configured to: send the replication instruction through a second designated pin among the second group of four pins; and send the replication address through the second group of four pins.
[0076] The instruction receiving module 605 may specifically be configured to: instruct pins corresponding to the first designated pin and the second designated pin in the dual four-wire off-chip memory to receive the original instruction and the replication instruction respectively; and instruct pins corresponding to the first group of four pins and the second group of four pins in the dual four-wire off-chip memory to receive the original address and the replication address respectively.
[0077] According to some embodiments, when the four-wire off-chip memory is configured in an instruction four-wire address four-wire mode and the OSPI is configured in an instruction eight-wire address eight-wire mode:
[0078] The replication module 602 may specifically be configured to: expand the original instruction to be sent by the first group of four pins in sequence according to the length of the off-chip memory instruction effective bit width to obtain a replication instruction; and expand the original address to be sent by the first group of four pins in sequence according to the length of the off-chip memory address effective bit width to obtain a replication address.
[0079] The first instruction sending module 603 may specifically be configured to: send the original instruction and the original address through the first group of four pins.
[0080] The second instruction sending module 604 may specifically be configured to: send the replication instruction and the replication address through the second group of four pins.
[0081] The instruction receiving module 605 may specifically be configured to: instruct pins corresponding to the first group of four pins and the second group of four pins in the dual four-wire off-chip memory to receive the original instruction and the original address as well as the replication instruction and the replication address.
[0082] According to the communication method and apparatus between the OSPI and the dual four-wire off-chip memory provided by the present application, the chip communicates with two four-wire off-chip memories through the OSPI module, and can simultaneously send instructions, addresses, and data to the two four-wire off-chip memories. Compared with the communication with a single four-wire off-chip memory, the communication rate of the chip and the utilization rate of the external storage space are improved; compared with the communication with an eight-wire off-chip memory, the four-wire off-chip memory adopted has a wider application range and lower cost, so that the proposed solution has a wider application scenario and lower communication cost.
[0083] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.
[0084] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.
[0085] In several embodiments provided by this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the described units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be an electrical connection or other forms.
[0086] Refer to Figure 7 , Figure 7 An electronic device is provided, including a processor and a memory. The memory stores computer instructions. When the computer instructions are executed by the processor, the processor executes the computer instructions to implement the method and refinement scheme as Figure 2 shown.
[0087] It should be understood that the above device embodiments are only illustrative. The device disclosed in the present invention can also be implemented in other ways. For example, the division of the units / modules described in the above embodiments is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units, modules or components can be combined, or integrated into another system, or some features can be ignored or not executed.
[0088] In addition, without special instructions, in each embodiment of the present invention, each functional unit / module can be integrated in one unit / module, or each unit / module can exist physically alone, or two or more units / modules can be integrated together. The above integrated unit / module can be implemented in the form of hardware or in the form of a software program module.
[0089] When the integrated unit / module is implemented in the form of hardware, the hardware can be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the processor or chip can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the on-chip cache, off-chip memory, and memory can be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), flash memory (FLASH), etc.
[0090] When the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to enable a computer electronic device (which can be a personal computer, a server, or a network electronic device, etc.) to execute all or part of the steps of the methods described in various embodiments of this disclosure. The aforementioned memory includes: USB flash drives, read-only memory (ROM), random access memory (RAM), mobile hard disks, magnetic disks, or optical discs, etc., all kinds of media that can store program codes.
[0091] The embodiments of this application also provide a non-transitory computer storage medium storing a computer program. When the computer program is executed by multiple processors, it enables the processors to execute the Figure 2 method and refinement scheme as shown.
[0092] The above has introduced the embodiments of the present application in detail. Specific examples are used in this text to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, any changes or deformations made by those skilled in the art based on the idea of the present application, within the specific implementation manner and application scope of the present application, fall within the protection scope of the present application. In summary, the content of this specification should not be construed as a limitation to the present application.
Claims
1. A communication method between an OSPI and a dual quad external memory, characterized in that, The first group of four pins and the second group of four pins in the OSPI are respectively connected to the dual quad external memory, and the method includes: Determine a first operating mode of the OSPI and a second operating mode of the dual quad external memory according to a configuration instruction, wherein the first operating mode and the second operating mode correspond to each other; Corresponding to the first operating mode, copy the original instruction and the original address to be sent by a specified pin among the first group of four pins to obtain a copied instruction and a copied address; Indicate to send the original instruction and the original address through the specified pin among the first group of four pins; Indicate to send the copied instruction and the copied address through the specified pin among the second group of four pins; and Indicate that the dual quad external memory receives the original instruction, the original address, the copied instruction, and the copied address according to the second operating mode.
2. The method according to claim 1, characterized in that, The first operating mode is an instruction single-line address single-line mode, the second operating mode is an instruction single-line address single-line mode, the specified pin among the first group of four pins is a first specified pin, and the specified pin among the second group of four pins is a second specified pin; The indicating that the dual quad external memory receives the original instruction, the original address, the copied instruction, and the copied address according to the second operating mode includes: Indicate that the pins in the dual quad external memory corresponding to the first specified pin and the second specified pin respectively receive the original instruction, the original address, the copied instruction, and the copied address.
3. The method according to claim 1, characterized in that, The first operating mode is an instruction single-line address eight-line mode, and the second operating mode is an instruction single-line address four-line mode. The copying the original instruction and the original address to be sent by the specified pin among the first group of four pins to obtain a copied instruction and a copied address includes: Copy the original instruction to be sent by the first specified pin among the first group of four pins to obtain a copied instruction; and Expand the original address to be sent by the first group of four pins in sequence according to the length of the effective bit width of the external memory address to obtain a copied address.
4. The method according to claim 3, characterized in that, The indicating to send the original instruction and the original address through the specified pin among the first group of four pins includes: Send the original instruction through the first specified pin among the first group of four pins; and Send the original address through the first group of four pins. And, the indicating to send the copied instruction and the copied address through the specified pin among the second group of four pins includes: Send the copied instruction through the second specified pin among the second group of four pins; and Send the copied address through the second group of four pins.
5. The method according to claim 4, characterized in that, The indicating that the dual quad external memory receives the original instruction, the original address, the copied instruction, and the copied address according to the second operating mode includes: Indicate that the pins in the dual quad external memory corresponding to the first specified pin and the second specified pin respectively receive the original instruction and the copied instruction; and Indicate that the pins corresponding to the first set of four pins and the second set of four pins in the dual four-wire external memory receive the original address and the replicated address respectively.
6. The method according to claim 1, characterized in that, The first working mode is the instruction eight-wire address eight-wire mode, and the second working mode is the instruction four-wire address four-wire mode. The replication of the original instruction and the original address to be sent by the specified pin among the first set of four pins includes: Successively expand the original instruction to be sent by the first set of four pins according to the length of the instruction valid bit width of the external memory to obtain a replicated instruction; and Successively expand the original address to be sent by the first set of four pins according to the length of the address valid bit width of the external memory to obtain a replicated address.
7. The method according to claim 6, characterized in that, The indication to send the original instruction and the original address through the specified pin among the first set of four pins includes: Send the original instruction and the original address through the first set of four pins; And, the indication to send the replicated instruction and the replicated address through the specified pin among the second set of four pins includes: Send the replicated instruction and the replicated address through the second set of four pins.
8. The method according to claim 7, characterized in that, The indication to the dual four-wire external memory to receive the original instruction and the original address and the replicated instruction and the replicated address according to the second working mode includes: Indicate that the pins corresponding to the first set of four pins and the second set of four pins in the dual four-wire external memory receive the original instruction and the original address and the replicated instruction and the replicated address.
9. A communication device between an OSPI and a dual-four-wire off-chip memory, characterized in that, The first set of four pins and the second set of four pins in the OSPI are respectively connected to the dual four-wire external memory. The device includes: A mode determination module for determining the first working mode of the OSPI and the second working mode of the dual four-wire external memory according to a configuration instruction, wherein the first working mode and the second working mode correspond to each other; A replication module for replicating the original instruction and the original address to be sent by the specified pin among the first set of four pins corresponding to the first working mode to obtain a replicated instruction and a replicated address; A first indication sending module for indicating to send the original instruction and the original address through the specified pin among the first set of four pins; A second indication sending module for indicating to send the replicated instruction and the replicated address through the specified pin among the second set of four pins; and An indication receiving module for indicating that the dual four-wire external memory receives the original instruction and the original address and the replicated instruction and the replicated address according to the second working mode.
10. An electronic device, characterized in that, It includes a memory and a processor. A computer program is stored on the memory. When the processor executes the computer program on the memory, the method according to any one of claims 1 to 8 is implemented.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.