Multi-chip system and inter-chip communication method for multi-chip system

Abstract

The present application relates to a multi-chip system and an inter-chip communication method for a multi-chip system. Based on the present application, the first on-chip logic circuit of the first chip and the second on-chip logic circuit of the second chip in the multi-chip system can reuse the existing GPIO interface of the chip to achieve inter-chip communication without the need to expand additional interfaces. In this case, the parameter configuration and status monitoring of the first on-chip logic circuit and the second on-chip logic circuit can be implemented by the first on-chip logic circuit based on inter-chip communication. Therefore, the second on-chip logic circuit of the second chip does not need to be equipped with a circuit structure for implementing parameter configuration and status monitoring. Thus, the circuit structure simplification of the second on-chip logic circuit can be supported without expanding additional interfaces, thereby helping to reduce the circuit area of ​​the on-chip logic circuit in the multi-chip system while taking into account the parameter configuration and status monitoring of the on-chip logic circuit of each chip in the multi-chip system.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a multi-chip system and an inter-chip communication method for the multi-chip system. Background Art

[0002] A multi-chip system can achieve the integration of chip processing capabilities by utilizing the collaborative work between chips. The collaborative work between chips includes data transmission between chips, and the data transmission between chips can be performed by the on-chip logic circuits of the chips.

[0003] Typically, a chip's on-chip logic circuits require parameter configuration and status monitoring. To this end, each chip's on-chip logic circuits typically integrate a software control unit (SCU) that runs a software program. The SCU then relies on the software program running within the SCU to perform parameter configuration and status monitoring. However, integrating a SCU into an on-chip logic circuit inevitably increases its circuit area. Therefore, integrating a SCU into every chip in a multi-chip system would conflict with the optimization goal of reducing circuit area.

[0004] As can be seen from the above, how to reduce the circuit area of ​​the on-chip logic circuit in a multi-chip system while taking into account the implementation of parameter configuration and status monitoring of the on-chip logic circuit of each chip in the multi-chip system has become a technical problem to be solved. Summary of the Invention

[0005] An embodiment of the present application provides a multi-chip system and an inter-chip communication method for a multi-chip system, which helps to reduce the circuit area of ​​the on-chip logic circuit in the multi-chip system while taking into account the parameter configuration and status monitoring of the on-chip logic circuit of each chip in the multi-chip system.

[0006] In one embodiment of the present application, a multi-chip system is provided, including a first chip, a second chip, and a storage medium;

[0007] The first chip has a first on-chip logic circuit;

[0008] The second chip has a second on-chip logic circuit;

[0009] The storage medium stores first circuit parameters for implementing parameter configuration on the first on-chip logic circuit and second circuit parameters for implementing parameter configuration on the second on-chip logic circuit, and the parameter configuration implemented on the first on-chip logic circuit and the second on-chip logic circuit is used to implement data transmission between the first on-chip logic circuit and the second on-chip logic circuit via a transmission bus;

[0010] The first on-chip logic circuit and the second on-chip logic circuit both have GPIO interfaces, and a communication bus independent of the transmission bus is connected between the GPIO interfaces of the first on-chip logic circuit and the second on-chip logic circuit;

[0011] The first on-chip logic circuit is configured as follows:

[0012] loading the first circuit parameter and the second circuit parameter from the storage medium;

[0013] sending the second circuit parameter to the second on-chip logic circuit via the communication bus;

[0014] The status information of the second on-chip logic circuit during the data transmission period is monitored via the communication bus.

[0015] In some examples, optionally, the first on-chip logic circuit is further configured to: send a handshake signal to the second on-chip logic circuit via the communication bus in response to successful loading of the first circuit parameters and the second circuit parameters; and monitor a feedback signal generated by the second on-chip logic circuit in response to the handshake signal via the communication bus; wherein the sending of the second circuit parameters to the second on-chip logic circuit via the communication bus is triggered in response to successful monitoring of the feedback signal.

[0016] In some examples, optionally, the inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit through the communication bus includes: read and write operations of the first on-chip logic circuit and the second on-chip logic circuit through the communication bus; wherein, in the read and write operations, the write operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus is used to enable the first on-chip logic circuit to send the second circuit parameter to the second on-chip logic circuit; and, in the read and write operations, the read operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus is used to enable the first on-chip logic circuit to monitor the status information from the second on-chip logic circuit; and the handshake signal and the feedback signal multiplex the signal lines used by the read and write operations in the communication bus.

[0017] In some examples, optionally, the communication bus includes: a status configuration signal line, a first simplex signal line unidirectionally output from the first on-chip logic circuit to the second on-chip logic circuit, and a second simplex signal line unidirectionally output from the second on-chip logic circuit to the first on-chip logic circuit; the first on-chip logic circuit is specifically configured to: set the status configuration signal line to a default invalid state; and send the handshake signal to the second on-chip logic circuit through the first simplex signal line while the status configuration signal line is in the invalid state; wherein, the second on-chip logic circuit monitors the handshake signal sent by the first on-chip logic circuit through the first simplex signal line and generates the feedback signal to the first on-chip logic circuit through the second simplex signal line while the status configuration signal line is in the invalid state, and the first on-chip logic circuit monitors the feedback signal through the second simplex signal line; in response to successful monitoring of the feedback signal, the status configuration signal line is set to a valid state; wherein, the read and write operations are implemented through at least one of the first simplex signal line and the second simplex signal line while the status configuration signal line is in the valid state.

[0018] In some examples, optionally, the inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit implemented through the communication bus includes: read and write operations of the first on-chip logic circuit and the second on-chip logic circuit through the communication bus; wherein: the first on-chip logic circuit sends the second circuit parameter to the second on-chip logic circuit through the communication bus, which is implemented by the first on-chip logic circuit performing a write operation on the second on-chip logic circuit through the communication bus during the read and write operations; the first on-chip logic circuit monitors the status information from the second on-chip logic circuit through the communication bus, which is implemented by the first on-chip logic circuit performing a read operation on the second on-chip logic circuit through the communication bus during the read and write operations; the write operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus, and the read operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus, both include a communication verification operation step.

[0019] In some examples, optionally, the read and write operation process includes: the first on-chip logic circuit sends an operation request for the read and write operation to the second on-chip logic circuit through the communication bus; the first on-chip logic circuit sends an idle bit for the second on-chip logic circuit to prepare to respond to the read and write operation to the second on-chip logic circuit through the communication bus; the first on-chip logic circuit and the second on-chip logic circuit exchange operation data of the read and write operation through the communication bus, and the operation data includes the second circuit parameters sent from the first on-chip logic circuit to the second on-chip logic circuit, or the status information returned from the second on-chip logic circuit to the first on-chip logic circuit; wherein the verification object of the communication verification includes the operation request and the operation data, and any one of the operation request and the operation data is triggered to be retransmitted in response to a verification error of the communication verification.

[0020] In some examples, optionally, the operation request includes: target address information, used to indicate the address of the first on-chip logic circuit performing a write operation on the second on-chip logic circuit through the communication bus, or the address of the first on-chip logic circuit performing a read operation on the second on-chip logic circuit through the communication bus; operation enable information, used to indicate the operation type of the currently initiated read and write operation that is enabled; valid data length, used to characterize the data length of the operation data; the verification object of the communication verification includes the target address information, the operation enable information, the valid data length and the operation data, and any one of the target address information, the operation enable information, the valid data length and the operation data is triggered to be retransmitted in response to a verification error of the communication verification.

[0021] In some examples, optionally, the first on-chip logic circuit is further configured to determine its role in the inter-chip communication based on the communication bus according to its own hardware configuration before obtaining the first circuit parameters; the second on-chip logic circuit is further configured to determine its role in the inter-chip communication based on the communication bus according to its own hardware configuration before obtaining the second circuit parameters; wherein, the first on-chip logic circuit loads the first circuit parameters and the second circuit parameters from the storage medium, sends the second circuit parameters to the second on-chip logic circuit through the communication bus, and monitors the status information of the second on-chip logic circuit, because its role in the inter-chip communication based on the communication bus is determined to be a master device and is enabled; because the role of the second on-chip logic circuit in the inter-chip communication based on the communication bus is determined to be a slave device, the second on-chip logic circuit determines the way to obtain the second circuit parameters as receiving from the first on-chip logic circuit through the communication bus and providing the status information for monitoring by the first on-chip logic circuit.

[0022] In some examples, optionally, the bus rate of the transmission bus is higher than the bus rate of the communication bus.

[0023] In some examples, optionally, the communication bus is configured as an SPI bus that supports inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit based on the SPI protocol.

[0024] In some examples, optionally, the first chip and the second chip are different packaged chips each having an independent physical package, or different dies independent of each other in the same physical package.

[0025] In another embodiment of the present application, an inter-chip communication method for a multi-chip system is provided, the multi-chip system comprising a first chip, a second chip, and a storage medium; the first chip comprising a first on-chip logic circuit; the second chip comprising a second on-chip logic circuit; the storage medium storing first circuit parameters for parameter configuration of the first on-chip logic circuit and second circuit parameters for parameter configuration of the second on-chip logic circuit; the parameter configurations implemented on the first on-chip logic circuit and the second on-chip logic circuit are used to implement data transmission between the first on-chip logic circuit and the second on-chip logic circuit via a transmission bus; the first on-chip logic circuit and the second on-chip logic circuit both comprising a GPIO interface; a communication bus independent of the transmission bus being connected between the GPIO interfaces of the first on-chip logic circuit and the second on-chip logic circuit; and the inter-chip communication method comprising the following steps performed in the first on-chip logic circuit:

[0026] loading the first circuit parameter and the second circuit parameter from the storage medium;

[0027] sending the second circuit parameter to the second on-chip logic circuit via the communication bus;

[0028] The status information of the second on-chip logic circuit during the data transmission period is monitored via the communication bus.

[0029] In some examples, optionally, the inter-chip communication method includes the following steps performed in the first on-chip logic circuit: in response to successful loading of the first circuit parameters and the second circuit parameters, sending a handshake signal to the second on-chip logic circuit via the communication bus; monitoring a feedback signal generated by the second on-chip logic circuit in response to the handshake signal via the communication bus; wherein the sending of the second circuit parameters to the second on-chip logic circuit via the communication bus is triggered in response to successful monitoring of the feedback signal.

[0030] In some examples, optionally, the communication bus includes a state configuration signal line, a first simplex signal line unidirectionally output from the first on-chip logic circuit to the second on-chip logic circuit, and a second simplex signal line unidirectionally output from the second on-chip logic circuit to the first on-chip logic circuit; the sending of a handshake signal to the second on-chip logic circuit via the communication bus includes: setting the state configuration signal line to a default invalid state; and, during the period when the state configuration signal line is in the invalid state, sending the handshake signal to the second on-chip logic circuit via the first simplex signal line; wherein, during the period when the state configuration signal line is in the invalid state, the second on-chip logic circuit sends the handshake signal via the communication bus. The first simplex signal line monitors the handshake signal sent by the first on-chip logic circuit, and generates the feedback signal to the first on-chip logic circuit through the second simplex signal line; the monitoring of the feedback signal generated by the second on-chip logic circuit in response to the handshake signal through the communication bus includes: the feedback signal through the second simplex signal line; the inter-chip communication method also includes the following steps performed in the first on-chip logic circuit: in response to successful monitoring of the feedback signal, setting the status configuration signal line to a valid state; wherein the read and write operations are implemented through at least one of the first simplex signal line and the second simplex signal line during the period when the status configuration signal line is in a valid state.

[0031] In some examples, optionally, the inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit through the communication bus includes read and write operations of the first on-chip logic circuit and the second on-chip logic circuit through the communication bus; wherein: the first on-chip logic circuit sends the second circuit parameter to the second on-chip logic circuit through the communication bus, which is achieved by the first on-chip logic circuit performing a write operation on the second on-chip logic circuit through the communication bus in the read and write operations; the first on-chip logic circuit monitors the status information from the second on-chip logic circuit through the communication bus, which is achieved by the first on-chip logic circuit performing a read operation on the second on-chip logic circuit through the communication bus in the read and write operations; the inter-chip communication method also includes communication verification operation steps performed on the first on-chip logic circuit and the second on-chip logic circuit, respectively, during the write operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus and the read operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus.

[0032] Based on the embodiments of the present application, the first on-chip logic circuit of the first chip and the second on-chip logic circuit of the second chip in a multi-chip system can reuse the existing GPIO interfaces of the chips, achieving inter-chip communication without the need to expand additional interfaces. In this case, parameter configuration and status monitoring of the first on-chip logic circuit and the second on-chip logic circuit can be implemented by the first on-chip logic circuit (e.g., a software control unit integrated in the first on-chip logic circuit) based on inter-chip communication. Therefore, the second on-chip logic circuit of the second chip does not need to be equipped with a circuit structure for implementing parameter configuration and status monitoring (e.g., it does not need to integrate a software control unit like the first on-chip logic circuit). Thus, the circuit structure of the second on-chip logic circuit can be simplified without the need to expand additional interfaces, thereby helping to reduce the circuit area of ​​the on-chip logic circuit in the multi-chip system while taking into account the implementation of parameter configuration and status monitoring for the on-chip logic circuit of each chip in the multi-chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings are only provided for schematic illustration and explanation of the present application and do not limit the scope of the present application:

[0034] Figure 1 This is a schematic diagram of an exemplary structure of a multi-chip system in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the working principle of the multi-chip system in an embodiment of the present application;

[0036] Figure 3 is a schematic diagram of an exemplary structure of a multi-chip system in a first comparative example;

[0037] Figure 4 is a schematic diagram of an exemplary structure of a multi-chip system in a second comparative example;

[0038] Figure 5 Schematic diagram of the extended working principle of the multi-chip system supporting the inter-chip handshake mechanism in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a working example of implementing inter-chip communication in a multi-chip system according to an embodiment of the present application;

[0040] Figure 7 A schematic diagram of the communication timing of a multi-chip system implementing inter-chip communication in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a data structure for implementing inter-chip communication in a multi-chip system according to an embodiment of the present application;

[0042] Figure 9 This is a schematic diagram of an exemplary flow chart of an inter-chip communication method for a multi-chip system in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of this application more clear, the application is further described in detail below with reference to the accompanying drawings and examples.

[0044] Figure 1 FIG. 1 is an exemplary structural diagram of a multi-chip system in an embodiment of the present application. Figure 1 As shown, in an embodiment of the present application, a multi-chip system may include a first chip 10 , a second chip 20 , and a storage medium 30 .

[0045] For example, in an embodiment of the present application, the first chip 10 and the second chip 20 can be different packaged chips each having an independent physical package, or the first chip 10 and the second chip 20 can also be different independent dies in the same physical package. The embodiment of the present application does not limit the packaging form of the first chip 10 and the second chip 20.

[0046] For example, in the embodiments of the present application, regardless of the packaging form of the first chip 10 and the second chip 20, at least one of the first chip 10 and the second chip 20 can be any one of a processor such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Computing on Graphics Processing Units). The examples provided herein are merely for facilitating understanding of the functions of the first chip 10 and the second chip 20 involved in the embodiments of the present application, and are not intended to impose unnecessary limitations on the first chip 10 and the second chip 20.

[0047] For example, in an embodiment of the present application, the storage medium 30 may be any non-volatile storage medium such as flash memory. The storage medium 30 may have a physical package independent of the first chip 10 and the second chip 20, or may be located in the same physical package as the first chip 10. The embodiment of the present application does not impose any restrictions on the packaging form of the storage medium 30.

[0048] For example, in an embodiment of the present application, the first chip 10 may include a first on-chip logic circuit 100 , and the second chip 20 may include a second on-chip logic circuit 200 .

[0049] For example, in an embodiment of the present application, a software control unit 130 may be integrated into the first on-chip logic circuit 100. The software control unit 130 may be referred to as an on-chip logic circuit processor or an on-chip logic circuit controller. The software control unit 130 may be used to run software programs such as management software, and the software programs run by the software control unit 130 may be used to implement on-chip logic circuit management (including parameter configuration and status monitoring of the on-chip logic circuit). That is, the first on-chip logic circuit 100 may have the ability to implement on-chip logic circuit management by integrating the software control unit 130.

[0050] For example, in an embodiment of the present application, the second on-chip logic circuit 200 may not have an integrated software control unit, that is, the second on-chip logic circuit 200 may not have the ability to implement on-chip logic circuit management. It should be understood that this statement is intended to convey that in an embodiment of the present application, the second on-chip logic circuit 200 is permitted to not have an integrated software control unit (that is, not have the ability to implement on-chip logic circuit management), rather than excluding an on-chip logic circuit that has an integrated software control unit and has the ability to implement on-chip logic circuit management from being used as the second on-chip logic circuit 200 in the implementation of the solution.

[0051] For example, in an embodiment of the present application, the storage medium 30 may store first circuit parameters for implementing parameter configuration for the first on-chip logic circuit 100, and second circuit parameters for implementing parameter configuration for the second on-chip logic circuit 200, and the parameter configuration implemented for the first on-chip logic circuit 100 and the second on-chip logic circuit 200 may be used to implement data transmission between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the transmission bus 50.

[0052] For example, in the embodiment of the present application, the data transmission between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the transmission bus 50 can be used to support the collaborative operation between the first chip 10 and the second chip 20. Furthermore, the data exchanged between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the data transmission can be business data associated with the collaborative operation between the first chip 10 and the second chip 20.

[0053] For example, in an embodiment of the present application, both the first on-chip logic circuit 100 and the second on-chip logic circuit 200 have GPIO (General Purpose Input Output) interfaces, and the GPIO interfaces of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be used to implement the application requirements of the first chip 10 and the second chip 20, respectively. For example, the GPIO interfaces of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be used to connect the first chip 10 and the second chip 20, respectively, to external devices. In other words, the GPIO interface is an existing interface or a default interface in the hardware configuration of the chip's on-chip logic circuit.

[0054] For example, in an embodiment of the present application, a communication bus 60 independent of the transmission bus 50 may be connected between the GPIO interfaces of the first on-chip logic circuit 100 and the second on-chip logic circuit 200. That is, the communication bus 60 may be established between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 by multiplexing the GPIO interface, and the communication bus 60 between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 is independent of the transmission bus 50. For example, the transmission bus 50 between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 may use a dedicated chip interface having an interface rate higher than that of the GPIO interface, and the bus rate of the transmission bus 50 between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 may be higher than the bus rate of the communication bus 60 between the first on-chip logic circuit 100 and the second on-chip logic circuit 200.

[0055] For example, in an embodiment of the present application, the communication bus 60 created by multiplexing the GPIO interface between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be configured as an SPI bus for inter-chip communication based on the SPI (Serial Peripheral Interface) protocol.

[0056] Figure 2 This is a schematic diagram of the working principle of the multi-chip system in the embodiment of this application. Figure 2 In an embodiment of the present application, inter-chip communication between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 based on the communication bus 60 can support parameter configuration and status monitoring. In this case, the first on-chip logic circuit 100 can be configured as follows:

[0057] Loading, from the storage medium 30 , first circuit parameters for implementing parameter configuration on the first on-chip logic circuit 100 and second circuit parameters for implementing parameter configuration on the second on-chip logic circuit 200 ;

[0058] sending the second circuit parameter for configuring the second on-chip logic circuit 200 to the second on-chip logic circuit 200 via the communication bus 60 created by multiplexing the GPIO interface; and

[0059] The communication bus 60 created by multiplexing the GPIO interface monitors the status information of the second on-chip logic circuit 200 during the period of data transmission with the first on-chip logic circuit 100 (ie, during the period of coordinated operation between the first chip 10 and the second chip 20).

[0060] For example, in an embodiment of the present application, information exchanged between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 through inter-chip communication may include circuit parameters for supporting data transmission functions and status information for characterizing the data transmission status.

[0061] For example, in an embodiment of the present application, the process of the first on-chip logic circuit 100 loading the first circuit parameters and the second circuit parameters from the storage medium 30 may be managed and controlled by the software control unit 130 integrated in the first on-chip logic circuit 100 .

[0062] For example, in an embodiment of the present application, the first on-chip logic circuit 100 may further include a loading interface independent of the GPIO interface, and the storage medium 30 may be connected to the loading interface of the first on-chip logic circuit 100. Furthermore, the first on-chip logic circuit 100 may load first circuit parameters for configuring the first on-chip logic circuit 100 and second circuit parameters for configuring the second on-chip logic circuit 200 from the storage medium 30 via the loading interface. Alternatively, the storage medium 30 may be connected to the GPIO interface of the first on-chip logic circuit 100. In this case, the first on-chip logic circuit 100 may load the first circuit parameters for configuring the first on-chip logic circuit 100 and the second circuit parameters for configuring the second on-chip logic circuit 200 from the storage medium 30 via the GPIO interface. Furthermore, the GPIO interface of the first on-chip logic circuit 100 may be multiplexed by the storage medium 30 and the communication bus 60. In other words, the embodiment of the present application does not impose any unnecessary restrictions on the connection method between the storage medium 30 and the first on-chip logic circuit 100.

[0063] For example, in an embodiment of the present application, after the first on-chip logic circuit 100 successfully loads the first circuit parameters, the first on-chip logic circuit 100 can use the first circuit parameters to configure its own parameters, and after completing its own parameter configuration, the first on-chip logic circuit 100 can enter the working mode and wait for the collaborative work between the first chip and the second chip, for example, enter the working mode and wait for data transmission between the first on-chip logic circuit 100 and the second on-chip logic circuit 200.

[0064] For example, in an embodiment of the present application, after the second circuit parameters are successfully sent to the second on-chip logic circuit 200 through the communication bus 60, the second on-chip logic circuit 200 can use the second circuit parameters received through the communication bus 60 to implement its own parameter configuration, that is, to implement the parameter configuration of the second on-chip logic circuit 200 by the first on-chip logic circuit 100, and after completing its own parameter configuration, the second on-chip logic circuit 200 can enter the working mode and wait for the collaborative work between the first chip 10 and the second chip 20, for example, enter the working mode and wait for data transmission between the first on-chip logic circuit 100 and the second on-chip logic circuit 200.

[0065] For example, in an embodiment of the present application, the first on-chip logic circuit 100 can also monitor its own status information during the period of data transmission with the second on-chip logic circuit 200 (i.e., during the period of collaborative work between the first chip 10 and the second chip 20), and the status information of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be reported by the first on-chip logic circuit 100 to the software program run by the software control unit 130 for processing.

[0066] Based on the embodiments of the present application, the first on-chip logic circuit 100 of the first chip 10 and the second on-chip logic circuit 200 of the second chip 20 in a multi-chip system can reuse the existing GPIO interfaces of the chips to achieve inter-chip communication without the need to expand additional interfaces. In this case, parameter configuration and status monitoring of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be implemented by the first on-chip logic circuit 100 (for example, the software control unit 130 integrated in the first on-chip logic circuit 100) based on inter-chip communication. Therefore, the second on-chip logic circuit 200 of the second chip 20 does not need to be equipped with a circuit structure for implementing parameter configuration and status monitoring (for example, it does not need to integrate the software control unit 130 like the first on-chip logic circuit 100).

[0067] Figure 3 Schematic diagram of the structure of the multi-chip system in the first comparative example. Figure 3 In the first comparative example, an additional software control unit 230 is integrated into the second on-chip logic circuit 200. Under the management and control of the additional software control unit 230, the second on-chip logic circuit 200 can load second circuit parameters from the storage medium 30 for autonomous parameter configuration. Furthermore, the second on-chip logic circuit 200 can monitor its own status and report it to the additional software control unit 230. In this case, the GPIO interfaces of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be idle, without establishing the communication bus 60. Furthermore, the integration of the additional software control unit 230 increases the circuit area of ​​the second on-chip logic circuit 200.

[0068] Figure 4 Schematic diagram of the structure of the multi-chip system in the second comparative example. Figure 4 In the second comparative example, an additional bus 40 is established between the first on-chip logic circuit 100 and the second on-chip logic circuit 200. The additional bus 40 does not use the GPIO interface and is independent of the transmission bus 50. In this case, the GPIO interfaces of the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can be idle. In addition, the first on-chip logic circuit 100 and the second on-chip logic circuit 200 have additional interface pins due to the addition of the additional bus 40. Consequently, the additional interface pins not only increase the complexity of the wiring layout but also increase the circuit area of ​​the first on-chip logic circuit 100 and the second on-chip logic circuit 200.

[0069] Thus, compared to Figure 3 The first comparative example shown and Figure 4 In the second comparative example shown in FIG. 1 , the embodiment of the present application can support the simplification of the circuit structure of the second on-chip logic circuit 200 without expanding the additional interface (for example, avoiding adding Figure 3 The additional software control unit 230 in the first comparative example shown in the figure) helps to reduce the circuit area of ​​the on-chip logic circuit in the multi-chip system while taking into account the parameter configuration and status monitoring of the on-chip logic circuit of each chip in the multi-chip system.

[0070] Illustratively, in an embodiment of the present application, the first on-chip logic circuit 100 and the second on-chip logic circuit 200 are both further configured to: determine their own roles in the inter-chip communication based on the communication bus 60 according to their own hardware configurations; wherein, the role of the first on-chip logic circuit 100 in the inter-chip communication based on the communication bus 60 is a master device, and the role of the second on-chip logic circuit 200 in the inter-chip communication based on the communication bus 60 is a slave device, and the master device is used to represent the loader and provider of circuit parameters, as well as the monitor of status information.

[0071] For example, in an embodiment of the present application, the first on-chip logic circuit 100 may be further configured to determine its role in inter-chip communication based on the communication bus 60 according to its own hardware configuration before obtaining the first circuit parameters (for example, during the initialization phase after power-on startup); the second on-chip logic circuit 200 may be further configured to determine its role in inter-chip communication based on the communication bus 60 according to its own hardware configuration before obtaining the second circuit parameters (for example, during the initialization phase after power-on startup); wherein:

[0072] The first on-chip logic circuit 100 loads the first circuit parameter and the second circuit parameter from the storage medium 30, sends the second circuit parameter to the second on-chip logic circuit 200 via the communication bus 60, and monitors the status information of the second on-chip logic circuit 200 via the second communication bus 60. This may be enabled because the first on-chip logic circuit 100 is determined to be a master device in the inter-chip communication based on the communication bus 60.

[0073] Since the second on-chip logic circuit 200 plays the role of a slave device in the inter-chip communication based on the communication bus 60, the way to obtain the second circuit parameters can be determined as receiving the status information from the first on-chip logic circuit 100 through the communication bus 60, and providing the status information for monitoring by the first on-chip logic circuit 100 through the communication bus 60 during the data transmission period.

[0074] Figure 5 This is a schematic diagram of the extended working principle of the multi-chip system supporting the inter-chip handshake mechanism in the embodiment of this application. Figure 5 In an embodiment of the present application, the inter-chip communication between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 based on the communication bus 60 may further support inter-chip handshaking. In this case, the transmission of the second circuit parameter from the first on-chip logic circuit 100 to the second on-chip logic circuit 200 via the communication bus 60 may be triggered in response to the successful inter-chip handshaking between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60.

[0075] Figure 6 This is a working example diagram of a multi-chip system implementing inter-chip communication in an embodiment of the present application. Figure 6 In the embodiment of the present application, in order to achieve Figure 5 For the inter-chip handshake shown, the first on-chip logic circuit 100 may be further configured as follows:

[0076] In response to the first circuit parameter and the second circuit parameter being loaded successfully from the storage medium 30 , sending a handshake signal to the second on-chip logic circuit 200 via the communication bus 60 ; and

[0077] monitoring, via the communication bus 60, a feedback signal generated by the second on-chip logic circuit 200 in response to the handshake signal;

[0078] In which, the successful monitoring of the feedback signal by the first on-chip logic circuit 100 indicates that the inter-chip handshake between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 is successful, and the sending of the second circuit parameter from the first on-chip logic circuit 100 to the second on-chip logic circuit 200 via the communication bus 60 can be triggered and executed in response to the successful monitoring of the feedback signal of the second on-chip logic circuit 200 by the first on-chip logic circuit 100.

[0079] For example, in an embodiment of the present application, the first on-chip logic circuit 100 configures its own parameters using the first circuit parameters, and does not need to wait for successful monitoring of the feedback signal of the second on-chip logic circuit 200, that is, does not need to wait for the success of the inter-chip handshake.

[0080] For example, in an embodiment of the present application, the process of the first on-chip logic circuit 100 determining whether the inter-chip handshake is successful by monitoring the feedback signal can be implemented in conjunction with timing the feedback signal. For example, the first on-chip logic circuit 100 can be further configured to: start timing in response to the successful transmission of the handshake signal; if a feedback signal generated by the second on-chip logic circuit 200 in response to the handshake signal is received via the communication bus 60 before the timing expires, then determine that the monitoring of the feedback signal is successful, and further determine that the inter-chip handshake between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 is successful; if the feedback signal generated by the second on-chip logic circuit 200 in response to the handshake signal is not received via the communication bus 60 when the timing expires, then determine that the monitoring of the feedback signal has failed, and further determine that the inter-chip handshake between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 has failed.

[0081] For example, in an embodiment of the present application, as described above, the first on-chip logic circuit 100 may be integrated with a software control unit 130 for running a software program, and, in addition to reporting status information to the software program run by the software control unit 130, the first on-chip logic circuit 100 may be further configured to: upon determining that the inter-chip handshake with the second on-chip logic circuit 200 through the communication bus 60 has failed (for example, the monitoring of the feedback signal has failed), report a failure alarm indicating the handshake failure to the software program run by the software control unit 130.

[0082] For example, in an embodiment of the present application, based on the inter-chip handshake between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60, the information interaction between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 can reduce the occurrence of problems such as high bit error rate or low communication efficiency due to circuit abnormalities of the second on-chip logic circuit 200, thereby making the information interaction between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 more reliable.

[0083] For example, in an embodiment of the present application, inter-chip communication between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60 may include read and write operations between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60. In the read and write operations, the write operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus 60 may be used to enable the first on-chip logic circuit 100 to send a second circuit parameter to the second on-chip logic circuit 200. Furthermore, the read operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus may be used to enable the first on-chip logic circuit 100 to monitor status information from the second on-chip logic circuit. In this case, the handshake signals and feedback signals involved in the inter-chip handshake may reuse the signal lines on the communication bus 60 used for the read and write operations.

[0084] Figure 7 Schematic diagram of the communication timing of the multi-chip system in the embodiment of the present application to achieve inter-chip communication. Figure 7 In an embodiment of the present application, the communication bus 60 may include a status configuration signal line GPIO_sel, a first simplex signal line GPIO_cm1 that is unidirectionally output from the first on-chip logic circuit 100 to the second on-chip logic circuit 200, and a second simplex signal line GPIO_cm2 that is unidirectionally output from the second on-chip logic circuit 200 to the first on-chip logic circuit 100. In this case, the handshake signals and feedback signals involved in the inter-chip handshake can be multiplexed with the read and write operations using the first simplex signal line GPIO_cm1 and the second simplex signal line GPIO_cm2 in the communication bus 60.

[0085] For example, in an embodiment of the present application, the state configuration signal line GPIO_sel can be selectively set to an invalid state and a valid state by the first on-chip logic circuit 100. The invalid state of the state configuration signal line GPIO_sel can indicate that the first simplex signal line GPIO_cm1 and the second simplex signal line GPIO_cm2 are used for inter-chip handshake; and the valid state of the state configuration signal line GPIO_sel can indicate that the first simplex signal line GPIO_cm1 and the second simplex signal line GPIO_cm2 are used for inter-chip communication.

[0086] For example, in an embodiment of the present application, the first on-chip logic circuit 100 may maintain the state configuration signal line GPIO_sel in a default inactive state before the inter-chip handshake succeeds. For example, the first on-chip logic circuit 100 may maintain the state configuration signal line GPIO_sel in a default first level state (e.g., a low level state) to indicate that the state configuration signal GPIO_sel is inactive. Furthermore, the first on-chip logic circuit 100 may maintain the state configuration signal line GPIO_sel in a second level state (e.g., a high level state) different from the first level state to indicate that the state configuration signal GPIO_sel is active.

[0087] For example, in an embodiment of the present application, the first on-chip logic circuit 100 can map the first simplex signal line GPIO_cm1 as a signal line for generating a handshake signal, and can also map the second simplex signal line GPIO_cm2 as a signal line for receiving a feedback signal during a period when the status configuration signal line GPIO_sel is in an invalid state; similarly, the second on-chip logic circuit 200 can map the first simplex signal line GPIO_cm1 as a signal line for receiving a handshake signal, and can also map the second simplex signal line GPIO_cm2 as a signal line for a feedback signal in response to the handshake signal during a period when the status configuration signal line GPIO_sel is in an invalid state.

[0088] Illustratively, in an embodiment of the present application, the first on-chip logic circuit 100 may switch the first simplex signal line GPIO_cm1 from a default first level state (e.g., a low level state) to a second level state (e.g., a high level state) different from the first level state during a period when the state configuration signal line GPIO_sel is in an invalid state, so as to utilize the second level state of the first simplex signal line to indicate that a handshake signal is currently generated through the first simplex signal line GPIO_cm1; accordingly, the second on-chip logic circuit 200 may recognize the second level state of the first simplex signal line GPIO_cm1 as a handshake signal during a period when the state configuration signal line GPIO_sel is in an invalid state.

[0089] Illustratively, in an embodiment of the present application, the second on-chip logic circuit 200 may switch the second simplex signal line GPIO_cm2 from a default first level state (e.g., a low level state) to a second level state (e.g., a high level state) different from the first level state during a period when the state configuration signal line GPIO_sel is in an invalid state, so as to utilize the second level state of the second simplex signal line to indicate that a feedback signal is currently generated through the second simplex signal line GPIO_cm2; accordingly, the first on-chip logic circuit 100 may identify the second level state of the second simplex signal line GPIO_cm2 as a feedback signal during a period when the state configuration signal line GPIO_sel is in an invalid state.

[0090] For example, in an embodiment of the present application, the first on-chip logic circuit 100 and the second on-chip logic circuit 200 can switch and map the first simplex signal line GPIO_cm1 and the second simplex signal line GPIO_cm2 to signal lines for read and write operations during the period when the status configuration signal line GPIO_sel is in a valid state.

[0091] For example, in an embodiment of the present application, the first on-chip logic circuit 100 may be specifically configured as follows:

[0092] Set the status configuration signal line GPIO_sel to the default invalid state;

[0093] During a period when the status configuration signal line GPIO_sel is in an invalid state, a handshake signal is sent to the second on-chip logic circuit 200 through the first simplex signal line GPIO_cm1. During a period when the status configuration signal line GPIO_sel is in an invalid state, the second on-chip logic circuit 200 monitors the handshake signal sent by the first on-chip logic circuit 100 through the first simplex signal line GPIO_cm1 and generates a feedback signal to the first on-chip logic circuit 100 through the second simplex signal line GPIO_cm2. The first on-chip logic circuit 100 monitors the feedback signal through the second simplex signal line GPIO_cm2. That is, the first on-chip logic circuit 100 can monitor the feedback signal through the second simplex signal line GPIO_cm2.

[0094] In response to successful monitoring of the feedback signal, the state configuration signal line GPIO_sel is set to a valid state; wherein the read and write operations are implemented through at least one of the first simplex signal line GPIO_cm1 and the second simplex signal line GPIO_cm2 during the period when the state configuration signal line GPIO_sel is in the valid state.

[0095] Illustratively, in an embodiment of the present application, the first on-chip logic circuit 100 may be configured to: during a period in which the status configuration signal line GPIO_sel is in a valid state, send an operation request for a read or write operation (e.g., a write request for a write operation or a read request for a read operation) through the first simplex signal line GPIO_cm1, and send operation data of a write operation in a read or write operation (i.e., a second circuit parameter sent to the second on-chip logic circuit 200) through the first simplex signal line GPIO_cm1, or receive operation data of a read operation in a read or write operation (i.e., status information read from the second on-chip logic circuit 200) through the second simplex signal line GPIO_cm2. Similarly, the second on-chip logic circuit 200 can be configured to: during the period when the status configuration signal line GPIO_sel is in a valid state, identify the operation request of the read and write operation (for example, a write request for a write operation or a read request for a read operation) sent by the first on-chip logic circuit through the first simplex signal line GPIO_cm1, and receive the operation data of the write operation in the read and write operation (that is, the second circuit parameters used to implement parameter configuration for the second on-chip logic circuit) through the first simplex signal line GPIO_cm1, or send the operation data of the read operation in the read and write operation (that is, the status information fed back to the first on-chip logic circuit 100 as read data) through the second simplex signal line GPIO_cm2.

[0096] For example, in an embodiment of the present application, the communication bus 60 may further include an operating clock signal line GPIO_clk. In this case, the first on-chip logic circuit 100 may be further configured to generate a clock signal for controlling read and write operations to the second on-chip logic circuit 200 via the operating clock signal line GPIO_clk while the status configuration signal line GPIO_sel is active. That is, if the inter-chip communication between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 further includes an inter-chip handshake, the clock signal for controlling read and write operations may be generated only after the inter-chip handshake is successful.

[0097] For example, in the embodiment of the present application, the inter-chip communication between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 based on the communication bus 60 may further support communication verification.

[0098] For example, in an embodiment of the present application, as described above, the first on-chip logic circuit 100 sends the second circuit parameter to the second on-chip logic circuit 200 via the communication bus 60, which can be achieved by the first on-chip logic circuit 100 performing a write operation on the second on-chip logic circuit 200 via the communication bus during a read or write operation; and the first on-chip logic circuit 100 monitors status information from the second on-chip logic circuit 200 via the communication bus 60, which can be achieved by the first on-chip logic circuit 100 performing a read operation on the second on-chip logic circuit 200 via the communication bus 60 during a read or write operation. In this case, both the write operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus 60 and the read operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus 60 can include a communication verification operation step.

[0099] For example, in an embodiment of the present application, the process of the first on-chip logic circuit 100 performing a read / write operation on the second on-chip logic circuit 200 may include:

[0100] The first on-chip logic circuit 100 sends an operation request for a read or write operation to the second on-chip logic circuit 200 via the communication bus 60 . For example, the operation request may be a write request for a write operation or a read request for a read operation.

[0101] The first on-chip logic circuit 100 sends an idle bit to the second on-chip logic circuit 200 via the communication bus 60 for the second on-chip logic circuit 200 to prepare for responding to the operation request;

[0102] The first on-chip logic circuit 100 and the second on-chip logic circuit 200 interact with each other through the communication bus 60 to read and write operation data. For example, the operation data may include a second circuit parameter sent from the first on-chip logic circuit 100 to the second on-chip logic circuit 200, or status information returned from the second on-chip logic circuit 200 to the first on-chip logic circuit 100.

[0103] Illustratively, in an embodiment of the present application, an operation request, idle bits, and operation data are sequentially transmitted between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60, and the operation data is triggered to be transmitted in response to a successful verification of the operation request. In addition, in the above-mentioned process of the read and write operations, the verification objects of the communication verification may include the operation request and operation data in addition to the idle bits, and any one of the operation request and operation data may be triggered to be retransmitted in response to a verification error of the communication verification.

[0104] Figure 8 This is a schematic diagram of the data structure for implementing inter-chip communication in a multi-chip system according to an embodiment of the present application. Figure 8In an embodiment of the present application, the operation request sent by the first on-chip logic circuit 100 to the second on-chip logic circuit 200 via the communication bus 60 may sequentially include: target address information, operation enable information, and valid data length.

[0105] For example, in the embodiments of the present application, the target address information may be used to indicate an address at which the first on-chip logic circuit 100 performs a write operation on the second on-chip logic circuit 200 via the communication bus 60, or an address at which the first on-chip logic circuit 100 performs a read operation on the second on-chip logic circuit 200 via the communication bus 60. For example, the address for the write operation may be a register address of a configuration register in the second on-chip logic circuit 200 for loading second circuit parameters, and the address for the read operation may be a register address of a status register in the second on-chip logic circuit 200 for recording status information of the second on-chip logic circuit 200.

[0106] For example, in an embodiment of the present application, the operation enable information may be used to indicate the type of operation enabled for the currently initiated read or write operation. For example, the operation enable information may indicate that the type of operation enabled for the currently initiated read or write operation is: a write operation for the first on-chip logic circuit 100 to send a second circuit parameter to the second on-chip logic circuit 200, or a read operation for the first on-chip logic circuit 100 to monitor status information from the second on-chip logic circuit.

[0107] For example, in embodiments of the present application, the effective data length can be used to represent the data length of the operation data. For example, if the read / write operation is a write operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus 60, the effective data length is used to represent the data length of the second circuit parameter serving as the operation data for the write operation; if the read / write operation is a read operation performed by the first on-chip logic circuit 100 on the second on-chip logic circuit 200 via the communication bus 60, the effective data length is used to represent the data length of the status information serving as the operation data for the read operation.

[0108] Exemplarily, in an embodiment of the present application, the verification object of the communication verification in the read and write operations may include all parts except the idle bits, that is, the verification object of the communication verification in the read and write operations may include the target address information, operation enable information and valid data length in the operation request, and the verification object of the communication verification in the read and write operations may also include operation data.

[0109] Illustratively, in an embodiment of the present application, target address information, operation enable information, valid data length, idle bits, and operation data are sequentially transmitted between the first on-chip logic circuit 100 and the second on-chip logic circuit 200 via the communication bus 60, and any one of the target address information, operation enable information, valid data length, and operation data is triggered for retransmission in response to a verification error in the communication verification, and each of the operation enable information, valid data length, and operation data can be triggered for transmission in response to a successful verification of a verification object that is sorted earlier.

[0110] In an embodiment of the present application, a method for inter-chip communication for a multi-chip system is also provided. The multi-chip system may include a first chip, a second chip, and a storage medium; the first chip may have a first on-chip logic circuit; the second chip may have a second on-chip logic circuit; the storage medium may store first circuit parameters for implementing parameter configuration for the first on-chip logic circuit, and second circuit parameters for implementing parameter configuration for the second on-chip logic circuit; the parameter configuration implemented on the first on-chip logic circuit and the second on-chip logic circuit is used to realize data transmission between the first on-chip logic circuit and the second on-chip logic circuit through a transmission bus; the first on-chip logic circuit and the second on-chip logic circuit may both have GPIO interfaces; a communication bus independent of the transmission bus may be connected between the GPIO interfaces of the first on-chip logic circuit and the second on-chip logic circuit. The specific structure and characteristics of the first on-chip logic circuit and the second on-chip logic circuit can be found in the previous description and will not be repeated here.

[0111] Figure 9 This is an exemplary flow chart of the inter-chip communication method for a multi-chip system in an embodiment of the present application. Figure 9 In an embodiment of the present application, an inter-chip communication method for a multi-chip system may include the following steps performed by a first on-chip logic circuit:

[0112] S910: Loading first circuit parameters for implementing parameter configuration on a first on-chip logic circuit and second circuit parameters for implementing parameter configuration on a second on-chip logic circuit from a storage medium;

[0113] S930: Sending the second circuit parameter used for parameter configuration of the second on-chip logic circuit to the second on-chip logic circuit via the communication bus created by multiplexing the GPIO interface; and

[0114] S950: Monitoring, via a communication bus created by multiplexing the GPIO interface, state information of the second on-chip logic circuit during a period of data transmission with the first on-chip logic circuit.

[0115] Based on the above-described inter-chip communication method, the first on-chip logic circuit of the first chip and the second on-chip logic circuit of the second chip in a multi-chip system can reuse the existing GPIO interfaces of the chips, achieving inter-chip communication without the need for additional interfaces. In this case, parameter configuration and status monitoring of the first and second on-chip logic circuits can be implemented by the first on-chip logic circuit (e.g., a software control unit integrated in the first on-chip logic circuit) based on inter-chip communication. Therefore, the second on-chip logic circuit of the second chip does not need to be equipped with a circuit structure for implementing parameter configuration and status monitoring (e.g., it does not need to integrate a software control unit like the first on-chip logic circuit). This simplifies the circuit structure of the second on-chip logic circuit without the need for additional interfaces, thereby helping to reduce the circuit area of ​​the on-chip logic circuits in the multi-chip system while ensuring parameter configuration and status monitoring for the on-chip logic circuits of each chip in the multi-chip system.

[0116] For example, in an embodiment of the present application, inter-chip communication between a first on-chip logic circuit and a second on-chip logic circuit via a communication bus may include read and write operations between the first on-chip logic circuit and the second on-chip logic circuit via the communication bus; wherein: the first on-chip logic circuit sending a second circuit parameter to the second on-chip logic circuit via the communication bus may be implemented by a write operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus during the read and write operations; and the first on-chip logic circuit monitoring status information from the second on-chip logic circuit via the communication bus may be implemented by a read operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus during the read and write operations. Therefore, S930 may specifically include: sending the second circuit parameter used for parameter configuration of the second on-chip logic circuit to the second on-chip logic circuit by performing a write operation on the communication bus on the second on-chip logic circuit; and S950 may specifically include: monitoring status information of the second on-chip logic circuit during data transmission with the first on-chip logic circuit by performing a write operation on the communication bus on the second on-chip logic circuit.

[0117] Illustratively, in an embodiment of the present application, the inter-chip communication method may further include (for example, after S910) executing the following steps for inter-chip handshake in the first on-chip logic circuit: in response to successful loading of the first circuit parameters and the second circuit parameters, sending a handshake signal to the second on-chip logic circuit via a communication bus; and monitoring, via the communication bus, a feedback signal generated by the second on-chip logic circuit in response to the handshake signal; wherein the sending of the second circuit parameters to the second on-chip logic circuit via the communication bus may be triggered to execute in response to successful monitoring of the feedback signal, that is, S930 may be triggered to execute in response to successful monitoring of the feedback signal.

[0118] Illustratively, in an embodiment of the present application, if the communication bus includes a status configuration signal line, a first simplex signal line unidirectionally output from a first on-chip logic circuit to a second on-chip logic circuit, and a second simplex signal line unidirectionally output from the second on-chip logic circuit to the first on-chip logic circuit, then, in the inter-chip communication method, in the following steps for inter-chip handshake performed by the first on-chip logic circuit:

[0119] Sending a handshake signal to the second on-chip logic circuit via the communication bus may include: setting a status configuration signal line to a default invalid state; and, while the status configuration signal line is in the invalid state, sending a handshake signal to the second on-chip logic circuit via the first simplex signal line; wherein, while the status configuration signal line is in the invalid state, the second on-chip logic circuit monitors the handshake signal sent by the first on-chip logic circuit via the first simplex signal line, and generates a feedback signal to the first on-chip logic circuit via the second simplex signal line.

[0120] Monitoring the feedback signal generated by the second on-chip logic circuit in response to the handshake signal through the communication bus may include: feeding back the signal through the second simplex signal line.

[0121] For example, in an embodiment of the present application, if the communication bus includes a status configuration signal line, a first simplex signal line unidirectionally output from a first on-chip logic circuit to a second on-chip logic circuit, and a second simplex signal line unidirectionally output from the second on-chip logic circuit to the first on-chip logic circuit, then the following steps for inter-chip handshake performed by the first on-chip logic circuit in the inter-chip communication method may further include: setting the status configuration signal line to an active state in response to successful monitoring of a feedback signal; wherein read and write operations are performed via at least one of the first and second simplex signal lines while the status configuration signal line is in the active state. The manner in which read and write operations are performed via at least one of the first and second simplex signal lines can be found in the previous description and will not be further elaborated here.

[0122] For example, in an embodiment of the present application, the inter-chip communication method may further include a communication verification step performed on the first on-chip logic circuit and the second on-chip logic circuit, respectively, during a write operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus, and during a read operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus. The communication verification step can be found in the previous description and will not be repeated here.

[0123] It can be understood that, in the embodiments of the present application, the various parts of the content exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the context in which it is connected, which can be a common limiting relationship of "and", or can also be an alternative limiting relationship of "or". Therefore, the various parts of the content with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the content respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0124] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A multi-chip system, characterized in that: comprising a first chip, a second chip, and a storage medium; The first chip has a first on-chip logic circuit; The second chip has a second on-chip logic circuit; The storage medium stores first circuit parameters for implementing parameter configuration on the first on-chip logic circuit and second circuit parameters for implementing parameter configuration on the second on-chip logic circuit, and the parameter configuration implemented on the first on-chip logic circuit and the second on-chip logic circuit is used to implement data transmission between the first on-chip logic circuit and the second on-chip logic circuit via a transmission bus; The first on-chip logic circuit and the second on-chip logic circuit both have GPIO interfaces, and a communication bus independent of the transmission bus is connected between the GPIO interfaces of the first on-chip logic circuit and the second on-chip logic circuit; The first on-chip logic circuit is configured as follows: loading the first circuit parameter and the second circuit parameter from the storage medium; sending the second circuit parameter to the second on-chip logic circuit via the communication bus; monitoring, via the communication bus, state information of the second on-chip logic circuit during the data transmission period; In which, the first on-chip logic circuit is also configured to monitor its own status information during the data transmission period, a software control unit is integrated in the first on-chip logic circuit, and the status information of the first on-chip logic circuit and the second on-chip logic circuit is used to report to the software program running by the software control unit for processing.

2. The multi-chip system according to claim 1, wherein: The first on-chip logic circuit is further configured as follows: In response to successful loading of the first circuit parameter and the second circuit parameter, sending a handshake signal to the second on-chip logic circuit via the communication bus; monitoring, via the communication bus, a feedback signal generated by the second on-chip logic circuit in response to the handshake signal; The sending of the second circuit parameter to the second on-chip logic circuit via the communication bus is triggered in response to successful monitoring of the feedback signal.

3. The multi-chip system according to claim 2, wherein: The inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit via the communication bus includes: read and write operations between the first on-chip logic circuit and the second on-chip logic circuit via the communication bus; wherein, in the read and write operations, the write operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus is used to enable the first on-chip logic circuit to send the second circuit parameter to the second on-chip logic circuit; and, in the read and write operations, the read operation performed by the first on-chip logic circuit on the second on-chip logic circuit via the communication bus is used to enable the first on-chip logic circuit to monitor status information of the second on-chip logic circuit from the second on-chip logic circuit. The handshake signal and the feedback signal multiplex the signal lines used by the read and write operations in the communication bus.

4. The multi-chip system according to claim 3, wherein: The communication bus includes: a status configuration signal line, a first simplex signal line unidirectionally output from the first on-chip logic circuit to the second on-chip logic circuit, and a second simplex signal line unidirectionally output from the second on-chip logic circuit to the first on-chip logic circuit; The first on-chip logic circuit is specifically configured as follows: Setting the state configuration signal line to a default invalid state; During a period when the status configuration signal line is in an invalid state, the handshake signal is sent to the second on-chip logic circuit through the first simplex signal line; wherein, during a period when the status configuration signal line is in an invalid state, the second on-chip logic circuit monitors the handshake signal sent by the first on-chip logic circuit through the first simplex signal line and generates the feedback signal to the first on-chip logic circuit through the second simplex signal line, and the first on-chip logic circuit monitors the feedback signal through the second simplex signal line; In response to successful monitoring of the feedback signal, the status configuration signal line is set to a valid state; wherein the read and write operations are implemented through at least one of the first simplex signal line and the second simplex signal line during the period when the status configuration signal line is in the valid state.

5. The multi-chip system according to claim 1, wherein: The inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit via the communication bus includes: read and write operations between the first on-chip logic circuit and the second on-chip logic circuit via the communication bus; in: The first on-chip logic circuit sends the second circuit parameter to the second on-chip logic circuit via the communication bus, which is achieved by the first on-chip logic circuit performing a write operation on the second on-chip logic circuit via the communication bus during the read and write operations; The first on-chip logic circuit monitors the status information of the second on-chip logic circuit from the second on-chip logic circuit via the communication bus, and this is achieved by the first on-chip logic circuit performing a read operation on the second on-chip logic circuit via the communication bus during the read and write operations; The write operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus, and the read operation performed by the first on-chip logic circuit on the second on-chip logic circuit through the communication bus, both include a communication verification operation step.

6. The multi-chip system according to claim 5, characterized in that: The process of the read and write operation includes: The first on-chip logic circuit sends the read / write operation request to the second on-chip logic circuit via the communication bus; The first on-chip logic circuit sends an idle bit to the second on-chip logic circuit via the communication bus, indicating that the second on-chip logic circuit is ready to respond to the read and write operations; The first on-chip logic circuit and the second on-chip logic circuit exchange operation data of the read and write operations via the communication bus, where the operation data includes the second circuit parameters sent from the first on-chip logic circuit to the second on-chip logic circuit, or status information of the second on-chip logic circuit returned from the second on-chip logic circuit to the first on-chip logic circuit; The verification object of the communication verification includes the operation request and the operation data, and any one of the operation request and the operation data is triggered to be retransmitted in response to a verification error of the communication verification.

7. The multi-chip system according to claim 6, wherein: The operation request includes: target address information, used to indicate an address at which the first on-chip logic circuit performs a write operation on the second on-chip logic circuit via the communication bus, or an address at which the first on-chip logic circuit performs a read operation on the second on-chip logic circuit via the communication bus; Operation enabling information, used to indicate the type of operation enabled for the currently initiated read and write operation; Valid data length, used to represent the data length of the operation data; The verification objects of the communication verification include the target address information, the operation enable information, the valid data length and the operation data, and any one of the target address information, the operation enable information, the valid data length and the operation data is triggered to be retransmitted in response to a verification error of the communication verification.

8. The multi-chip system according to claim 1, wherein: The first on-chip logic circuit is further configured to, before acquiring the first circuit parameter, determine its own role in the inter-chip communication based on the communication bus based on its hardware configuration; the second on-chip logic circuit is further configured to, before acquiring the second circuit parameter, determine its own role in the inter-chip communication based on the communication bus based on its hardware configuration; wherein, the first on-chip logic circuit loads the first circuit parameter and the second circuit parameter from the storage medium, sends the second circuit parameter to the second on-chip logic circuit via the communication bus, and monitors the status information of the second on-chip logic circuit because its own role in the inter-chip communication based on the communication bus is determined to be a master device and is therefore enabled; because the second on-chip logic circuit is determined to be a slave device in the inter-chip communication based on the communication bus, it determines the way to acquire the second circuit parameter to receive the status information of the second on-chip logic circuit from the first on-chip logic circuit via the communication bus and provide the status information of the second on-chip logic circuit for monitoring by the first on-chip logic circuit; and / or, The bus rate of the transmission bus is higher than the bus rate of the communication bus; and / or, The communication bus is configured as an SPI bus that supports inter-chip communication between the first on-chip logic circuit and the second on-chip logic circuit based on the SPI protocol; and / or, The first chip and the second chip are different packaged chips having independent physical packages, or different bare chips independent of each other in the same physical package.

9. An inter-chip communication method for a multi-chip system, characterized in that: The multi-chip system includes a first chip, a second chip, and a storage medium; the first chip has a first on-chip logic circuit; the second chip has a second on-chip logic circuit; the storage medium stores first circuit parameters for implementing parameter configuration on the first on-chip logic circuit, and second circuit parameters for implementing parameter configuration on the second on-chip logic circuit; the parameter configuration implemented on the first on-chip logic circuit and the second on-chip logic circuit is used to realize data transmission between the first on-chip logic circuit and the second on-chip logic circuit via a transmission bus; the first on-chip logic circuit and the second on-chip logic circuit both have GPIO interfaces; a communication bus independent of the transmission bus is connected between the GPIO interfaces of the first on-chip logic circuit and the second on-chip logic circuit; and the inter-chip communication method includes the following steps performed in the first on-chip logic circuit: loading the first circuit parameter and the second circuit parameter from the storage medium; sending the second circuit parameter to the second on-chip logic circuit via the communication bus; monitoring, via the communication bus, state information of the second on-chip logic circuit during the data transmission period; In which, the first on-chip logic circuit is also configured not to monitor its own status information during the period of transmission with the data, a software control unit is integrated in the first on-chip logic circuit, and the status information of the first on-chip logic circuit and the second on-chip logic circuit is used to report to the software program running by the software control unit for processing.

10. The inter-chip communication method according to claim 9, wherein: The inter-chip communication method comprises the following steps performed by the first on-chip logic circuit: In response to successful loading of the first circuit parameter and the second circuit parameter, sending a handshake signal to the second on-chip logic circuit via the communication bus; monitoring, via the communication bus, a feedback signal generated by the second on-chip logic circuit in response to the handshake signal; The sending of the second circuit parameter to the second on-chip logic circuit via the communication bus is triggered in response to successful monitoring of the feedback signal.

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