Fractional delay compensation method and device for spatial VLBI related processor

Abstract

The invention relates to a fractional delay compensation method and device for a spatial VLBI related processor. The method comprises the following steps: acquiring data between a sampling starting moment and a sampling ending moment; determining a compensation time sequence; wherein the compensation time sequence comprises a plurality of compensation time points which are sequentially ranked from small to large; determining a fractional time delay corresponding to each compensation time point; a compensation time period is formed between every two adjacent compensation time points, and for each compensation time period, fractional time delay compensation is performed on the data in the compensation time period by using a fractional filter corresponding to the compensation time period to obtain the data after fractional time delay compensation; the filter coefficient of the fractional filter corresponding to each compensation time period is calculated according to the fractional time delay corresponding to the smaller one of the two compensation time points forming the compensation time period. The fractional time delay compensation method and device for the space VLBI related processor are high in calculation precision and high in calculation speed.

Description

Technical Field

[0001] The present invention relates to the technical field of very long baseline interferometry, and more particularly to a fractional delay compensation method and apparatus for a spatial VLBI correlation processor. Background Art

[0002] Very Long Baseline Interferometry (VLBI) technology is an observation technology with high resolution and high measurement accuracy, and is widely used in fields such as astrophysics, astrometry, and deep space exploration. The angular resolution θ is one of the most important technical indicators of VLBI, and is expressed as where λ is the wavelength and B is the baseline length, that is, the distance between two telescopes. The longer the baseline, the higher the angular resolution. Ground-based VLBI consists of telescopes on the Earth's surface, and the baseline length does not exceed the Earth's diameter. To obtain a higher angular resolution, spatial VLBI is one of the important development directions. For example, China's LOVEX (Lunar Orbit VLBI EXperiment, LOVEX) project launches a radio telescope into space to form a space-ground baseline with a ground-based radio telescope. Its Earth-moon baseline length can far exceed the Earth's diameter, achieving a higher angular resolution.

[0003] The correlation processor is the core device for VLBI data processing. According to the order of data multiplication (X) and Fourier transform (F) in the correlation processing flow, the correlation processor can be divided into two types: XF and FX. The FX type is superior to the XF type in terms of computational complexity. In addition, according to the computing platform, the correlation processor can be divided into a software correlation processor and a hardware correlation processor. With the rapid development of general computing devices and software technology in the past two decades, the software correlation processor has gradually replaced the hardware correlation processor and become the mainstream of VLBI data processing. VLBI correlation processing usually includes the following modules: a decoding module, a delay compensation module, a fringe rotation module, a time-frequency conversion module, a conjugate multiplication and integration module. Among them, the delay compensation module is further divided into two categories: integer delay compensation that is an integer multiple of the sampling period and fractional delay compensation that is not an integer multiple of the sampling period. Currently, mainstream software correlation processors have the above modules, but their order and implementation methods are different, resulting in differences in computational accuracy and speed.

[0004] Existing mainstream software-related processors such as DiFX (Distributed FX), CVN (Chinese VLBI Network), and SFXC (Super FX Correlator) all adopt the FX-type structure. Due to its flexibility and open-source nature, DiFX has been adopted by multiple international research institutions and organizations and is currently the most widely used software-related processor. DiFX was developed by Swinburne University of Technology in Australia, runs on a cluster with an x86 architecture, and improves processing efficiency by using the Intel IPP (Integrated Performance Primitives) and OpenMPI (Open Message Passing Interface) libraries (see Reference 1). The CVN software-related processor was developed by the Shanghai Astronomical Observatory and mainly serves China's lunar exploration project and deep space exploration missions. The CVN processor is developed in C language, and the cluster version runs on the Linux system. It adopts a two-level parallel structure of multi-threading and MPI that complies with the POSIX standard and uses the Intel IPP library to improve performance (see Reference 2). SFXC was developed by JIVE (Joint Institute for VLBI in Europe), is developed based on the C++ language and MPI, and runs on a cluster with a Linux system and an x86 architecture. SFXC was initially used for the mission of tracking the Cassini-Huygens probe. After years of development, it has now become the EVN (European VLBI Network) software-related processor and is widely used in astrophysical observations (see Reference 3).

[0005] The existing DiFX and CVN-related processors have a relatively high processing speed but insufficient accuracy, while the SFXC-related processor has high accuracy but a relatively low processing speed. Therefore, how to make the related processor have both high accuracy and high processing speed is a technical problem that needs to be urgently solved by those skilled in the art.

[0006] Reference 1: DiFX: A Software Correlator for Very Long Baseline Interferometry Using Multiprocessor Computing Environments[J]. Publications of the Astronomical Society of the Pacific, 2007, 119(853): 318 - 336.

[0007] Reference 2: Tong Li. Postdoctoral Research Report, Shanghai: Shanghai Astronomical Observatory, Chinese Academy of Sciences, 2014: 15.

[0008] Reference 3: Keimpema A, Kettenis M M, Pogrebenko S V, et al. The SFXC software correlator for very long baseline interferometry: algorithms and implementation[J]. Experimental Astronomy, 2015, 39: 259 - 279. Summary of the Invention

[0009] The object of the present invention is to provide a fractional delay compensation method and device for a spatial VLBI correlator, so that the correlator has both high precision and high processing speed.

[0010] Based on the above object, on the one hand, the present invention provides a fractional delay compensation method for a spatial VLBI correlator, including:

[0011] Obtain data between the sampling start time and the sampling end time;

[0012] Based on the pre - obtained delay model, sampling interval, preset control parameters, the sampling start time and the sampling end time, determine a compensation time series; where the compensation time series includes a plurality of compensation time points sorted in ascending order;

[0013] For each compensation time point, based on the compensation time point, the delay model and the sampling interval, determine the fractional delay corresponding to the compensation time point;

[0014] A compensation time period is formed between every two adjacent compensation time points. For each compensation time period, use the fractional filter corresponding to the compensation time period to perform fractional delay compensation on the data within the compensation time period to obtain the data after fractional delay compensation; where the filter coefficients of the fractional filter corresponding to each compensation time period are calculated according to the fractional delay corresponding to the smaller of the two compensation time points forming the compensation time period.

[0015] Further, the first compensation time point of the compensation time series is equal to the sampling start time, the maximum compensation time point of the compensation time series is greater than or equal to the sampling end time, and the second - largest compensation time point of the compensation time series is less than the sampling end time.

[0016] Further, any two adjacent compensation time points satisfy the following relationship:

[0017] t i+1 = t i + Δt × step i

[0018]

[0019] where t i+1 is the larger of any two adjacent compensation time points, and t i is the smaller of any two adjacent compensation time points, Δt is the sampling interval, and step i is the time increment corresponding to the compensation time point t i , α is the control parameter, and g(t i ) is the derivative of the time delay model at t i , and is the floor symbol.

[0020] Furthermore, the control parameter is less than 0.01.

[0021] Furthermore, the fractional filter is a Farrow structure filter.

[0022] On the other hand, the present invention provides a fractional time delay compensation device for a spatial VLBI correlation processor, including:

[0023] An acquisition module for acquiring data within the sampling start time and the sampling end time;

[0024] A first determination module for determining a compensation time series based on a pre-acquired time delay model, a sampling interval, a preset control parameter, the sampling start time, and the sampling end time; wherein the compensation time series includes a plurality of compensation time points sorted in ascending order;

[0025] A second determination module for determining the fractional time delay corresponding to each compensation time point based on the compensation time point, the time delay model, and the sampling interval;

[0026] A compensation module for performing fractional time delay compensation on the data within each compensation time period by using the fractional filter corresponding to the compensation time period to obtain the data after fractional time delay compensation; wherein, a compensation time period is formed between every two adjacent compensation time points, and the filter coefficients of the fractional filter corresponding to each compensation time period are calculated according to the fractional time delay corresponding to the smaller of the two compensation time points forming the compensation time period.

[0027] Further, the first compensation time point of the compensation time series is equal to the sampling start time, the maximum compensation time point of the compensation time series is greater than or equal to the sampling end time, and the second largest compensation time point of the compensation time series is less than the sampling end time.

[0028] Further, any two adjacent compensation time points satisfy the following relational expression:

[0029] t i+1 = t i + Δt × step i

[0030]

[0031] wherein, t i+1 is the larger one of any two adjacent compensation time points, t i is the smaller one of any two adjacent compensation time points, Δt is the sampling interval, step i is the time increment corresponding to the compensation time point t i , α is the control parameter, g(t i ) is the derivative of the delay model at t i , and is the floor symbol.

[0032] Further, the control parameter is less than 0.01.

[0033] Further, the fractional filter is a Farrow structure filter.

[0034] The fractional delay compensation device for a space VLBI correlation processor according to the present invention dynamically calculates compensation time points based on a delay model, divides the total sampling time into multiple compensation time periods by the compensation time points, and the data within each compensation time period is subjected to fractional delay compensation by a respective corresponding fractional filter. Thus, the amount of data within each compensation time period can be dynamically adjusted. When the delay changes rapidly, the amount of data is smaller; when the delay changes slowly, the amount of data is higher. Such dynamic processing can make the compensation accuracy higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a flowchart of a fractional delay compensation method for a space VLBI correlation processor according to an embodiment of the present invention;

[0036] Figure 2 is a structural block diagram of a fractional delay compensation device for a space VLBI correlation processor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following presents preferred embodiments of the present invention in conjunction with the accompanying drawings and describes them in detail.

[0038] As Figure 1 shown, an embodiment of the present invention provides a fractional delay compensation method for a spatial VLBI correlation processor, which includes the following steps:

[0039] S100: Obtain the data within the sampling start time and the sampling end time.

[0040] The sampling start time and the sampling end time can be selected as needed. The sampling end time minus the sampling start time is the total sampling time. When performing fractional delay compensation, it is necessary to first obtain all the data within the total sampling time, and then perform fractional delay compensation on these data. Assuming that the sampling start time is 0 and the sampling end time is T, the total sampling time is also T, and the obtained data is all the data from time 0 to time T.

[0041] S200: Determine the compensation time sequence based on the pre-obtained delay model, sampling interval, preset control parameters, sampling start time, and sampling end time; wherein the compensation time sequence includes multiple compensation time points sorted in ascending order.

[0042] The delay model is the time difference between the arrival of the same signal at the station and the reference station (usually the geocenter), which is a continuous function f(t) of time t. The delay model can be calculated according to the ephemeris file of the observation target, which is external input information of the correlation processor, and its calculation method is also well known in the art and will not be elaborated here.

[0043] The specific value of the sampling interval can be determined by comprehensively considering the observation target, observation frequency, system performance, and data processing requirements, etc. Its determination method is well known in the art and will not be elaborated here.

[0044] In some embodiments, the method for determining the compensation time sequence based on the pre-obtained delay model, sampling interval, preset control parameters, sampling start time, and sampling end time is as follows:

[0045] a) Let i = 0, t0 = sampling start time, that is, 0;

[0046] b) Calculate where step i is the time increment corresponding to the compensation time point t i , is the floor symbol, α is the control parameter, and g(t) is the first derivative of the delay model;

[0047] c) Calculate t i+1 = t i + Δt × step i ; where Δt is the sampling interval;

[0048] d) Let \(i = i + 1\), then repeat steps b)-d) until \(t\) i \(\geq T\).

[0049] Thus, the compensation time series \(\{t\}\) can be obtained. The compensation time points in the compensation time series are sorted in chronological order. Assuming the number of compensation time points in the compensation time series is \(U\), then the first compensation time point in the compensation time series is \(t_0 = 0\), and the last compensation time point (i.e., the maximum compensation time point) \(t\) i \(\geq T\), and the compensation time point adjacent to the last compensation time point (i.e., the second largest compensation time point) \(t\) U-1 \(< T\). U-2 <T.

[0050] The control parameter \(\alpha\) is an adjustable parameter introduced in the present invention for controlling the compensation accuracy. When \(\alpha < 0.01\), the method of the present invention can achieve high accuracy.

[0051] S300: For each compensation time point, determine the fractional delay corresponding to this compensation time point based on this compensation time point, the delay model, and the sampling interval.

[0052] In some embodiments, the calculation method of the fractional delay corresponding to each compensation time point is as follows:

[0053]

[0054] where \(d\) i is the fractional delay corresponding to the compensation time point \(t\) i , \(f(t)\) is the delay model, and \(f(t\) i ) is the delay value at the compensation time point \(t\) i .

[0055] S400: A compensation time period is formed between every two adjacent compensation time points. For each compensation time period, use the fractional filter corresponding to this compensation time period to perform fractional delay compensation on the data within this compensation time period to obtain the data after fractional delay compensation; among them, the filter coefficients of the fractional filter corresponding to each compensation time period are calculated based on the fractional delay corresponding to the smaller one of the two compensation time points forming this compensation time period.

[0056] A compensation time period is formed between every two adjacent compensation time points. For example, for the compensation time points \(t\) i and \(t\) i+1 , the formed compensation time period is \([t\) i , \(t\) i+1, so that each compensation time point can divide the total sampling time T into multiple compensation time periods. Each compensation time period has a corresponding fractional filter, and the filter coefficient of the fractional filter is determined by the fractional delay corresponding to the smaller of the two compensation time points forming the compensation time period; for example, the compensation time period [t i , t i+1 corresponds to the filter coefficient of the fractional filter determined by the fractional delay d i corresponding to the compensation time point t i . Therefore, the fractional filters corresponding to each compensation time period are different, and the data within each compensation time period is compensated for fractional delay by the fractional filter corresponding to that compensation time period, so that the data after fractional delay compensation can be obtained.

[0057] In some embodiments, the fractional filter is a Farrow structure filter. For example, for each fractional delay d i , a (2N + 1)-order FIR (finite impulse response) filter can be designed, is the filter coefficient corresponding to the fractional delay d i , where n is the order index; for h(n, d i ), it can be approximated by a polynomial with d i as a variable to obtain a set of coefficients C(n, m) that satisfy the Farrow structure approximation criterion, and here the minimum mean square error criterion can be used for approximation; assuming the polynomial has M orders, the above process can be expressed as:

[0058] n = -N, -N + 1, …, 0, … N; m = 0, 1, …, M - 1

[0059] C(n, m) can be obtained in advance, and then when performing the fractional delay compensation process, d i can be directly substituted into the above polynomial to obtain an approximate value of the filter coefficient h(n, d i ).

[0060] The fractional delay compensation method for the spatial VLBI correlation processor according to the embodiments of the present invention dynamically calculates the compensation time points according to the delay model, divides the total sampling time into multiple compensation time periods by the compensation time points, and the data within each compensation time period is compensated for fractional delay by the respective corresponding fractional filter. Thus, the amount of data within each compensation time period can be dynamically adjusted. When the delay changes rapidly, the amount of data is smaller, and when the delay changes slowly, the amount of data is higher. Such dynamic processing can make the compensation accuracy higher.

[0061] Such as Figure 2As shown in the figure, an embodiment of the present invention further provides a fractional delay compensation device for a spatial VLBI related processor, which includes an acquisition module 10, a first determination module 20, a second determination module 30, and a compensation module 40.

[0062] The acquisition module 10 is used to acquire data within the sampling start time and the sampling end time.

[0063] The first determination module 20 is used to determine a compensation time series based on a pre-acquired delay model, a sampling interval, preset control parameters, the sampling start time, and the sampling end time; wherein the compensation time series includes multiple compensation time points sorted in ascending order.

[0064] The second determination module 30 is used to determine the fractional delay corresponding to each compensation time point based on the compensation time point, the delay model, and the sampling interval.

[0065] The compensation module 40 is used to perform fractional delay compensation on the data within each compensation time period by using the fractional filter corresponding to the compensation time period to obtain the data after fractional delay compensation; wherein, a compensation time period is formed between every two adjacent compensation time points, and the filter coefficients of the fractional filters corresponding to each compensation time period are calculated according to the fractional delay corresponding to the smaller one of the two compensation time points forming the compensation time period.

[0066] The specific implementation methods of the first determination module 20, the second determination module 30, and the compensation module 40 are the same as those in the method embodiment, and for details, reference can be made to the method embodiment, which will not be elaborated here.

[0067] The fractional delay compensation device for a spatial VLBI related processor according to the embodiment of the present invention dynamically calculates compensation time points according to the delay model, divides the total sampling time into multiple compensation time periods by the compensation time points, and the data within each compensation time period is subjected to fractional delay compensation by the corresponding fractional filter. Thus, the amount of data within each compensation time period can be dynamically adjusted. When the delay changes rapidly, the amount of data is smaller; when the delay changes slowly, the amount of data is higher. Such dynamic processing can make the compensation accuracy higher.

[0068] Another embodiment of the present invention provides a readable storage medium, on which a computer program is stored. When the computer program is executed on a computer, the computer is made to execute the steps of the fractional delay compensation method for a spatial VLBI related processor in the above embodiment of the present invention.

[0069] Another embodiment of the present invention provides an electronic device, which includes a memory and a processor. An executable code is stored in the memory. When the processor executes the executable code, it executes the steps of the fractional delay compensation method for a spatial VLBI related processor in the above embodiment of the present invention.

[0070] When performing relevant processing, usually the data observed by the radio telescopes of two stations are both converted to the reference station (usually the geocenter) and then the data of the two stations are processed correlatively. The working process of the correlator adopting the fractional delay compensation method of the present invention is as follows:

[0071] 1) For the data observed by each station, the correlator will process it as follows: raw data decoding, integer delay compensation, fractional delay compensation, and fringe rotation.

[0072] The original signal is a 1-bit or 2-bit digital signal after quantization. Raw data decoding is to decode and map the original signal to a floating point number to improve the signal-to-noise ratio of the signal. Among them, the 1-bit binary signal {02, 12} is mapped to {1, -1}; the 2-bit binary signal {002, 012, 102, 112} is mapped to the floating point numbers {-3.336, -1, 1, 3.336}.

[0073] The delay at different times can be divided into an integer delay part and a fractional delay part. Therefore, it is necessary to perform integer delay compensation and fractional delay compensation on the data respectively. The integer delay compensation of the delay model at time t is The integer delay compensation is compensated by sampling interval translation. For example, at time t, take the data at the moment, that is, offset by for the sampling interval.

[0074] The fractional delay compensation means performing fractional delay compensation on the data after integer delay compensation. The fractional delay compensation method is the fractional delay compensation method described in the embodiments of the present invention, which will not be elaborated here.

[0075] The fringe rotation means performing fringe rotation on the data after fractional delay compensation. Suppose the data sequence after fractional delay compensation is {x i}, and the data sequence after fringe rotation is {y i}, and their change relationship is as follows:

[0076] y i =x i e -j2πf(iΔt)

[0077] where j is the imaginary unit.

[0078] 2) The data obtained after the original data decoding, integer delay compensation, fractional delay compensation, and fringe rotation for the two stations in sequence are respectively subjected to FFT (Fast Fourier Transform), transforming the data from the time domain to the frequency domain, and then the frequency domain data of the two stations are multiplied conjugately and integrated to obtain the data after correlation processing. The specific steps of FFT and conjugate multiplication and integration are well-known in the art and will not be elaborated here.

[0079] Since the original data decoding, integer delay compensation, fractional delay compensation, and fringe rotation are all performed in the time domain, the relevant processor adopting the fractional delay compensation method of the embodiment of the present invention only needs to perform one conversion from the time domain to the frequency domain, that is, only one FFT needs to be performed. Therefore, its computational amount is smaller and the computational speed is faster; and the fractional delay compensation method of the embodiment of the present invention has high computational accuracy. Therefore, the relevant processor has both high accuracy and fast processing speed.

[0080] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0081] For the convenience of description, when describing the above device, it is divided into various units according to functions for separate description. Of course, when implementing the present invention, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0082] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] The present invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each flow and / or block of the flowchart illustrations and / or block diagrams, and combinations of flows and / or blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processors of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing device create means for implementing the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or means for implementing the functions specified in a block or blocks.

[0084] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or means for implementing the functions specified in a block or blocks.

[0085] These computer program instructions may also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are performed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the flow Figure 1 one or more flows and / or blocks Figure 1 or means for implementing the functions specified in a block or blocks.

[0086] In a typical configuration, an electronic device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0087] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0088] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by electronic devices. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0089] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0090] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0091] The present invention may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0092] Each embodiment in the present invention is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the corresponding part of the method embodiment for the relevant content.

[0093] The specific embodiments of the present invention have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. That is, all simple, equivalent changes and modifications made in accordance with the claims and the content of the specification of the present invention application fall within the scope of the claims of the present invention patent. The content not described in detail in the present invention is all conventional technical content.

Claims

1. A fractional delay compensation method for a spatial VLBI correlation processor, characterized in that: include: Obtain data between the sampling start time and the sampling end time; Determine a compensation time sequence based on a pre-acquired delay model and sampling interval, preset control parameters, the sampling start time and the sampling end time; The compensation time series includes a plurality of compensation time points arranged in order from small to large; For each compensation time point, determine a fractional delay corresponding to the compensation time point based on the compensation time point, the delay model and the sampling interval; A compensation time period is formed between every two adjacent compensation time points. For each compensation time period, a fractional filter corresponding to the compensation time period is used to perform fractional delay compensation on the data in the compensation time period to obtain data after fractional delay compensation; wherein the filter coefficient of the fractional filter corresponding to each compensation time period is calculated based on the fractional delay corresponding to the smaller of the two compensation time points forming the compensation time period.

2. The fractional delay compensation method for a spatial VLBI correlation processor according to claim 1, characterized in that: The first compensation time point of the compensation time sequence is equal to the sampling start time, the maximum compensation time point of the compensation time sequence is greater than or equal to the sampling end time, and the second largest compensation time point of the compensation time sequence is less than the sampling end time.

3. The fractional delay compensation method for a spatial VLBI correlation processor according to claim 2, characterized in that: Any two adjacent compensation time points satisfy the following relationship: t i+1 =t i +Δt×step i Among them, t i+1 is the larger of any two adjacent compensation time points, t i is the smaller of any two adjacent compensation time points, Δt is the sampling interval, step i The compensation time point t i The corresponding time increment, α is the control parameter, g(t i ) is the time delay model at t i The derivative at The floor symbol.

4. The fractional delay compensation method for a spatial VLBI correlation processor according to claim 3, characterized in that: The control parameter is less than 0.

01.

5. The fractional delay compensation method for a spatial VLBI correlation processor according to claim 1, characterized in that: The fractional filter is a Farrow structure filter.

6. A fractional delay compensation device for a spatial VLBI correlation processor, characterized in that: include: An acquisition module is used to acquire data within the sampling start time and the sampling end time; A first determination module, configured to determine a compensation time sequence based on a pre-acquired delay model and a sampling interval, preset control parameters, the sampling start time and the sampling end time; The compensation time series includes a plurality of compensation time points arranged in order from small to large; A second determination module is used to determine, for each compensation time point, a fractional delay corresponding to the compensation time point based on the compensation time point, the delay model and the sampling interval; The compensation module is used to perform fractional delay compensation on the data in each compensation time period by using the fractional filter corresponding to the compensation time period to obtain the data after fractional delay compensation; wherein, each two adjacent compensation time points form a compensation time period, and the filter coefficient of the fractional filter corresponding to each compensation time period is calculated according to the fractional delay corresponding to the smaller of the two compensation time points forming the compensation time period.

7. The fractional delay compensation device for a spatial VLBI correlation processor according to claim 6, characterized in that: The first compensation time point of the compensation time sequence is equal to the sampling start time, the maximum compensation time point of the compensation time sequence is greater than or equal to the sampling end time, and the second largest compensation time point of the compensation time sequence is less than the sampling end time.

8. The fractional delay compensation device for a spatial VLBI correlation processor according to claim 7, characterized in that: Any two adjacent compensation time points satisfy the following relationship: t i+1 =t i +Δt×step i Among them, t i+1 is the larger of any two adjacent compensation time points, t i is the smaller of any two adjacent compensation time points, Δt is the sampling interval, step i The compensation time point t i The corresponding time increment, α is the control parameter, g(t i ) is the time delay model at t i The derivative at The floor symbol.

9. The fractional delay compensation device for a spatial VLBI correlation processor according to claim 8, characterized in that: The control parameter is less than 0.

01.

10. The fractional delay compensation device for a spatial VLBI correlation processor according to claim 6, characterized in that: The fractional filter is a Farrow structure filter.

11. A readable storage medium having a computer program stored thereon, which, when executed in a computer, enables the computer to implement the fractional delay compensation method for a spatial VLBI correlation processor as claimed in any one of claims 1 to 5.

12. An electronic device comprising a memory and a processor, wherein the memory stores executable codes, and when the processor executes the executable codes, it implements the fractional delay compensation method for a spatial VLBI correlation processor as described in any one of claims 1 to 5.

Images